19-5245; Rev 0; 4/10
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs
General Description
The MAX11102/MAX11103/MAX11105/MAX11106/MAX11110 MAX11111/MAX11115/MAX11116/MAX11117 are 12-/10/8-bit, compact, high-speed, low-power, successive approximation analog-to-digital converters (ADCs). These high-performance ADCs include a high-dynamic range sample-and-hold and a high-speed serial interface. These ADCs accept a full-scale input from 0V to the power supply or to the reference voltage. The MAX11102/MAX11103/MAX11106/MAX11111 feature dual, single-ended analog inputs connected to the ADC core using a 2:1 MUX. The devices also include a separate supply input for data interface and a dedicated input for reference voltage. In contrast, the single-channel devices generate the reference voltage internally from the power supply. These ADCs operate from a 2.2V to 3.6V supply and consume only 8.3mW at 3Msps and 6.2mW at 2Msps. The devices include full power-down mode and fast wake-up for optimal power management and a highspeed 3-wire serial interface. The 3-wire serial interface directly connects to SPIK, QSPIK, and MICROWIREK devices without external logic. Excellent dynamic performance, low voltage, low power, ease of use, and small package size make these converters ideal for portable battery-powered data-acquisition applications, and for other applications that demand low-power consumption and minimal space. S 12-/10-/8-Bit Resolution S 1-/2-Channel, Single-Ended Analog Inputs S Variable I/O: 1.5V to 3.6V (Dual-Channel Only) Allows the Serial Interface to Connect Directly to 1.5V, 1.8V, 2.5V, or 3V Digital Systems S 2.2V to 3.6V Supply Voltage S Low Power 8.3mW at 3Msps 6.2mW at 2Msps Very Low Power Consumption at 2.5µA/ksps S External Reference Input (Dual-Channel Devices Only) S 1.3µA Power-Down Current S SPI-/QSPI-/MICROWIRE-Compatible Serial Interface S 10-Pin, 3mm x 3mm TDFN Package S 10-Pin, 3mm x 5mm µMAX Package S 6-Pin, 2.8mm x 2.9mm SOT23 Package S Wide -40NC to +125NC Operation
Features
S 2Msps/3Msps Conversion Rate, No Pipeline Delay
MAX11102/03/05/06/10/11/15/16/17
IM
BITS 12 12 12
IN
PR EL
PART PIN-PACKAGE 10 FMAX-EP* 10 TDFN-EP* 10 FMAX-EP* MAX11102AUB+ MAX11103AUB+
These ADCs are available in a 10-pin TDFN package, 10-pin FMAX® package, and a 6-pin SOT23 package. These devices operate over the -40NC to +125NC temperature range.
AR
Data Acquisition Portable Data Logging Medical Instrumentation Battery-Operated Systems Communication Systems Automotive Systems
SPEED (Msps) 2 2 3
MAX11102ATB+**
Ordering Information continued at end of data sheet. Note: All devices are specified over the -40°C to +125°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. **Future product—contact factory for availability.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. µMAX is a registered trademark of Maxim Integrated Products, Inc.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Y
2 2 2
S Low-Noise 73dB SNR
Applications
Ordering Information
NO. OF CHANNELS
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17
ABSOLUTE MAXIMUM RATINGS
VDD to GND ............................................................ -0.3V to +4V REF, OVDD, AIN1, AIN2, AIN to GND ........-0.3V to the lower of (VDD + 0.3V) and +4V CS, SCLK, CHSEL, DOUT TO GND ............-0.3V to the lower of (VOVDD + 0.3V) and +4V AGND to GND ...................................................... -0.3V to +0.3V Input/Output Current (all pins) ...........................................50mA Continuous Power Dissipation (TA = +70NC) 6-Pin SOT23 (derate 8.7mW/NC above +70NC) ......... ..696mW 10-Pin TDFN (derate 24.4mW/NC above +70NC) ...... .1951mW 10-Pin FMAX (derate 8.8mW/NC above +70NC)...... ..707.3mW Operating Temperature Range ....................... .-40NC to +125NC Junction Temperature .....................................................+150NC Storage Temperature Range............................ -65NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS (MAX11102/MAX11103/MAX11105)
PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Total Unadjusted Error Channel-to-Channel Offset Matching Channel-to-Channel Gain Matching
SYMBOL
IN
CONDITIONS
(VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps (MAX11103); fSCLK = 32MHz, 50% duty cycle, 2Msps (MAX11102/MAX11105), CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) MIN 12 Q1 Q1 Q0.3 Q1 Q1.5 Q0.4 Q0.05 Q3 Q3 TYP MAX UNITS Bits LSB LSB LSB LSB LSB LSB LSB
12 bits INL OE GE DNL
PR EL
Signal-to-Noise and Distortion Signal-to-Noise Ratio SINAD SNR
DYNAMIC PERFORMANCE (MAX11102/MAX11105: fIN = 0.5MHz, MAX11103: fIN = 1MHz) MAX11103 MAX11102/MAX11105 MAX11103 MAX11102/MAX11105 MAX11103 MAX11102/MAX11105 MAX11103 MAX11102/MAX11105 f1 = 1.0003MHz, f2 = 0.99955MHz (MAX11103), f1 = 500.15kHz, f2 = 499.56 kHz (MAX11102/MAX11105) -3dB point SINAD > 68dB 76 77 70 70 70.5 70.5 72 72.5 72 73 -85 -85 85 85 -75 -76 dB dB dB dB
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
IM
No missing codes TUE THD SFDR IMD
Excluding offset and reference errors
MAX11102/MAX11103 MAX11102/MAX11103
AR
-84 40 2.5
Full-Power Bandwidth Full-Linear Bandwidth
2
______________________________________________________________________________________
Y
dB
MHz MHz
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11102/MAX11103/MAX11105) (continued)
(VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps (MAX11103); fSCLK = 32MHz, 50% duty cycle, 2Msps (MAX11102/MAX11105), CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) Small-Signal Bandwidth Crosstalk CONVERSION RATE Throughput Conversion Time Acquisition Time Aperture Delay Aperture Jitter Serial-Clock Frequency ANALOG INPUT (AIN1, AIN2/AIN) Input Voltage Range Input Leakage Current Input Capacitance VINA__ IILA CAIN_ fCLK MAX11103 tACQ MAX11103 MAX11103 MAX11102/MAX11105 MAX11102/MAX11105 From CS falling edge MAX11102/MAX11103
MAX11102/03/05/06/10/11/15/16/17
AR
0.02 260 391 52 4 15 0.48 0.32 0 2nA 20 4 1 0.005 5 75 15 1nA 2 85 4 2.2 1.5
IN
MAX11102/MAX11105
IM
Track Hold VREF IILR Conversion stopped CREF (Note 2) (Note 2) (Note 2) Inputs at GND or VDD VIL IIL VHYST CIN VOH VOL IOL ISOURCE = 200FA (Note 2) ISINK = 200FA (Note 2) COUT VDD VOVDD MAX11102/MAX11103
EXTERNAL REFERENCE INPUT (REF) (MAX11102/MAX11103) Reference Input Voltage Range Reference Input Leakage Current Reference Input Capacitance
PR EL
DIGITAL INPUTS (SCLK, CS, CHSEL) Digital Input High Voltage VIH Digital Input Low Voltage Digital Input Hysteresis
Digital Input Leakage Current Digital Input Capacitance Output High Voltage Output Low Voltage DIGITAL OUTPUT (DOUT)
High-Impedance Leakage Current High-Impedance Output Capacitance POWER SUPPLY Positive Supply Voltage Digital I/O Supply Voltage
_______________________________________________________________________________________
Y
45 -90 0.03 3 2 48 32 VREF Q1 VDD + 0.05 Q1 25 Q1 15 Q1.0 3.6 VDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS MHz dB
Msps ns ns ps MHz
V FA pF
V FA pF %OVDD %OVDD %OVDD FA pF %OVDD %OVDD FA pF
V V
3
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17
ELECTRICAL CHARACTERISTICS (MAX11102/MAX11103/MAX11105) (continued)
(VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps (MAX11103); fSCLK = 32MHz, 50% duty cycle, 2Msps (MAX11102/MAX11105), CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER SYMBOL CONDITIONS fSAMPLE = 3Msps, MAX11103, VIN = GND fSAMPLE = 2Msps, MAX11102/MAX11105, VIN = GND MAX11103, VIN = GND MAX11102, VIN = GND MAX11103 Leakage only MAX11102/MAX11105 MIN TYP MAX 3.3 2.6 UNITS
AR
1.98 1.48 1.3 0.7 4 10 5 1 40 40 5 2.5 MIN 10 TYP Q0.3 Q0.5 Q0.15 Q0.7
Positive Supply Current (Full-Power Mode)
IVDD
IOVDD Positive Supply Current (FullPower Mode), No Clock Power-Down Current Line Rejection TIMING CHARACTERISTICS (Note 3) Quiet Time CS Pulse Width CS Fall to SCLK Setup CS Falling Until DOUT High Impedance Disabled Data Access Time After SCLK Falling Edge SCLK Pulse Width Low SCLK Pulse Width High Data Hold Time from SCLK Falling Edge tQ t1 t2 t3 t4 t5 t6 t7 t8 IVDD IPD
VDD = 2.2V to 3.6V, VREF = 2.2V
IN
CONDITIONS
IM
Figure 3 Figure 4 (Note 1) Conversion cycle SYMBOL 10 bits INL DNL OE No missing codes MAX11117 GE MAX11117
(Note 1)
Figure 2, VOVDD = 2.2V - 3.6V Figure 2, VOVDD = 1.5V - 2.2V Percentage of clock period Percentage of clock period
PR EL
SCLK Falling Until DOUT High Impedance Power-Up Time
ELECTRICAL CHARACTERISTICS (MAX11106/MAX11110/MAX11117))
(VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps (MAX11106/MAX11117); fSCLK = 32MHz, 50% duty cycle, 2Msps (MAX11110), CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER MAX UNITS Bits Q0.5 Q0.5 Q1.2 Q1.65 Q1 Q1.4 MAX11106/MAX11110 Excluding offset and reference errors, MAX11106/MAX11110 LSB LSB LSB DC ACCURACY Resolution
Integral Nonlinearity Differential Nonlinearity Offset Error
Gain Error
4
______________________________________________________________________________________
Y
0.33 0.22 10 15 16.5 60 60 14 1
mA
mA FA LSB/V ns ns ns ns ns % % ns ns Cycle
LSB
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11106/MAX11110/MAX11117) (continued)
(VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps (MAX11106/MAX11117); fSCLK = 32MHz, 50% duty cycle, 2Msps (MAX11110), CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER Total Unadjusted Error Channel-to-Channel Offset Matching Channel-to-Channel Gain Matching SYMBOL TUE MAX11106 MAX11106 CONDITIONS MIN TYP Q1 MAX UNITS LSB LSB LSB
MAX11102/03/05/06/10/11/15/16/17
DYNAMIC PERFORMANCE (MAX11106/MAX11117: fIN = 1MHz, MAX11110: fIN = 0.5MHz) Signal-to-Noise and Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range SINAD SNR THD SFDR MAX11106/MAX11117 MAX11110 MAX11110 MAX11110 MAX11110
AR
Q0.1 59 59 61.5 61.5 61.5 61.5 -85 -85 75 75 60.5 60.5 -74 -73 -82 40 2.5 45 -90 0.03 0.02 260 391 52 4 15 0.48 0.32 0 2nA 20 4 1 VDD + 0.05 0.005 Q1 48 32 VREF Q1 3 2
MAX11106/MAX11117 MAX11106/MAX11117 MAX11106/MAX11117
IN
Intermodulation Distortion
IM
IMD -3dB point SINAD > 60dB MAX11106 MAX11110 MAX11110 From CS falling edge tACQ fCLK MAX11110 VINA__ IILA CAIN_ Track Hold VREF IILR Conversion stopped
f1 = 1.0003MHz, f2 = 0.99955MHz (MAX11106/MAXX11117); f1 = 500.15kHz, f2 = 499.56 kHz (MAX11110)
Full-Power Bandwidth Full-Linear Bandwidth Small-Signal Bandwidth Crosstalk CONVERSION RATE Throughput
PR EL
MAX11106/MAX11117 MAX11106/MAX11117
Y
Q0.1
dB dB dB dB
dB
MHz MHz MHz dB Msps Msps ns ns ns ns ps MHz
Conversion Time Acquisition Time Aperture Delay Aperture Jitter
Serial-Clock Frequency
MAX11106/MAX11117
ANALOG INPUT (AIN1/AIN2 for MAX11106) (AIN for MAX11110/MAX11117) Input Voltage Range V FA pF Input Leakage Current Input Capacitance
EXTERNAL REFERENCE INPUT (REF) (MAX11106) Reference Input Voltage Range Reference Input Leakage Current V FA 5
_______________________________________________________________________________________
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17
ELECTRICAL CHARACTERISTICS (MAX11106/MAX11110/MAX11117) (continued)
(VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps (MAX11106/MAX11117); fSCLK = 32MHz, 50% duty cycle, 2Msps (MAX11110), CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER Reference Input Capacitance SYMBOL CREF (Note 2) (Note 2) (Note 2) CONDITIONS MIN TYP 5 MAX UNITS pF
Digital Input Hysteresis Digital Input Leakage Current Digital Input Capacitance DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage High-Impedance Leakage Current High-Impedance Output Capacitance POWER SUPPLY Positive Supply Voltage Digital I/O Supply Voltage Positive Supply Current (FullPower Mode) Positive Supply Current (FullPower Mode), No Clock Power-Down Current Line Rejection Quiet Time
VHYST IIL CIN VOH VOL IOL COUT
AR
15 2 0.001 85 4 2.2 1.5 1.98 1.48 1.3 0.17 4 10 5 1 40 40 5 2.5
DIGITAL INPUTS (SCLK, CS, CHSEL) Digital Input High Voltage VIH Digital Input Low Voltage VIL
Inputs at GND or VDD
ISOURCE = 200µA (Note 2) ISINK = 200µA (Note 2)
IN
MAX11106 fSAMPLE = 3Msps, MAX11106, VIN = GND fSAMPLE = 2Msps, MAX11110, VIN = GND fSAMPLE = 3Msps, MAX11117, VIN = GND MAX11106 MAX11110 Leakage only VDD = 2.2V to 3.6V, VREF = 2.2V MAX11106/MAX11117 (Note 1) Figure 2 VOVDD = 2.2V - 3.6V VOVDD = 1.5V - 2.2V Percentage of clock period Percentage of clock period Figure 3 Figure 4 (Note 1) Conversion cycle
IM
VDD VOVDD IVDD IOVDD IVDD IPD tQ t1 t2 t3 t4 t5 t6 t7 t8
Y
75 25 Q1 15 Q1.0 3.6 VDD 3.3 2.6 3.55 0.33 10 15 16.5 60 60 14 1
%OVDD %OVDD %OVDD FA pF
%OVDD %OVDD FA pF
V V
mA
PR EL
mA FA LSB/V ns ns ns ns ns % % ns ns Cycle
TIMING CHARACTERISTICS (Note 3) CS Pulse Width
CS Fall to SCLK Setup
CS Falling Until DOUT High Impedance Disabled
Data Access Time After SCLK Falling Edge SCLK Pulse Width High Data Hold Time from SCLK Falling Edge
SCLK Pulse Width Low
SCLK Falling Until DOUT High Impedance Power-Up Time 6
______________________________________________________________________________________
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11111/MAX11115/MAX11116)
(VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps (MAX11111/MAX11116); fSCLK = 32MHz, 50% duty cycle, 2Msps (MAX11115), CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Total Unadjusted Error Channel-to-Channel Offset Matching Channel-to-Channel Gain Matching INL DNL OE GE TUE MAX11111 MAX11111 No missing codes 8 bits SYMBOL CONDITIONS MIN 8 TYP MAX UNITS Bits
MAX11102/03/05/06/10/11/15/16/17
AR
Q0.45 Q0.04 Q0.75 0.025 0.025 49 49 49 49 49.5 49.5 49.5 49.5 -70 -75 63 63 66 66 -65 40 2.5 45 -90 0.03 0.02 260 391 52 4 15 0.48 0.32
Excluding offset and reference errors
DYNAMIC PERFORMANCE (MAX11111/MAX11116: fIN = 1MHz, MAX11115: fIN = 500kHz) Signal-to-Noise and Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range SINAD SNR THD MAX11111/MAX11116 MAX11115 MAX11115 MAX11115 MAX11115 MAX11111/MAX11116 MAX11111/MAX11116 MAX11111/MAX11116 f1 = 1.0003MHz, f2 = 0.99955MHz (MAX11111/MAX11116); f1 = 500.15kHz, f2 = 499.56kHz (MAX11115) -3dB point SINAD > 49dB dB dB -66 -67 dB dB
PR EL
Intermodulation Distortion
IM
SFDR IMD MAX11111 MAX11115 MAX11115 tACQ fCLK MAX11115
IN
Y
Q0.25 Q0.25 Q0.75 Q0.5 3 2 48 32
LSB LSB LSB LSB LSB LSB LSB
dB
Full-Power Bandwidth
MHz MHz MHz dB
Full-Linear Bandwidth Crosstalk
Small-Signal Bandwidth CONVERSION RATE Throughput
MAX11111/MAX11116 MAX11111/MAX11116
Msps ns ns ns ps MHz
Conversion Time Acquisition Time Aperture Delay Aperture Jitter
From CS falling edge MAX11111/MAX11116
Serial-Clock Frequency
_______________________________________________________________________________________
7
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17
ELECTRICAL CHARACTERISTICS (MAX11111/MAX11115/MAX11116) (continued)
(VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps (MAX11111/MAX11116); fSCLK = 32MHz, 50% duty cycle, 2Msps (MAX11115), CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER Input Voltage Range Input Leakage Current Input Capacitance SYMBOL VINA_ IILA CAIN Track Hold CONDITIONS MIN 0 TYP MAX VREF Q1 UNITS V FA pF ANALOG INPUT (AIN1/AIN2 for MAX11111)(AIN for MAX11115/MAX11116)
EXTERNAL REFERENCE INPUT (REF) Reference Input Voltage Range Reference Input Leakage Current Reference Input Capacitance DIGITAL INPUTS (SCLK, CS) Digital Input High Voltage Digital Input Low Voltage Digital Input Hysteresis Digital Input Leakage Current Digital Input Capacitance DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage High-Impedance Output Capacitance POWER SUPPLY Positive Supply Voltage VIH VIL VHYST IIL CIN VREF IILR CREF (Note 2) (Note 2) (Note 2)
AR
4 1 0.005 5 75 15 0.001 2 85 4 2.2 1.5 1.98 1.48 1.3 0.17 4 10 5
Y
2nA 20 VDD + 0.05 Q1 25 Q1 15 Q1.0 3.6 VDD 3.3 2.6 3.55 10
V FA pF %OVDD %OVDD %OVDD FA pF %OVDD %OVDD FA pF
Conversion stopped
Inputs at GND or VDD
High-Impedance Leakage Current
PR EL
COUT VDD
IM
VOH VOL IOL VOVDD MAX11111 IVDD IVDD IPD Leakage only tQ t1 t2
ISOURCE = 200µA (Note 2) ISINK = 200µA (Note 2)
IN
V V
Digital I/O Supply Voltage
fSAMPLE = 3Msps, MAX11111, VIN = GND fSAMPLE = 2Msps, MAX11115, VIN = GND fSAMPLE = 3Msps, MAX11116, VIN = GND MAX11111/MAX11116, VIN = GND MAX11115, VIN = GND VDD = 2.2V to 3.6V, VREF = 2.2V
Positive Supply Current (FullPower Mode)
mA
Positive Supply Current (FullPower Mode), No Clock Power-Down Current Line Rejection
mA FA LSB/V ns ns ns
TIMING CHARACTERISTICS (Note 3) Quiet Time CS Pulse Width CS Fall to SCLK Setup
8
______________________________________________________________________________________
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11111/MAX11115/MAX11116) (continued)
(VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps (MAX11111/MAX11116); fSCLK = 32MHz, 50% duty cycle, 2Msps (MAX11115), CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER CS Falling Until DOUT High Impedance Disabled Data Access Time After SCLK Falling Edge SCLK Pulse Width Low SCLK Pulse Width High Data Hold Time from SCLK Falling Edge SCLK Falling Until DOUT High Impedance Power-Up Time SYMBOL t3 t4 t5 t6 t7 t8 (Note 1) Figure 2 VOVDD = 2.2V - 3.6V VOVDD = 1.5V - 2.2V CONDITIONS MIN 1 TYP MAX UNITS ns ns % % ns 14 1 ns Cycles
MAX11102/03/05/06/10/11/15/16/17
Percentage of clock period Percentage of clock period Figure 3 Figure 4 (Note 1) Conversion cycle
AR
40 40 5 2.5
Note 1: Guaranteed by design and characterization; not production tested. Note 2: VOVDD is tied to VDD internally for all SOT devices. Note 3: All timing specifications given are with a 10pF load capacitor.
PR EL
_______________________________________________________________________________________
IM
9
IN
Y
15 60 60 16.5
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17
SAMPLE SAMPLE
t1 CS t2 SCLK 16 1 2 3 4 5 6 7 8 9 10 11 t6 t5
Y
12 13 14 15 16 D2 D1 D0 0 0 t8 tQUIET tACQ
1
DOUT
HIGH IMPEDANCE t3
0
D11 (MSB)
D10
D9
D8
D7
D6
AR
D5 D4 D3
HIGH IMPEDANCE
t4
t7 tCONVERT
1/fSAMPLE
Figure 1. Interface Signals for Maximum Throughput, 12-Bit Devices
IN
SCLK
t4 SCLK
t7
IM
VIH VIL NEW DATA t8 SCLK DOUT
VIH VIL
PR EL
Figure 2. Setup Time After SCLK Falling Edge Figure 4. SCLK Falling Edge DOUT Three-State 10
DOUT
OLD DATA
DOUT
OLD DATA
NEW DATA
Figure 3. Hold Time After SCLK Falling Edge
HIGH IMPEDANCE
_____________________________________________________________________________________
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17
µMAX Typical Operating Characteristics
(MAX11103AUB+, TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX11102 toc01
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX11102 toc02
OFFSET ERROR vs. TEMPERATURE
Y
2 1 0 -1 -2 -3 TEMPERATURE (˚C) 2048 2049 2050 600 900 1200 1500 fIN (kHz)
MAX11102 toc07 MAX11102 toc05
fS = 3.0Msps
fS = 3.0Msps
0
0
-0.5
-0.5
-1.0 0 1000 2000 3000 4000 DIGITAL OUTPUT CODE
-1.0 0 1000 2000
GAIN ERROR vs. TEMPERATURE
3 2 GAIN ERROR (LSB) 1 0 -1 -2
MAX11102 toc04
IM
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (˚C)
CODE COUNT
PR EL
-3
SNR AND SINAD vs. ANALOG INPUT FREQUENCY
fS = 3Msps
MAX11102 toc06
75 74 73 72 71 70
SNR AND SINAD (dB)
SNR
THD (dB)
SINAD
0
300
600
900
1200
fIN (kHz)
______________________________________________________________________________________
IN
DIGITAL OUTPUT CODE 35,000 30,000 25,000 20,000 15,000 10,000 5000 0 2046 -60 fS = 3Msps -70 -80 -90 -100 -110 -120 0 300 1500
AR
3000 4000 2047 DIGITAL CODE OUTPUT
OFFSET ERROR (LSB)
0.5 INL (LSB)
0.5 DNL (LSB)
-40 -25 -10 5 20 35 50 65 80 95 110 125
HISTOGRAM FOR 30,000 CONVERSIONS
THD vs. ANALOG INPUT FREQUENCY
11
MAX11102 toc03
1.0
1.0
3
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17
µMAX Typical Operating Characteristics (continued)
(MAX11103AUB+, TA = +25°C, unless otherwise noted.)
SFDR vs. ANALOG INPUT FREQUENCY
MAX11102 toc08
THD vs. INPUT RESISTANCE
fS = 3Msps 120 110 SFDR (dB) 100 90 80 70 0 300 600 900 1200
-75 -80 THD (dB) -85 -90 -95
fIN (kHz)
IN
MAX11102 toc10
1500
1MHz SINE-WAVE INPUT (16,834-POINT FFT PLOT)
0 -20 AMPLITUDE (dB) -40 -60 -80 fS = 3.0Msps fIN = 1.0183MHz
AR
-100 0 20 40 60 80 RIN (I)
REFERENCE CURRENT vs. SAMPLING RATE
MAX11102 toc11
200
IM
AHD2 = -110.3dB 750 1000 1250 1500 FREQUENCY (kHz)
MAX11102 toc12
150 IREF (µA)
100
AHD3 = -91.2dB
PR EL
-100 -120 0 250 500
50
0 0 500 1000 1500 fS (ksps) 2000 2500 3000
ANALOG SUPPLY CURRENT vs. TEMPERATURE
SNR vs. REFERENCE VOLTAGE
fS = 3Msps fIN = 1.0183MHz
MAX11102 toc13
3.5 3.2 2.9 2.6
73.5 73.0 72.5 72.0 71.5
VDD = 3.6V
IVDD (mA)
VDD = 3.0V 2.3 VDD = 2.2V 2.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (˚C)
71.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VREF (V)
12
_____________________________________________________________________________________
SNR (dB)
Y
100
fS = 3.0Msps fIN = 1.0183MHz
MAX11102 toc09
130
-70
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs
SOT Typical Operating Characteristics
(MAX11105AUB+, TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX11102 toc14
MAX11102/03/05/06/10/11/15/16/17
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
fS = 2.0Msps 0.5 DNL (LSB)
fS = 2.0Msps 0.5 INL (LSB)
0
-0.5
-1.0 0 1000 2000 3000 4000 DIGITAL OUTPUT CODE
OFFSET ERROR vs. TEMPERATURE
3 2 OFFSET ERROR (LSB) 1 0 -1 -2
MAX11102 toc16
IN
2 1 0 -1 -2 -3 -4 GAIN ERROR (LSB)
MAX11102 toc18
PR EL
-3 TEMPERATURE (˚C) 35,000 30,000 25,000 20,000 15,000 10,000 5000 0 2046 2047 2048 2049 2050 DIGITAL CODE OUTPUT CODE COUNT
-40 -25 -10 5 20 35 50 65 80 95 110 125
IM
HISTOGRAM FOR 30,000 CONVERSIONS
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (˚C)
SNR AND SINAD vs. ANALOG INPUT FREQUENCY
fS = 2.0Msps 73.0 SNR 72.5
MAX11102 toc19
73.5
SNR AND SINAD (dB)
72.0
SINAD
71.5 0 200 400 600 800 1000 fIN (kHz)
______________________________________________________________________________________
MAX11102 toc17
AR
0 -0.5 -1.0 0 1000 2000 3000 4000 DIGITAL OUTPUT CODE
GAIN ERROR vs. TEMPERATURE
Y
MAX11102 toc15
1.0
1.0
13
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17
SOT Typical Operating Characteristics (continued)
(MAX11105AUB+, TA = +25°C, unless otherwise noted.)
THD vs. ANALOG INPUT FREQUENCY
MAX11102 toc20
SFDR vs. ANALOG INPUT FREQUENCY
fS = 2.0Msps 105 100 SFDR (dB) 95 90 85
fS = 2.0Msps -85 -90 THD (dB) -95 -100 -105 -110 0 200 400 600 800
fIN (kHz)
IN
MAX11102 toc22
1000
THD vs. INPUT RESISTANCE
-75 -80 -85 -90 -95 fS = 2.0Msps fIN = 500.122kHz
IM
40 60 80 100 RIN (I)
MAX11102 toc24
-20 AMPLITUDE (dB) -40 -60 -80 -100 -120 0
fS = 2.0Msps fIN = 500.122kHz
THD (dB)
AHD3 = -96.5dB
AHD2 = -92.0dB
PR EL
-100 0 20
250
500 FREQUENCY (kHz)
750
1000
ANALOG SUPPLY CURRENT vs. TEMPERATURE
SNR vs. REFERENCE VOLTAGE (VDD)
fS = 2.0Msps fIN = 500.122kHz 74 SNR (dB)
MAX11102 toc25
2.6 2.4 2.2 2.0 1.8 1.6
75
VDD = 3.6V
IVDD (mA)
VDD = 3.0V
73
VDD = 2.2V
72
71
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (˚C)
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VDD (V)
14
_____________________________________________________________________________________
MAX11102 toc23
AR
80 0 200 400 600 800 fIN (kHz)
500kHz SINE-WAVE INPUT (16,834-POINT FFT PLOT)
0
Y
1000
MAX11102 toc21
-80
110
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs
Pin Configurations
TOP VIEW TOP VIEW
AIN1 AIN2 AGND REF VDD 1 2 3 4 5
MAX11102/03/05/06/10/11/15/16/17
TOP VIEW + MAX11102 MAX11103
EP*
10 9 8 7 6 SCLK DOUT OVDD CHSEL CS VDD 1 + 6 CS
AIN2 AGND REF VDD
2 3 4 5
7
CHSEL CS
EP*
6
TDFN
*CONNECT EXPOSED PAD TO GROUND PLANE. DEVICES DO NOT OPERATE WHEN EP IS NOT CONNECTED TO GROUND!
IN
PIN TDFN 1 2 — — 3 4 µMAX 1 2 — — 3 4 SOT23 — — 3 2
NAME AIN1 AIN2 AIN
PR EL
— —
AGND REF
5
5
1
6 7 8 9
6 7 8 9
6
— — 5 4 —
CHSEL OVDD DOUT SCLK GND
10 EP
10 EP
______________________________________________________________________________________
IM
GND VDD CS
Analog Input Channel 1. Single-ended analog input with respect to AGND with range of 0V to VREF. Analog Input Channel 2. Single-ended analog input with respect to AGND with range of 0V to VREF. Analog Input Channel. Single-ended analog input with respect to GND with range of 0V to VDD. Ground. Connect GND to the GND ground plane. Analog Ground. Connect AGND directly the GND ground plane. External Reference Input. REF defines the signal range of the input signal AIN1/AIN2: 0V to VREF. The range of VREF is 1V to VDD. Bypass REF to AGND with 10FF || 0.1FF capacitor.
Positive Supply Voltage. Bypass VDD with a 10FF || 0.1FF capacitor to GND. VDD range is 2.2V to 3.6V. For the SOT23 package, VDD also defines the signal range of the input signal AIN: 0V to VDD. Active-Low Chip-Select Input. The falling edge of CS samples the analog input signal, starts a conversion, and frames the serial data transfer. Channel Select. Set CHSEL high to select AIN2 for conversion. Set CHSEL low to select AIN1 for conversion. Digital Interface Supply for SCLK, CS, DOUT, and CHSEL. The OVDD range is 1.5V to VDD. Bypass OVDD with a 10FF || 0.1FF capacitor to GND. Three-State Serial Data Output. ADC conversion results are clocked out on the falling edge of SCLK, MSB first. See Figure 1. Serial Clock Input. SCLK drives the conversion process. DOUT is updated on the falling edge of SCLK. See Figures 2 and 3. Exposed Pad. Connect EP directly to a solid ground plane. Devices do not operate when EP is not connected to ground! 15
AR
µMAX
MAX11102 MAX11103 MAX11106 MAX11111
9 8
DOUT OVDD
FUNCTION
Y
GND 2 AIN 3
AIN1
1
+
10
SCLK
MAX11105 MAX11110 MAX11115 MAX11116 MAX11117
5
DOUT
4
SCLK
SOT23
Pin Description
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17
Functional Diagrams
VDD OVDD VDD
CS SCLK
CONTROL LOGIC
MAX11102/MAX11103/ MAX11106/MAX11111
CS SCLK
CONTROL LOGIC
SAR
OUTPUT BUFFER
DOUT
CHSEL AIN1 AIN2 REF
MUX
CDAC
AGND
GND (EP)
IN
OVDD VOVDD
MAX11102 MAX11103 MAX11106 MAX11111
+3V
PR EL
AIN1 AIN2 ANALOG INPUTS AGND REF +2.5V GND (EP) VDD +3V GND (EP) ANALOG INPUT AIN
IM
VDD
MAX11105 MAX11110 MAX11115 MAX11116 MAX11117
SCLK
DOUT CS CHSEL
SCLK DOUT
CS
16
_____________________________________________________________________________________
AR
SAR OUTPUT BUFFER AIN CDAC VREF = VDD GND (EP) SCK CPU MISO SS SCK MISO CPU SS
Typical Operating Circuit
Y
DOUT
MAX11105/MAX11110/ MAX11115/MAX11116/ MAX11117
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs
Detailed Description
The MAX11102/MAX11103/MAX11105/MAX11106/MAX11110/ MAX11111/MAX11115/MAX11116/MAX11117 are fast, 12-/10-/8-bit, low-power, single-supply ADCs. The devices operate from a 2.2V to 3.6V supply and consume only 8.3mW at 3Msps and 6.2mW at 2Msps. The 3Msps devices are capable of sampling at full rate when driven by a 48MHz clock and the 2Msps devices can sample at full rate when driven by a 32MHz clock. The dual-channel devices provide a separate digital supply input (OVDD) to power the digital interface enabling communication with 1.5V, 1.8V, 2.5V, or 3V digital systems. The conversion result appears at DOUT, MSB first, with a leading zero followed by the 12-bit, 10-bit, or 8-bit result. A 12-bit result is followed by two trailing zeros, a 10-bit result is followed by four trailing zeros, and an 8-bit result is followed by six trailing zeros. See Figures 1 and 5. The dual-channel devices feature a dedicated reference input (REF). The input signal range for AIN1/AIN2 is defined as 0V to VREF with respect to AGND. The single-channel devices use VDD as the reference. The input signal range of AIN is defined as 0V to VDD with respect to GND. These ADCs include a power-down feature allowing minimized power consumption at 2.5FA/ksps for lower throughput rates. The wake-up and power-down feature is controlled using the SPI interface as described in the Operating Modes section. The devices feature a 3-wire serial interface that directly connects to SPI, QSPI, and MICROWIRE devices without external logic. Figures 1 and 5 show the interface signals for a single conversion frame to achieve maximum throughput. The falling edge of CS defines the sampling instant. Once CS transitions low, the external clock signal (SCLK) controls the conversion. The SAR core successively extracts binary-weighted bits in every clock cycle. The MSB appears on the data bus during the 2nd clock cycle with a delay outlined in the timing specifications. All extracted data bits appear successively on the data bus with the LSB appearing during the 13th/11th/9th clock cycle for 12-/10-/8-bit operation. The serial data stream of conversion bits is preceded by a leading “zero” and succeeded by trailing “zeros.” The data output (DOUT) goes into high-impedance state during the 16th clock cycle.
MAX11102/03/05/06/10/11/15/16/17
SAMPLE
IM
4 5 6 7 8 D8 D7 D6 D5 D4 4 5 6 7 8 D6 D5 D4 D3 D2
IN
9 10 11 D3 D2 D1 9 10 11 D1 D0 0
AR
12 13 14 D0 0 0 0 12 13 14 0 0 0 0
PR EL
CS
SCLK
16
1
2
3
Y
15 16 0 HIGH IMPEDANCE 15 16 0 HIGH IMPEDANCE
Serial Interface
SAMPLE
1
DOUT
HIGH IMPEDANCE
0
D9
SAMPLE
SAMPLE
CS
SCLK
16
1
2
3
1
DOUT
HIGH IMPEDANCE
0
D7
Figure 5. 10-/8-Bit Timing Diagrams ______________________________________________________________________________________ 17
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17
To sustain the maximum sample rate, all devices have to be resampled immediately after the 16th clock cycle. For lower sample rates, the CS falling edge can be delayed leaving DOUT in a high-impedance condition. Pull CS high after the 10th SCLK falling edge (see the Operating Modes section). The devices produce a digital output that corresponds to the analog input voltage within the specified operating range of 0 to VREF for the dual-channel devices and 0 to VDD for the single-channel devices. The source impedance of the external driving stage in conjunction with the sampling switch resistance affects the settling performance. The THD vs. Input Resistance graph in the Typical Operating Characteristics shows THD sensitivity as a function of the signal source impedance. Keep the source impedance at a minimum for high-dynamic performance applications. Use a highperformance op amp such as the MAX4430 to drive the analog input, thereby decoupling the signal source and the ADC. While the ADC is in conversion mode, the sampling switch is open presenting a pin capacitance, CP (CP = 5pF), to the driving stage. See the Applications Information section for information on choosing an appropriate buffer for the ADC. The ICs offer two modes of operation: normal mode and power-down mode. The logic state of the CS signal during a conversion activates these modes. The powerdown mode can be used to optimize power dissipation with respect to sample rate. Normal Mode In normal mode, the devices are powered up at all times, thereby achieving their maximum throughput rates. Figure 7 shows the timing diagram of these devices in normal mode. The falling edge of CS samples the analog input signal, starts a conversion, and frames the serial data transfer. To remain in normal mode, keep CS low until the falling edge of the 10th SCLK cycle. Pulling CS high after the 10th SCLK falling edge keeps the part in normal mode. However, pulling CS high before the 10th SCLK falling edge terminates the conversion, DOUT goes into highimpedance mode, and the device enters power-down mode. See Figure 8.
Analog Input
PR EL
VDD
SWITCH CLOSED IN TRACK MODE SWITCH OPEN IN CONVERSION MODE
D1
AIN1/AIN2 AIN
CP
D2
Figure 6. Analog Input Circuit
KEEP CS LOW UNTIL AFTER THE 10TH SCLK FALLING EDGE
IM
R CS
4 5 6 7 8
The electric load presented to the external stage driving the analog input varies depending on which mode the ADC is in: track mode vs. conversion mode. In track mode, the internal sampling capacitor CS (16pF) has to be charged through the resistor R (R = 50I) to the input voltage. For faithful sampling of the input, the capacitor voltage on CS has to settle to the required accuracy during the track time.
CS
SCLK
1
2
3
IN
9 10 VALID DATA
Figure 6 shows an equivalent circuit for the analog input AIN (for single-channel devices) and AIN1/AIN2 (for dual-channel devices). Internal protection diodes D1/D2 confine the analog input voltage within the power rails (VDD, GND). The analog input voltage can swing from GND - 0.3V to VDD + 0.3V without damaging the device.
AR
11 12 13 14
PULL CS HIGH AFTER THE 10TH SCLK FALLING EDGE
DOUT
HIGH IMPEDANCE
Figure 7. Normal Mode 18 _____________________________________________________________________________________
Y
15
Operating Modes
16
HIGH IMPEDANCE
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17
PULL CS HIGH AFTER THE 2ND AND BEFORE THE 10TH SCLK FALLING EDGE CS
DOUT
INVALID DATA OR HIGH IMPEDANCE
Figure 8. Entering Power-Down Mode
CS
SCLK DOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
N
AR
HIGH IMPEDANCE
1 2 3 4 5 6 7 8 9 10 11 12
VALID DATA
HIGH IMPEDANCE
INVALID DATA
HIGH IMPEDANCE
INVALID DATA (DUMMY CONVERSION)
IN
HIGH IMPEDANCE
Figure 9. Exiting Power-Down Mode
OUTPUT CODE 111...111 111...110 111...101
PR EL
000...010 000...001 000...000
0
1
2
3
IM
FS - 1.5 x LSB 2n-2 2n-1 2n ANALOG INPUT (LSB) FULL SCALE (FS): AIN1/AIN2 = REF (TDFN, µMax) AIN = VDD (SOT) n = RESOLUTION
conversions is ideal for saving power when sampling the analog input infrequently. Entering Power-Down Mode To enter power-down mode, drive CS high between the 2nd and 10th falling edges of SCLK (see Figure 8). By pulling CS high, the current conversion terminates and DOUT enters high impedance. Exiting Power-Down Mode To exit power-down mode, implement one dummy conversion by driving CS low for at least 10 clock cycles (see Figure 9). The data on DOUT is invalid during this dummy conversion. The first conversion following the dummy cycle contains a valid conversion result. The power-up time equals the duration of the dummy cycle, and is dependent on the clock frequency. The power-up time for 3Msps operation (48MHz SCLK) is 333ns. The power-up time for 2Msps operation (32MHz SCLK) is 500ns. The output format is straight binary. The code transitions midway between successive integer LSB values such as 0.5 LSB, 1.5 LSB, etc. The LSB size for singlechannel devices is VDD/2n and for dual-channel devices is VREF/2n, where n is the resolution. The ideal transfer characteristic is shown in Figure 10.
19
Figure 10. ADC Transfer Function
Power-Down Mode In power-down mode, all bias circuitry is shut down drawing typically only 1.3FA of leakage current. To save power, put the device in power-down mode between conversions. Using the power-down mode between
______________________________________________________________________________________
Y
13 14 15 16
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
HIGH IMPEDANCE
ADC Transfer Function
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17
For applications requiring lower throughput rates, the user can reduce the clock frequency (fSCLK) to lower the sample rate. Figure 11 shows the typical supply current (IVDD) as a function of sample rate (fS) for the 3Msps devices. The part operates in normal mode and is never powered down. Figure 13 pertains to the 2Msps devices.
Supply Current vs. Sampling Rate
4 3 2 1 0 0
VDD = 3V fSCLK = VARIABLE 16 CYCLES/CONVERSION
MAX11102 fig11
5
500
1000
1500 fS (ksps)
2000
2500
3000
IN
1 0 0 2.0 1.5 IVDD (mA) 1.0 0.5 0 0
AR
4 3 VDD = 3V fSCLK = VARIABLE 16 CYCLES/CONVERSION IVDD (mA) 2 500 1000 fS (ksps) 1500 2000
IVDD (mA)
Figure 11. Supply Current vs. Sample Rate (Normal Operating Mode, 3Msps Devices)
3.0 2.5 2.0 1.5 1.0 0.5 0
PR EL
IVDD (mA) 0 1000
VDD = 3V fSCLK = 48MHz
IM
600 800
Figure 13. Supply Current vs. Sample Rate (Normal Operating Mode, 2Msps Devices)
VDD = 3V fSCLK = 32MHz
200
400
100
fS (ksps)
Figure 12. Supply Current vs. Sample Rate (Device Powered Down Between Conversions, 3Msps Devices)
Figure 14. Supply Current vs. Sample Rate (Device Powered Down Between Conversions, 2Msps Devices)
20
_____________________________________________________________________________________
Y
200 300 400 500 fS (ksps)
The user can also power down the ADC between conversions by using the power-down mode. Figure 12 shows for the 3Msps device that as the sample rate is reduced, the device remains in the power-down state longer and the average supply current (IVDD) drops accordingly over time. Figure 14 pertains to the 2Msps devices.
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17
Dual-Channel Operation
The MAX11102/MAX11103/MAX11106/MAX11111 feature dual-input channels. These devices use a channelselect (CHSEL) input to select between analog input AIN1 (CHSEL = 0) or AIN2 (CHSEL = 1). As shown in Figure 15, the CHSEL signal is required to change between the 2nd and 12th clock cycle within a regular conversion to guarantee proper switching between channels. The ICs can operate with 14 cycles per conversion. Figure 16 shows the corresponding timing diagram. Observe that DOUT does not go into high-impedance mode. Also, observe that tACQ needs to be sufficiently long to guarantee proper settling of the analog input voltage. See the Electrical Characteristics table for tACQ requirements and the Analog Input section for a description of the analog inputs.
Applications Information
For best performance, use PCBs with a solid ground plane. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another or digital lines underneath the ADC package. Noise in the VDD power supply, OVDD, and REF affects the ADC’s performance. Bypass the VDD, OVDD, and REF to ground with 0.1FF and 10FF bypass capacitors. Minimize capacitor lead and trace lengths for best supply-noise rejection. It is important to match the settling time of the input amplifier to the acquisition time of the ADC. The conversion results are accurate when the ADC samples the input signal for an interval longer than the input signal’s worst-case settling time. By definition, settling time is the interval between the application of an input voltage step and the point at which the output signal reaches
Layout, Grounding, and Bypassing
CS
SCLK CHSEL DOUT
1
2
3
4
5
6
7
IM
8 9 10 11 12 13 14 15 16
IN
1 2 3 4 5
AR
6 7 8 9 10 11 12
14-Cycle Conversion Mode
Choosing an Input Amplifier
PR EL
DATA CHANNEL AIN2
DATA CHANNEL AIN1
Figure 15. Channel Select Timing Diagram
SAMPLE
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
DOUT
0
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
D3
Y
13 14 15
16
SAMPLE
12
13
14
1
D2
D1
D0 tACQ
0
0
1/fSAMPLE tCONVERT
Figure 16. 14-Clock Cycle Operation ______________________________________________________________________________________ 21
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17
and stays within a given error band centered on the resulting steady-state amplifier output level. The ADC input sampling capacitor charges during the sampling cycle, referred to as the acquisition period. During this acquisition period, the settling time is affected by the input resistance and the input sampling capacitance. This error can be estimated by looking at the settling of an RC time constant using the input capacitance and the source impedance over the acquisition time period. Figure 17 shows a typical application circuit. The MAX4430, offering a settling time of 37ns at 16 bits, is an excellent choice for this application. See the THD vs. Input Resistance graph in the Typical Operating Characteristics.
+5V
0.1µF
10µF
IN
3V VDD
0.1µF 10µF
100pF COG
500I
IM
5 1
10I -5V
AIN1
500I
3
MAX4430
VDC
4
2
470pF COG CAPACITOR
PR EL
0.1µF 10µF +5V 0.1µF 10µF
470pF COG CAPACITOR
10µF
100pF COG
500I
0.1µF
AIN2
500I
3
5
1
10I
MAX4430
VDC
4 2
0.1µF 10µF
-5V
Figure 17. Typical Application Circuit 22 _____________________________________________________________________________________
AR
VOVDD OVDD
0.1µF
For devices using an external reference, the choice of the reference determines the output accuracy of the ADC. An ideal voltage reference provides a perfect initial accuracy and maintains the reference voltage independent of changes in load current, temperature, and time. Considerations in selecting a reference include initial voltage accuracy, temperature drift, current source, sink capability, quiescent current, and noise. Figure 17 shows a typical application circuit using the MAX6126 to provide the reference voltage. The MAX6033 and MAX6043 are also excellent choices.
Choosing a Reference
AGND AIN1
MAX11102 MAX11103 MAX11106 MAX11111
AIN2
REF EP
7 8
OUTF OUTS
MAX6126
IN
4 3
GNDS GND
NR
Y
10µF
SCLK DOUT CS CHSEL
SCK MISO SS CPU
+3V 2
1µF 0.1µF
1
0.1µF
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs
Definitions
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. For these devices, the straight line is a line drawn between the end points of the transfer function after offset and gain errors are nulled.
Integral Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of ±1 LSB or less guarantees no missing codes and a monotonic transfer function. The deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, AGND + 0.5 LSB. The deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal after adjusting for the offset error, that is, VREF - 1.5 LSB.
Offset Error
Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: 2 2 2 V 2 + V3 + V4 + V5 THD = 20 × log 2 V1
Gain Error
Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples.
IM
Aperture Jitter
PR EL
Aperture delay (tAD) is the time between the falling edge of sampling clock and the instant when an actual sample is taken.
Aperture Delay
SNR is a dynamic figure of merit that indicates the converter’s noise performance. For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR (dB) (MAX) = (6.02 x N + 1.76) (dB) In reality, there are other noise sources such as thermal noise, reference noise, and clock jitter that also degrade SNR. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Ratio (SNR)
IN
where V1 is the fundamental amplitude and V2–V5 are the amplitudes of the 2nd- through 5th-order harmonics. SFDR is a dynamic figure of merit that indicates the lowest usable input signal amplitude. SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. SFDR is specified in decibels with respect to the carrier (dBc). Full-power bandwidth is the frequency at which the input signal amplitude attenuates by 3dB for a full-scale input. Full-linear bandwidth is the frequency at which the signal-to-noise ratio and distortion (SINAD) is equal to a specified value. Any device with nonlinearities creates distortion products when two sine waves at two different frequencies (f1 and f2) are applied into the device. Intermodulation distortion (IMD) is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones, f1 and f2. The individual input tone levels are at -6dBFS.
______________________________________________________________________________________
AR
Differential Nonlinearity
.
SIGNAL RMS SINAD(dB) = 20 × log (NOISE + DISTORTION) RMS
Spurious-Free Dynamic Range (SFDR)
Y
SINAD is a dynamic figure of merit that indicates the converter’s noise and distortion performance. SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset:
Signal-to-Noise Ratio and Distortion (SINAD)
MAX11102/03/05/06/10/11/15/16/17
Total Harmonic Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
Intermodulation Distortion
23
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11102/03/05/06/10/11/15/16/17
Ordering Information (continued)
PART MAX11103ATB+** MAX11105AUT+ MAX11106ATB+** MAX11110AUT+ MAX11111ATB+** MAX11115AUT+ MAX11116AUT+ MAX11117AUT+ PIN-PACKAGE 10 TDFN-EP* 6 SOT23 10 TDFN-EP* 6 SOT23 10 TDFN-EP* 6 SOT23 6 SOT23 6 SOT23 BITS 12 12 10 10 8 8 8 10 SPEED (Msps) 3 2 3 2 3 2 3 3 NO. OF CHANNELS 2 1
AR
PACKAGE TYPE 10 TDFN-EP 10 FMAX 6 SOT23 PACKAGE CODE T1033+2 U10+2 U6+1
Note: All devices are specified over the -40°C to +125°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. **Future product—contact factory for availability.
PROCESS: CMOS
IM
Chip Information
IN
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
DOCUMENT NO. 21-0137 21-0061 21-0058
PR EL
24
_____________________________________________________________________________________
Y
1 2 1 1 1
2
Package Information
2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs
Revision History
REVISION NUMBER 0 REVISION DATE 4/10 Initial release DESCRIPTION PAGES CHANGED —
MAX11102/03/05/06/10/11/15/16/17
PR EL
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©
IM
25 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
IN
AR
Y
工商网监
湘ICP备2023018690号
