MAX1123EGK

19-3028; Rev 1; 2/04 1.8V, 10-Bit, 210Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications General Description The MAX1123 is a monolithic 10-bit, 210Msps analogto-digital converter (ADC) optimized for outstanding dynamic performance at high IF frequencies up to 500MHz. The product operates with conversion rates of up to 210Msps while consuming only 460mW. At 210Msps and an input frequency of 100MHz, the MAX1123 achieves a spurious-free dynamic range (SFDR) of 74.5dBc. Its excellent signal-to-noise ratio (SNR) of 57.4dB at 10MHz remains flat (within 1.5dB) for input tones up to 500MHz. This makes the MAX1123 ideal for wideband applications such as digital predistortion in cellular base-station transceiver systems. The MAX1123 requires a single 1.8V supply. The analog input is designed for either differential or singleended operation and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2 clock circuit, which allows the user to apply clock frequencies as high as 420MHz. This helps to reduce the phase noise of the input clock source. A differential LVDS sampling clock is recommended for best performance. The converter’s digital outputs are LVDS compatible, and the data format can be selected to be either two’s complement or offset binary. The MAX1123 is available in a 68-pin QFN with exposed paddle (EP) and is specified over the industrial (-40°C to +85°C) temperature range. For pin-compatible, lower and higher speed versions of the MAX1123, refer to the MAX1122 (170Msps) and the MAX1124 (250Msps) data sheets. For a higher speed, pin-compatible 8-bit version of the MAX1123, refer to the MAX1121 data sheet. ♦ 210Msps Conversion Rate ♦ SNR = 57.4dB/56dB at fIN = 100MHz/500MHz ♦ SFDR = 74.5dBc/62.6dBc at fIN = 100MHz/500MHz ♦ NPR = 53.6dB at fNOTCH = 28.8MHz ♦ Single 1.8V Supply ♦ 460mW Power Dissipation at 210Msps ♦ On-Chip Track-and-Hold and Internal Reference ♦ On-Chip Selectable Divide-by-2 Clock Input ♦ LVDS Digital Outputs with Data Clock Output ♦ Evaluation Kit Available (Order MAX1124EVKIT) Features MAX1123 Ordering Information PART MAX1123EGK TEMP RANGE -40°C to +85°C PIN-PACKAGE 68 QFN-EP* *EP = Exposed paddle. Pin Configuration TOP VIEW OGND AGND AGND AGND AVCC OVCC AVCC AVCC ORN ORP D9N D8N D7N 51 D6P 50 D6N 49 D5P 48 D5N 47 D4P 46 D4N 45 OGND 44 OVCC 43 DCLKP 42 DCLKN 41 OVCC 40 D3P 39 D3N 38 D2P 37 D2N 36 D1P 35 D1N D9P D8P N.C. 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 Applications Wireless and Wired Broadband Communication Cable-Head End Systems Digital Predistortion Receivers Communications Test Equipment Radar and Satellite Subsystems Antenna Array Processing AVCC AGND REFIO REFADJ AGND AVCC AGND INP INN 1 2 3 4 5 6 7 8 9 EP AGND 10 AVCC 11 AVCC 12 AVCC 13 AVCC 14 AGND 15 AGND 16 CLKDIV 17 MAX1123 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 AGND AVCC N.C. CLKP CLKN OGND AGND AGND AGND N.C. N.C. D0N D7P T/B AVCC OVCC ________________________________________________________________ Maxim Integrated Products OVCC D0P 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1.8V, 10-Bit, 210Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications MAX1123 ABSOLUTE MAXIMUM RATINGS AVCC to AGND ......................................................-0.3V to +2.1V OVCC to OGND .....................................................-0.3V to +2.1V AGND to OGND ....................................................-0.3V to +0.3V Analog Inputs to AGND ...........................-0.3V to (AVCC + 0.3V) Digital Inputs to AGND.............................-0.3V to (AVCC + 0.3V) REF, REFADJ to AGND............................-0.3V to (AVCC + 0.3V) Digital Outputs to OGND .........................-0.3V to (OVCC + 0.3V) ESD on All Pins (Human Body Model).............................±2000V Continuous Power Dissipation (TA = +70°C) 68-Pin QFN (derate 41.7mW/°C above +70°C) .........3333mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Maximum Current into Any Pin............................................50mA Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω ±1%, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. ≥25°C guaranteed by production test, 20MHz to work appropriately and according to data sheet specifications. Clock Outputs (DCLKP, DCLKN) The MAX1123 features a differential clock output, which can be used to latch the digital output data with an external latch or receiver. Additionally, the clock output can be used to synchronize external devices (e.g., FPGAs) to the ADC. DCLKP and DCLKN are differential outputs with LVDS-compatible voltage levels. There is a 2.1ns delay time between the rising (falling) edge of CLKP (CLKN) and the rising edge of DCLKP (DCLKN). See Figure 4 for timing details. Divide-by-2 Clock Control (CLKDIV) The MAX1123 offers a clock control line (CLKDIV), which supports the reduction of clock jitter in a system. Connect CLKDIV to OGND to enable the ADC’s internal divide-by-2 clock divider. Data is now updated at onehalf the ADC’s input clock rate. CLKDIV has an internal pulldown resistor and can be left open for applications that only operate with update rates one-half of the converter’s sampling rate. Connecting CLKDIV to OVCC allows data to be updated at the speed of the ADC input clock. System Timing Requirements Figure 4 depicts the relationship between the clock input and output, analog input, sampling event, and data output. The MAX1123 samples on the rising (falling) edge of CLKP (CLKN). Output data is valid on the next rising (falling) edge of the DCLKP (DCLKN) clock, but has an internal latency of eight clock cycles. 12 ______________________________________________________________________________________ 1.8V, 10-Bit, 210Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications Digital Outputs (D0P/N–D9P/N, DCLKP/N, ORP/N) and Control Input T/B The digital outputs D0P/N–D9P/N, DCLKP/N, and ORP/N are LVDS compatible, and data on D0P/N–D9P/N is presented in either binary or two’s complement format (Table 1). The T/B control line is an LVCMOS-compatible input, which allows the user to select the desired output format. Pulling T/B low outputs data in two’s complement and pulling it high presents data in offset binary format on the 10-bit parallel bus. T/B has an internal pulldown resistor and may be left unconnected in applications using only two’s complement output format. All LVDS outputs provide a typical voltage swing of 0.4V around a common-mode voltage of approximately 1.2V, and must be terminated at the far end of each transmission line pair (true and complementary) with 100Ω. The LVDS outputs are powered from a separate power supply, which can be operated between 1.7V and 1.9V. The MAX1123 offers an additional differential output pair (ORP, ORN) to flag out-of-range conditions, where out of range is above positive or below negative full scale. An out-of-range condition is identified with ORP (ORN) transitioning high (low). Note: Although differential LVDS reduces single-ended transients to the supply and ground planes, capacitive loading on the digital outputs should still be kept as low as possible. Using LVDS buffers on the digital outputs of the ADC when driving off-board may improve overall performance and reduce system timing constraints. VCLK 0.1µF MAX1123 ADC FULL-SCALE = REFT - REFB REFT REFB REFERENCE BUFFER G REFERENCESCALING AMPLIFIER REFIO 0.1µF 1V REFADJ CONTROL LINE TO DISABLE REFERENCE BUFFER 13kΩ TO 1MΩ 13kΩ TO 1MΩ AVCC AVCC / 2 Figure 6. Circuit Suggestions to Adjust the ADC’s Full-Scale Range Applications Information Full-Scale Range Adjustments Using the Internal Bandgap Reference The MAX1123 supports a full-scale adjustment range of 10% (±5%). To decrease the full-scale range, an external resistor value ranging from 13kΩ to 1MΩ may be added between REFADJ and AGND. A similar approach can be taken to increase the ADCs full-scale range. Adding a variable resistor, potentiometer, or 8 SINGLE-ENDED INPUT TERMINAL 0.1µF 7 2 MC100LVEL16 50Ω 3 150Ω 0.1µF 6 CLKN CLKP D0P/N–D9P/N AVCC OVCC 0.1µF 510Ω 510Ω 4 0.01µF 5 150Ω INP MAX1123 INN 10 VGND AGND OGND Figure 7. Differential, AC-Coupled, PECL-Compatible Clock Input Configuration ______________________________________________________________________________________ 13 1.8V, 10-Bit, 210Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications MAX1123 AVCC SINGLE-ENDED INPUT TERMINAL 0.1µF 15Ω 25Ω OVCC ADT1–1WT INP D0P/N–D9P/N 25Ω 15Ω MAX1123 INN 10 0.1µF AGND OGND Figure 8. Transformer-Coupled Analog Input Configuration with Secondary-Side Termination predetermined resistor value between REFADJ and REFIO increases the full-scale range of the data converter. Figure 6 shows the two possible configurations and their impact on the overall full-scale range adjustment of the MAX1123. Do not use resistor values of less than 13kΩ to avoid instability of the internal gain regulation loop for the bandgap reference. AVCC SINGLE-ENDED INPUT TERMINAL OVCC 0.1µF INP D0P/N–D9P/N 50Ω 0.1µF Differential, AC-Coupled, PECL-Compatible Clock Input The preferred method of clocking the MAX1123 is differentially with LVDS- or PECL-compatible input levels. To accomplish this, a 50Ω reverse-terminated clock signal source with low phase noise is AC-coupled into a fast differential receiver such as the MC100LVEL16 (Figure 7). The receiver produces the necessary PECL output levels to drive the clock inputs of the data converter. MAX1123 INN 10 25Ω AGND OGND Figure 9. Single-Ended AC-Coupled Analog Input Configuration Single-Ended, AC-Coupled Analog Input Although not recommended, the MAX1123 can be used in single-ended mode (Figure 9). Analog signals can be AC-coupled to the positive input INP through a 0.1µF capacitor and terminated with a 50Ω resistor to AGND. The negative input should be 25Ω reverse-terminated and AC grounded with a 0.1µF capacitor. Differential, AC-Coupled Analog Input An RF transformer provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1123 for optimum dynamic performance. In general, the MAX1123 provides the best SFDR and THD with fully differential input signals and it is not recommended to drive the ADC inputs in single-ended configuration. In differential input mode, even-order harmonics are usually lower since INP and INN are balanced, and each of the ADC inputs only requires half the signal swing compared to a single-ended configuration. Figure 8 depicts a secondary-side termination of the 1:1 transformer into two separate 25Ω loads. Terminating the transformer in this fashion reduces the potential effects of transformer parasitics. The source impedance combined with the shunt capacitance provided by a PC board and the ADC’s parasitic capacitance reduce the combined bandwidth to approximately 550MHz. 14 Grounding, Bypassing, and Board Layout Considerations The MAX1123 requires board layout design techniques suitable for high-speed data converters. This ADC provides separate analog and digital power supplies. The analog and digital supply voltage pins accept input voltage ranges of 1.7V to 1.9V. Although both supply types can be combined and supplied from one source, it is recommended to use separate sources to cut down on performance degradation caused by digital switching currents, which can couple into the analog supply network. Isolate analog and digital supplies (AVCC and ______________________________________________________________________________________ 1.8V, 10-Bit, 210Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications MAX1123 BYPASSING—ADC LEVEL AVCC OVCC BYPASSING—BOARD LEVEL AVCC 0.1µF 0.1µF 1µF 10µF 47µF ANALOG POWERSUPPLY SOURCE AGND OGND D0P/N–D9P/N OVCC MAX1123 10 1µF AGND OGND 10µF 47µF DIGITAL/OUTPUTDRIVER POWERSUPPLY SOURCE NOTE: EACH POWER-SUPPLY PIN (ANALOG AND DIGITAL) SHOULD BE DECOUPLED WITH AN INDIVIDUAL 0.1µF CAPACITOR CLOSE TO THE ADC. Figure 10. Grounding, Bypassing, and Decoupling Recommendations for the MAX1123 OVCC) where they enter the PC board with separate networks of ferrite beads and capacitors to their corresponding grounds (AGND, OGND). To achieve optimum performance, provide each supply with a separate network of a 47µF tantalum capacitor in parallel with 10µF and 1µF ceramic capacitors. Additionally, the ADC requires each supply pin to be bypassed with separate 0.1µF ceramic capacitors (Figure 10). Locate these capacitors directly at the ADC supply pins or as close as possible to the MAX1123. Choose surface-mount capacitors, which are preferably located on the same side as the converter, to save space and minimize the inductance. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arranged to match the physical location of analog and digital ground on the ADC’s package. The two ground planes should be joined at a single point so the noisy digital ground currents do not interfere with the analog ground plane. A major concern with this approach are the dynamic currents that may need to travel long distances before they are recombined at a common source ground, resulting in large and undesirable ground loops. Ground loops can add to digital noise by coupling back to the analog front end of the converter, resulting in increased spur activity and a decreased noise performance. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground. To minimize the effects of digital noise coupling, ground return vias can be positioned throughout the layout to divert digital switching currents away from the sensitive analog sections of the ADC. This does not require additional ground splitting, but can be accomplished by placing substantial ground connections between the analog front end and the digital outputs. The MAX1123 is packaged in a 68-pin QFN-EP package (package code: G6800-4), providing greater design flexibility, increased thermal efficiency, and optimized AC performance of the ADC. The EP must be soldered down to AGND. In this package, the data converter die is attached to an EP lead frame with the back of this frame exposed at the package bottom surface, facing the PC board side of the package. This allows a solid attachment of the package to the PC board with standard infrared (IR) flow soldering techniques. Note that thermal efficiency is not the key factor, since the MAX1123 features low-power operation. The exposed pad is the key element to ensure a solid ground connection between the DAC and the PC board’s analog ground layer. Considerable care must be taken, when routing the digital output traces for a high-speed, high-resolution data converter. It is essential to keep trace lengths at a minimum and place minimal capacitive loading—less than 5pF—on any digital trace to prevent coupling to sensitive analog sections of the ADC. It is recommended to run the LVDS output traces as differential lines with 100Ω characteristic impedance from the ADC to the LVDS load device. 15 ______________________________________________________________________________________ 1.8V, 10-Bit, 210Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications MAX1123 Static Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. However, the static linearity parameters for the MAX1123 are measured using the histogram method with an input frequency of 10MHz. CLKP CLKN ANALOG INPUT tAD tAJ SAMPLED DATA (T/H) Differential Nonlinearly (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. The MAX1123’s DNL specification is measured with the histogram method based on a 10MHz input tone. T/H TRACK HOLD TRACK Figure 11. Aperture Jitter/Delay Specifications Dynamic Parameter Definitions Aperture Jitter Figure 11 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value of the next-largest noise or harmonic distortion component. SFDR is usually measured in dBc with respect to the carrier frequency amplitude or in dBFS with respect to the ADC’s full-scale range. Aperture Delay Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 11). Two-Tone Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -7dB full scale. Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNRdB[max] = 6.02dB x N + 1.76dB In reality, other noise sources such as thermal noise, clock jitter, signal phase noise, and transfer function nonlinearities are also contributing to the SNR calculation and should be considered when determining the SNR in ADC. Pin-Compatible Higher Speed/ Lower Resolution Versions PART MAX1122 MAX1124 MAX1121 RESOLUTION (Bits) 10 10 8 SPEED GRADE (Msps) 170 250 250 Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to all spectral components excluding the fundamental and the DC offset. In case of the MAX1123, SINAD is computed from a curve fit. 16 ______________________________________________________________________________________ 1.8V, 10-Bit, 210Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 68L QFN.EPS MAX1123 PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.