MAX1134BCAP

19-2464; Rev 0; 4/02 16-Bit ADCs, 150ksps, 3.3V Single Supply General Description The MAX1134/MAX1135 are 150ksps, 16-bit ADCs. These serially interfaced ADCs connect directly to SPI™, QSPI™, and MICROWIRE™ devices without external logic. They combine an input scaling network, internal track/hold (T/H), clock, and three general-purpose digital output pins (for external multiplexer or PGA control) in a 20-pin SSOP package. The excellent dynamic performance (THD ≥ 90dB), high speed (150ksps in bipolar mode), and low power (8.0mA) of these ADCs make them ideal for applications such as industrial process control, instrumentation, and medical applications. The MAX1134 accepts input signals of 0 to +6V (unipolar) or ±6V (bipolar), while the MAX1135 accepts input signals of 0 to +2.048V (unipolar) or ±2.048V (bipolar). Operating from a single 3.135V to 3.465V analog and digital supply, power-down modes reduce current consumption to 0.15mA at 10ksps and further reduce supply current to less than 20µA at slower data rates. A serial strobe output (SSTRB) allows direct connection to the TMS320 family digital-signal processors. The MAX1134/MAX1135 user can select either the internal clock or an external serial-interface clock for the ADC to perform analog-to-digital conversions. The MAX1134/MAX1135 feature internal calibration circuitry to correct linearity and offset errors. On-demand calibration allows the user to optimize performance. Three user-programmable logic outputs are provided for the control of an 8-channel mux or PGA. The MAX1134/MAX1135 are available in a 20-pin SSOP package and are fully specified over the -40°C to +85°C temperature range. Features o 150ksps (Bipolar) and 125ksps (Unipolar) Sampling ADC o 16 Bits, No Missing Codes o 1LSB INL (typ) Guaranteed o -100dB THD o 3.3V Single-Supply Operation o Low-Power Operation 4.5mA (typ) (Unipolar Mode) o 1.2µA Shutdown Mode o Software-Configurable Unipolar and Bipolar Input Ranges 0 to +6V and ±6V (MAX1134) 0 to +2.048V and ±2.048V (MAX1135) o Internal or External Clock o SPI/QSPI/MICROWIRE TMS320-Compatible Serial Interface o Three User-Programmable Logic Outputs o Small 20-Pin SSOP Package MAX1134/MAX1135 Ordering Information PART MAX1134BCAP MAX1134BEAP TEMP RANGE 0°C to +70°C -40°C to +85°C PINPACKAGE 20 SSOP 20 SSOP INL (LSB) ±2.5 ±2.5 Ordering Information continued at end of data sheet. Applications Industrial Process Control Industrial I/O Modules Data-Acquisition Systems Medical Instruments Portable and Battery-Powered Equipment TOP VIEW REF 1 AVDD 2 AGND 3 AVDD 4 DGND 5 Pin Configuration 20 AIN 19 AGND 18 CREF 17 CS Functional Diagram and Typical Application Circuit appear at end of data sheet. SHDN 6 P2 7 P1 8 PO 9 MAX1134 MAX1135 16 DIN 15 DVDD 14 DGND 13 SCLK 12 RST 11 DOUT SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor, Corp. SSTRB 10 SSOP ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 16-Bit ADCs, 150ksps, 3.3V Single Supply MAX1134/MAX1135 ABSOLUTE MAXIMUM RATINGS AVDD to AGND, DVDD to DGND ..............................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V AIN to AGND ....................................................................±16.5V CREF, REF to AGND ................................-0.3V to (AVDD + 0.3V) Digital Inputs to DGND.............................................-0.3V to +6V Digital Outputs to DGND .........................-0.3V to (DVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 20-Pin SSOP (derate 8.00mW/°C above +70°C) .........640mW Operating Temperature Ranges MAX113_ _CAP...................................................0°C to +70°C MAX113_ _EAP ................................................-40°C to +85°C Storage Temperature Range .............................-60°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = DVDD = 3.3V ±5%, fSCLK = 3.6MHz, external clock (50% duty cycle), 24 clocks/conversion (150ksps), bipolar input, VREF = 2.048V, CREF = 4.7µF, CCREF = 1µF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy No Missing Codes Differential Nonlinearity Transition Noise Offset Error Gain Error (Note 3) Offset Drift (Bipolar and Unipolar) Gain Drift (Bipolar and Unipolar) Unipolar Bipolar Unipolar Bipolar Excluding reference drift Excluding reference drift ±1 ±4 DNL Bipolar mode MAX113_B INL Bipolar mode (Note 2) MAX113_B 16 -1 1.5 ±4 ±6 ±0.2 ±0.3 +1.75 16 1.0 ±2.5 Bits LSB Bits LSB LSBRMS mV %FSR ppm/°C ppm/°C SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC SPECIFICATIONS (5kHz SINE-WAVE INPUT, 150ksps, 3.6MHz CLOCK, BIPOLAR INPUT MODE. MAX1134, 12VP-P. MAX1135, 4.096VP-P.) Signal-to-Noise Plus Distortion (SINAD) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) ANALOG INPUT MAX1134 Input Range MAX1135 Unipolar Bipolar Unipolar Bipolar 0 -6 0 -2.048 +6 +6 +2.048 +2.048 V fIN = 5kHz fIN = 75kHz fIN = 5kHz fIN = 75kHz fIN = 5kHz fIN = 75kHz fIN = 5kHz fIN = 75kHz 92 80 80 84 83 84 83 -100 -93 105 97 -90 dB dB dB dB 2 _______________________________________________________________________________________ 16-Bit ADCs, 150ksps, 3.3V Single Supply ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 3.3V ±5%, fSCLK = 3.6MHz, external clock (50% duty cycle), 24 clocks/conversion (150ksps), bipolar input, VREF = 2.048V, CREF = 4.7µF, CCREF = 1µF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL MAX1134 Input Impedance MAX1135 Input Capacitance CONVERSION RATE Internal Clock Frequency Aperture Delay Aperture Jitter tAD tAJ Unipolar Bipolar Unipolar Bipolar 0.1 0.1 4.17 4.17 8 6.7 3 10 50 3.0 3.6 125 150 240 µs 240 MHz ns ps CONDITIONS Unipolar Bipolar Unipolar Bipolar MIN 7.5 5.9 100 3.4 TYP 10.5 8.4 1000 5.3 32 pF kΩ MAX UNITS MAX1134/MAX1135 MODE 1 (24 EXTERNAL CLOCK CYCLES PER CONVERSION) External Clock Frequency Sample Rate fSCLK fS = fSCLK / 24 MHz ksps Conversion Time (Note 4) tCONV+ACQ Unipolar = 24 / Bipolar fSCLK MODE 2 (INTERNAL CLOCK MODE) External Clock Frequency (Data Transfer Only) Conversion Time Acquisition Time (Note 5) (SSTRB low pulse width) Unipolar Bipolar fSCLK fS = fSCLK / 32 Unipolar or bipolar Unipolar or bipolar 1.67 1.39 0.1 3.125 3.6 112 5.3 4 7 MHz µs µs MODE 3 (32 EXTERNAL CLOCK CYCLES PER CONVERSION) External Clock Frequency Sample Rate MHz ksps Conversion Time (Note 4) EXTERNAL REFERENCE Input Range Input Current DIGITAL INPUTS Input High Voltage Input Low Voltage Input Leakage tCONV+ACQ = 32 / Unipolar or bipolar fSCLK (Notes 6, 7) VREF = 2.048V, fSCLK = 3.6MHz VREF = 2.048V, fSCLK = 0 In power-down, fSCLK = 0 VIH VIL IIN VIN = 0 or DVDD 8.89 320 µs 1.9 2.048 110 100 0.1 2.2 V µA 2.4 0.8 -1 +1 V V µA _______________________________________________________________________________________ 3 16-Bit ADCs, 150ksps, 3.3V Single Supply MAX1134/MAX1135 ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 3.3V ±5%, fSCLK = 3.6MHz, external clock (50% duty cycle), 24 clocks/conversion (150ksps), bipolar input, VREF = 2.048V, CREF = 4.7µF, CCREF = 1µF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Input Hysteresis Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER SUPPLIES Analog Supply Digital Supply Analog Supply Current AVDD DVDD Unipolar mode IANALOG Bipolar mode SHDN = 0, or software power-down mode Digital Supply Current Power-Supply Rejection Ratio (Note 8) IDIGITAL PSRR Unipolar or bipolar mode SHDN = 0, or software power-down mode AVDD = DVDD = 3.135V to 3.465V 3.135 3.135 3.3 3.3 3.9 7 0.1 1 1.1 65 3.465 3.465 8 11 10 2 10 V V mA µA mA µA dB VOH VOL IL ISOURCE = 0.5mA ISINK = 5mA ISINK = 16mA CS = DVDD CS = DVDD -10 10 DVDD 0.5 0.4 0.8 +10 V V µA pF SYMBOL VHYST CIN CONDITIONS MIN TYP 0.2 10 MAX UNITS V pF TIMING CHARACTERISTICS (Figures 5 and 6) (AVDD = DVDD = 3.3V ±5%, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER DIN to SCLK Setup DIN to SCLK Hold SCLK to DOUT Valid CS Fall to DOUT Enable CS Rise to DOUT Disable CS to SCLK Rise Setup CS to SCLK Rise Hold SCLK High Pulse Width SCLK Low Pulse Width SCLK Fall to SSTRB CS Fall to SSTRB Enable CS Rise to SSTRB Disable SSTRB Rise to SCLK Rise RST Pulse Width SYMBOL tDS tDH tDO tDV tTR tCSS tCSH tCH tCL tSSTRB tSDV tSTR tSCK tRS CLOAD = 50pF CLOAD = 50pF, external clock mode CLOAD = 50pF, external clock mode Internal clock mode 0 278 70 CLOAD = 50pF CLOAD = 50pF 100 0 120 120 80 80 80 CONDITIONS MIN 50 0 70 80 80 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 _______________________________________________________________________________________ 16-Bit ADCs, 150ksps, 3.3V Single Supply TIMING CHARACTERISTICS (Figures 5 and 6) (continued) (AVDD = DVDD = 3.3V ±5%, TA = TMIN to TMAX, unless otherwise noted.) Note 1: Tested at AVDD = DVDD = 3.3V, bipolar input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset error have been nullified. Note 3: Offset nullified. Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Includes the acquisition time. Note 5: Acquisition time is 5 clock cycles in short acquisition mode and 13 clock cycles in long acquisition mode. Note 6: Performance is limited by the converter’s noise floor, typically 300µVP-P. Note 7: When an external reference has a different voltage than the specified typical value, the full scale of the ADC scales proportionally. Note 8: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage. MAX1134/MAX1135 Typical Operating Characteristics (MAX1134/MAX1135, AVDD = DVDD = 3.3V, fSCLK = 3.6MHz, external clock (50% duty cycle), 24 clocks/conversion (150ksps), bipolar input, REF = 2.048V, 4.7µF on REF, 1µF on CREF, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE MAX1134/35 toc01 DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE MX1134/35 toc02 TOTAL SUPPLY CURRENT vs. TEMPERATURE 8.9 TOTAL SUPPLY CURRENT (mA) 8.8 8.7 8.6 8.5 8.4 8.3 8.2 8.1 8.0 A C B A: AVDD, DVDD = 3.135V B: AVDD, DVDD = 3.3V C: AVDD, DVDD = 3.465V MAX1134/35 toc03 3 INTEGRAL NONLINEARITY (LSB) 2 1 0 -1 -2 -3 1 13273 26545 39817 53089 59725 DIGITAL OUTPUT CODE 1.0 DIFFERENTIAL NONLINEARITY (LSB) 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 1 13649 27297 40945 54593 61417 DIGITAL OUTPUT CODE 9.0 -40 -20 0 20 40 60 80 TEMPERATURE (°C) _______________________________________________________________________________________ 5 16-Bit ADCs, 150ksps, 3.3V Single Supply MAX1134/MAX1135 Typical Operating Characteristics (continued) (MAX1134/MAX1135, AVDD = DVDD = 3.3V, fSCLK = 3.6MHz, external clock (50% duty cycle), 24 clocks/conversion (150ksps), bipolar input, REF = 2.048V, 4.7µF on REF, 1µF on CREF, TA = +25°C, unless otherwise noted.) OFFSET VOLTAGE vs. TEMPERATURE MAX1134/35 toc04 GAIN ERROR vs. TEMPERATURE MAX1134/35 toc05 TOTAL SUPPLY CURRENT vs. CONVERSION RATE (USING SHUTDOWN) MAX1134/35 toc06 -0.5 GAIN ERROR (% FULL SCALE) -1.0 OFFSET ERROR (mV) B TOTAL SUPPLY CURRENT (mA) A: AVDD, DVDD = 3.135V B: AVDD, DVDD = 3.3V C: AVDD, DVDD = 3.465V 0.06 0.05 0.04 C 0.03 0.02 0.01 A A: AVDD, DVDD = 3.135V B: AVDD, DVDD = 3.3V C: AVDD, DVDD = 3.465V -40 -20 0 20 40 60 80 100 10 -1.5 C A 1 -2.0 -2.5 B -3.0 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 0.1 0 TEMPERATURE (°C) 0.01 0 1 10 100 1000 CONVERSION RATE (ksps) FFT PLOT MAX1134/35 toc07 SINAD PLOT 90 80 AMPLITUDE (dB) 70 60 50 40 30 20 10 fSAMPLE = 150kHz MAX1134/35 toc08 0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 0 10 20 30 40 50 60 fSAMPLE = 150kHz fIN = 5kHz 100 0 70 0.1 1 10 100 FREQUENCY (kHz) FREQUENCY (kHz) SFDR PLOT MAX1134/35 toc09 THD PLOT -10 -20 -30 AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 -110 fSAMPLE = 150kHz MAX1134/35 toc10 120 110 100 90 AMPLITUDE (dB) 80 70 60 50 40 30 20 10 0 0.1 1 0 fSAMPLE = 150kHz 10 100 0.1 1 10 100 FREQUENCY (kHz) FREQUENCY (kHz) 6 _______________________________________________________________________________________ 16-Bit ADCs, 150ksps, 3.3V Single Supply Pin Description PIN 1 2 3 4 5 6 7 8 9 10 NAME REF AVDD AGND AVDD DGND SHDN P2 P1 P0 SSTRB FUNCTION ADC Reference Input. Connect a 2.048V voltage source to REF. Bypass REF to AGND with a 4.7µF capacitor. Analog Supply. Connect to pin 4. Analog Ground. This is the primary analog ground (star ground). Analog Supply, 3.3V ±5%. Bypass AVDD to AGND (pin 3) with a 0.1µF capacitor. Digital Ground Shutdown Control Input. Drive SHDN low to put the ADC in shutdown mode. User-Programmable Output 2 User-Programmable Output 1 User-Programmable Output 0 Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC begins a conversion and goes high when the conversion is finished. In external clock mode, SSTRB pulses high for one clock period before the MSB decision. It is high impedance when CS is high in external clock mode. Serial Data Output. MSB first, straight binary format for unipolar input, two’s complement for bipolar input. Each bit is clocked out of DOUT at the falling edge of SCLK. Reset Input. Drive RST low to put the device in the power-on default mode. See the Power-On Reset section. Serial Data Clock Input. Serial data on DIN is loaded on the rising edge of SCLK, and serial data is updated on DOUT on the falling edge of SCLK. In external clock mode, SCLK sets the conversion speed. Digital Ground. Connect to pin 5. Digital Supply, 3.3V ±5%. Bypass DVDD to DGND (pin 14) with a 0.1µF capacitor. Serial Data Input. Serial data on DIN is latched on the rising edge of SCLK. Chip-Select Input. Drive CS low to enable the serial interface. When CS is high, DOUT is high impedance. In external clock mode, SSTRB is high impedance when CS is high. Reference Buffer Bypass. Bypass CREF to AGND (pin 3) with a 1µF capacitor. Analog Ground. Connect to pin 3. Analog Input MAX1134/MAX1135 11 12 13 14 15 16 17 18 19 20 DOUT RST SCLK DGND DVDD DIN CS CREF AGND AIN _______________________________________________________________________________________ 7 16-Bit ADCs, 150ksps, 3.3V Single Supply MAX1134/MAX1135 Detailed Description The MAX1134/MAX1135 ADCs use a successiveapproximation technique and input track/hold (T/H) circuitry to convert an analog signal to a 16-bit digital output. The MAX1134/MAX1135 easily interface to microprocessors (µPs). The data bits can be read either during the conversion in external clock mode or after the conversion in internal clock mode. In addition to a 16-bit ADC, the MAX1134/MAX1135 include an input scaler, an internal digital microcontroller, calibration circuitry, and an internal clock generator. The input scaler for the MAX1134 enables conversion of input signals ranging from 0 to +6V (unipolar input) or ± 6V (bipolar input). The MAX1135 accepts 0 to +2.048V (unipolar input) or ±2.048V (bipolar input). The input range is software selectable. Calibration To minimize linearity, offset, and gain errors, the MAX1134/MAX1135 have on-demand software calibration. Initiate calibration by writing a control byte with bit M1 = 0 and bit M0 = 1 (Table 1). Select internal or external clock for calibration by setting the INT/EXT bit in the control byte. Calibrate the MAX1134/MAX1135 with the same clock mode used for performing conversions. Offsets resulting from synchronous noise (such as the conversion clock) are canceled by the MAX1134/ MAX1135’s calibration circuitry. However, because the magnitude of the offset produced by a synchronous signal depends on the signal ’s shape, recalibration may be appropriate if the shape or relative timing of the clock, or other digital signals change, as may occur if more than one clock signal or frequency is used. S1 R1 2.5kΩ R2 AIN R3 BIPOLAR VOLTAGE REFERENCE UNIPOLAR TRACK S2 HOLD CHOLD 32pF T/H OUT TRACK S3 HOLD S1 = BIPOLAR/UNIPOLAR S2, S3 = T/H SWITCH R2 = 7.6kΩ (MAX1134) OR 2.5kΩ (MAX1135) R3 = 3.9kΩ (MAX1134) OR INFINITY (MAX1135) Input Scaler The MAX1134/MAX1135 have an input scaler, which allows conversion of true bipolar input voltages while operating from a single 3.3V supply. The input scaler attenuates and shifts the input as necessary to map the external input range to the input range of the internal ADC. The MAX1134 analog input range is 0 to +6V (unipolar) or ±6V (bipolar). The MAX1135 analog input Figure 1. Equivalent Input Circuit Table 1. Control Byte Format BIT 7 (MSB) 6 5 4 NAME START UNI/BIP INT/EXT M1 DESCRIPTION The first logic 1 bit after CS goes low defines the beginning of the control byte. 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, analog input signals from 0 to +6V (MAX1134) or 0 to +VREF (MAX1135) can be converted. In bipolar mode, analog input signals from -6V to +6V (MAX1134) or -VREF to +VREF (MAX1135) can be converted. Selects the internal or external conversion clock. 1 = internal, 0 = external. M1 0 0 3 2 1 0 (LSB) M0 P2 P1 P0 These 3 bits are stored in a port register and output to pins P2, P1, and P0 for use in addressing a mux or PGA. These 3 bits are updated in the port register simultaneously when a new control byte is written. 1 1 M0 0 1 0 1 Mode 24 external clocks per conversion (short acquisition mode) Start calibration: starts internal calibration Software power-down mode 32 external clocks per conversion (long acquisition mode) 8 _______________________________________________________________________________________ 16-Bit ADCs, 150ksps, 3.3V Single Supply MAX1134/MAX1135 CS tACQ SCLK 1 UNI/ INT/ EXT 4 8 12 15 21 24 DIN SSTRB START BIP M1 M0 P2 P1 P0 DOUT A/D STATE IDLE ACQUISITION B15 MSB B14 B13 B12 B11 B10 B9 B4 B3 B2 B1 B0 LSB FILLED WITH ZEROS IDLE CONVERSION Figure 2. Short Acquisition Mode (24 Clock Cycles) External Clock Table 2. User-Programmable Outputs OUTPUT PIN PROGRAMMED THROUGH CONTROL BYTE Bit 2 Bit 1 Bit 0 POWER-ON OR RST DEFAULT 0 0 0 DESCRIPTION User-programmable outputs follow the state of the control byte’s 3 LSBs, and are updated simultaneously when a new control byte is written. Outputs are push-pull. In hardware and software shutdown, these outputs are unchanged and remain low impedance. P2 P1 P0 range is 0 to +2.048V (unipolar) or ±2.048V (bipolar). Unipolar and bipolar mode selection is configured with bit 6 of the serial control byte (Table 1). Figure 1 shows the equivalent input circuit of the MAX1134/MAX1135. The resistor network on the analog input provides ±16.5V fault protection. This circuit limits the current going into or out of the pin to less than 2mA. The overvoltage protection is active even if the device is in a power-down mode, or if AVDD = 0. low or after a conversion or calibration completes, the first logic 1 clocked into DIN is interpreted as the START bit, the MSB of the 8-bit control byte. The SCLK input is the serial-data-transfer clock, which clocks data in and out of the MAX1134/MAX1135. SCLK also drives the ADC conversion steps in external clock mode (see the Internal and External Clock Modes section). DOUT is the serial output of the conversion result. DOUT is updated on the falling edge of SCLK. DOUT is high impedance when CS is high. CS must be low for the MAX1134/MAX1135 to accept a control byte. The serial interface is disabled when CS is high. Digital Interface The digital interface pins consist of S HDN , R ST , SSTRB, DOUT, SCLK, DIN, and CS. Bringing SHDN low places the MAX1134/MAX1135 in its 1.2µA shutdown mode. A logic low on RST halts the MAX1134/MAX1135 operation and returns the part to its power-on-reset state. In external clock mode, SSTRB is low and pulses high for one clock cycle at the start of conversion. In internal clock mode, SSTRB goes low at the start of the conversion, and goes high to indicate that the conversion is finished. The DIN input accepts control byte data, which is clocked in on each rising edge of SCLK. After CS goes User-Programmable Outputs The MAX1134/MAX1135 have three user-programmable outputs: P0, P1, and P2. The power-on default state for the programmable outputs is zero. These are push-pull CMOS outputs suitable for driving a multiplexer, a PGA, or other signal preconditioning circuitry. Bits 0, 1, and 2 of the control byte control the user-programmable outputs (Tables 1, 2). _______________________________________________________________________________________ 9 16-Bit ADCs, 150ksps, 3.3V Single Supply MAX1134/MAX1135 CS tACQ SCLK 1 UNI/ INT/ EXT 4 8 14 15 29 32 DIN SSTRB START BIP M1 M0 P2 P1 P0 DOUT A/D STATE IDLE ACQUISITION B15 MSB B14 B13 B4 B3 B2 B1 B0 FILLED WITH ZEROS LSB IDLE CONVERSION Figure 3. Long Acquisition Mode (32 Clock Cycles) External Clock CS tSDV tSTR SSTRB tSSTRB tSSTRB SCLK P1 CLOCKED IN Figure 4. External Clock Mode SSTRB Detailed Timing The user-programmable outputs are set to zero during power-on reset or when RST goes low. During hardware or software shutdown, P0, P1, and P2 are unchanged and remain low impedance. Internal and External Clock Modes The MAX1134/MAX1135 use either the external serial clock or the internal clock to perform the successiveapproximation conversion. In both clock modes, the external clock shifts data in and out of the MAX1134/MAX1135. Bit 5 (INT/EXT) of the control byte programs the clock mode. External Clock In external clock mode, the external clock not only shifts data in and out, but also drives the ADC conversion steps. In short acquisition mode, SSTRB pulses high for one clock period after the seventh falling edge of SCLK following the start bit. The MSB of the conversion is available at DOUT on the eighth falling edge of SCLK (Figure 2). Starting a Conversion Start a conversion by clocking a control byte into the device’s internal shift register. With CS low, each rising edge on SCLK clocks a bit from DIN into the MAX1134/MAX1135s’ internal shift register. After CS goes low or after a conversion or calibration completes, the first arriving logic 1 is defined as the start bit of the control byte. Until this first start bit arrives, any number of logic 0 bits can be clocked into DIN with no effect. If at any time during acquisition or conversion CS is brought high and then low again, the part is placed into a state where it can recognize a new start bit. If a new start bit occurs before the current conversion is complete, the conversion is aborted and a new acquisition is initiated. 10 ______________________________________________________________________________________ 16-Bit ADCs, 150ksps, 3.3V Single Supply MAX1134/MAX1135 CS tACQ SCLK 1 UNI/ INT/ EXT 4 8 9 10 21 24 DIN SSTRB START BIP M1 M0 P2 P1 P0 tCONV DOUT B15 MSB B14 B13 B4 B3 B2 B1 B0 LSB FILLED WITH ZEROS Figure 5. Internal Clock Mode Timing, Short Acquisition CS tCONV tCSS tSCK tCSH SSTRB t SSTRB SCLK P0 CLOCKED IN NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION. Figure 6. Internal Clock Mode SSTRB Detailed Timing In long acquisition mode, when using external clock, SSTRB pulses high for one clock period after the 15th falling edge of SCLK following the start bit. The MSB of the conversion is available at DOUT on the 16th falling edge of SCLK (Figure 3). In external clock mode, SSTRB is high impedance when CS is high (Figure 4). CS is normally held low during the entire conversion. If CS goes high during the conversion, SCLK is ignored until CS goes low. This allows external clock mode to be used with 8-bit bytes. Internal Clock In internal clock mode, the MAX1134/MAX1135 generate their own conversion clock. This frees the microprocessor from the burden of running the SAR conversion clock, and allows the conversion results to be read back at the processor’s convenience, at any clock rate up to 4MHz. SSTRB goes low at the start of the conversion and goes high when the conversion is complete. SSTRB is low for a maximum of 7µs, during which time SCLK should remain low for best noise performance. An internal register stores data when the conversion is in progress. SCLK clocks the data out of the internal storage register at any time after the conversion is complete. The MSB of the conversion is available at DOUT when SSTRB goes high. The subsequent 15 falling edges on SCLK shift the remaining bits out of the internal storage register (Figure 5). CS does not need to be held low once a conversion is started. When internal clock mode is selected, SSTRB does not go into a high-impedance state when CS goes high. Figure 6 shows the SSTRB timing in internal clock mode. In internal clock mode, data can be shifted into the MAX1134/MAX1135 at clock rates up to 4MHz, pro- ______________________________________________________________________________________ 11 16-Bit ADCs, 150ksps, 3.3V Single Supply MAX1134/MAX1135 Table 3. Unipolar Full Scale and Zero Scale PART MAX1134 MAX1135 ZERO SCALE 0 0 FULL SCALE +6 (VREF/2.048) +VREF Table 4. Bipolar Full Scale, Zero Scale, and Negative Full Scale PART MAX1134 MAX1135 NEGATIVE FULL SCALE -6 (VREF/2.048) -VREF ZERO SCALE 0 0 FULL SCALE +6 (VREF/2.048) +VREF vided the minimum acquisition time, t ACQ , is kept above 1.39µs in bipolar mode and 1.67µs in unipolar mode. Data can be clocked out at 4MHz. Output Data The output data format is straight binary for unipolar conversions and two’s complement in bipolar mode. The MSB is shifted out of the MAX1134/MAX1135 first in both modes. Data Framing The falling edge of CS does not start a conversion on the MAX1134/MAX1135. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte. A conversion starts on the falling edge of SCLK, after the seventh bit of the control byte (the P1 bit) is clocked into DIN. The start bit is defined as: • The first high bit clocked into DIN with CS low anytime the converter is idle, e.g., after AV DD is applied. • The first high bit clocked into DIN after CS is pulsed high then low. If a falling edge on CS forces a start bit before the conversion or calibration is complete, then the current operation terminates and a new one starts. power supplies and the reference voltage have fully settled prior to initiating the calibration sequence. Initiate calibration by setting M1 = 0 and M0 = 1 in the control byte. In internal clock mode, SSTRB goes low at the beginning of calibration and goes high to signal the end of calibration, approximately 80,000 clock cycles later. In external clock mode, SSTRB goes high at the beginning of calibration and goes low to signal the end of calibration. Calibration should be performed in the same clock mode that is used for conversions. Reference The MAX1134/MAX1135 require a 2.048V reference. The reference must be bypassed with a 4.7µF capacitor. The input impedance at REF is a minimum of 16kΩ for DC currents. During conversion, the external reference at REF must deliver up to 150µA DC load current and have an output impedance of 10Ω or less. Analog Input The MAX1134/MAX1135 use a capacitive DAC that provides an inherent track/hold function. Drive AIN with a source impedance less than 10Ω. Any signal conditioning circuitry must settle with 16-bit accuracy in less than 500ns. Limit the input bandwidth to less than half the sampling frequency to eliminate aliasing. The MAX1134/MAX1135 have a complex input impedance that varies from unipolar to bipolar mode (Figure 1). Input Range The analog input range in unipolar mode is 0 to +6V for the MAX1134, and 0 to +2.048V for the MAX1135. In bipolar mode, the analog input can be -6V to +6V for the MAX1134, or -2.048V to +2.048V for the MAX1135. Unipolar or bipolar mode is programmed with the UNI/BIP bit of the control byte. When using a reference other than the suggested 2.048V, the full-scale input range varies accordingly. The full-scale input range depends on the voltage at REF and the sampling mode selected (Tables 3 and 4). Applications Information Power-On Reset When power is first applied to the MAX1134/MAX1135, or if RST is pulsed low, the internal calibration registers are set to their default values. The user-programmable registers (P0, P1, and P2) are low, and the device is configured for bipolar mode with internal clocking. Calibration Periodically calibrate the MAX1134/MAX1135 to compensate for temperature drift and other variations. After any change in ambient temperature of more than +10°C, the device should be recalibrated. A 100mV change in supply voltage or any change in the reference voltage should be followed by a calibration. Calibration corrects for errors in gain, offset, integral nonlinearity, and differential nonlinearity. The MAX1134/MAX1135 should be calibrated after power-up or after the assertion of reset. Make sure the 12 ______________________________________________________________________________________ 16-Bit ADCs, 150ksps, 3.3V Single Supply 1kW VCC MAX1134/MAX1135 0.1mF 2 7 6 100pF AIN IN 3 4 0.1mF VEE 0.0033mF 1kW Figure 7. AIN Buffer for AC/DC Use Input Acquisition and Settling Clocking in a control byte starts input acquisition. The main capacitor array starts acquiring the input as soon as a start bit is recognized, using the same input range as the previous conversion. If the opposite input range is selected by the second DIN bit, the part immediately switches to the new sampling mode. Acquisition time is one-and-a-half clock cycles shorter when switching from unipolar to bipolar or bipolar to unipolar modes than when continuously converting in the same mode. Acquisition can be extended by eight clock cycles by setting M1 = 1 and M0 = 1 (long acquisition mode). The sampling instant in short acquisition completes on the falling edge of the sixth clock cycle after the start bit (Figure 2). Acquisition is five clock cycles in short acquisition mode and 13 clock cycles in long acquisition mode. Short acquisition mode is 24 clock cycles per conversion. Using the external clock to run the conversion process limits unipolar conversion speed to 125ksps instead of 150ksps as in bipolar mode. The input resistance in unipolar mode is larger than that of bipolar mode (Figure 1). The RC time constant in unipolar mode is larger than that of bipolar mode, reducing the maximum conversion rate in 24 external clock mode. Long acquisition mode with external clock allows both unipolar and bipolar sampling of 112ksps (3.6MHz / 32 clock cycles) by adding eight extra clock cycles to the conversion. Most applications require an input buffer amplifier. If the input signal is multiplexed, the input channel should be switched immediately after acquisition, rather than near the end of or after a conversion. This allows more time for the input buffer amplifier to respond to a large step change in input signal. The input amplifier must have a high enough slew rate to complete the required output voltage change before the beginning of the acquisition time. At the beginning of acquisition, the capacitive DAC is connected to the amplifier output, causing some output disturbance. Ensure that the sampled voltage has settled to within the required limits before the end of the acquisition time. If the frequency of interest is low, AIN can be bypassed with a large enough capacitor to charge the capacitive DAC with very little change in voltage. However, for AC use, AIN must be driven by a wideband buffer (at least 10MHz), which must be stable with the DAC’s capacitive load (in parallel with any AIN bypass capacitor used) and also must settle quickly (Figure 7). Digital Noise Digital noise can couple to AIN and REF. The conversion clock (SCLK) and other digital signals that are active during input acquisition contribute noise to the conversion result. If the noise signal is synchronous to the sampling interval, an effective input offset is produced. Asynchronous signals produce random noise on the input, whose high-frequency components may be aliased into the frequency band of interest. Minimize noise by presenting a low impedance (at the frequencies contained in the noise signal) at the inputs. This requires bypassing AIN to AGND, or buffering the input with an amplifier that has a small-signal bandwidth of several MHz, or preferably both. AIN has a bandwidth of about 4MHz. ______________________________________________________________________________________ 13 16-Bit ADCs, 150ksps, 3.3V Single Supply MAX1134/MAX1135 Offsets resulting from synchronous noise (such as the conversion clock) are canceled by the MAX1134/ MAX1135s’ calibration scheme. However, because the magnitude of the offset produced by a synchronous signal depends on the signal’s shape, recalibration may be appropriate if the shape or relative timing of the clock or other digital signals change, which can occur if more than one clock signal or frequency is used. Distortion Avoid degrading dynamic performance by choosing an amplifier with distortion much less than the MAX1134/MAX1135s’ THD (-90dB) at frequencies of interest. If the chosen amplifier has insufficient commonmode rejection, which results in degraded THD performance, use the inverting configuration to eliminate errors from common-mode voltage. Low-temperature-coefficient resistors reduce linearity errors caused by resistance changes due to self-heating. To reduce linearity errors due to finite amplifier gain, use an amplifier circuit with sufficient loop gain at the frequencies of interest. DC Accuracy If DC accuracy is important, choose a buffer with an offset much less than the MAX1134/MAX1135s’ maximum offset (±6mV), or whose offset can be trimmed while maintaining good stability over the required temperature range. used to do conversions. The part remains in calibration mode for approximately 80,000 clock cycles unless the calibration is aborted. Calibration is halted if RST or SHDN goes low, or if a valid start condition occurs. Software Shutdown A software power-down is initiated by setting M1 = 1 and M0 = 0. After the conversion completes, the part shuts down. It reawakens upon receiving a new start bit. Conversions initiated with M1 = 1 and M0 = 0 (shutdown) use the acquisition mode selected for the previous conversion. Shutdown Mode The MAX1134/MAX1135 may be shut down by pulling SHDN low or by asserting software shutdown. In addition to lowering power dissipation to 4.0µW, considerable power can be saved by shutting down the converter for short periods between conversions. There is no need to perform a calibration after the converter has been shut down unless the time in shutdown is long enough that the supply voltage or ambient temperature has changed. Supplies, Layout, Grounding, and Bypassing For best system performance, use separate analog and digital ground planes. The two ground planes should be tied together at the MAX1134/MAX1135. Use pin 3 and pin 14 as the primary AGND and DGND, respectively. If the analog and digital supplies come from the same source, isolate the digital supply from the analog with a low-value resistor (10Ω). The MAX1134/MAX1135 are not sensitive to the order of AVDD and DVDD sequencing. Either supply can be present in the absence of the other. Do not apply an external reference voltage until after both AVDD and DVDD are present. Be sure that digital return currents do not pass through the analog ground. All return-current paths must be low impedance. A 5mA current flowing through a PC board ground trace impedance of only 0.05Ω creates an error voltage of about 250µV, or about 2LSBs error with a ±4V full-scale system. The board layout should ensure that digital and analog signal lines are kept separate. Do not run analog and digital lines parallel to one another. If you must cross one with the other, do so at right angles. The ADC is sensitive to high-frequency noise on the AVDD power supply. Bypass this supply to the analog ground plane with 0.1µF. If the main supply is not adequately bypassed, add an additional 1µF or 10µF lowESR capacitor in parallel with the primary bypass capacitor. Operating Modes and Serial Interfaces The MAX1134/MAX1135 are fully compatible with MICROWIRE and SPI/QSPI devices. MICROWIRE and SPI/QSPI both transmit a byte and receive a byte at the same time. The simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the 16-bit conversion result). Short Acquisition Mode (24 SCLK) Configure short acquisition by setting M1 = 0 and M0 = 0. In short acquisition mode, the acquisition time is 5 clock cycles. The total period is 24 clock cycles per conversion. Long Acquisition Mode (32 SCLK) Configure long acquisition by setting M1 = 1 and M0 = 1. In long acquisition mode, the acquisition time is 13 clock cycles. The total period is 32 clock cycles per conversion. Calibration Mode A calibration is initiated through the serial interface by setting M1 = 0 and M0 = 1. Calibration can be done in either internal or external clock mode, though it is desirable that the part be calibrated in the same mode in which it will be 14 ______________________________________________________________________________________ 16-Bit ADCs, 150ksps, 3.3V Single Supply MAX1134/MAX1135 OUTPUT CODE OUTPUT CODE 11 . . . 111 11 . . . 110 11 . . . 101 000 . . . 010 000 . . . 001 FS = 2.048V 1LSB = FS 65536 000 . . . 000 111 . . . 111 111 . . . 110 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 0 1 2 3 FS - 3/2LSB FS -FS INPUT VOLTAGE (LSBs) 100 . . . 001 100 . . . 000 0 INPUT VOLTAGE (LSBs) +FS - 1LSB 111 . . . 101 FULL-SCALE TRANSITION 011 . . . 111 011 . . . 110 +FS = +2.048V -FS = -2.048V 1LSB = 4.096V 65536 Figure 8. MAX1135 Unipolar Transfer Function, 2.048V = Full Scale Figure 9. MAX1135 Bipolar Transfer Function, 4.096V = Full Scale Transfer Function Figures 8 and 9 show the MAX1135s’ transfer functions. In unipolar mode, the output data is in binary format and in bipolar mode it is in two’s complement format. Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of fullscale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC ’ s resolution (N-bits): SNR = (6.02 x N + 1.76) dB In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is calculated by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. INL for the MAX1134/MAX1135 is measured using the endpoint method. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to the RMS equivalent of all other ADC output signals: SINAD (dB) = 20 x log (SignalRMS / NoiseRMS) Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. Aperture Delay Aperture delay (t AD ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. ______________________________________________________________________________________ 15 16-Bit ADCs, 150ksps, 3.3V Single Supply MAX1134/MAX1135 Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as:  2 2 2 2   V2 + V3 + V4 + V5  THD = 20 × log   V1         Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest distortion component. where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Functional Diagram AVDD AGND CREF REF AIN INPUT SCALING NETWORK DAC COMPARATOR MAX1134 MAX1135 ANALOG TIMING CONTROL DVDD DGND CS SCLK DIN RST SHDN SERIAL INPUT PORT CLOCK GENERATOR MEMORY CALIBRATION ENGINE SERIAL OUTPUT PORT SSTRB DOUT P2 P1 P0 CONTROL 16 ______________________________________________________________________________________ 16-Bit ADCs, 150ksps, 3.3V Single Supply Typical Application Circuit 3.3V 0.1µF Ordering Information (continued) PART MAX1135BCAP MAX1135BEAP TEMP RANGE 0°C to +70°C -40°C to +85°C PINPACKAGE 20 SSOP 20 SSOP INL (LSB) ±2.5 ±2.5 MAX1134/MAX1135 AVDD SHDN DVDD AIN 0.1µF 3.3V MAX1134/ MAX1135 2.048V REF CREF 4.7µF 1µ F DGND CS SCLK DIN DOUT RST SSTRB AGND MC68HCXX I/O SCLK MOSI MISO I/O Chip Information TRANSISTOR COUNT: 21,807 PROCESS: BiCMOS ______________________________________________________________________________________ 17 16-Bit ADCs, 150ksps, 3.3V Single Supply MAX1134/MAX1135 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) SSOP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.