MAX115

19-1928; Rev 0; 1/01 KIT ATION EVALU ABLE AVAIL 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs ____________________________Features o Four Simultaneous-Sampling T/H Amplifiers with Two Multiplexed Inputs (Eight Single-Ended Inputs Total) o 2µs Conversion Time per Channel o Throughput: 390ksps (1 Channel) 218ksps (2 Channels) 152ksps (3 Channels) 116ksps (4 Channels) o Input Range: ± 5V (MAX115) ± 2.5V (MAX116) o Fault-Protected Input Multiplexer (±17V) o Internal +2.5V or External Reference Operation o Programmable On-Board Sequencer o High-Speed Parallel DSP Interface o Internal 10MHz Clock ________________General Description The MAX115/MAX116 are high-speed, multichannel, 12-bit data-acquisition systems (DAS) with simultaneous track/holds (T/Hs). These devices contain a 12-bit, 2µs, successive-approximation analog-to-digital converter (ADC), a +2.5V reference, a buffered reference input, and a bank of four simultaneous-sampling T/H amplifiers that preserve the relative phase information of the sampled inputs. The MAX115/MAX116 have two multiplexed inputs for each T/H, allowing a total of eight inputs. In addition, the converter is overvoltage tolerant to ±17V. A fault condition on any channel will not damage the IC. Available input ranges are ±5V (MAX115) and ±2.5V (MAX116). The parallel interface’s data access and bus release timing specifications are compatible with most popular digital signal processors and 16-bit/32-bit microprocessors. The MAX115/MAX116 conversion results can be accessed without resorting to wait-states. MAX115/MAX116 ________________________Applications Multiphase Motor Control Power-Grid Synchronization Power-Factor Monitoring Digital Signal Processing Vibration and Waveform Analysis PART MAX115CAX MAX115EAX MAX116CAX MAX116EAX Ordering Information TEMP. RANGE 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C PIN-PACKAGE 36 SSOP 36 SSOP 36 SSOP 36 SSOP Pin Configuration TOP VIEW CH2B 1 CH2A 2 CH1B 3 CH1A 4 AVDD 5 REFIN 6 REFOUT 7 AGND 8 D11 (MSB) 9 D10 10 D9 11 D8 12 D7 13 D6 14 D5 15 D4 16 DVDD 17 DGND 18 36 AGND 35 CH3B 34 CH3A 33 CH4B 32 CH4A Typical Operating Circuit CH1A CH1B CH2A CH2B CH3A CH3B CH4A CH4B +5V 0.1µF 0.1µF -5V 0.1µF AVSS REFIN DVDD +5V 0.1µF REFOUT 4.7µF CLK 16MHz CONTROL INTERFACE CONVST INT CS RD WR DGND AVDD AGND A0 A1 D0/A2 D1/A3 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 MAX115 MAX116 31 AVSS 30 INT 29 CONVST 28 RD 27 WR 26 CS 25 CLK 24 A0 23 A1 22 D0/A2 (LSB) 21 D1/A3 20 D2 19 D3 MAX115 MAX116 SSOP ________________________________________________________________ Maxim Integrated Products 1 For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs MAX115/MAX116 ABSOLUTE MAXIMUM RATINGS AVDD to AGND ...........................................................-0.3V to 6V AVSS to AGND ............................................................0.3V to -6V DVDD to DGND ...........................................................-0.3V to 6V AGND to DGND .......................................................-0.3V to 0.3V CH_ _ to AGND....................................................................±17V REFIN, REFOUT to AGND ..........................................-0.3V to 6V Digital Inputs/Outputs to DGND ..............-0.3V to (DVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 36-Pin SSOP (derate 11.8mW/°C above +70°C) ..........941mW Operating Temperature Ranges MAX115_CAX/MAX116_CAX ...............................0°C to +70°C MAX115_EAX/MAX116_EAX ............................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s)....................................300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = +5V ±5%, AVSS = -5V ±5%, DVDD = +5V ±5%, VREFIN = +2.5V (external reference), AGND = DGND = 0, 4.7µF capacitor from REFOUT to AGND, 0.1µF capacitor from REFIN to AGND, fCLK = 16MHz, external clock, 50% duty cycle. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER DC ACCURACY (Note 1) Resolution Integral Nonlinearity (Note 2) Differential Nonlinearity N INL DNL MAX115 Bipolar Zero Error MAX116 Bipolar Zero-Error Match Zero-Code Tempco Between all channels MAX115 MAX116 MAX115 Gain Error MAX116 Gain Error Match Gain Error Tempco MAX115 MAX116 SNR THD SFDR (Note 4) (Notes 4, 5) (Note 4) (Note 6) 80 80 69 -80 TA = +25°C TA = TMIN to TMAX TA = +25°C TA = TMIN to TMAX 2 120 60 ±5 TA = +25°C TA = TMIN to TMAX TA = +25°C TA = TMIN to TMAX 2 180 90 ±5 ±15 ±25 ±10 ±18 5 mV µV/°C mV ±5 All channels 12 0.6 0.6 ±5 ±1 ±1 ±15 ±30 ±10 ±18 5 mV µV/°C mV Bits LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE (fCLK = 16MHz, fIN = 10.06kHz) (Notes 1, 3) Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Isolation dB dB dB dB 2 _______________________________________________________________________________________ 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs MAX115/MAX116 ELECTRICAL CHARACTERISTICS (continued) (AVDD = +5V ±5%, AVSS = -5V ±5%, DVDD = +5V ±5%, VREFIN = +2.5V (external reference), AGND = DGND = 0, 4.7µF capacitor from REFOUT to AGND, 0.1µF capacitor from REFIN to AGND, fCLK = 16MHz, external clock, 50% duty cycle. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER ANALOG INPUT Input Voltage Range Input Current Input Capacitance TRACK/HOLD Acquisition Time Small-Signal Bandwidth Full-Power Bandwidth Drop Rate Aperture Delay Aperture Jitter Aperture-Delay Matching REFERENCE OUTPUT (Note 7) Output Voltage External Load Regulation REFOUT Tempco External Capacitive Bypass at REFIN External Capacitive Bypass at REFOUT REFERENCE INPUT Input Voltage Range Input Current Input Resistance (Note 9) Input Capacitance EXTERNAL CLOCK External Clock Frequency INTERNAL CLOCK Internal Clock Frequency DIGITAL INPUTS (CONVST, RD, WR, CS, CLK, A0–A3) (Note 1) Input High Voltage Input Low Voltage Input Current Input Capacitance VIH VIL IIN CIN CONVST, RD, WR, CS, CLK A0–A3 15 2.4 0.8 ±1 ±10 V V µA pF 5.6 10 14.8 MHz 16 MHz 10 10 2.40 2.50 2.60 ±50 V µA kΩ pF VREFOUT TA = +25°C 0 < IREF < 1mA (Note 8) 0.1 4.7 22 2.462 2.5 0.5 30 2.532 V mV/mA ppm/°C µF µF tACQ 600 10 1.3 2 10 30 500 ns MHz MHz mV/ms ns ps ps VIN IIN CIN MAX115 MAX116 MAX115 (-5V to +5V range) MAX116 (-2.5V to +2.5V range) 16 ±5 ±2.5 ±625 ±15 V µA pF SYMBOL CONDITIONS MIN TYP MAX UNITS _______________________________________________________________________________________ 3 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs MAX115/MAX116 ELECTRICAL CHARACTERISTICS (continued) (AVDD = +5V ±5%, AVSS = -5V ±5%, DVDD = +5V ±5%, VREFIN = +2.5V (external reference), AGND = DGND = 0, 4.7µF capacitor from REFOUT to AGND, 0.1µF capacitor from REFIN to AGND, fCLK = 16MHz, external clock, 50% duty cycle. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Output High Voltage Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Positive Supply Voltage Negative Supply Voltage Digital Supply Voltage Positive Supply Current Negative Supply Current Digital Supply Current Shutdown Positive Current Shutdown Negative Current Shutdown Digital Current Positive Supply Rejection Negative Supply Rejection Power Dissipation PSRR+ PSRR(Note 10) (Note 10) (Note 11) 175 AVDD AVSS DVDD IAVDD IAVSS -20 4.75 -5.25 4.75 5 -5 5 17 -15 3 1 -1 13 ±1 ±1 6 5.25 -4.75 5.25 25 V V V mA mA mA µA µA µA LSB LSB mW SYMBOL VOH VOL IOUT = 1mA IOUT = -1.6mA D0–D11 10 CONDITIONS MIN 4 0.4 ±10 TYP MAX UNITS V V µA pF DIGITAL OUTPUTS (D0–D11, INT) TIMING CHARACTERISTICS (See Figure 4, AVDD = +5V, AVSS = -5V, DVDD = +5V, AGND = DGND = 0, TA = TMIN to TMAX, Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER CONVST Pulse Width CS to WR Setup Time CS to WR Hold Time WR Low Pulse Width Address Setup Time Address Hold Time RD to INT Delay Delay Time Between Reads CS to RD Setup Time CS to RD Hold Time RD Low Pulse Width Data-Access Time Bus-Relinquish Time SYMBOL tCW tCWS tCWH tWR tAS tAH tID tRD tCRS tCRH tRD tDA tDH 25pF load (Note 12) 25pF load (Note 13) 5 Guaranteed by design Guaranteed by design 25pF load 45 0 0 30 40 45 Guaranteed by design Guaranteed by design CONDITIONS MIN 30 0 0 30 30 0 55 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns 4 _______________________________________________________________________________________ 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs MAX115/MAX116 TIMING CHARACTERISTICS (continued) (See Figure 4, AVDD = +5V, AVSS = -5V, DVDD = +5V, AGND = DGND = 0, TA = TMIN to TMAX, Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS Mode 1, Channel 1 Conversion Time tCONV Mode 2, Channel 2 Mode 3, Channel 3 Mode 4, Channel 4 Mode 1, Channel 1 Conversion Rate Mode 2, Channel 2 Mode 3, Channel 3 Mode 4, Channel 4 Startup Time Exiting shutdown 20 MIN TYP MAX 2 4 6 8 390 218 152 116 ms ksps µs UNITS Note 1: AVDD = +5V, AVSS = -5V, DVDD = +5V, VREFIN = 2.500V (external), VIN = ±5V (MAX115) or ±2.5V (MAX116). Note 2: Integral nonlinearity is the analog value’s deviation at any code from its theoretical value after the full-scale range and offset have been calibrated. Note 3: CLK synchronized with CONVST. Note 4: fIN = 10.06kHz, VIN = ±5V (MAX115) or ±2.5V (MAX116). Note 5: First five harmonics. Note 6: All inputs except CH1A driven with ±5V (MAX115) or ±2.5V (MAX116) 10.06kHz signal, CH1A connected to AGND and digitized. Note 7: AVDD = DVDD = +5V, AVSS = -5V, VIN = 0V (all channels). Note 8: Temperature drift is defined as the change in output voltage from +25°C to TMIN or TMAX. It is calculated as TC = [∆REFOUT/REFOUT] / ∆T. Note 9: See Figure 2. Note 10: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage. Tested with one input at full scale and all others at AGND. VREFIN = +2.5V (internal). Note 11: Tested with all inputs connected to AGND. VREFIN = +2.5V (internal). Note 12: The data access time is defined as the time required for an output to cross +0.8V or +2.0V. It is measured using the circuit of Figure 1. The measured number is then extrapolated back to determine the value with a 25pF load. Note 13: The bus relinquish time is derived from the measured time taken for the data outputs to change +0.5V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging and discharging the 120pF capacitor. The time given is the part’s true bus relinquish time, which is independent of the external bus loading capacitance. _______________________________________________________________________________________ 5 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs MAX115/MAX116 ______________________________________________________________Pin Description PIN 1, 2 3, 4 5 6 7 8, 36 9–16 17 18 19, 20 21, 22 23, 24 25 26 27 28 29 30 31 32, 33 34, 35 NAME CH2B, CH2A CH1B, CH1A AVDD REFIN REFOUT AGND D11–D4 DVDD DGND D3, D2 D1/A3, D0/A2 A1, A0 CLK CS WR RD CONVST INT AVSS CH4A, CH4B CH3A, CH3B FUNCTION Channel 2 Multiplexed Inputs (single-ended) Channel 1 Multiplexed Inputs (single-ended) Analog Supply Voltage External reference input/internal reference output. Bypass with a 0.1µF capacitor to AGND. Reference-Buffer output. Bypass with a 4.7µF capacitor to AGND. Analog ground. Both pins must be connected to ground. Data Bits. D11 = MSB. Digital Supply Voltage Digital Ground Data Bits Bidirectional Data Bits/Address Bits Address Bits Clock Input (duty cycle must be 30% to 70%). Connect CLK to DVDD to activate internal clock. Chip-Select Input (active-low) Write Input (active-low) Read Input (active-low) Conversion-Start input. Rising edge initiates sampling and conversion sequence. Interrupt output. Falling edge indicates the end of a conversion sequence. Analog Supply Voltage Channel 4 Multiplexed Inputs (single-ended) Channel 3 Multiplexed Inputs (single-ended) _______________Detailed Description 1.6mA TO OUTPUT PIN 120pF 1.6V 1.0mA Figure 1. Load Circuit for Access Time and Bus Relinquish Time 6 The MAX115/MAX116 use a successive-approximation conversion technique and four simultaneous-sampling track/hold (T/H) amplifiers to convert analog signals into 12-bit digital outputs. Each T/H has two multiplexed inputs, allowing a total of eight inputs. Each T/H output is converted and stored in memory to be accessed sequentially by the parallel interface with successive read cycles. The MAX115/MAX116 internal microsequencer can be programmed to digitize one, two, three, or four inputs sampled simultaneously from either of the two banks of four inputs (Figure 2). The MAX115/MAX116 can operate with either an external or internal clock. For internal operation, connect CLK to DVDD. _______________________________________________________________________________________ 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs MAX115/MAX116 REFIN AGND REFOUT BANDGAP REFERENCE 10kΩ CH1A A CH1B B MUX T/H 2.50V CH2A A B MUX T/H VREF MUX CH2B CH3A A B CH3B MUX T/H COMP CH4A A CH4B B MUX T/H 12-BIT DAC SAR VREF A0 4x12 RAM AVDD D1/A3 AGND THREE-STATE OUTPUT DRIVERS D2 D3 A1 D0/A2 AVSS CONTROL LOGIC 10MHz CLOCK D11 (MSB) MAX115 MAX116 BUS INTERFACE CLK CONVST INT CS RD WR DVDD DGND Figure 2. Functional Diagram _______________________________________________________________________________________ 7 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs MAX115/MAX116 HOLD R1 BUFFER CH_A R2 S1A C IN R3 S3A MUX R1 S1B CH_B R2 S2B S2A HOLD C HOLD 7pF TRACK FROM MICROSEQUENCER TRACK C IN R3 S3B REFOUT DAC MAX115 MAX116 MAX115: R1 = ∞, R2 = R3 = 5kΩ MAX116: R1 = R2 = 5kΩ, R3 = ∞ SAR Figure 3. Equivalent Input Circuit The conversion timing and control sequences are derived from either an internal clock or an external clock, the CONVST signal, and the programmed mode. The T/H amplifiers hold the input voltages at the CONVST rising edge. Additional CONVST pulses are ignored until the last conversion for the sample is complete. An on-board sequencer converts one to four channels per CONVST pulse. In the default mode, one T/H output (CH1A) is converted. An interrupt signal (INT) is provided after the last conversion is complete. Convert two to four channels by reprogramming the MAX115/MAX116 through the bidirectional parallel interface. Once programmed, the MAX115/MAX116 continues to convert the specified number of channels per CONVST pulse until they are reprogrammed. The channels are converted sequentially, beginning with CH1. The INT signal always follows the end of the last conversion in a conversion sequence. The ADC converts each assigned channel in 2µs and stores the result in an internal 4 x 12-bit memory. At the end of the last conversion, INT goes low and the T/H amplifiers begin to track the inputs again. The data can be accessed by applying successive pulses to the RD pin. Successive reads access data words sequen8 tially. The memory is not random-access and data from CH1 is always read first. After performing four consecutive reads or initiating a new conversion, the address pointer selects CH1 again. Additional read pulses cycle through the data words. CS can be held low during successive reads. Input Bandwidth The T/H’s input tracking circuitry has a 10MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid highfrequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. Analog Input Range and Input Protection The MAX115’s input range is ±5V, and the MAX116’s input range is ±2.5V. The input resistance for the MAX115 is 10kΩ (typ), and the input resistance for the MAX116 is 1MΩ (typ). An input protection structure allows input voltages to ±17V without harming the IC. This protection is also active in shutdown mode. _______________________________________________________________________________________ 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs MAX115/MAX116 tCW CONVST tCONV INT tCWS CS tCRS RD tRD t WR WR tDA tDH DATA tAS tAH D ATA IN CH1 CH2 CH3 CH4 t RD tCRH tCWH tID tACQ Figure 4. Timing Diagram CS WR A0 (LSB) A1 acquisition time between conversions. The analog input appears as a 10k Ω resistor in parallel with a 16pF capacitor for the MAX115 and as a 1MΩ resistor in parallel with a 16pF capacitor for the MAX116. Between conversions, the buffer input is connected to channel 1 of the selected track/hold bank. When a channel is not selected, switches S1, S2, and S3 are placed in hold mode to improve channel-to-channel isolation. Digital Interface A2 A3 Figure 5. Programming a Four-Channel Conversion, Input Mux A Track/Holds The MAX115/MAX116 feature four simultaneous T/Hs. Each T/H has two multiplexed inputs. A T-switch input configuration provides excellent hold-mode isolation. Allow 600ns acquisition time for 12-bit accuracy. The T/H aperture delay is typically 10ns. The 500ps aperture-delay mismatch between the T/Hs allows the relative phase information of up to four different inputs to be preserved. Figure 3 shows the equivalent input circuit, illustrating the ADC’s sampling architecture. Only one of four T/H stages with its two multiplexed inputs (CH_A and CH_B) is shown. All switches are in track configuration for channel A. An internal buffer charges the hold capacitor to minimize the required Input data (A0–A3) and output data (D0–D11) are multiplexed on a three-state bidirectional interface. This parallel I/O can easily be interfaced with a microprocessor (µP) or DSP. CS, WR, and RD control the write and read operations. CS is the standard chip-select signal, which enables the controller to address the MAX115/MAX116 as an I/O port. When CS is high, it disables the WR and RD inputs and forces the interface into a high-Z state. Figure 4 details the interface timing. Programming Modes The MAX115/MAX116 have eight conversion modes plus power-down, which are programmed through a bidirectional parallel interface. At power-up, the devices default to the Input Mux A/Single-Channel Conversion mode. The user can select between two banks (mux inputs A or mux inputs B) of four simultaneous-sampled input channels, as illustrated in Figure 2. An internal microsequencer can be programmed to convert one to four channels of the selected bank per sample. For a single-channel conversion, CH1 is digitized, and then INT goes low to indicate completion of the conversion. 9 _______________________________________________________________________________________ 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs MAX115/MAX116 Table 1. Modes of Operation A3 0 0 0 0 0 0 0 0 1 X = Don’t care A2 0 0 0 0 1 1 1 1 X A1 0 0 1 1 0 0 1 1 X A0 0 1 0 1 0 1 0 1 X CONVERSION TIME (µs) 2 4 6 8 2 4 6 8 — MODE Input Mux A/Single-Channel Conversion (default at power-up) Input Mux A/Two-Channel Conversion Input Mux A/Three-Channel Conversion Input Mux A/Four-Channel Conversion Input Mux B/Single-Channel Conversion Input Mux B/Two-Channel Conversion Input Mux B/Three-Channel Conversion Input Mux B/Four-Channel Conversion Power-Down TO DAC REFOUT 7 (2.5V) 4.7µF AV = 1 REFIN 6 (2.5V) Starting a Conversion After programming the MAX115/MAX116 as outlined in the Programming Modes section, pulse CONVST low to initiate a conversion sequence. The analog inputs are sampled at the CONVST rising edge. Do not start a new conversion while the conversion is in progress. Monitor the INT output. A falling edge indicates the end of a conversion sequence. Reading a Conversion Digitized data from up to four channels is stored in memory to be read out through the parallel interface. After receiving an INT signal, the user can access up to four conversion results by performing up to four read operations. With C S low, the conversion results from CH1_ are accessed, and INT is reset high on the first RD falling edge. On the R D rising edge, the internal address pointer is advanced. If a single conversion is programmed, only one RD pulse is required. For multichannel conversions, up to four R D falling edges sequentially access the data for channels 1 through 4. For any number of channels converted, the address pointer is reset to CH1_ after four R D pulses. The address pointer also resets after receiving a CNVST pulse. Do not perform a read operation during conversion; it will corrupt the conversion’s accuracy. MAX115 MAX116 10kΩ 0.1µF 2.5V Figure 6. Internal Reference For multichannel conversions, INT goes low after the last channel has been digitized. To input data into the MAX115/MAX116, pull CS low, program the bidirectional pins A0–A3 (Table 1), and pulse WR low. Data is latched into the devices on the WR or CS rising edge. The ADC is now ready to convert. Once programmed, the ADC continues operating in the same mode until reprogrammed or until power is removed. Figure 5 shows an example of programming a four-channel conversion using Input Mux A. __________Applications Information Clock The MAX115/MAX116 have an internal 10MHz (typ) clock, which is activated by connecting CLK to DVDD (internal clock startup time is 165µs typ). The CLK input also accepts an external clock with duty cycle between 30% and 70%. 10 ______________________________________________________________________________________ 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs MAX115/MAX116 OUTPUT CODE 011 . . . 111 TO DAC REFOUT 7 (2.5V) 4.7µF 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 AV = 1 MAX115 MAX116 REFIN 6 (2.5V) OUT MAX6325 10k 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 - FS MAX115: FS = 2 x VREFOUT, 1LSB = 4VREFOUT 4096 MAX116: FS = VREFOUT, 1LSB = 2VREFOUT 4096 ZERO INPUT VOLTAGE (LSB) +FS - 1LSB 2.5V Figure 7. External Reference Figure 8. Bipolar Transfer Function Internal and External Reference The MAX115/MAX116 can be used with an internal or external reference voltage. An external +2.5 reference can be connected directly at REFIN. An internal buffer with a gain of +1 provides +2.5V at REFOUT. Internal Reference The full-scale range with the internal reference is ±5V for the MAX115 and ±2.5V for the MAX116. Bypass REFIN with a 0.1µF capacitor to AGND, and bypass the REFOUT pin with a 4.7µF (min) capacitor to AGND (Figure 6). The maximum value to compensate the reference buffer is 22µF. Larger values are acceptable if low-ESR capacitors are used. External Reference For operation over a wide temperature range, an external +2.5V reference with tighter specifications improves accuracy. The MAX6325 is an excellent choice to match the MAX115/MAX116 accuracy over the commercial and extended temperature ranges with a 1ppm/°C (max) temperature drift. Connect an external reference at REFIN as shown in Figure 7. The minimum impedance is 7kΩ for DC currents in both normal operation and shutdown. Bypass REFOUT with a 4.7µF lowESR capacitor. is Input Mux A/Single Channel Conversion. See the Programming Modes section if other configurations are desired. After the power supplies have been stabilized, the reset time is 5µs. No conversions should be performed during this phase. At power-up, data-in memory is undefined. Software Power-Down Software power-down is activated by setting bit A3 of the control word high (Table 1). It is asserted after the WR or CS rising edge, at which point the ADC immediately powers down to a low quiescent-current state. IAVDD and IAVSS drop to less than 1µA (typ), and IDVDD drops to 13µA (typ). The ADC circuitry and reference buffer are turned off, but the digital interface and the reference remain active for fast power-up recovery. Wake up the MAX115/MAX116 by writing a control word (A0–A3, Table 1). The bidirectional interface interprets a logic zero at A3 as the start signal, and powers up in the mode selected by A0, A1, and A2. The reference buffer’s settling time and the bypass capacitor’s value dominate the power-up delay. With the recommended 4.7µF at REFOUT, the power-up delay is typically 20ms. Power-On Reset When power is first applied, the internal power-on reset (POR) circuitry activates the MAX115/MAX116 with INT = high, ready to convert. The default conversion mode Transfer Function The MAX115/MAX116 have bipolar input ranges. Figure 8 shows the bipolar/output transfer function. Code transitions occur at successive-integer least significant bit 11 ______________________________________________________________________________________ 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs MAX115/MAX116 VCC VCC 1/2 HC74 PRE D CLR VCC A B C D (LSB) 0 1 2 3 RCO P0 P1 P2 P3 P4 EXTERNAL CLOCK P5 P6 P7 Q Q CLR ENP ENT LOAD HC688 HC161 RD INT P=Q VCC Q0 Q1 Q2 Q3 10kΩ Q4 Q5 Q6 Q7 G CH1 CH2 CH3 CH4 0 1 0 1 0 0 1 1 EXTERNAL CLOCK LATCH CLOCK (TO 16373 LATCH) Figure 9. Output Demultiplexer Circuit (LSB) values. Output coding is two-complement binary with 1LSB = 2.44mV for the MAX115 and 1LSB = 1.22mV for the MAX116. Motor-Control Applications Vector motor control requires monitoring of the individual phase currents. In their most basic application, the MAX115/MAX116 simultaneously sample two currents (CH1A and CH2A, Figure 10) and preserve the necessary relative phase information. Only two of the three phase currents have to be digitized because the third component can be mathematically derived with a coordinate transformation. The circuit of Figure 10 shows a typical vector motorcontrol application using all available inputs of the MAX115/MAX116. CH1A and CH2A are connected to two isolated Hall-effect current sensors and are a Output Demultiplexer An output demultiplexer circuit is useful for isolating data from one channel in a four-channel conversion sequence. Figure 9’s circuit uses the external 16MHz clock and the INT signal to generate four RD pulses and a latch clock to save data from the desired channel. CS must be low during the four RD pulses. The channel is selected with the binary coding of two switches. A 16-bit 16373 latch simplifies layout. 12 ______________________________________________________________________________________ 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs MAX115/MAX116 MAIN DC RESOLVER/ ENCODER EXTERNAL SETPOINTS CONTROLLER POWER STAGE AC AC MOTOR MOTOR R/E BUFFER 12 SIMULTANEOUS T/H CH1 B A AUX DSP MAX115 MAX116 CH2 B A MAIN DC 12 BIT ADC + MICROSEQUENCER CH3 B A TEMP VELOCITY FEEDBACK CH4 B µC Figure 10. Vector Motor Control part of the current (torque) feedback loop. The MAX115/MAX116 digitize the currents and deliver raw data to the following DSP and controller stages, where the vector processing takes place. Sensorless vector control uses a computer model for the motor and an algorithm to split each output current into its magnetizing (stator current) and torque-producing (rotor current) components. If a two-to-three phase conversion is not practical, three currents can be sampled simultaneously with the addition of a third sensor (not shown). Optional voltage (position) feedback can be derived by measuring two phase voltages (CH3A, CH4A). Typically, an isolated differential amplifier is used between the motor and the MAX115/MAX116. Again, the third phase voltage can be derived from the magnitude (phase voltage) and its relative phase. For optimum speed control and good load regulation close to zero speed, additional velocity and position feedback are derived from an encoder or resolver and brought to the MAX115/MAX116 at CH4B. The addi- tional channels can be used to evaluate slower analog inputs, such as the main DC bus voltage (CH2B), temperature sensors (CH3B), or other analog inputs (AUX, CH1B). VOLTAGE/POSITION FEEDBACK A CURRENT/TORQUE FEEDBACK Power-Supply Bypassing and Ground Management For optimum system performance, use printed circuit boards with separate analog and digital ground planes. Wire-wrapped boards are not recommended. Connect the two ground planes together at the low-impedance power-supply source. For the best ground connection, connect the DGND and AGND pins together and connect that point to the system analog ground plane to avoid interference from other digital noise sources. If DGND is connected to the system digital ground, digital noise may get through to the ADC’s analog portion. The AGND pins must be connected directly to a lowimpedance ground plane. Extra impedance between the pins and the ground plane increases crosstalk and degrades INL. ______________________________________________________________________________________ 13 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs MAX115/MAX116 Bypass AVDD and AVSS with 0.1µF ceramic capacitors to AGND. Mount them with short leads close to the device. Ferrite beads may also be used to further isolate the analog and digital power supplies. Bypass DVDD with a 0.1µF ceramic capacitor to DGND. Chip Information TRANSISTOR COUNT: 4116 SUBSTRATE CONNECTED TO AVSS PROCESS: BiCMOS ________________________________________________________Package Information SSOP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.