MAX1161BCPI

19-1190; Rev 0; 3/97 KIT ATION EVALU BLE AVAILA 10-Bit, 40Msps, TTL-Output ADC ____________________________Features o o o o o o Monolithic 40Msps Converter On-Chip Track/Hold Bipolar, ±2V Analog Input 57dB SNR at 3.58MHz Input 5pF Input Capacitance TTL Outputs _______________General Description The MAX1161 10-bit, monolithic analog-to-digital converter (ADC) is capable of 40Msps minimum word rates. An on-board track/hold ensures excellent dynamic performance without the need for external components. A 5pF input capacitance minimizes drive requirement problems. Inputs and outputs are TTL compatible. An overrange output is provided to indicate overflow conditions. Output data format is straight binary. Power dissipation is low at only 1W with +5V and -5.2V power-supply voltages. The MAX1161 also accepts wide, ±2V input voltages. The MAX1161 is available in 28-pin DIP and SO packages in the commercial temperature range. MAX1161 ________________________Applications Medical Imaging Professional Video Radar Receivers Instrumentation Digital Communications ______________Ordering Information PART MAX1161ACPI MAX1161BCPI MAX1161ACWI MAX1161BCWI TEMP. RANGE 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C PIN-PACKAGE 28 Wide Plastic DIP 28 Wide Plastic DIP 28 SO 28 SO ________________Functional Diagram ANALOG INPUT 4 COARSE ADC ANALOG PRESCALER __________________Pin Configuration TOP VIEW TOP VIEW DGND D0 D1 D2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 DVCC 27 VEE 26 AGND 25 VCC VFB VSB DECODING NETWORK T/H AMPLIFIER BANK D3 D4 DIGITAL OUTPUT D5 D6 D7 D8 D9 D10 DGND MAX1161 24 23 22 VRM 21 VIN 20 VST 19 18 17 16 15 VFT VCC AGND VEE CLK SUCCESSIVE INTERPOLATION STAGE i 10 SUCCESSIVE INTERPOLATION STAGE i + 1 . . . . SUCCESSIVE INTERPOLATION STAGE N DVCC DIP/SO 1 ________________________________________________________________ Maxim Integrated Products For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 10-Bit, 40Msps, TTL-Output ADC MAX1161 ABSOLUTE MAXIMUM RATINGS VCC ........................................................................................+6V VEE ..........................................................................................-6V Analog Input.......................................................VFB ≤ VIN ≤ VFT VFT, VFB ...........................................................................3V, -3V Reference-Ladder Current..................................................12mA CLK Input...............................................................................VCC Digital Outputs.....................................................30mA to -30mA Continuous Power Dissipation (TA = +70°C) Plastic DIP ........................................................................1.14W SO .........................................................................................1W Operating Temperature Range...............................0°C to +70°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec). ............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +5.0V, VEE = -5.2V, DVCC = +5.0V, VIN = ±2.0V, VSB = -2.0V, VST = +2.0V, fCLK = 40MHz, 50% clock duty cycle, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Resolution DC ACCURACY (±full scale, 250kHz sample rate, TA = +25°C) Integral Nonlinearity Differential Nonlinearity No Missing Codes ANALOG INPUT Input Voltage Range Input Bias Current Input Bias Current Input Resistance Input Resistance Input Capacitance Input Bandwidth Positive Full-Scale Error Negative Full-Scale Error REFERENCE INPUT Reference-Ladder Resistance Reference-Ladder Tempco TIMING CHARACTERISTICS Maximum Conversion Rate Overvoltage Recovery Time Pipeline Delay (Latency) Output Delay Aperture Delay Time Aperture Jitter Time Acquisition Time 2 TA = +25°C TA = +25°C TA = +25°C TA = +25°C VI V VI V V V V 14 1 5 12 40 20 1 18 14 1 5 12 40 20 1 18 MHz ns Clock Cycle ns ns ps-RMS ns VI V 500 800 0.8 500 800 0.8 Ω Ω/°C 3dB small signal TA = -55°C to +125°C VIN = 0V TA = -55°C to +125°C VI VI VI VI VI VI V V V 100 75 300 300 5 120 ±2.0 ±2.0 ±2.0 30 60 75 100 75 300 300 5 120 ±2.0 ±2.0 ±2.0 30 60 75 V µA µA kΩ kΩ pF MHz LSB LSB I I ±1.0 ±0.5 Guaranteed ±1.5 ±0.75 Guaranteed LSB LSB CONDITIONS TEST LEVEL MIN 10 MAX1161A TYP MAX MIN 10 MAX1161B TYP MAX UNITS Bits _______________________________________________________________________________________ 10-Bit, 40Msps, TTL-Output ADC ELECTRICAL CHARACTERISTICS (continued) (VCC = +5.0V, VEE = -5.2V, DVCC = +5.0V, VIN = ±2.0V, VSB = -2.0V, VST = +2.0V, fCLK = 40MHz, 50% clock duty cycle, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER DYNAMIC PERFORMANCE Effective Number of Bits (ENOB) fIN = 1MHz fIN = 3.58MHz fIN = 10.0MHz TA = +25°C fIN = 1MHz Signal-to-Noise Ratio (without harmonics) (SNR) TA = 0°C to +70°C, TA = -25°C to +85°C TA = +25°C fIN = 3.58MHz TA = 0°C to +70°C, TA = -25°C to +85°C TA = +25°C fIN = 10.0MHz TA = 0°C to +70°C, TA = -25°C to +85°C TA = +25°C fIN = 1MHz TA = 0°C to +70°C, TA = -25°C to +85°C TA = +25°C fIN = 3.58MHz TA = 0°C to +70°C, TA = -25°C to +85°C TA = +25°C fIN = 10.0MHz TA = 0°C to +70°C, TA = -25°C to +85°C TA = +25°C fIN = 1MHz Signal-to-Noise and Distortion Ratio (SINAD) TA = 0°C to +70°C, TA = -25°C to +85°C TA = +25°C fIN = 3.58MHz TA = 0°C to +70°C, TA = -25°C to +85°C TA = +25°C fIN = 10.0MHz Spurious-Free Dynamic Range (SFDR) Differential Phase Differential Gain TA = 0°C to +70°C, TA = -25°C to +85°C TA = +25°C TA = +25°C TA = +25°C I IV I IV I IV I IV I IV I IV I IV I IV I IV V V V 55 53 55 53 48 45 54 51 54 51 46 45 52 49 52 49 44 43 67 0.2 0.5 46 54 57 55 57 55 50 47 56 53 56 53 48 47 54 8.7 8.7 7.3 52 50 52 50 46 43 52 49 52 49 43 41 49 46 49 46 41 40 67 0.2 0.7 dB Degrees % 43 51 dB 54 52 54 52 48 45 54 51 54 51 45 44 51 dB dB 8.2 8.2 6.9 Bits CONDITIONS TEST LEVEL MAX1161A MIN TYP MAX MAX1161B MIN TYP MAX UNITS MAX1161 Total Harmonic Distortion (THD) fIN = 1MHz fIN = 3.58MHz, 4.35MHz fIN = 3.58MHz, 4.35MHz _______________________________________________________________________________________ 3 10-Bit, 40Msps, TTL-Output ADC MAX1161 ELECTRICAL CHARACTERISTICS (continued) (VCC = +5.0V, VEE = -5.2V, DVCC = +5.0V, VIN = ±2.0V, VSB = -2.0V, VST = +2.0V, fCLK = 40MHz, 50% clock duty cycle, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER DIGITAL INPUTS Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Pulse Width Low (CLK) Pulse Width High (CLK) DIGITAL OUTPUTS Logic 1 Voltage Logic 0 Voltage POWER-SUPPLY REQUIREMENTS VCC Voltages DVCC -VEE ICC Currents Power Dissipation Power-Supply Rejection TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. Unless otherwise noted, all tests are pulsed; therefore, Tj = TC = TA. CONDITIONS TEST LEVEL V V MAX1161A MIN TYP MAX 2.4 4.5 0.8 0 0 10 10 2.4 0.6 4.75 4.75 5.0 118 40 40 1.0 1.0 -4.95 -5.2 5.25 5.25 145 55 57 1.3 300 5 5 20 20 MAX1161B MIN TYP MAX 2.4 4.0 0.8 0 0 10 10 2.4 0.6 4.75 4.75 5.0 118 40 40 1.0 1.0 5.25 5.25 -5.45 145 55 57 1.3 300 5 5 20 20 UNITS V V µA µA ns ns V V TA = +25°C TA = +25°C IV IV IV IV IV IV IV IV IV VI VI VI VI V V -5.45 -4.95 -5.2 DICC -IEE VCC = 5V ±0.25V, VEE = -5.2V ±0.25V mA W LSB TEST LEVEL TEST PROCEDURE I 100% production tested at the specified temperature. II 100% production tested at TA = +25°C, and sample tested at the specified III IV V VI temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25°C. Parameter is guaranteed over specified temperature range. ______________________________________________________________Pin Description PIN 1, 13 2 3–10 11 12 14, 28 15 16, 27 NAME DGND D0 D1–D8 D9 D10 DVCC CLK VEE FUNCTION Digital Ground TTL Output (LSB) TTL Outputs TTL Output (MSB) TTL Output Overrange +5V Supply (digital) Clock -5.2V Supply (analog) PIN 17, 26 18, 25 19 20 21 22 23 24 NAME AGND VCC VFT VST VIN VRM VSB VFB FUNCTION Analog Ground +5V Supply (analog) Force for Top of Reference Ladder Sense for Top of Reference Ladder Analog Input Middle of Voltage Reference Ladder Sense for Bottom of Reference Ladder Force for Bottom of Reference Ladder 4 _______________________________________________________________________________________ 10-Bit, 40Msps, TTL-Output ADC __________________________________________Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) TOTAL HARMONIC DISTORTION vs. INPUT FREQUENCY MAX1161-01 MAX1161 SIGNAL-TO-NOISE vs. INPUT FREQUENCY MAX1161-02 SIGNAL-TO-NOISE AND DISTORTION vs. INPUT FREQUENCY fS = 40Msps 70 60 SINAD (dB) 50 40 30 20 MAX1161-03 80 fS = 40Msps 70 60 THD (dB) 50 40 30 20 1 10 INPUT FREQUENCY (MHz) 80 fS = 40Msps 70 60 SNR (dB) 50 40 30 20 80 100 1 10 INPUT FREQUENCY (MHz) 100 1 10 INPUT FREQUENCY (MHz) 100 SNR, THD, SINAD vs. SAMPLE RATE MAX1161-04 SNR, THD, SINAD vs. TEMPERATURE MAX1161-06 SPECTRAL RESPONSE fS = 40Msps fIN = 1MHz -30 AMPLITUDE (dB) MAX1161-05 80 fIN = 1MHz 70 SNR, THD, SINAD (dB) SNR 60 50 40 30 20 1 10 SAMPLE RATE (Msps) 65 0 60 SNR, THD, SINAD (dB) 55 SNR THD SINAD -60 THD SINAD 50 45 -90 fS = 40Msps fIN = 1MHz -120 -25 0 25 50 75 0 2 4 6 8 10 TEMPERATURE (°C) INPUT FREQUENCY (MHz) 40 100 _______________Detailed Description The MAX1161 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the MAX1161 in normal circuit operation. The following section provides a description of the pin functions, and outlines critical performance criteria to consider for achieving optimal device performance. Power Supplies and Grounding The MAX1161 requires -5.2V and +5V analog supply voltages. The +5V supply is common to analog VCC and digital DVCC. A ferrite bead in series with each supply line reduces the transient noise injected into the analog VCC. These beads should be connected as close to the device as possible. The connection between the beads and the MAX1161 should not be shared with any other device. Bypass each power-supply pin as close to the device as possible. Use 0.1µF for VEE and VCC, and 0.01µF for DVCC (chip capacitors are recommended). The MAX1161 has two grounds: AGND and DGND. These internal grounds are isolated on the device. Use ground planes for optimum device performance. Use DGND for the DVCC return path (typically 40mA) and for the return path for all digital output logic interfaces. Separate AGND and DGND from each other, connecting them together only through a ferrite bead at the device. 5 _______________________________________________________________________________________ 10-Bit, 40Msps, TTL-Output ADC MAX1161 N tpwH tpwL N+1 N+2 CLK td CLK td OUTPUT DATA DATA VALID N DATA VALID N+1 N-2 N-1 OUTPUT DATA DATA VALID Figure 1a. Timing Diagram Figure 1b. Single-Event Clock Table 1. Timing Parameters PARAMETER td tpwH tpwL DESCRIPTION CLK to Data Valid Propagation Delay CLK High Pulse Width CLK Low Pulse Width 10 10 MIN TYP 14 MAX 18 300 UNITS ns ns ns Connect a Schottky or hot carrier diode between AGND and VEE. The use of separate power supplies between VCC and DVCC is not recommended due to potential power-supply-sequencing latchup conditions. For optimum performance, use the recommended circuit shown in Figure 2. Voltage Reference The MAX1161 requires the use of two voltage references: VFT and VFB. VFT is the force for the top of the voltage-reference ladder (typically +2.5V); VFB (typically -2.5V) is the force for the bottom of the voltagereference ladder. Both voltages are applied across an 800Ω internal reference-ladder resistance. The +2.5V voltage source for reference VFT must be current limited to 20mA (max) if a different driving circuit is used in place of the recommended reference circuit shown in Figures 2 and 3. In addition, there are three referenceladder taps (VST, VRM, and VSB). VST is the sense for the top of the reference ladder (+2V), VRM is the midpoint of the ladder (typically 0V), and VSB is the sense for the bottom of the reference ladder (-2V). The voltages at VST and VSB are the device’s true full-scale input voltages when VFT and VFB are driven to the recommended voltages (+2.5V and -2.5V, respectively). These points should be used to monitor the device’s actual full-scale input range. When not being used, a decoupling capacitor of 0.01µF (chip carrier preferred) connected to AGND from each tap is recommended to minimize high-frequency noise injection. Figure 2 shows an example of a recommended reference-driver circuit. IC1 (MAX6225) is a +2.5V reference with 0.2% accuracy. Potentiometer R1 is 10kΩ and supports a minimum adjustable range of 0.6%. Use an OP07 or equivalent device for IC2. R2 and R3 must be matched to within 0.1% with good TC tracking to maintain 0.3LSB matching between VFT and VFB. If 0.1% matching is not met, then R4 can be used to adjust the VFB voltage to the desired level. Adjust VFT and VFB such that VST and VSB are exactly +2V and -2V, respectively. The analog input range scales proportionally with respect to the reference voltage if a different input range is required. The maximum scaling factor for device operation is ±20% of the recommended reference voltages of VFT and VFB. However, because the device is laser trimmed to optimize performance with ±2.5V references, its accuracy degrades if operated beyond a ±2% range. The following errors are defined: +FS error = top of ladder offset voltage = ∆ (+FS - VST + 1LSB) -FS error = bottom of ladder offset voltage = ∆ (-FS - VSB - 1LSB) where the +FS (full-scale) input voltage is defined as the output transition between 11 1111 1110 and 11 1111 1111, and the -FS input voltage is defined as the output transition between 00 0000 0000 and 00 0000 0001 (Table 2). 6 _______________________________________________________________________________________ 10-Bit, 40Msps, TTL-Output ADC MAX1161 CLK (TTL) VIN (±2V) +5V 1µF 4 CLK R5 100Ω ±2.5V MAX 2 VIN 6 IC1 VOUT 2.5V 1µF R2 30k 3 1 R4 10k 2 4 0.01µF 7 6 -2.5V 1µF = AGND = DGND C5 0.01µF AGND AGND VEE VEE VFB -5.2V R3 30k C4 0.01µF VIN VFT R ANALOG PRESCALER COARSE ADC MAX1161 4 MAX6225 GND VTRIM R1 10k 5 C2 0.01µF C1 VST 0.01µF D10 (OVERRANGE) D9 (MSB) D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) R SUCCESSIVE INTERPOLATION STAGE N DIGITAL OUTPUTS C3 0.01µF 2R VRM 2R 2R IC2 OP07 8 SUCCESSIVE INTERPOLATION STAGE 1 VSB +5V 0.01µF DGND C10 0.01µF C11 0.01µF NOTES: 1) D1 = SCHOTTKY OR HOT CARRIER DIODE 2) FB = FERRITE BEAD, FAIR RITE #2743001111 TO BE MOUNTED AS CLOSELY TO THE DEVICE AS POSSIBLE. THE FERRITE BEAD TO ADC CONNECTION SHOULD NOT BE SHARED WITH ANY OTHER DEVICE. 3) C1–C11 = CHIP CAPACITOR (RECOMMENDED) MOUNTED AS CLOSE TO DEVICE'S PIN AS POSSIBLE. 4) USE OF A SEPARATE SUPPLY FOR VCC AND DVCC IS NOT RECOMMENDED. 5) R5 PROVIDES CURRENT LIMITING TO 45mA. C6 0.1µF C7 0.1µF C8 0.1µF C9 0.1µF FB FB DGND DVCC DVCC VCC VCC DECODING NETWORK 2R FB D1 10µF -5.2V AGND 10µF +5V DGND Figure 2. Typical Operating Circuit Analog Input VIN is the analog input. The full-scale input range will be 80% of the reference voltage, or ±2V with VFB = -2.5V and VFT = +2.5V. The analog input’s drive requirements are minimal when compared to conventional flash converters. This is due to the MAX1161’s extremely low (5pF) input capacitance and very high (300kΩ) input resistance. For example, for an input signal of ±2Vp-p with a 10MHz input frequency, the peak output current required for the driving circuit is only 628µA. VCC VIN ANALOG PRESCALER VFT VEE Figure 3. Analog Equivalent Input Circuit _______________________________________________________________________________________ 7 10-Bit, 40Msps, TTL-Output ADC MAX1161 Table 2. Output Data Information ANALOG INPUT > +2V + 1/2LSB +2V - 1LSB 0.0V -2V + 1LSB < 2V OVERRANGE D10 1 0 0 0 0 OUTPUT CODE D9–D0 1 1 1 111 1111 1 1 1 111 111 Ø ØØ ØØØØ ØØØØ 00 0000 000 Ø 00 0000 0000 Digital Outputs The format of the output data (D0–D9) is straight binary (Table 2). The outputs are latched on the rising edge of CLK with a propagation delay typically at 14ns. There is a one-clock-cycle latency between CLK and the valid output data (Figure 1a). The digital outputs’ rise and fall times are not symmetrical. Typical propagation delay is 14ns for the rise time and 6ns for the fall time (Figure 5). The nonsymmetrical rise and fall times create approximately 8ns of invalid data. (Ø indicates the flickering bit between logic 0 and 1.) Clock Input The MAX1161 is driven from a single-ended TTL input (CLK). The CLK pulse width (t pwH ) must be kept between 10ns and 300ns to ensure proper operation of the internal track/hold amplifier (Figure 1a). When operating the MAX1161 at sampling rates above 3Msps, it is recommended that the clock input duty cycle be kept at 50% to optimize performance (Figure 4). The analog input signal is latched on the rising edge of CLK. The clock input must be driven from fast TTL logic (VIH ≤ 4.5V, tRISE