MAX11666

19-5530; Rev 4; 1/12 TION KIT EVALUA BLE ILA AVA 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs Features S 500ksps Conversion Rate, No Pipeline Delay S 12-/10-/8-Bit Resolution S 1-/2-Channel, Single-Ended Analog Inputs S Low-Noise 73dB SNR S Variable I/O: 1.5V to 3.6V (Dual-Channel Only) Allows the Serial Interface to Connect Directly to 1.5V, 1.8V, 2.5V, or 3V Digital Systems S 2.2V to 3.6V Supply Voltage S Low Power 3.3mW Very Low Power Consumption at 8µA/ksps S External Reference Input (Dual-Channel Devices Only) S 1.3µA Power-Down Current S SPI-/QSPI-/MICROWIRE-Compatible Serial Interface S 10-Pin, 3mm x 5mm µMAX Package S 6-Pin, 2.8mm x 2.9mm SOT23 Package S Wide -40NC to +125NC Operation General Description The MAX11661−MAX11666 are 12-/10-/8-bit, compact, low-power, successive approximation analog-to-digital converters (ADCs). These high-performance ADCs include a high-dynamic range sample-and-hold and a high-speed serial interface. These ADCs accept a full-scale input from 0V to the power supply or to the reference voltage. The MAX11662/MAX11664/MAX11666 feature dual, single-ended analog inputs connected to the ADC core using a 2:1 MUX. The devices also include a separate supply input for data interface and a dedicated input for reference voltage. In contrast, the single-channel devices generate the reference voltage internally from the power supply. These ADCs operate from a 2.2V to 3.6V supply and consume only 3.3mW. The devices include full powerdown mode and fast wake-up for optimal power management and a high-speed 3-wire serial interface. The 3-wire serial interface directly connects to SPI, QSPIK, and MICROWIRE® devices without external logic. Excellent dynamic performance, low voltage, low power, ease of use, and small package size make these converters ideal for portable battery-powered data-acquisition applications, and for other applications that demand low-power consumption and minimal space. These ADCs are available in a 10-pin FMAX® package, and a 6-pin SOT23 package. These devices operate over the -40NC to +125NC temperature range. MAX11661–MAX11666 Applications Data Acquisition Portable Data Logging Medical Instrumentation Battery-Operated Systems Communication Systems Automotive Systems Ordering Information PART MAX11661AUT+ MAX11662AUB+ MAX11663AUT+ MAX11664AUB+ MAX11665AUT+ MAX11666AUB+ MAX11666AUB/V+ PIN-PACKAGE 6 SOT23 10 FMAX-EP* 6 SOT23 10 FMAX-EP* 6 SOT23 10 FMAX-EP* 10 FMAX-EP* BITS 8 8 10 10 12 12 12 NO. OF CHANNELS 1 2 1 2 1 2 2 Note: All devices are specified over the -40°C to +125°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. /V denotes an automotive qualified part. QSPI is a trademark of Motorola, Inc. MICROWIRE is a registered trademark of National Semiconductor Corp. µMAX is a registered trademark of Maxim Integrated Products, Inc. _______________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11661–MAX11666 ABSOLUTE MAXIMUM RATINGS VDD to GND............................................................. -0.3V to +4V REF, OVDD, AIN1, AIN2, AIN to GND ........-0.3V to the lower of (VDD + 0.3V) and +4V CS, SCLK, CHSEL, DOUT TO GND ............-0.3V to the lower of (VOVDD + 0.3V) and +4V AGND to GND ...................................................... -0.3V to +0.3V Input/Output Current (all pins) ...........................................50mA Continuous Power Dissipation (TA = +70NC) 6-Pin SOT23 (derate 8.7mW/NC above +70NC) ......... ..696mW 10-Pin FMAX (derate 8.8mW/NC above +70NC)...... ..707.3mW Operating Temperature Range ....................... .-40NC to +125NC Junction Temperature .....................................................+150NC Storage Temperature Range............................ -65NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (MAX11666) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD. fSCLK = 8MHz, 50% duty cycle, 500ksps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Total Unadjusted Error Channel-to-Channel Offset Matching Channel-to-Channel Gain Matching DYNAMIC PERFORMANCE (fAIN = 250kHz) Signal-to-Noise and Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth Small-Signal Bandwidth Crosstalk SINAD SNR THD SFDR IMD f1 = 239.8kHz, f2 = 200.2kHz -3dB point SINAD > 68dB 75.5 70 70.5 72 72.5 -85 85 -84 40 2.5 45 -90 -74.5 dB dB dB dB dB MHz MHz MHz dB INL DNL OE GE TUE Excluding offset and reference errors No missing codes Q0.3 Q1 Q1 Q0.4 Q0.05 12 Q1 Q1 Q4 Q3 Bits LSB LSB LSB LSB LSB LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS 2 ______________________________________________________________________________________ 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11666) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD. fSCLK = 8MHz, 50% duty cycle, 500ksps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER CONVERSION RATE Throughput Conversion Time Acquisition Time Aperture Delay Aperture Jitter Serial-Clock Frequency ANALOG INPUT (AIN1, AIN2) Input Voltage Range Input Leakage Current Input Capacitance VAIN_ IILA CAIN_ Track Hold 0 0.002 20 4 VDD + 0.05 0.005 5 0.75 x VOVDD 0.25 x VOVDD 0.15 x VOVDD Inputs at GND or VDD 0.001 2 0.85 x VOVDD 0.15 x VOVDD Q1.0 4 Q1 Q1 VREF Q1 V FA pF fCLK 0.08 tACQ From CS falling edge 5 1.56 52 4 15 8 500 ksps Fs ns Fs ps MHz SYMBOL CONDITIONS MIN TYP MAX UNITS MAX11661–MAX11666 EXTERNAL REFERENCE INPUT (REF) Reference Input Voltage Range Reference Input Leakage Current Reference Input Capacitance VREF IILR CREF Conversion stopped 1 V FA pF DIGITAL INPUTS (SCLK, CS, CHSEL) Digital Input High Voltage Digital Input Low Voltage Digital Input Hysteresis Digital Input Leakage Current Digital Input Capacitance DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage High-Impedance Leakage Current High-Impedance Output Capacitance VOH VOL IOL COUT ISOURCE = 200FA ISINK = 200FA V V FA pF VIH VIL VHYST IIL CIN V V V FA pF _______________________________________________________________________________________ 3 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11661–MAX11666 ELECTRICAL CHARACTERISTICS (MAX11666) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD. fSCLK = 8MHz, 50% duty cycle, 500ksps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER POWER SUPPLY Positive Supply Voltage Digital I/O Supply Voltage Positive Supply Current (Full-Power Mode) Positive Supply Current (FullPower Mode), No Clock Power-Down Current Line Rejection TIMING CHARACTERISTICS (Note 2) Quiet Time CS Pulse Width CS Fall to SCLK Setup CS Falling Until DOUT HighImpedance Disabled Data Access Time After SCLK Falling Edge SCLK Pulse Width Low SCLK Pulse Width High Data Hold Time From SCLK Falling Edge SCLK Falling Until DOUT High Impedance Power-Up Time tQ t1 t2 t3 t4 t5 t6 t7 t8 (Note 3) (Note 3) (Note 3) (Note 3) Figure 2, VOVDD = 2.2V to 3.6V Figure 2, VOVDD = 1.5V to 2.2V Percentage of clock period (Note 3) Percentage of clock period (Note 3) Figure 3 Figure 4 (Note 3) Conversion cycle (Note 3) 40 40 5 2.5 14 1 4 10 5 1 15 16.5 60 60 ns ns ns ns ns % % ns ns Cycle VDD VOVDD IVDD IOVDD IVDD IPD Leakage only VDD = 2.2V to 3.6V, VREF = 2.2V VAIN_ = VGND VAIN_ = VGND 1.5 1.3 0.7 10 2.2 1.5 3.6 VDD 1.67 0.1 V V mA mA FA LSB/V SYMBOL CONDITIONS MIN TYP MAX UNITS ELECTRICAL CHARACTERISTICS (MAX11665) (VDD = 2.2V to 3.6V, fSCLK = 8MHz, 50% duty cycle, 500ksps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Total Unadjusted Error Signal-to-Noise and Distortion Signal-to-Noise Ratio INL DNL OE GE TUE SINAD SNR 70 70.5 Excluding offset and reference errors No missing codes Q1.5 Q1 Q1.5 72.5 73 12 Q1 Q1 Q4 Q3 Bits LSB LSB LSB LSB LSB dB dB SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE (fAIN = 250kHz) 4 ______________________________________________________________________________________ 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11665) (continued) (VDD = 2.2V to 3.6V, fSCLK = 8MHz, 50% duty cycle, 500ksps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth Small-Signal Bandwidth CONVERSION RATE Throughput Conversion Time Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency ANALOG INPUT Input Voltage Range Input Leakage Current Input Capacitance VAIN IILA CAIN Track Hold 0.75 x VVDD 0.25 x VVDD 0.15 x VVDD Inputs at GND or VDD 0.001 2 0.85 x VVDD 0.15 x VVDD Q1.0 4 Q1 0 0.002 20 4 VDD Q1 V FA pF fCLK 0.08 tACQ From CS falling edge 5 1.56 52 4 15 8 500 ksps Fs ns ns ps MHz SYMBOL THD SFDR IMD f1 = 239.8kHz, f2 = 200.2kHz -3dB point SINAD > 68dB 77 CONDITIONS MIN TYP -85 85 -84 40 2.5 45 MAX -76 UNITS dB dB dB MHz MHz MHz MAX11661–MAX11666 DIGITAL INPUTS (SCLK, CS, CHSEL) Digital Input High Voltage Digital Input Low Voltage Digital Input Hysteresis Digital Input Leakage Current Digital Input Capacitance DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage High-Impedance Leakage Current High-Impedance Output Capacitance POWER SUPPLY Positive Supply Voltage Positive Supply Current (Full-Power Mode) VDD IVDD VAIN = VGND 2.2 3.6 1.76 V mA VOH VOL IOL COUT ISOURCE = 200FA ISINK = 200FA V V FA pF VIH VIL VHYST IIL CIN V V V FA pF _______________________________________________________________________________________ 5 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11661–MAX11666 ELECTRICAL CHARACTERISTICS (MAX11665) (continued) (VDD = 2.2V to 3.6V, fSCLK = 8MHz, 50% duty cycle, 500ksps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER Positive Supply Current (FullPower Mode), No Clock Power-Down Current Line Rejection TIMING CHARACTERISTICS (Note 2) Quiet Time CS Pulse Width CS Fall to SCLK Setup CS Falling Until DOUT HighImpedance Disabled Data Access Time After SCLK Falling Edge SCLK Pulse Width Low SCLK Pulse Width High Data Hold Time From SCLK Falling Edge SCLK Falling Until DOUT High Impedance Power-Up Time tQ t1 t2 t3 t4 t5 t6 t7 t8 (Note 3) (Note 3) (Note 3) (Note 3) Figure 2, VDD = 2.2V to 3.6V Percentage of clock period (Note 3) Percentage of clock period (Note 3) Figure 3 Figure 4 (Note 3) Conversion cycle (Note 3) 40 40 5 2.5 14 1 4 10 5 1 15 60 60 ns ns ns ns ns % % ns ns Cycle SYMBOL IVDD IPD Leakage only VDD = 2.2V to 3.6V CONDITIONS MIN TYP 1.48 1.3 0.7 10 MAX UNITS mA FA LSB/V ELECTRICAL CHARACTERISTICS (MAX11664) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 8MHz, 50% duty cycle, 500ksps; CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Total Unadjusted Error Channel-to-Channel Offset Matching Channel-to-Channel Gain Matching DYNAMIC PERFORMANCE (fAIN = 250kHz) Signal-to-Noise and Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range SINAD SNR THD SFDR 75 60.5 60.5 61.6 61.6 -83 -73 dB dB dB dB INL DNL OE GE TUE Excluding offset and reference errors No missing codes Q0.5 0 Q0.5 Q0.1 Q0.05 10 Q0.5 Q0.5 Q1.3 Q1.3 Bits LSB LSB LSB LSB LSB LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS 6 ______________________________________________________________________________________ 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11664) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 8MHz, 50% duty cycle, 500ksps; CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth Small-Signal Bandwidth Crosstalk CONVERSION RATE Throughput Conversion Time Acquisition Time Aperture Delay Aperture Jitter Serial-Clock Frequency ANALOG INPUT (AIN1, AIN2) Input Voltage Range Input Leakage Current Input Capacitance VAIN_ IILA CAIN-_ Track Hold 0 0.002 20 4 VDD + 0.05 0.005 5 0.75 x VOVDD 0.25 x VOVDD 0.15 x VOVDD Inputs at GND or VDD 0.001 2 0.85 x VOVDD 0.15 x VOVDD Q1.0 4 Q1 Q1 VREF Q1 V FA pF fCLK 0.08 tACQ From CS falling edge 5 1.56 52 4 15 8 500 ksps Fs ns ns ps MHz SYMBOL IMD -3dB point SINAD > 60dB CONDITIONS f1 = 239.8kHz, f2 = 200.2kHz MIN TYP -82 40 2.5 45 -90 MAX UNITS dB MHz MHz MHz dB MAX11661–MAX11666 EXTERNAL REFERENCE INPUT (REF) Reference Input Voltage Range Reference Input Leakage Current Reference Input Capacitance VREF IILR CREF Conversion stopped 1 V FA pF DIGITAL INPUTS (SCLK, CS, CHSEL) Digital Input High Voltage Digital Input Low Voltage Digital Input Hysteresis Digital Input Leakage Current Digital Input Capacitance DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage High-Impedance Leakage Current High-Impedance Output Capacitance VOH VOL IOL COUT ISOURCE = 200µA ISINK = 200µA V V FA pF VIH VIL VHYST IIL CIN V V V FA pF _______________________________________________________________________________________ 7 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11661–MAX11666 ELECTRICAL CHARACTERISTICS (MAX11664) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 8MHz, 50% duty cycle, 500ksps; CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER POWER SUPPLY Positive Supply Voltage Digital I/O Supply Voltage Positive Supply Current (Full-Power Mode) Positive Supply Current (Full-Power Mode), No Clock Power-Down Current Line Rejection TIMING CHARACTERISTICS (Note 2) Quiet Time CS Pulse Width CS Fall to SCLK Setup CS Falling Until DOUT HighImpedance Disabled Data Access Time After SCLK Falling Edge (Figure 2) SCLK Pulse Width Low SCLK Pulse Width High Data Hold Time From SCLK Falling Edge SCLK Falling Until DOUT High Impedance Power-Up Time tQ t1 t2 t3 t4 t5 t6 t7 t8 (Note 3) (Note 3) (Note 3) (Note 3) VOVDD = 2.2V to 3.6V VOVDD = 1.5V to 2.2V Percentage of clock period (Note 3) Percentage of clock period (Note 3) Figure 3 Figure 4 (Note 3) Conversion cycle (Note 3) 40 40 5 2.5 14 1 4 10 5 1 15 16.5 60 60 ns ns ns ns ns % % ns ns Cycle VDD VOVDD IVDD IOVDD IVDD IPD Leakage only VDD = 2.2V to 3.6V, VREF = 2.2V VAIN_ = VGND VAIN_ = VGND 1.5 1.3 0.17 10 2.2 1.5 3.6 VDD 1.67 0.1 V V mA mA FA LSB/V SYMBOL CONDITIONS MIN TYP MAX UNITS ELECTRICAL CHARACTERISTICS (MAX11663) (VDD = 2.2V to 3.6V. fSCLK = 8MHz, 50% duty cycle, 500ksps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Total Unadjusted Error INL DNL OE GE TUE Excluding offset and reference errors No missing codes Q0.3 Q0.15 Q1 10 Q0.5 Q0.5 Q1.3 Q1.3 Bits LSB LSB LSB LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS 8 ______________________________________________________________________________________ 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11663) (continued) (VDD = 2.2V to 3.6V. fSCLK = 8MHz, 50% duty cycle, 500ksps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER Signal-to-Noise and Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth Small-Signal Bandwidth CONVERSION RATE Throughput Conversion Time Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency ANALOG INPUT (AIN) Input Voltage Range Input Leakage Current Input Capacitance VAIN IILA CAIN Track Hold 0.75 x VVDD 0.25 x VVDD 0.15 x VVDD Inputs at GND or VDD 0.001 2 Q1 0 0.002 20 4 VDD Q1 V FA pF fCLK 0.08 tACQ From CS falling edge 5 1.56 52 4 15 8 500 ksps Fs ns ns ps MHz SYMBOL SINAD SNR THD SFDR IMD f1 = 239.8kHz, f2 = 200.2kHz -3dB point SINAD > 60dB 75 -82 40 2.5 45 CONDITIONS MIN 60.5 60.5 TYP 61.5 61.5 -85 -73 MAX UNITS dB dB dB dB dB MHz MHz MHz DYNAMIC PERFORMANCE (fAIN = 250kHz) MAX11661–MAX11666 DIGITAL INPUTS (SCLK, CS, CHSEL) Digital Input High Voltage Digital Input Low Voltage Digital Input Hysteresis Digital Input Leakage Current Digital Input Capacitance VIH VIL VHYST IIL CIN V V V FA pF _______________________________________________________________________________________ 9 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11661–MAX11666 ELECTRICAL CHARACTERISTICS (MAX11663) (continued) (VDD = 2.2V to 3.6V. fSCLK = 8MHz, 50% duty cycle, 500ksps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage High-Impedance Leakage Current High-Impedance Output Capacitance POWER SUPPLY Positive Supply Voltage Positive Supply Current (Full-Power Mode) Positive Supply Current (Full-Power Mode), No Clock Power-Down Current Line Rejection TIMING CHARACTERISTICS (Note 2) Quiet Time CS Pulse Width CS Fall to SCLK Setup CS Falling Until DOUT HighImpedance Disabled Data Access Time After SCLK Falling Edge SCLK Pulse Width Low SCLK Pulse Width High Data Hold Time From SCLK Falling Edge SCLK Falling Until DOUT High Impedance Power-Up Time tQ t1 t2 t3 t4 t5 t6 t7 t8 (Note 3) (Note 3) (Note 3) (Note 3) Figure 2, VDD = 2.2V to 3.6V Percentage of clock period (Note 3) Percentage of clock period (Note 3) Figure 3 Figure 4 (Note 3) Conversion cycle (Note 3) 40 40 5 2.5 14 1 4 10 5 1 15 60 60 ns ns ns ns ns % % ns ns Cycle VDD IVDD IVDD IPD Leakage only VDD = 2.2V to 3.6V VAIN = VGND 1.48 1.3 0.17 10 2.2 3.6 1.76 V mA mA FA LSB/V VOH VOL IOL COUT 4 ISOURCE = 200µA ISINK = 200µA 0.85 x VVDD 0.15 x VVDD Q1.0 V V FA pF SYMBOL CONDITIONS MIN TYP MAX UNITS 10 _____________________________________________________________________________________ 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11662) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 8MHz, 50% duty cycle, 500ksps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Total Unadjusted Error Channel-to-Channel Offset Matching Channel-to-Channel Gain Matching DYNAMIC PERFORMANCE (fAIN = 250kHz) Signal-to-Noise and Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth Small-Signal Bandwidth Crosstalk CONVERSION RATE Throughput Conversion Time Acquisition Time Aperture Delay Aperture Jitter Serial-Clock Frequency ANALOG INPUT (AIN1, AIN2) Input Voltage Range Input Leakage Current Input Capacitance VAIN_ IILA CAIN_ Track Hold 0 0.002 20 4 VDD + 0.05 0.005 5 Q1 VREF Q1 V FA pF fCLK 0.08 tACQ From CS falling edge 5 1.56 52 4 15 8 500 ksps Fs ns ns ps MHz SINAD SNR THD SFDR IMD f1 = 239.8kHz, f2 = 200.2kHz -3dB point SINAD > 49dB 63 49 49 49.7 49.7 -75 67 -65 40 2.5 45 -90 -67 dB dB dB dB dB MHz MHz MHz dB INL DNL OE GE TUE Excluding offset and reference errors No missing codes 0.45 0 0.5 0.01 0.01 8 Q0.25 Q0.25 Q0.8 Q0.25 Bits LSB LSB LSB LSB LSB LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS MAX11661–MAX11666 EXTERNAL REFERENCE INPUT (REF) Reference Input Voltage Range Reference Input Leakage Current Reference Input Capacitance VREF IILR CREF Conversion stopped 1 V FA pF ______________________________________________________________________________________ 11 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11661–MAX11666 ELECTRICAL CHARACTERISTICS (MAX11662) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 8MHz, 50% duty cycle, 500ksps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER DIGITAL INPUTS (SCLK, CS) Digital Input High Voltage Digital Input Low Voltage Digital Input Hysteresis Digital Input Leakage Current Digital Input Capacitance DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage High-Impedance Leakage Current High-Impedance Output Capacitance POWER SUPPLY Positive Supply Voltage Digital I/O Supply Voltage Positive Supply Current (Full-Power Mode) Positive Supply Current (Full-Power Mode), No Clock Power-Down Current Line Rejection TIMING CHARACTERISTICS (Note 2) Quiet Time CS Pulse Width CS Fall to SCLK Setup CS Falling Until DOUT HighImpedance Disabled Data Access Time After SCLK Falling Edge (Figure 2) SCLK Pulse Width Low SCLK Pulse Width High Data Hold Time From SCLK Falling Edge SCLK Falling Until DOUT High Impedance Power-Up Time tQ t1 t2 t3 t4 t5 t6 t7 t8 (Note 3) (Note 3) (Note 3) (Note 3) VOVDD = 2.2V to 3.6V (Note 3) VOVDD = 1.5V to 2.2V (Note 3) Percentage of clock period Percentage of clock period Figure 3 Figure 4 (Note 3) Conversion cycle (Note 3) 40 40 5 2.5 14 1 4 10 5 1 15 16.5 60 60 ns ns ns ns ns % % ns ns Cycle VOH VOL IOL COUT VDD VOVDD IVDD IOVDD IVDD IPD Leakage only VDD = 2.2V to 3.6V, VREF = 2.2V VAIN_ = VGND VAIN_ = VGND 1.5 1.3 0.17 10 2.2 1.5 4 3.6 VDD 1.67 0.1 ISOURCE = 200µA (Note 3) ISINK = 200µA (Note 3) 0.85 x VOVDD 0.15 x VOVDD Q1.0 V V FA pF V V mA mA FA LSB/V VIH VIL VHYST IIL CIN Inputs at GND or VDD 0.15 x VOVDD 0.001 2 Q1 0.75 x VOVDD 0.25 x VOVDD V V V FA pF SYMBOL CONDITIONS MIN TYP MAX UNITS 12 _____________________________________________________________________________________ 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11661) (VDD = 2.2V to 3.6V. fSCLK = 8MHz, 50% duty cycle, 500ksps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Total Unadjusted Error Signal-to-Noise and Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth Small-Signal Bandwidth CONVERSION RATE Throughput Conversion Time Acquisition Time Aperture Delay Aperture Jitter Serial-Clock Frequency ANALOG INPUT (AIN) Input Voltage Range Input Leakage Current Input Capacitance DIGITAL INPUTS (SCLK, CS) Digital Input High Voltage Digital Input Low Voltage Digital Input Hysteresis Digital Input Leakage Current Digital Input Capacitance VIH VIL VHYST IIL CIN Inputs at GND or VDD 0.15 VVDD 0.001 2 Q1 0.75 x VVDD 0.25 x VVDD V V V FA pF VAIN IILA CAIN Track Hold 0 0.002 20 4 VDD Q1 V FA pF fCLK 0.08 tACQ From CS falling edge 5 1.56 52 4 15 8 500 ksps Fs ns ns ps MHz INL DNL OE GE TUE SINAD SNR THD SFDR IMD f1 = 239.8kHz, f2 = 200.2kHz -3dB point SINAD > 49dB 63 49 49 Excluding offset and reference errors No missing codes Q0.45 Q0.04 Q0.75 49.5 49.5 -70 66 -65 40 2.5 45 -67 8 Q0.25 Q0.25 Q0.8 Q0.5 Bits LSB LSB LSB LSB LSB dB dB dB dB dB MHz MHz MHz SYMBOL CONDITIONS MIN TYP MAX UNITS MAX11661–MAX11666 DYNAMIC PERFORMANCE (fAIN = 250kHz) ______________________________________________________________________________________ 13 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11661–MAX11666 ELECTRICAL CHARACTERISTICS (MAX11661) (continued) (VDD = 2.2V to 3.6V. fSCLK = 8MHz, 50% duty cycle, 500ksps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage High-Impedance Leakage Current High-Impedance Output Capacitance POWER SUPPLY Positive Supply Voltage Positive Supply Current (Full-Power Mode) Positive Supply Current (Full-Power Mode), No Clock Power-Down Current Line Rejection TIMING CHARACTERISTICS (Note 2) Quiet Time CS Pulse Width CS Fall to SCLK Setup CS Falling Until DOUT HighImpedance Disabled Data Access Time After SCLK Falling Edge SCLK Pulse Width Low SCLK Pulse Width High Data Hold Time From SCLK Falling Edge SCLK Falling Until DOUT High Impedance Power-Up Time tQ t1 t2 t3 t4 t5 t6 t7 t8 (Note 3) (Note 3) (Note 3) (Note 3) Figure 2, VDD = 2.2V to 3.6V Percentage of clock period (Note 3) Percentage of clock period (Note 3) Figure 3 Figure 4 (Note 3) Conversion cycle (Note 3) 40 40 5 2.5 14 1 4 10 5 1 15 60 60 ns ns ns ns ns % % ns ns Cycle VDD IVDD IVDD IPD Leakage only VDD = 2.2V to 3.6V VAIN = VGND 1.48 1.3 0.17 10 2.2 3.6 1.76 V mA mA FA LSB/V VOH VOL IOL COUT 4 ISOURCE = 200µA ISINK = 200µA 0.85 x VVDD 0.15 x VVDD Q1.0 V V FA pF SYMBOL CONDITIONS MIN TYP MAX UNITS Note 1: Limits at TA = -40NC are guaranteed by design and not production tested. Note 2: All timing specifications given are with a 10pF capacitor. Note 3: Guaranteed by design in characterization; not production tested. 14 _____________________________________________________________________________________ 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11661–MAX11666 SAMPLE SAMPLE t1 CS t2 SCLK 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 t6 t5 DOUT HIGH IMPEDANCE t3 0 D11 (MSB) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 HIGH IMPEDANCE t8 tQUIET t4 t7 tCONVERT 1/fSAMPLE tACQ Figure 1. Interface Signals for Maximum Throughput, 12-Bit Devices t4 SCLK SCLK t7 VIH DOUT OLD DATA NEW DATA VIL DOUT VIH VIL OLD DATA NEW DATA Figure 2. Setup Time After SCLK Falling Edge Figure 3. Hold Time After SCLK Falling Edge t8 SCLK DOUT HIGH IMPEDANCE Figure 4. SCLK Falling Edge DOUT Three-State ______________________________________________________________________________________ 15 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11661–MAX11666 Typical Operating Characteristics (MAX11665AUT+, TA = +25°C, unless otherwise noted.) SOT23 TYPICAL OPERATING CHARACTERISTICS INTEGRAL NONLINEARITY (INL) vs. OUTPUT CODE MAX11661 toc01 DIFFERENTIAL NONLINEARITY (DNL) vs. OUTPUT CODE MAX11661 toc02 OFFSET ERROR vs. TEMPERATURE MAX11661 toc03 1.0 1.0 3 OFFSET ERROR (LSB) 0 1000 2000 3000 4000 DIGITAL OUTPUT CODE (DECIMAL) 0.5 INL (LSB) 0.5 DNL (LSB) 2 0 0 1 -0.5 -0.5 -1.0 0 1000 2000 3000 4000 DIGITAL OUTPUT CODE (DECIMAL) -1.0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) GAIN ERROR vs. TEMPERATURE MAX11661 toc04 SIGNAL-TO-NOISE RATIO (SNR) vs. ANALOG INPUT FREQUENCY MAX11661 toc05 2 76 1 GAIN ERROR (LSB) 74 0 SNR (dB) 72 -1 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 70 0 50 100 150 200 250 fIN (kHz) -2 THD vs. ANALOG INPUT FREQUENCY MAX11661 toc06 SPURIOUS-FREE DYNAMIC RANGE (SFDR) vs. ANALOG INPUT FREQUENCY MAX11661 toc07 -70 95 93 91 89 87 -80 SFDR (dB) -90 -100 0 50 100 150 200 250 fIN (kHz) THD (dB) 85 0 50 100 150 200 250 fIN (kHz) 16 _____________________________________________________________________________________ 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs Typical Operating Characteristics (continued) (MAX11665AUT+, TA = +25°C, unless otherwise noted.) MAX11661–MAX11666 SOT23 TYPICAL OPERATING CHARACTERISTICS SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) vs. ANALOG INPUT FREQUENCY MAX11661 toc08 100kHz SINE-WAVE INPUT fIN = 99.4kHz fS = 500ksps VDD = 3V MAX11661 toc09 76 0 -20 MAGNITUDE (dB) -40 -60 -80 -100 74 SINAD (dB) 72 AHD2 = - 88dB 70 0 50 100 150 200 250 fIN (kHz) -120 0 50 100 150 200 250 FREQUENCY (kHz) SUPPLY CURRENT vs. TEMPERATURE MAX11661 toc10 SIGNAL-TO-NOISE RATIO (SNR) vs. SUPPLY VOLTAGE (VDD) MAX11661 toc11 1.6 VDD = 3.6V 1.5 IVDD (mA) 75 VDD = 3V SNR (dB) 74 1.4 VDD = 2.2V 73 1.3 72 1.2 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 71 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDD (V) HISTOGRAM FOR 30,000 CONVERSIONS MAX11661 toc12 THD vs. INPUT RESISTANCE fS = 500ksps fIN = 250kHz MAX11661 toc13 35,000 30,000 25,000 CODE COUNT 20,000 15,000 10,000 5000 0 2046 2047 2048 2049 2050 DIGITAL CODE OUTPUT -75 -80 -85 -90 -95 -100 0 20 40 RIN (I) 60 80 THD (dB) 100 ______________________________________________________________________________________ 17 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11661–MAX11666 Pin Configurations TOP VIEW AIN1 AIN2 AGND REF VDD 1 2 3 4 5 TOP VIEW + MAX11662 MAX11664 MAX11666 EP* 10 9 8 7 6 SCLK DOUT OVDD CHSEL CS AIN 3 GND 2 VDD 1 + 6 CS MAX11661 MAX11663 MAX11665 5 DOUT 4 SCLK µMAX SOT23 *CONNECT EP TO GROUND PLANE. DEVICES DO NOT OPERATE WHEN EP IS NOT CONNECTED TO GROUND! Pin Description PIN µMAX 1 2 — — 3 4 SOT23 — — 3 2 — — NAME AIN1 AIN2 AIN GND AGND REF FUNCTION Analog Input Channel 1. Single-ended analog input with respect to AGND with range of 0V to VREF. Analog Input Channel 2. Single-ended analog input with respect to AGND with range of 0V to VREF. Analog Input Channel. Single-ended analog input with respect to GND with range of 0V to VDD. Ground. Connect GND to the GND ground plane. Analog Ground. Connect AGND directly the GND ground plane. External Reference Input. REF defines the signal range of the input signal AIN1/AIN2: 0V to VREF. The range of VREF is 1V to VDD. Bypass REF to AGND with 10FF || 0.1FF capacitor. Positive Supply Voltage. Bypass VDD with a 10FF || 0.1FF capacitor to GND. VDD range is 2.2V to 3.6V. For the SOT23 package, VDD also defines the signal range of the input signal AIN: 0V to VDD. Active-Low Chip-Select Input. The falling edge of CS samples the analog input signal, starts a conversion, and frames the serial-data transfer. Channel Select. Set CHSEL high to select AIN2 for conversion. Set CHSEL low to select AIN1 for conversion. Digital Interface Supply for SCLK, CS, DOUT, and CHSEL. The OVDD range is 1.5V to VDD. Bypass OVDD with a 10FF || 0.1FF capacitor to GND. Three-State Serial-Data Output. ADC conversion results are clocked out on the falling edge of SCLK, MSB first. See Figure 1. Serial-Clock Input. SCLK drives the conversion process. DOUT is updated on the falling edge of SCLK. See Figures 2 and 3. Exposed Pad (µMAX Only). Connect EP directly to a solid ground plane. Devices do not operate when EP is not connected to ground! 5 1 VDD 6 7 8 9 10 — 6 — — 5 4 — CS CHSEL OVDD DOUT SCLK EP 18 _____________________________________________________________________________________ 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs Functional Diagrams VDD OVDD VDD MAX11661–MAX11666 CS SCLK CONTROL LOGIC MAX11662 MAX11664 MAX11666 CS SCLK CONTROL LOGIC MAX11661 MAX11663 MAX11665 SAR OUTPUT BUFFER DOUT SAR OUTPUT BUFFER DOUT CHSEL AIN1 AIN2 REF AIN MUX CDAC CDAC VREF = VDD AGND GND (EP) GND Typical Operating Circuit VDD +3V AIN1 ANALOG INPUTS AIN2 AGND REF +2.5V GND (EP) MAX11662 MAX11664 MAX11666 OVDD VOVDD SCLK SCK CPU DOUT CS CHSEL MISO SS VDD +3V GND MAX11661 MAX11663 MAX11665 SCLK DOUT SCK MISO CPU ANALOG INPUT AIN CS SS ______________________________________________________________________________________ 19 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11661–MAX11666 Detailed Description The MAX11661–MAX11666 are fast, 12-/10-/8-bit, lowpower, single-supply ADCs. The devices operate from a 2.2V to 3.6V supply and consume only 2.98mW (VDD = 2.2V) or 4.37mW (VDD = 3V). These devices are capable of sampling at full rate when driven by an 8MHz clock. The dual-channel devices provide a separate digital supply input (OVDD) to power the digital interface enabling communication with 1.5V, 1.8V, 2.5V, or 3V digital systems. The conversion result appears at DOUT, MSB first, with a leading zero followed by the 12-bit, 10-bit, or 8-bit result. A 12-bit result is followed by two trailing zeros, a 10-bit result is followed by four trailing zeros, and an 8-bit result is followed by six trailing zeros. See Figures 1 and 5. The dual-channel devices feature a dedicated reference input (REF). The input signal range for AIN1/AIN2 is defined as 0V to VREF with respect to AGND. The single-channel devices use VDD as the reference. The input signal range of AIN is defined as 0V to VDD with respect to GND. These ADCs include a power-down feature allowing minimized power consumption at 2.5FA/ksps for lower SAMPLE throughput rates. The wake-up and power-down feature is controlled by using the SPI interface as described in the Operating Modes section. The devices feature a 3-wire serial interface that directly connects to SPI, QSPI, and MICROWIRE devices without external logic. Figures 1 and 5 show the interface signals for a single conversion frame to achieve maximum throughput. The falling edge of CS defines the sampling instant. Once CS transitions low, the external clock signal (SCLK) controls the conversion. The SAR core successively extracts binary-weighted bits in every clock cycle. The MSB appears on the data bus during the 2nd clock cycle with a delay outlined in the timing specifications. All extracted data bits appear successively on the data bus with the LSB appearing during the 13th/11th/9th clock cycle for 12-/10-/8-bit operation. The serial data stream of conversion bits is preceded by a leading “zero” and succeeded by trailing “zeros.” The data output (DOUT) goes into a high-impedance state during the 16th clock cycle. Serial Interface SAMPLE CS SCLK 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 DOUT HIGH IMPEDANCE 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 HIGH IMPEDANCE SAMPLE SAMPLE CS SCLK 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 DOUT HIGH IMPEDANCE 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 HIGH IMPEDANCE Figure 5. 10-/8-Bit Timing Diagrams 20 _____________________________________________________________________________________ 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs To sustain the maximum sample rate, all devices have to be resampled immediately after the 16th clock cycle. For lower sample rates, the CS falling edge can be delayed leaving DOUT in a high-impedance condition. Pull CS high after the 10th SCLK falling edge (see the Operating Modes section). The devices produce a digital output that corresponds to the analog input voltage within the specified operating range of 0V to VREF for the dual-channel devices and 0V to VDD for the single-channel devices. The source impedance of the external driving stage in conjunction with the sampling switch resistance affects the settling performance. The THD vs. Input Resistance graph in the Typical Operating Characteristics shows THD sensitivity as a function of the signal source impedance. Keep the source impedance at a minimum for high-dynamic-performance applications. Use a highperformance op amp such as the MAX4430 to drive the analog input, thereby decoupling the signal source and the ADC. While the ADC is in conversion mode, the sampling switch is open presenting a pin capacitance, CP (CP = 5pF), to the driving stage. See the Applications Information section for information on choosing an appropriate buffer for the ADC. The output format is straight binary. The code transitions midway between successive integer LSB values such as 0.5 LSB, 1.5 LSB, etc. The LSB size for singlechannel devices is VDD/2n and for dual-channel devices is VREF/2n, where n is the resolution. The ideal transfer characteristic is shown in Figure 10. The ICs offer two modes of operation: normal mode and power-down mode. The logic state of the CS signal during a conversion activates these modes. The powerdown mode can be used to optimize power dissipation with respect to sample rate. Normal Mode In normal mode, the devices are powered up at all times, thereby achieving their maximum throughput rates. Figure 7 shows the timing diagram of these devices in normal mode. The falling edge of CS samples the analog input signal, starts a conversion, and frames the serialdata transfer. MAX11661–MAX11666 Analog Input Figure 6 shows an equivalent circuit for the analog input AIN (for single-channel devices) and AIN1/AIN2 (for dual-channel devices). Internal protection diodes D1/D2 confine the analog input voltage within the power rails (VDD, GND). The analog input voltage can swing from GND - 0.3V to VDD + 0.3V without damaging the device. The electric load presented to the external stage driving the analog input varies depending on which mode the ADC is in: track mode vs. conversion mode. In track mode, the internal sampling capacitor CS (16pF) has to be charged through the resistor R (R = 50I) to the input voltage. For faithful sampling of the input, the capacitor voltage on CS has to settle to the required accuracy during the track time. ADC Transfer Function Operating Modes VDD D1 AIN1/AIN2 AIN CP D2 SWITCH CLOSED IN TRACK MODE SWITCH OPEN IN CONVERSION MODE R CS Figure 6. Analog Input Circuit KEEP CS LOW UNTIL AFTER THE 10TH SCLK FALLING EDGE CS PULL CS HIGH AFTER THE 10TH SCLK FALLING EDGE SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DOUT HIGH IMPEDANCE VALID DATA HIGH IMPEDANCE Figure 7. Normal Mode ______________________________________________________________________________________ 21 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11661–MAX11666 PULL CS HIGH AFTER THE 2ND AND BEFORE THE 10TH SCLK FALLING EDGE CS SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DOUT HIGH IMPEDANCE INVALID DATA INVALID DATA OR HIGH IMPEDANCE HIGH IMPEDANCE Figure 8. Entering Power-Down Mode CS SCLK DOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HIGH IMPEDANCE INVALID DATA (DUMMY CONVERSION) HIGH IMPEDANCE VALID DATA HIGH IMPEDANCE Figure 9. Exiting Power-Down Mode OUTPUT CODE 111...111 111...110 111...101 FS - 1.5 x LSB However, pulling CS high before the 10th SCLK falling edge terminates the conversion, DOUT goes into highimpedance mode, and the device enters power-down mode. See Figure 8. Power-Down Mode In power-down mode, all bias circuitry is shut down drawing typically only 1.3FA of leakage current. To save power, put the device in power-down mode between conversions. Using the power-down mode between conversions is ideal for saving power when sampling the analog input infrequently. Entering Power-Down Mode To enter power-down mode, drive CS high between the 2nd and 10th falling edges of SCLK (see Figure 8). By pulling CS high, the current conversion terminates and DOUT enters high impedance. Exiting Power-Down Mode To exit power-down mode, implement one dummy conversion by driving CS low for at least 10 clock cycles (see Figure 9). The data on DOUT is invalid during this dummy conversion. The first conversion following the dummy cycle contains a valid conversion result. The power-up time equals the duration of the dummy cycle, and is dependent on the clock frequency. The power-up time for 500ksps operation (8MHz SCLK) is 2Fs. 000...010 000...001 000...000 0 1 2 3 2n-2 2n-1 2n ANALOG INPUT (LSB) FULL SCALE (FS): AIN1/AIN2 = REF (TDFN, µMAX) AIN = VDD (SOT23) n = RESOLUTION Figure 10. ADC Transfer Function To remain in normal mode, keep CS low until the falling edge of the 10th SCLK cycle. Pulling CS high after the 10th SCLK falling edge keeps the part in normal mode. 22 _____________________________________________________________________________________ 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs For applications requiring lower throughput rates, the user can reduce the clock frequency (fSCLK) to lower the sample rate. Figure 11 shows the typical supply current (IVDD) as a function of sample rate (fS) for the 500ksps devices. The part operates in normal mode and Supply Current vs. Sampling Rate is never powered down. The user can also power down the ADC between conversions by using the power-down mode. Figure 12 shows for the 500ksps device that as the sample rate is reduced, the device remains in the power-down state longer and the average supply current (IVDD) drops accordingly. MAX11661–MAX11666 SUPPLY CURRENT vs. SAMPLING RATE 2.0 VDD = 3V fSCLK = VARIABLE 16 CYCLES/CONVERSIONS 1.5 SUPPLY CURRENT vs. SAMPLING RATE VDD = 3V fSCLK = 8MHz 1.5 IVDD (mA) 1.0 1.0 IVDD (mA) 0.5 0.5 0 0 100 200 300 400 500 0 20 40 60 80 100 120 140 160 SAMPLING RATE (ksps) SAMPLING RATE (ksps) 0 Figure 11. Supply Current vs. Sample Rate (Normal Operating Mode) Figure 12. Supply Current vs. Sample Rate (Device Powered Down Between Conversions) ______________________________________________________________________________________ 23 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11661–MAX11666 Dual-Channel Operation The MAX11662/MAX11664/MAX11666 feature dual-input channels. These devices use a channel-select (CHSEL) input to select between analog input AIN1 (CHSEL = 0) or AIN2 (CHSEL = 1). As shown in Figure 13, the CHSEL signal is required to change between the 2nd and 12th clock cycle within a regular conversion to guarantee proper switching between channels. The ICs can operate with 14 cycles per conversion. Figure 14 shows the corresponding timing diagram. Observe that DOUT does not go into high-impedance mode. Also, observe that tACQ needs to be sufficiently long to guarantee proper settling of the analog input voltage. See the Electrical Characteristics table for tACQ requirements and the Analog Input section for a description of the analog inputs. Applications Information For best performance, use PCBs with a solid ground plane. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another or digital lines underneath the ADC package. Noise in the VDD power supply, OVDD, and REF affects the ADC’s performance. Bypass the VDD, OVDD, and REF to ground with 0.1FF and 10FF bypass capacitors. Minimize capacitor lead and trace lengths for best supply-noise rejection. It is important to match the settling time of the input amplifier to the acquisition time of the ADC. The conversion results are accurate when the ADC samples the input signal for an interval longer than the input signal’s worst-case settling time. By definition, settling time is the interval between the application of an input voltage step and the point at which the output signal reaches Layout, Grounding, and Bypassing 14-Cycle Conversion Mode Choosing an Input Amplifier CS SCLK CHSEL DOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DATA CHANNEL AIN1 DATA CHANNEL AIN2 Figure 13. Channel Select Timing Diagram SAMPLE SAMPLE CS SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 DOUT 0 D11 (MSB) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 tACQ 0 0 1/fSAMPLE tCONVERT Figure 14. 14-Clock Cycle Operation 24 _____________________________________________________________________________________ 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs and stays within a given error band centered on the resulting steady-state amplifier output level. The ADC input sampling capacitor charges during the sampling cycle, referred to as the acquisition period. During this acquisition period, the settling time is affected by the input resistance and the input sampling capacitance. This error can be estimated by looking at the settling of an RC time constant using the input capacitance and the source impedance over the acquisition time period. Figure 15 shows a typical application circuit. The MAX4430, offering a settling time of 37ns at 16 bits, is an excellent choice for this application. See the THD vs. Input Resistance graph in the Typical Operating Characteristics. For devices using an external reference, the choice of the reference determines the output accuracy of the ADC. An ideal voltage reference provides a perfect initial accuracy and maintains the reference voltage independent of changes in load current, temperature, and time. Considerations in selecting a reference include initial voltage accuracy, temperature drift, current source, sink capability, quiescent current, and noise. Figure 15 shows a typical application circuit using the MAX6126 to provide the reference voltage. The MAX6033 and MAX6043 are also excellent choices. Choosing a Reference MAX11661–MAX11666 +5V 0.1µF 10µF 100pF C0G 500I 3V VDD 0.1µF 10µF VOVDD OVDD 0.1µF 10µF AIN1 500I 4 5 1 MAX4430 AGND AIN1 MAX11662 MAX11664 MAX11666 10I -5V 470pF C0G CAPACITOR VDC 3 2 0.1µF 10µF SCLK DOUT CS SCK MISO SS CPU AIN2 470pF C0G CAPACITOR REF +5V 10µF CHSEL EP +5V 0.1µF 10µF 7 100pF C0G 500I 0.1µF OUTF OUTS MAX6126 IN 2 1µF 0.1µF 6 AIN2 500I 4 4 5 1 MAX4430 GNDS GND NR 1 0.1µF 10I -5V 3 VDC 3 2 0.1µF 10µF Figure 15. Typical Application Circuit ______________________________________________________________________________________ 25 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11661–MAX11666 Definitions Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. For these devices, the straight line is a line drawn between the end points of the transfer function after offset and gain errors are nulled. Integral Nonlinearity SINAD is a dynamic figure of merit that indicates the converter’s noise and distortion performance. SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset: .   SIGNAL RMS SINAD(dB) 20 × log  =   (NOISE + DISTORTION) RMS    Signal-to-Noise Ratio and Distortion (SINAD) Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of ±1 LSB or less guarantees no missing codes and a monotonic transfer function. The deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, AGND + 0.5 LSB. The deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal after adjusting for the offset error, that is, VREF - 1.5 LSB. Differential Nonlinearity Offset Error Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as:  2 2 2 V 2 + V3 + V4 + V5  THD 20 × log 2 =     V1   where V1 is the fundamental amplitude and V2–V5 are the amplitudes of the 2nd- through 5th-order harmonics. SFDR is a dynamic figure of merit that indicates the lowest usable input signal amplitude. SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. SFDR is specified in decibels with respect to the carrier (dBc). Full-power bandwidth is the frequency at which the input signal amplitude attenuates by 3dB for a full-scale input. Full-linear bandwidth is the frequency at which the signal-to-noise ratio and distortion (SINAD) is equal to a specified value. Any device with nonlinearities creates distortion products when two sine waves at two different frequencies (f1 and f2) are applied into the device. Intermodulation distortion (IMD) is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones, f1 and f2. The individual input tone levels are at -6dBFS. Total Harmonic Distortion Gain Error Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. Aperture Jitter Aperture delay (tAD) is the time between the falling edge of sampling clock and the instant when an actual sample is taken. SNR is a dynamic figure of merit that indicates the converter’s noise performance. For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR (dB) (MAX) = (6.02 x N + 1.76) (dB) In reality, there are other noise sources such as thermal noise, reference noise, and clock jitter that also degrade SNR. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset. Aperture Delay Spurious-Free Dynamic Range (SFDR) Signal-to-Noise Ratio (SNR) Full-Power Bandwidth Full-Linear Bandwidth Intermodulation Distortion 26 _____________________________________________________________________________________ 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs Chip Information PROCESS: CMOS Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 10 µMAX 6 SOT23 PACKAGE CODE U10E+3 U6+1 OUTLINE NO. 21-0109 21-0058 LAND PATTERN NO. 90-0148 90-0175 MAX11661–MAX11666 ______________________________________________________________________________________ 27 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11661–MAX11666 Revision History REVISION NUMBER 0 1 2 3 4 REVISION DATE 11/10 1/11 6/11 11/11 1/12 Initial release Released the MAX11663 and updated Figures 11 and 12. Released the MAX11662/MAX11664/MAX11666. Updated the Electrical Characteristics. Updated the Electrical Characteristics, Figures 13 and 15. Updated Ordering Information. DESCRIPTION PAGES CHANGED — 1, 23 1–14 4, 5, 6, 8, 10, 12, 14, 24, 25 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 28 © Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.