MAX1180ECM

19-2097; Rev 0; 7/01 Dual 10-Bit, 105Msps, +3.3V, Low-Power ADC with Internal Reference and Parallel Outputs General Description The MAX1180 is a +3.3V, dual 10-bit, analog-to-digital converter (ADC) featuring fully-differential wideband track-and-hold (T/H) inputs, driving two pipelined, ninestage ADCs. The MAX1180 is optimized for low-power, high-dynamic performance applications in imaging, instrumentation, and digital communication applications. The MAX1180 operates from a single +2.7V to +3.6V supply, consuming only 413mW, while delivering a typical signal-to-noise ratio (SNR) of 58.5dB at an input frequency of 20MHz and a sampling rate of 105Msps. The T/H driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters may also be operated with single-ended inputs. In addition to low operating power, the MAX1180 features a 2.8mA sleep mode, as well as a 1µA power-down mode to conserve power during idle periods. An internal +2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of the internal or external reference, if desired for applications requiring increased accuracy or a different input voltage range. The MAX1180 features parallel, CMOS-compatible three-state outputs. The digital output format is set to two’s complement or straight offset binary through a single control pin. The device provides for a separate output power supply of +1.7V to +3.6V for flexible interfacing. The MAX1180 is available in a 7mm ✕ 7mm, 48pin TQFP package, and is specified for the extended industrial (-40°C to +85°C) temperature range. Pin-compatible higher and lower speed versions of the MAX1180 are also available. Please refer to the MAX1181 data sheet for 80Msps, the MAX1182 data sheet for 65Msps, the MAX1183 data sheet for 40Msps, and the MAX1184 data sheet for 20Msps. In addition to these speed grades, this family includes a 20Msps multiplexed output version (MAX1185), for which digital data is presented time-interleaved on a single, parallel 10-bit output port. Features o Single +3.3V Operation o Excellent Dynamic Performance: 58.5dB SNR at fIN = 20MHz 72dB SFDR at fIN = 20MHz o SNR Flat within 1dB for fIN = 202MHz to 100MHz o Low Power: 125mA (Normal Operation) 2.8mA (Sleep Mode) 1µA (Shutdown Mode) o 0.02dB Gain and 0.25° Phase Matching (typ) o Wide ±1Vp-p Differential Analog Input Voltage Range o 400MHz, -3dB Input Bandwidth o On-Chip +2.048V Precision Bandgap Reference o User-Selectable Output Format—Two’s Complement or Offset Binary o 48-Pin TQFP Package with Exposed Pad for Improved Thermal Dissipation MAX1180 Ordering Information PART MAX1180ECM TEMP. RANGE -40°C to +85°C PIN-PACKAGE 48 TQFP-EP Pin Configuration REFN REFP REFIN REFOUT D9A D8A D7A D6A D5A D4A D3A D2A 48 47 46 45 44 43 42 41 40 39 38 COM VDD GND INA+ INAVDD GND INBINB+ GND VDD CLK 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 D1A D0A OGND OVDD OVDD OGND D0B D1B D2B D3B D4B D5B Applications High Resolution Imaging I/Q Channel Digitization Multichannel IF Undersampling Instrumentation Video Application MAX1180 Functional Diagram appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products GND VDD VDD GND T/B SLEEP PD OE D9B D8B D7B D6B 48 TQFP-EP 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Dual 10-Bit, 105Msps, +3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1180 ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V INA+, INA-, INB+, INB- to GND ...............................-0.3V to VDD REFIN, REFOUT, REFP, REFN, CLK, COM to GND ............................................-0.3V to (VDD + 0.3V) OE, PD, SLEEP, T/B, D9A–D0A, D9B–D0B to OGND ................................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 48-Pin TQFP (derate 12.5mW/°C above +70°C).........1000mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +3.3V, OVDD = +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 5), fCLK = 105.263MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT Differential Input Voltage Range Common-Mode Input Voltage Range Input Resistance Input Capacitance CONVERSION RATE Maximum Clock Frequency Data Latency DYNAMIC CHARACTERISTICS (fCLK = 105.263MHz, 4096-point FFT) fINA or B = 7.47MHz, TA = +25°C Signal-to-Noise Ratio SNR fINA or B = 20MHz, TA = +25°C fINA or B = 50.078MHz (Note 1) Signal-to-Noise and Distortion (up to 5th harmonic) fINA or B = 7.47MHz, TA = +25°C SINAD fINA or B = 20MHz, TA = +25°C fINA or B = 50.078MHz (Note 1) Spurious-Free Dynamic Range fINA or B = 7.47MHz, TA = +25°C SFDR fINA or B = 20MHz, TA = +25°C fINA or B = 50.078MHz, (Note 1) fINA or B = 7.47MHz Third-Harmonic Distortion HD3 fINA or B = 20MHz fINA or B = 50.078MHz (Note 1) 60 54.7 55 59 58.5 58 58.2 58.1 57.6 72 72 70 -75 -75 -73 dBc dBc dB dB fCLK 105 5 MHz Clock Cycles VDIFF VCM RIN CIN Switched capacitor load Differential or single-ended inputs ±1.0 VDD/2 ± 0.5 20 5 V V kΩ pF INL DNL fIN = 7.47MHz fIN = 7.47MHz, no missing codes guaranteed -1 10 ±0.75 ±0.4 < ±1 0 ±2.5 +1.5 ±1.7 ±2 Bits LSB LSB % FS % FS SYMBOL CONDITIONS MIN TYP MAX UNITS 2 _______________________________________________________________________________________ Dual 10-Bit, 105Msps, +3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1180 ELECTRICAL CHARACTERISTICS (continued) (VDD = +3.3V, OVDD = +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 5), fCLK = 105.263MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Intermodulation Distortion (first five odd-order IMDs) Total Harmonic Distortion (first five harmonics) Small-Signal Bandwidth Full-Power Bandwidth Aperture Delay Aperture Jitter Overdrive Recovery Time Differential Gain Differential Phase Output Noise INTERNAL REFERENCE Reference Output Voltage Reference Temperature Coefficient Load Regulation BUFFERED EXTERNAL REFERENCE (VREFIN = +2.048V) REFIN Input Voltage VREFIN Positive Reference Output Voltage Negative Reference Output Voltage Differential Reference Output Voltage Range REFIN Resistance Maximum REFP, COM Source Current Maximum REFP, COM Sink Current Maximum REFN Source Current Maximum REFN Sink Current VREFP VREFN ∆VREF RREFIN ISOURCE ISINK ISOURCE ISINK ∆VREF = VREFP - VREFN 0.98 REFOUT TCREF 2.048 ±3% 60 1.25 2.048 2.162 1.138 1.024 >50 5 -250 250 -5 1.07 V ppm/°C mV/mA V V V V MΩ mA µA µA mA INA+ = INA- = INB+ = INB- = COM FPBW tAD tAJ For 1.5 ✕ full-scale input SYMBOL IMD CONDITIONS fINA or B = 38.055MHz at -6.5dB FS fINA or B = 42.926MHz at -6.5dB FS (Note 2) fINA or B = 7.47MHz, TA = +25°C fINA or B = 20MHz, TA = +25°C fINA or B = 50.078MHz, (Note 1) Input at -20dB FS, differential inputs Input at -0.5dB FS, differential inputs MIN TYP -74 -71 -70 -69 500 400 1 2 2 ±1 ±0.25 0.2 MHz MHz ns psRMS ns % degrees LSBRMS -59 dBc MAX UNITS dBc THD _______________________________________________________________________________________ 3 Dual 10-Bit, 105Msps, +3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1180 ELECTRICAL CHARACTERISTICS (continued) (VDD = +3.3V, OVDD = +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 5), fCLK = 105.263MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL RREFP, RREFN ∆VREF VCOM VREFP VREFN CONDITIONS Measured between REFP and COM and REFN and COM ∆VREF = VREFP - VREFN MIN TYP MAX UNITS UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM ) REFP, REFN Input Resistance Differential Reference Input Voltage Range COM Input Voltage Range REFP Input Voltage REFN Input Voltage 4 1.024 ±10% VDD/2 ±10% VCOM+ ∆VREF /2 VCOM ∆VREF /2 0.8 x VDD 0.8 x OVDD 0.2 x VDD 0.2 x OVDD 0.1 VIH = OVDD or VDD (CLK) VIL = 0 5 ISINK = -200µA ISOURCE = 200µA OE = OVDD OE = OVDD 2.7 1.7 Operating, fINA or B = 20MHz at -0.5dB FS Analog Supply Current IVDD Sleep mode Shutdown, clock idle, PD = OE = OVDD 5 3.3 2.5 125 2.8 1 15 3.6 3.6 155 OVDD - 0.2 ±10 0.2 ±5 ±5 V µA pF V V µA pF V V mA µA kΩ V V V V DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B) CLK Input High Threshold VIH PD, OE, SLEEP, T/B CLK Input Low Threshold VIL PD, OE, SLEEP, T/B Input Hysteresis Input Leakage Input Capacitance Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Range Output Supply Voltage Range VDD OVDD VHYST IIH IIL CIN VOL VOH ILEAK COUT V V DIGITAL OUTPUTS (D9A–D0A, D9B–D0B) 4 _______________________________________________________________________________________ Dual 10-Bit, 105Msps, +3.3V, Low-Power ADC with Internal Reference and Parallel Outputs ELECTRICAL CHARACTERISTICS (continued) (VDD = +3.3V, OVDD = +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential w.r.t. COM), CL = 10pF at digital outputs (Note 5), fCLK = 105.263MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS Operating, CL = 15pF , fINA or B = 20MHz at -0.5dB FS Output Supply Current IOVDD Sleep mode Shutdown, clock idle, PD = OE = OVDD Operating, fINA or B = 20MHz at -0.5dB FS Power Dissipation PDISS Sleep mode Shutdown, clock idle, PD = OE = OVDD Power-Supply Rejection Ratio TIMING CHARACTERISTICS CLK Rise to Output Data Valid Output Enable Time Output Disable Time CLK Pulse Width High CLK Pulse Width Low Wake-Up Time tDO tENABLE tDISABLE tCH tCL tWAKE Figure 3 (Note 3) Figure 4 Figure 4 Figure 3, clock period: 9.5ns Figure 3, clock period: 9.5ns Wakeup from sleep mode (Note 4) Wakeup from shutdown (Note 4) fINA or B = 20MHz at -0.5dB FS fINA or B = 20MHz at -0.5dB FS fINA or B = 20MHz at -0.5dB FS 5 10 1.5 4.75 ±1.5 4.75 ±1.5 0.18 1.5 -70 0.02 0.25 ±0.2 8 ns ns ns ns ns µs PSRR Offset Gain MIN TYP 15 100 2 413 9.2 3 ±0.2 ±0.1 50 10 511 MAX UNITS mA µA µA mW µW mV/V %/V MAX1180 CHANNEL-TO-CHANNEL MATCHING Crosstalk Gain Matching Phase Matching dB dB degrees Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS, referenced to a +1.024V full-scale input voltage range. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is 6dB or better, if referenced to the two-tone envelope. Note 3: Digital outputs settle to VIH, VIL. Parameter guaranteed by design. Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down. Note 5: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL. _______________________________________________________________________________________ 5 Dual 10-Bit, 105Msps, +3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1180 Typical Operating Characteristics (VDD = +3.3V, OVDD = +2.5V, internal reference, differential input at -0.5dB FS, fCLK = 105.0005678MHz, CL ≈ 10pF. TA = +25°C, unless otherwise noted.) FFT PLOT CHA (8192-POINT RECORD, DIFFERENTIAL INPUT) MAX1180 toc01 FFT PLOT CHB (8192-POINT RECORD, DIFFERENTIAL INPUT) MAX1180 toc02 FFT PLOT CHA (8192-POINT RECORD, DIFFERENTIAL INPUT) -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 CHA fINA = 20.084947MHz fINB = 25.006849MHz fCLK = 105.00057MHz AINA = -0.54dB FS MAX1180 toc03 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 10 20 30 40 50 CHA fINA = 6.242099MHz fINB = 7.523844MHz fCLK = 105.00057MHz AINA = -0.52dB FS 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 CHB fINA = 6.242099MHz fINB = 7.523844MHz fCLK = 105.00057MHz AINB = -0.48dB FS 0 60 0 10 20 30 40 50 60 0 10 20 30 40 50 60 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) FFT PLOT CHB (8192-POINT RECORD, DIFFERENTIAL INPUT) -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 10 20 30 40 50 60 ANALOG INPUT FREQUENCY (MHz) CHB MAX1180 toc04 FFT PLOT CHA (8192-POINT RECORD, DIFFERENTIAL INPUT) MAX1180 toc05 FFT PLOT CHB (8192-POINT RECORD, DIFFERENTIAL INPUT) -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 fINA = 52.23259MHz fINB = 57.050479MHz fCLK = 105.00057MHz AINB = -0.47dB FS CHB MAX1180 toc06 0 fINA = 20.084947MHz fINB = 25.006849MHz fCLK = 105.00057MHz AINA = -0.54dB FS 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 10 20 30 40 50 fINA = 52.23259MHz fINB = 57.050479MHz fCLK = 105.00057MHz AINA = -0.47dB FS CHA 0 60 0 10 20 30 40 50 60 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) TWO-TONE IMD PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT) MAX1180 toc07 SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY DIFFERENTIAL INPUT CONFIGURATION 59 CHB 58 SINAD (dB) SNR (dB) CHA 57 56 55 55 54 53 1 10 ANALOG INPUT FREQUENCY (MHz) 100 1 57 MAX1180 toc08 SIGNAL-TO-NOISE + DISTORTION vs. ANALOG INPUT FREQUENCY DIFFERENTIAL INPUT CONFIGURATION 59 MAX1180 toc09 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 10 20 30 40 50 fIN1 2ND ORDER 3RD ORDER IMD IMD fIN2 3RD ORDER IMD fINA = 38.055015MHz fINB = 41.925886MHz fCLK = 105.00057MHz AIN = -6.5dB FS TWO-TONE ENVELOPE = -0.51dB FS 60 61 CHB CHA 60 10 ANALOG INPUT FREQUENCY (MHz) 100 ANALOG INPUT FREQUENCY (MHz) 6 _______________________________________________________________________________________ Dual 10-Bit, 105Msps, +3.3V, Low-Power ADC with Internal Reference and Parallel Outputs Typical Operating Characteristics (continued) (VDD = +3.3V, OVDD = +2.5V, internal reference, differential input at -0.5dB FS, fCLK = 105.0005678MHz, CL ≈ 10pF. TA = +25°C, unless otherwise noted.) TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY MAX1180 toc10 MAX1180 SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY MAX1180 toc11 FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED MAX1180 toc12 -64 DIFFERENTIAL INPUT CONFIGURATION -66 76 DIFFERENTIAL INPUT CONFIGURATION 74 CHB 72 SFDR (dB) 6 4 2 GAIN (dB) 0 -2 -4 -6 -8 THD (dB) -68 CHA 70 68 CHA -70 -72 CHB 66 64 1 10 ANALOG INPUT FREQUENCY (MHz) 100 1 10 ANALOG INPUT FREQUENCY (MHz) 100 -74 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz) SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED VIN = 100mVp-p MAX1180 toc13 SIGNAL-TO-NOISE RATIO vs. INPUT POWER (fIN = 20.084947MHz) MAX1180 toc14 SIGNAL-TO-NOISE + DISTORTION vs. INPUT POWER (fIN = 20.084947MHz) MAX1180 toc15 6 4 2 GAIN (dB) 0 -2 -4 -6 -8 1 10 100 65 60 55 50 45 40 35 65 60 55 SINAD (dB) 50 45 40 35 SNR (dB) 1000 -20 -16 -12 -8 -4 0 -20 -16 -12 -8 -4 0 ANALOG INPUT FREQUENCY (MHz) INPUT POWER (dB FS) INPUT POWER (dB FS) TOTAL HARMONIC DISTORTION vs. INPUT POWER (fIN = 20.084947MHz) MAX1180 toc16 SPURIOUS-FREE DYNAMIC RANGE vs. INPUT POWER (fIN = 20.084947MHz) MAX1180 toc17 INTEGRAL NONLINEARITY (BEST ENDPOINT FIT) MAX1180 toc18 -55 80 1.0 -60 76 0.5 SFDR (dB) INL (LSB) THD (dB) -65 72 0 -70 68 -75 64 -0.5 -80 -20 -16 -12 -8 -4 0 INPUT POWER (dB FS) 60 -20 -16 -12 -8 -4 0 INPUT POWER (dB FS) -1.0 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE _______________________________________________________________________________________ 7 Dual 10-Bit, 105Msps, +3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1180 Typical Operating Characteristics (continued) (VDD = +3.3V, OVDD = +2.5V, internal reference, differential input at -0.5dB FS, fCLK = 105.0005678MHz, CL ≈ 10pF. TA = +25°C, unless otherwise noted.) DIFFERENTIAL NONLINEARITY MAX1180 toc19 OFFSET ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = +2.048V) MAX1180 toc20 GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = +2.048V) MAX1180 toc21 0.50 1.0 1.0 OFFSET ERROR (%FS) 0.25 DNL (LSB) 0.5 0.5 GAIN ERROR (%FS) CHA 0 CHB 0 0 -0.5 CHB -1.0 -0.25 -0.5 CHA -0.50 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE -1.0 -40 -15 10 35 60 85 TEMPERATURE (°C) -1.5 -40 -15 10 35 60 85 TEMPERATURE (°C) ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE MAX1180 toc22 ANALOG SUPPLY CURRENT vs. TEMPERATURE MAX1180 toc23 ANALOG POWER-DOWN CURRENT vs. ANALOG POWER SUPPLY OE = PD = OVDD 0.8 MAX1180 toc24 150 150 1.0 140 140 IVDD (mA) IVDD (mA) 120 120 IVDD (µA) -40 -15 10 35 60 85 130 130 0.6 0.4 110 110 0.2 100 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 100 TEMPERATURE (°C) 0 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 SFDR, SNR, THD, SINAD vs. CLOCK DUTY CYCLE MAX1180 toc25 INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE MAX1180 toc26 90 fIN = 20.08495MHz SFDR, SNR, THD, SINAD (dB) 80 THD SFDR 2.050 2.046 70 SNR VREFOUT (V) SINAD 52 56 60 2.042 60 2.038 50 2.034 40 40 44 48 CLOCK DUTY CYCLE (%) 2.030 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 8 _______________________________________________________________________________________ Dual 10-Bit, 105Msps, +3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1180 Typical Operating Characteristics (continued) (VDD = +3.3V, OVDD = +2.5V, internal reference, differential input at -0.5dB FS, fCLK = 105.0005678MHz, CL ≈ 10pF. TA = +25°C, unless otherwise noted.) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX1180 toc27 OUTPUT NOISE HISTOGRAM (DC INPUT) 64676 MAX1180 toc28 2.065 7000 6000 5000 2.055 VREFOUT (V) COUNTS 2.045 4000 3000 2000 2.035 2.025 1000 2.015 -40 -15 10 35 60 85 TEMPERATURE (°C) 0 0 N-2 607 N-1 N 252 N+1 0 N+2 DIGITAL OUTPUT NOISE Pin Description PIN 1 2, 6, 11, 14, 15 3, 7, 10, 13, 16 4 5 8 9 12 17 NAME COM VDD GND INA+ INAINBINB+ CLK T/B FUNCTION Common-Mode Voltage Input/Output. Bypass to GND with a ≥ 0.1µF capacitor. Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. Analog Ground Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+. Channel A Negative Analog Input. For single-ended operation, connect INA- to COM. Channel B Negative Analog Input. For single-ended operation, connect INB- to COM. Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+. Converter Clock Input T/B selects the ADC digital output format. High: Two’s complement. Low: Straight offset binary. Sleep Mode Input. High: Deactivates the two ADCs, but leaves the reference bias circuit active. Low: Normal operation. Power-Down Input. High: Power-down mode Low: Normal operation Output Enable Input. High: Digital outputs disabled Low: Digital outputs enabled 18 SLEEP 19 PD 20 OE _______________________________________________________________________________________ 9 Dual 10-Bit, 105Msps, +3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1180 Pin Description (continued) PIN 21 22 23 24 25 26 27 28 29 30 31, 34 32, 33 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NAME D9B D8B D7B D6B D5B D4B D3B D2B D1B D0B OGND OVDD D0A D1A D2A D3A D4A D5A D6A D7A D8A D9A REFOUT REFIN REFP REFN Three-State Digital Output, Bit 8, Channel B Three-State Digital Output, Bit 7, Channel B Three-State Digital Output, Bit 6, Channel B Three-State Digital Output, Bit 5, Channel B Three-State Digital Output, Bit 4, Channel B Three-State Digital Output, Bit 3, Channel B Three-State Digital Output, Bit 2, Channel B Three-State Digital Output, Bit 1, Channel B Three-State Digital Output, Bit 0 (LSB), Channel B Output Driver Ground Output Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2µF in parallel with 0.1µF. Three-State Digital Output, Bit 0 (LSB), Channel A Three-State Digital Output, Bit 1, Channel A Three-State Digital Output, Bit 2, Channel A Three-State Digital Output, Bit 3, Channel A Three-State Digital Output, Bit 4, Channel A Three-State Digital Output, Bit 5, Channel A Three-State Digital Output, Bit 6, Channel A Three-State Digital Output, Bit 7, Channel A Three-State Digital Output, Bit 8, Channel A Three-State Digital Output, Bit 9 (MSB), Channel A Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor divider. Reference Input. VREFIN = 2 ✕ (VREFP - VREFN). Bypass to GND with a >1nF capacitor. Positive Reference Input/Output. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. Negative Reference Input/Output. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. FUNCTION Three-State Digital Output, Bit 9 (MSB), Channel B 10 ______________________________________________________________________________________ Dual 10-Bit, 105Msps, +3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1180 VIN T/H Σ x2 VOUT VIN T/H Σ x2 VOUT FLASH ADC 1.5 BITS DAC FLASH ADC 1.5 BITS DAC 2-BIT FLASH ADC STAGE 1 STAGE 2 STAGE 8 STAGE 9 STAGE 1 STAGE 2 STAGE 8 2-BIT FLASH ADC STAGE 9 DIGITAL CORRECTION LOGIC T/H 10 D9A–D0A T/H DIGITAL CORRECTION LOGIC 10 D9B–D0B VINA VINB VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE-ENDED) VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE-ENDED) Figure 1. Pipelined Architecture—Stage Blocks Detailed Description The MAX1180 uses a nine-stage, fully-differential pipelined architecture (Figure 1), that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. Counting the delay through the output latch, the clockcycle latency is five clock cycles. 1.5-bit (two-comparator) flash ADCs convert the heldinput voltages into a digital code. The digital-to-analog converters (DACs) convert the digitized results back into analog voltages, which are then subtracted from the original held-input signals. The resulting error signals are then multiplied by two and the residues are passed along to the next pipeline stages where the process is repeated until the signals have been processed by all nine stages. Digital error correction compensates for ADC comparator offsets in each of these pipeline stages and ensures no missing codes. (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1, sampling the input waveform. Switches S4a and S4b are then opened before switches S3a and S3b, connect capacitors C1a and C1b to the output of the amplifier, and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers are used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1180 to trackand-sample/hold analog inputs of high frequencies (> Nyquist). Both ADC inputs (INA+, INB+, INA-, and INB-) can be driven either differentially or single-ended. Match the impedance of INA+ and INA-, as well as INB+ and INB-, and set the common-mode voltage to midsupply (VDD/2) for optimum performance. Input Track-and-Hold (T/H) Circuits Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuits in both track-andhold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a and S5b are closed. The fully-differential circuits sample the input signals onto the two capacitors Analog Inputs and Reference Configurations The full-scale range of the MAX1180 is determined by the internally generated voltage difference between REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 V REFIN /4).The full-scale range for both on-chip 11 ______________________________________________________________________________________ Dual 10-Bit, 105Msps, +3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1180 INTERNAL BIAS S2a C1a S4a INA+ C2a S4c S1 OUT S4b C2b C1b S3b S2b INTERNAL BIAS S5b COM HOLD INTERNAL BIAS S2a C1a S4a INB+ C2a S4c S1 OUT S4b C2b C1b S3b S2b INTERNAL BIAS S5b COM OUT TRACK HOLD TRACK CLK INTERNAL NONOVERLAPPING CLOCK SIGNALS OUT COM S5a S3a INA- COM S5a S3a INB- MAX1180 Figure 2. MAX1180 T/H Amplifiers ADCs is adjustable through the REFIN pin, which is provided for this purpose. REFOUT, REFP, COM (VDD/2), and REFN are internally buffered low-impedance outputs. The MAX1180 provides three modes of reference operation: • Internal reference mode • Buffered external reference mode • Unbuffered external reference mode In the internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g., 10k Ω ) or resistor divider, if an application 12 ______________________________________________________________________________________ Dual 10-Bit, 105Msps, +3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1180 5 CLOCK-CYCLE LATENCY N N+1 N+2 N+3 N+4 N+5 N+6 ANALOG INPUT CLOCK INPUT tD0 DATA OUTPUT D9A–D0A N-6 N-5 N-4 tCH N-3 tCL N-2 N-1 N N+1 DATA OUTPUT D9B–D0B N-6 N-5 N-4 N-3 N-2 N-1 N N+1 Figure 3. System Timing Diagram Table 1. MAX1180 Output Codes For Differential Inputs DIFFERENTIAL INPUT VOLTAGE* VREF ✕ 511/512 VREF ✕ 1/512 0 -VREF ✕ 1/512 -VREF ✕ 511/512 -VREF ✕ 512/512 DIFFERENTIAL INPUT +FULL SCALE - 1LSB + 1 LSB Bipolar Zero - 1 LSB -FULL SCALE + 1 LSB -FULL SCALE STRAIGHT OFFSET BINARY T/B = 0 11 1111 1111 10 0000 0001 10 0000 0000 01 1111 1111 00 0000 0001 00 0000 0000 TWO’S COMPLEMENT T/B = 1 01 1111 1111 00 0000 0001 00 0000 0000 11 1111 1111 10 0000 0001 10 0000 0000 *VREF = VREFP – VREFN requires a reduced full-scale range. For stability and noise filtering purposes, bypass REFIN with a >10nF capacitor to GND. In internal reference mode, REFOUT, COM, REFP, and REFN become low-impedance outputs. In the buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accurate voltage at REFIN. In this mode, COM, REFP, and REFN become outputs. REFOUT may be left open or connected to REFIN through a >10kΩ resistor. In the unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REFP, COM, and REFN. With their buffers shut down, these nodes become high impedance and may be driven through separate external reference sources. Clock Input (CLK) The MAX1180’s CLK input accepts CMOS-compatible clock signals. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows: 13 ______________________________________________________________________________________ Dual 10-Bit, 105Msps, +3.3V, Low-Power ADC with Internal Reference and Parallel Outputs SNRdB = 20 ✕ log10 (1 / [2π x fIN ✕ tAJ]), where fIN represents the analog input frequency and tAJ is the time of the aperture jitter. Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines. The MAX1180 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50%, must meet the specifications for high and low periods as stated in the Electrical Characteristics. MAX1180 OE tENABLE OUTPUT D9A–D0A HIGH-Z tDISABLE HIGH-Z VALID DATA OUTPUT D9B–D0B HIGH-Z VALID DATA HIGH-Z Figure 4. Output Timing Diagram System Timing Requirements Figure 3 depicts the relationship between the clock input, analog input, and data output. The MAX1180 samples at the rising edge of the input clock. Output data for channels A and B is valid on the next rising edge of the input clock. The output data has an internal latency of five clock cycles. Figure 4 also determines the relationship between the input clock parameters and the valid output data on channels A and B. disabled) and current consumption is reduced to 2.8mA. To enter full power-down mode, pull PD high. With OE simultaneously low, all outputs are latched at the last value prior to the power-down. Pulling OE high, forces the digital outputs into a high-impedance state. Applications Information Figure 5 depicts a typical application circuit containing two single-ended to differential converters. The internal reference provides a VDD/2 output voltage for levelshifting purposes. The input is buffered and then split to a voltage follower and inverter. One lowpass filter per ADC suppresses some of the wideband noise associated with high-speed operational amplifiers. The user may select the RISO and CIN values to optimize the filter performance to suit a particular application. For the application in Figure 5, a RISO of 50Ω is placed before the capacitive load to prevent ringing and oscillation. The 22pF C IN capacitor acts as a small bypassing capacitor. Digital Output Data, Output Data Format Selection (T/B), Output Enable (OE) All digital outputs, D0A–D9A (Channel A) and D0B–D9B (Channel B), are TTL/CMOS logic-compatible. There is a five clock cycle latency between any particular sample and its corresponding output data. The output coding can be chosen to be either straight offset binary or two’s complement (Table 1) controlled by a single pin (T/B). Pull T/B low to select offset binary and high to activate two’s complement output coding. The capacitive load on the digital outputs D0A–D9A and D0B–D9B should be kept as low as possible (