MAX1183ECM

19-2173; Rev 0; 9/01 Dual 10-Bit, 40Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs General Description The MAX1183 is a +3V, dual 10-bit analog-to-digital converter (ADC) featuring fully differential wideband track-and-hold (T/H) inputs, driving two pipelined, ninestage ADCs. The MAX1183 is optimized for low-power, high dynamic performance applications in imaging, instrumentation, and digital communication applications. This ADC operates from a single +2.7V to +3.6V supply, consuming only 120mW while delivering a typical signal-to-noise ratio (SNR) of 59.6dB at an input frequency of 20MHz and a sampling rate of 40Msps. The T/H driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters may also be operated with single-ended inputs. In addition to low operating power, the MAX1183 features a 2.8mA sleep mode as well as a 1µA power-down mode to conserve power during idle periods. An internal +2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of this internal or an externally derived reference, if desired for applications requiring increased accuracy or a different input voltage range. The MAX1183 features parallel, CMOS-compatible three-state outputs. The digital output format can be set to two’s complement or straight offset binary through a single control pin. The device provides for a separate output power supply of +1.7V to +3.6V for flexible interfacing. The MAX1183 is available in a 7mm ✕ 7mm, 48pin TQFP package, and is specified for the extended industrial (-40°C to +85°C) temperature range. Pin-compatible lower and higher speed versions of the MAX1183 are also available. Refer to the MAX1180 data sheet for 105Msps, the MAX1181 data sheet for 80Msps, the MAX1182 data sheet for 65Msps, and the MAX1184 data sheet for 20Msps. In addition to these speed grades, this family includes a multiplexed output version, for which digital data is presented time-interleaved and on a single, parallel 10-bit output port. o Single +3V Operation o Excellent Dynamic Performance 59.6dB SNR at fIN = 20MHz 73dB SFDR at fIN = 20MHz o Low Power 40mA (Normal Operation) 2.8mA (Sleep Mode) 1µA (Shutdown Mode) o 0.02dB Gain and 0.25° Phase Matching o Wide ±1Vp-p Differential Analog Input Voltage Range o 400MHz -3dB Input Bandwidth o On-Chip +2.048V Precision Bandgap Reference o User-Selectable Output Format—Two’s Complement or Offset Binary o 48-Pin TQFP Package with Exposed Paddle for Improved Thermal Dissipation Features MAX1183 Ordering Information PART MAX1183ECM TEMP. RANGE -40°C to +85°C PIN-PACKAGE 48 TQFP-EP Pin Configuration REFN REFP REFIN REFOUT D9A D8A D7A D6A D5A D4A D3A D2A 48 47 46 45 44 43 42 41 40 39 38 COM VDD GND INA+ INAVDD GND INBINB+ GND VDD CLK 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 D1A D0A OGND OVDD OVDD OGND D0B D1B D2B D3B D4B D5B Applications High-Resolution Imaging I/Q Channel Digitization Multichannel IF Sampling Instrumentation Video Application Ultrasound MAX1183 Functional Diagram appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products VDD VDD GND T/B SLEEP PD OE D9B D8B D7B D6B GND 48 TQFP-EP 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Dual 10-Bit, 40Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1183 ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND .............................................. -0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V INA+, INA-, INB+, INB- to GND ...............................-0.3V to VDD REFIN, REFOUT, REFP, REFN, COM, CLK to GND .................................-0.3V to (VDD + 0.3V) OE, PD, SLEEP, T/B D9A–D0A, D9B–D0B to OGND ...........-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 48-Pin TQFP (derate 12.5mW/°C above +70°C)........1000mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +3V, OVDD = +2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential with respect to COM), CL = 10pF at digital outputs (Note 5), fCLK = 40MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT Differential Input Voltage Range Common-Mode Input Voltage Range Input Resistance Input Capacitance CONVERSION RATE Maximum Clock Frequency Data Latency DYNAMIC CHARACTERISTICS (fCLK = 40MHz, 4096-point FFT) Signal-to-Noise Ratio Signal-to-Noise and Distortion Spurious-Free Dynamic Range Third-Harmonic Distortion SNR SINAD SFDR HD3 fINA or B = 7.51MHz, TA = +25°C fINA or B = 20MHz, TA = +25°C fINA or B = 7.51MHz, TA = +25°C fINA or B = 20MHz, TA = +25°C fINA or B = 7.51MHz, TA = +25°C fINA or B = 20MHz, TA = +25°C fINA or B = 7.51MHz fINA or B = 20MHz fINA or B = 11.6066MHz at -6.5dB FS, fINA or B = 13.3839MHz at -6.5dB FS (Note 2) fINA or B = 7.51MHz, TA = +25°C fINA or B = 20MHz, TA = +25°C 57.3 56.8 57 56.5 65 65 59.6 59.6 59.4 59 76 73 -76 -73 -78 -73 -73 -64 -63 dB dB dBc dB fCLK 40 5 MHz Clock Cycles VDIFF VCM RIN CIN Switched capacitor load Differential or single-ended inputs ±1.0 VDD/2 ±0.5 50 5 V V kΩ pF INL DNL fIN = 7.51MHz fIN = 7.51MHz, no missing codes guaranteed 10 ±0.5 ±0.25 50 5 -250 250 -5 1.07 V V V V MΩ mA µA µA mA REFOUT TCREF 2.048 ±3% 60 1.25 V ppm/ °C mV/mA INA+ = INA- = INB+ = INB- = COM FPBW tAD tAJ For 1.5 x full-scale input SYMBOL CONDITIONS Input at -20dB FS, differential inputs Input at -0.5dB FS, differential inputs MIN TYP 500 400 1 2 2 ±1 ±0.25 0.2 MAX UNITS MHz MHz ns psRMS ns % Degrees LSBRMS MAX1183 UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM) REFP, REFN Input Resistance Differential Reference Input Voltage Range COM Input Voltage Range REFP Input Voltage REFN Input Voltage 4 1.024 ±10% VDD/2 ±10% VCOM + ∆VREF/2 VCOM ∆VREF/2 kΩ V V V V _______________________________________________________________________________________ 3 Dual 10-Bit, 40Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1183 ELECTRICAL CHARACTERISTICS (continued) (VDD = +3V, OVDD = +2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential with respect to COM), CL = 10pF at digital outputs (Note 5), fCLK = 40MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN 0.8 x VDD 0.8 x OVDD 0.2 x VDD 0.2 x OVDD 0.1 VIH = OVDD or VDD (CLK) VIL = 0 5 ISINK = -200µA ISOURCE = 200µA OE = OVDD OE = OVDD 5 OVDD - 0.2 ±10 0.2 ±5 ±5 TYP MAX UNITS DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B) CLK Input High Threshold VIH PD, OE, SLEEP, T/B CLK Input Low Threshold VIL PD, OE, SLEEP, T/B Input Hysteresis Input Leakage Input Capacitance Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Leakage Capacitance POWER REQUIREMENTS Analog Supply Voltage Range Output Supply Voltage Range Analog Supply Current VDD OVDD Operating, fINA or B = 20MHz at -0.5dB FS IVDD Sleep mode Shutdown, clock idle, PD = OE = OVDD Operating, CL = 15pF, fINA or B = 20MHz at -0.5dB FS Sleep mode Shutdown, clock idle, PD = OE = OVDD Operating, fINA or B = 20MHz at -0.5dB FS Power Dissipation PDISS Sleep mode Shutdown, clock idle, PD = OE = OVDD Power-Supply Rejection TIMING CHARACTERISTICS CLK Rise to Output Data Valid Output Enable Time Output Disable Time tDO tENABLE tDISABLE Figure 3 (Note 3) Figure 4 Figure 4 5 10 1.5 8 ns ns ns PSRR Offset Gain 2.7 1.7 3 2.5 40 2.8 1 5.8 100 2 120 8.4 3 ±0.2 ±0.1 45 10 180 15 3.6 3.6 60 V V mA µA mA µA mW µW mV/V %V VHYST IIH IIL CIN VOL VOH ILEAK COUT V V V µA pF V V µA pF DIGITAL OUTPUTS (D9A–D0A, D9B–D0B) Output Supply Current IOVDD 4 _______________________________________________________________________________________ Dual 10-Bit, 40Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs ELECTRICAL CHARACTERISTICS (continued) (VDD = +3V, OVDD = +2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential with respect to COM), CL = 10pF at digital outputs (Note 5), fCLK = 40MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CLK Pulse Width High CLK Pulse Width Low Wake-Up Time tCH tCL tWAKE Figure 3, clock period: 25ns Figure 3, clock period: 25ns Wake up from sleep mode (Note 4) Wake up from shutdown (Note 4) fINA or B = 20MHz at -0.5dB FS fINA or B = 20MHz at -0.5dB FS fINA or B = 20MHz at -0.5dB FS 12.5 ±3.8 12.5 ±3.8 0.41 1.5 -70 0.02 0.25 ±0.2 ns ns µs MAX1183 CHANNEL-TO-CHANNEL MATCHING Crosstalk Gain Matching Phase Matching dB dB Degrees Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a +1.024V full-scale input voltage range. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is 6dB better, if referenced to the two-tone envelope. Note 3: Digital outputs settle to VIH, VIL. Parameter guaranteed by design. Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down. Note 5: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL. Typical Operating Characteristics (VDD = +3V, OVDD = +2.5V, VREFIN = +2.048V, differential input at -0.5dB FS, fCLK = 40.0006MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) FFT PLOT CHA (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) MAX1183 toc01 FFT PLOT CHB (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) MAX1183 toc02 FFT PLOT CHA (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 HD3 HD2 fCLK = 40.0005678MHz fINA = 24.9661747MHz fINB = 19.8879776MHz AINA = -0.552dB FS CHA MAX1183 toc03 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 2 4 6 8 HD3 HD2 CHA fCLK = 40.0005678MHz fINA = 7.5342866MHz fINB = 6.1475482MHz AINA = -0.498dB FS 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 HD2 HD3 CHB fCLK = 40.0005678MHz fINB = 6.1475482MHz fINA = 7.524866MHz AINB = -0.534dB FS 0 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 5 Dual 10-Bit, 40Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1183 Typical Operating Characteristics (continued) (VDD = +3V, OVDD = +2.5V, VREFIN = +2.048V, differential input at -0.5dB FS, fCLK = 40.0006MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) FFT PLOT CHB (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) MAX1183 toc04 TWO-TONE IMD PLOT (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) MAX1183 toc05 SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY CHA MAX1183 toc06 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 2 4 6 8 HD2 HD3 fCLK = 40.0005678MHz fINA = 24.9661747MHz fINB = 19.8879776MHz AINB = -0.525dB FS CHB 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 IMD2 fIN1 IMD3 IMD2 fCLK = 40.0005678MHz fIN1 = 11.606610MHz fIN2 = 13.383979MHz AIN = -6.5dB FS TWO-TONE ENVELOPE = -0.525dB FS 61 60 59 SNR (dB) CHB 58 57 56 55 fIN2 IMD3 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 1 10 ANALOG INPUT FREQUENCY (MHz) 100 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) SIGNAL-TO-NOISE + DISTORTION vs. ANALOG INPUT FREQUENCY MAX1183 toc07 TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY MAX1183 toc08 SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY CHA 76 SFDR (dBc) MAX1183 toc09 62 -65 80 60 SINAD (dB) -68 CHB CHA THD (dBc) -71 72 CHB 68 58 CHB 56 -74 CHA -77 64 54 1 10 ANALOG INPUT FREQUENCY (MHz) 100 -80 1 10 ANALOG INPUT FREQUENCY (MHz) 100 60 1 10 ANALOG INPUT FREQUENCY (MHz) 100 FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED MAX1183 toc10 SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED MAX1183 toc11 SIGNAL-TO-NOISE RATIO vs. INPUT POWER (fIN = 19.8879776MHz) MAX1183 toc12 6 4 2 GAIN (dB) 6 VIN = 100mVp-p 4 2 GAIN (dB) 0 -2 -4 -6 -8 65 60 55 SNR (dB) 50 45 40 35 0 -2 -4 -6 -8 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz) 1 10 100 1000 -20 -16 -12 -8 -4 0 ANALOG INPUT FREQUENCY (MHz) INPUT POWER (dB FS) 6 _______________________________________________________________________________________ Dual 10-Bit, 40Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs Typical Operating Characteristics (continued) (VDD = +3V, OVDD = +2.5V, VREFIN = +2.048V, differential input at -0.5dB FS, fCLK = 40.0006MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE + DISTORTION vs. INPUT POWER (fIN = 19.8879776MHz) MAX1183 toc13 MAX1183 TOTAL HARMONIC DISTORTION vs. INPUT POWER (fIN = 19.8879776MHz) MAX1183 toc14 SPURIOUS-FREE DYNAMIC RANGE vs. INPUT POWER (fIN = 19.8879776MHz) MAX1183 toc15 65 60 55 50 45 40 35 -20 -16 -12 -8 -4 0 INPUT POWER (dB FS) -55 80 -60 76 SFDR (dBc) SINAD (dB) THD (dBc) -65 72 -70 68 -75 64 -80 -20 -16 -12 -8 -4 0 INPUT POWER (dB FS) 60 -20 -16 -12 -8 -4 0 INPUT POWER (dB FS) INTEGRAL NONLINEARITY (BEST END-POINT FIT) MAX1183 toc16 DIFFERENTIAL NONLINEARITY MAX1183 toc17 GAIN ERROR vs. TEMPERATURE MAX1183 toc18 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0 0.3 0.2 0.1 DNL (LSB) 0 -0.1 -0.2 -0.3 0.5 0.4 GAIN ERROR (% FS) 0.3 0.2 0.1 0 -0.1 CHA CHB INL (LSB) 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE -40 -15 10 35 60 85 TEMPERATURE (°C) OFFSET ERROR vs. TEMPERATURE MAX1183 toc19 ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE MAX1183 toc20 ANALOG SUPPLY CURRENT vs. TEMPERATURE MAX1183 toc21 0.2 0.1 OFFSET ERROR (% FS) 0 -0.1 -0.2 -0.3 CHA -0.4 -40 -15 10 35 60 CHB 50 50 46 46 IVDD (mA) IVDD (mA) 42 42 38 38 34 34 30 85 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 TEMPERATURE (°C) 30 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 7 Dual 10-Bit, 40Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1183 Typical Operating Characteristics (continued) (VDD = +3V, OVDD = +2.5V, VREFIN = +2.048V, differential input at -0.5dB FS, fCLK = 40.0006MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) ANALOG POWER-DOWN CURRENT vs. ANALOG POWER SUPPLY MAX1183 toc22 SFDR, SNR, THD, SINAD vs. CLOCK DUTY CTCLE fIN = 7.5342866MHz SFDR SFDR, SNR, THD, SINAD (dB) 80 MAX1183 toc23 INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE MAX1183 toc24 0.5 OE = PD = OVDD 0.4 90 2.0020 2.0014 VREFOUT (V) IVDD (µA) 0.3 70 SNR 60 THD 2.0008 0.2 2.0002 SINAD 50 1.9996 0.1 0 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 40 25 35 45 55 65 75 CLOCK DUTY CYCLE (%) 1.9990 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX1183 toc25 OUTPUT NOISE HISTOGRAM (DC INPUT) 63,000 56,000 49,000 COUNTS 42,000 35,000 28,000 64,515 MAX1183 toc26 2.010 2.005 2.000 1.995 1.990 1.985 1.980 -40 -15 10 35 60 70,000 VREFOUT (V) 21,000 14,000 7,000 0 85 TEMPERATURE (°C) 0 N-2 869 N-1 N 152 N+1 0 N+2 DIGITAL OUTPUT CODE 8 _______________________________________________________________________________________ Dual 10-Bit, 40Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs Pin Description PIN 1 2, 6, 11, 14, 15 3, 7, 10, 13, 16 4 5 8 9 12 17 NAME COM VDD GND INA+ INAINBINB+ CLK T/B FUNCTION Common-Mode Voltage Input/Output. Bypass to GND with a ≥0.1µF capacitor. Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. Analog Ground Channel A Positive Analog Input. For single-ended operation connect signal source to INA+. Channel A Negative Analog Input. For single-ended operation connect INA- to COM. Channel B Negative Analog Input. For single-ended operation connect INB- to COM. Channel B Positive Analog Input. For single-ended operation connect signal source to INB+. Converter Clock Input T/B Selects the ADC Digital Output Format. High: Two’s complement. Low: Straight offset binary. Sleep Mode Input. High: Deactivates the two ADCs, but leaves the reference bias circuit active. Low: Normal operation. Power Down Input. High: Power-down mode. Low: Normal operation. Output Enable Input. High: Digital outputs disabled. Low: Digital outputs enabled. Three-State Digital Output, Bit 9 (MSB), Channel B Three-State Digital Output, Bit 8, Channel B Three-State Digital Output, Bit 7, Channel B Three-State Digital Output, Bit 6, Channel B Three-State Digital Output, Bit 5, Channel B Three-State Digital Output, Bit 4, Channel B Three-State Digital Output, Bit 3, Channel B Three-State Digital Output, Bit 2, Channel B Three-State Digital Output, Bit 1, Channel B Three-State Digital Output, Bit 0 (LSB), Channel B Output Driver Ground. Output Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2µF in parallel with 0.1µF. Three-State Digital Output, Bit 0 (LSB), Channel A Three-State Digital Output, Bit 1, Channel A Three-State Digital Output, Bit 2, Channel A Three-State Digital Output, Bit 3, Channel A Three-State Digital Output, Bit 4, Channel A Three-State Digital Output, Bit 5, Channel A MAX1183 18 SLEEP 19 PD 20 21 22 23 24 25 26 27 28 29 30 31, 34 32, 33 35 36 37 38 39 40 OE D9B D8B D7B D6B D5B D4B D3B D2B D1B D0B OGND OVDD D0A D1A D2A D3A D4A D5A _______________________________________________________________________________________ 9 Dual 10-Bit, 40Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1183 Pin Description (continued) PIN 41 42 43 44 45 46 47 48 NAME D6A D7A D8A D9A REFOUT REFIN REFP REFN Three-State Digital Output, Bit 6, Channel A Three-State Digital Output, Bit 7, Channel A Three-State Digital Output, Bit 8, Channel A Three-State Digital Output, Bit 9 (MSB), Channel A Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor divider. Reference Input. VREFIN = 2 ✕ (VREFP - VREFN). Bypass to GND with a >1nF capacitor. Positive Reference Input/Output. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. Negative Reference Input/Output. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. FUNCTION Detailed Description The MAX1183 uses a nine-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. Including the delay through the output latch, the total clock-cycle latency is five clock cycles. One-and-a-half bit (2-comparator) flash ADCs convert the held-input voltages into a digital code. The digitalVIN VOUT to-analog converters (DACs) convert the digitized results back into analog voltages, which are then subtracted from the original held-input signals. The resulting error signals are then multiplied by two, and the residues are passed along to the next pipeline stages where the process is repeated until the signals have been processed by all nine stages. Digital error correction compensates for ADC comparator offsets in each of these pipeline stages and ensures no missing codes. T/H Σ x2 VIN T/H Σ x2 VOUT FLASH ADC 1.5 BITS DAC FLASH ADC 1.5 BITS DAC 2-BIT FLASH ADC STAGE 1 STAGE 2 STAGE 8 STAGE 9 STAGE 1 STAGE 2 STAGE 8 2-BIT FLASH ADC STAGE 9 DIGITAL CORRECTION LOGIC T/H 10 D9A–D0A T/H DIGITAL CORRECTION LOGIC 10 D9B–D0B VINA VINB VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED) VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED) Figure 1. Pipelined Architecture—Stage Blocks 10 ______________________________________________________________________________________ Dual 10-Bit, 40Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs Input Track-and-Hold (T/H) Circuits Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuits in both track-andhold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1, sampling the input waveform. Switches S4a and S4b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers are used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1183 to track and sample/hold analog inputs of high frequencies (> Nyquist). Both ADC inputs (INA+, INB+, INA- and INB-) can be driven either differentially or single ended. Match the impedance of INA+ and INA-, as well as INB+ and INB- and set the common-mode voltage to midsupply (VDD/2) for optimum performance. MAX1183 Analog Inputs and Reference Configurations The full-scale range of the MAX1183 is determined by the internally generated voltage difference between REFP (V DD /2 + V REFIN /4) and REFN (V DD /2 VREFIN/4). The full-scale range for both on-chip ADCs is adjustable through the REFIN pin, which is provided for this purpose. REFOUT, REFP, COM (VDD/2), and REFN are internally buffered low-impedance outputs. The MAX1183 provides three modes of reference operation: • Internal reference mode • Buffered external reference mode • Unbuffered external reference mode INTERNAL BIAS S2a C1a S4a INA+ C2a S4c S1 COM S5a S3a OUT INAS4b C2b C1b S3b S2b INTERNAL BIAS S5b COM OUT HOLD INTERNAL BIAS S2a C1a S4a INB+ C2a S4c S1 OUT S4b C2b C1b S3b S2b INTERNAL BIAS S5b COM OUT TRACK HOLD TRACK CLK INTERNAL NONOVERLAPPING CLOCK SIGNALS COM S5a S3a In internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g., 10kΩ) or resistor divider, if an application requires a reduced full-scale range. For stability and noise filtering purposes, bypass REFIN with a >10nF capacitor to GND. In internal reference mode, REFOUT, COM, REFP, and REFN become low-impedance outputs. In buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accurate voltage at REFIN. In this mode, COM, REFP, and REFN become outputs. REFOUT may be left open or connected to REFIN through a >10kΩ resistor. In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REFP, COM, and REFN. With their buffers shut down, these nodes become high impedance and may be driven through separate, external reference sources. Clock Input (CLK) MAX1183 INB- The MAX1183’s CLK input accepts CMOS-compatible clock signals. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (