MAX1186

19-2263; Rev 0; 12/01 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs General Description The MAX1186 is a 3V, dual 10-bit analog-to-digital converter (ADC) featuring fully-differential wideband trackand-hold (T/H) inputs, driving two pipelined, nine-stage ADCs. The MAX1186 is optimized for low-power, high dynamic performance applications in imaging, instrumentation, and digital communication applications. This ADC operates from a single 2.7V to 3.6V supply, consuming only 105mW while delivering a typical signal-tonoise ratio (SNR) of 59.4dB at an input frequency of 20MHz and a sampling rate of 40Msps. Digital outputs A and B are updated alternating on the rising (CHA) and the falling (CHB) edge of the clock. The T/H driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters may also be operated with singleended inputs. In addition to low operating power, the MAX1186 features a 2.8mA sleep mode as well as a 1µA power-down mode to conserve power during idle periods. An internal 2.048V precision bandgap reference sets the full-scale range of the ADCs. A flexible reference structure allows the use of this internal or an externally derived reference, if desired for applications requiring increased accuracy or a different input voltage range. The MAX1186 features parallel, multiplexed, CMOScompatible three-state outputs. The digital output format can be set to two’s complement or straight offset binary through a single control pin. The device provides for a separate output power supply of 1.7V to 3.6V for flexible interfacing. The MAX1186 is available in a 7mm x 7mm, 48-pin TQFP-EP package, and is specified for the extended industrial (-40°C to +85°C) temperature range. Pin-compatible, nonmultiplexed, high-speed versions of the MAX1186 are also available. Please refer to the MAX1180 data sheet for 105Msps, the MAX1181 data sheet for 80Msps, the MAX1182 data sheet for 65Msps, the MAX1183 data sheet for 40Msps, and the MAX1184 data sheet for 20Msps. For a pin-compatible lower speed version (20Msps) of the MAX1186, please refer to the MAX1185 data sheet. o Single 3V Operation o Excellent Dynamic Performance: 59.4dB SNR at fIN = 20MHz 72dBc SFDR at fIN = 20MHz o Low Power: 35mA (Normal Operation) 2.8mA (Sleep Mode) 1µA (Shutdown Mode) o 0.02dB Gain and 0.25° Phase Matching o Wide ±1VP-P Differential Analog Input Voltage Range o 400MHz, -3dB Input Bandwidth o On-Chip 2.048V Precision Bandgap Reference o Single 10-Bit Bus for Multiplexed, Digital Outputs o User-Selectable Output Format–Two’s Complement or Offset Binary o 48-Pin TQFP Package with Exposed Paddle For Improved Thermal Dissipation Features MAX1186 Ordering Information PART MAX1186ECM TEMP RANGE -40°C to +85°C PIN-PACKAGE 48 TQFP-EP Functional Diagram appears at end of data sheet. Pin Configuration REFN REFP REFIN REFOUT D9A/B D8A/B D7A/B D6A/B D5A/B D4A/B D3A/B D2A/B 48 47 46 45 44 43 42 41 40 39 38 COM VDD GND INA+ INAVDD GND INBINB+ GND VDD CLK 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 D1A/B D0A/B OGND OVDD OVDD OGND A/B N.C. N.C. N.C. N.C. N.C. MAX1186 30 29 28 27 26 25 Applications High-Resolution Imaging I/Q Channel Digitization Multichannel IF Sampling Instrumentation Video Application Ultrasound ________________________________________________________________ Maxim Integrated Products GND VDD VDD GND T/B SLEEP PD OE N.C. N.C. N.C. N.C. 48 TQFP-EP 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1186 ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V INA+, INA-, INB+, INB- to GND ...............................-0.3V to VDD REFIN, REFOUT, REFP, REFN, COM, CLK to GND............................................-0.3V to (VDD + 0.3V) OE, PD, SLEEP, T/B, D9A/B–D0A/B, A/B to OGND .......................................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 48-Pin TQFP (derate 12.5mW/°C above +70°C).......1000mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3V, OVDD = 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k Ω resistor, V IN = 2V P-P (differential w.r.t. COM), C L = 10pF at digital outputs (Note 5), f CLK = 40MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT Differential Input Voltage Range Common-Mode Input Voltage Range Input Resistance Input Capacitance CONVERSION RATE Maximum Clock Frequency Data Latency fCLK CHA CHB fINA or B = 7.5MHz, TA = +25°C fINA or B = 20MHz, TA = +25°C fINA or B = 7.5MHz, TA = +25°C fINA or B = 20MHz, TA = +25°C fINA or B = 7.5MHz, TA = +25°C fINA or B = 20MHz, TA = +25°C 57.3 56.8 57 56.5 64 64 40 5 5.5 59.5 59.4 59.4 59.2 74 72 MHz Clock Cycles VDIFF VCM RIN CIN Switched capacitor load Differential or single-ended inputs ±1 VDD/2 ± 0.5 100 5 V V kΩ pF INL DNL fIN = 7.5MHz fIN = 7.5MHz, no missing codes guaranteed 10 ±0.5 ±0.25 < ±1 0 ±1.7 ±1.0 ±1.7 ±2 Bits LSB LSB % FS % FS SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS (fCLK = 40MHz, 4096-point FFT) Signal-to-Noise Ratio Signal-to-Noise and Distortion Spurious-Free Dynamic Range SNR SINAD SFDR dB dB dBc 2 _______________________________________________________________________________________ Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k Ω resistor, V IN = 2V P-P (differential w.r.t. COM), C L = 10pF at digital outputs (Note 5), f CLK = 40MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Third-Harmonic Distortion Intermodulation Distortion Total Harmonic Distortion (first four harmonics) Small-Signal Bandwidth Full-Power Bandwidth Aperture Delay Aperture Jitter Overdrive Recovery Time Differential Gain Differential Phase Output Noise INTERNAL REFERENCE Reference Output Voltage Reference Temperature Coefficient Load Regulation BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V) REFIN Input Voltage Positive Reference Output Voltage Negative Reference Output Voltage Differential Reference Output Voltage Range REFIN Resistance VREFIN VREFP VREFN ∆VREF RREFIN ∆VREF = VREFP - VREFN 0.98 2.048 2.012 0.988 1.024 >50 1.07 V V V V MΩ REFOUT TCREF 2.048 ±3% 60 1.25 V ppm/°C mV/mA INA+ = INA- = INB+ = INB- = COM FPBW tAD tAJ For 1.5 ✕ full-scale input SYMBOL HD3 IMD THD CONDITIONS fINA or B = 7.5MHz fINA or B = 20MHz fINA or B = 11.6066MHz at -6.5dB FS fINA or B = 13.3839MHz at -6.5dB FS (Note 2) fINA or B = 7.5MHz, TA = +25°C fINA or B = 20MHz Input at -20dB FS, differential inputs Input at -0.5dB FS, differential inputs MIN TYP -74 -72 -76 -72 -71 500 400 1 2 2 ±1 ±0.25 0.2 -64 -63 MAX UNITS dBc dBc dBc MHz MHz ns psrms ns % degrees LSBRMS MAX1186 _______________________________________________________________________________________ 3 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1186 ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k Ω resistor, V IN = 2V P-P (differential w.r.t. COM), C L = 10pF at digital outputs (Note 5), f CLK = 40MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Maximum REFP, COM Source Current Maximum REFP, COM Sink Current Maximum REFN Source Current Maximum REFN Sink Current SYMBOL ISOURCE ISINK ISOURCE ISINK RREFP, RREFN ∆VREF VCOM VREFP VREFN Measured between REFP and COM, and REFN and COM ∆VREF = VREFP - VREFN CONDITIONS MIN TYP 5 -250 250 -5 MAX UNITS mA µA µA mA UNBUFFERED EXTERNAL REFERENCE (VREFIN = GND, reference voltage applied to REFP, REFN, and COM) REFP, REFN Input Resistance Differential Reference Input Voltage COM Input Voltage REFP Input Voltage REFN Input Voltage 4 1.024 ±10% VDD/2 ±10% VCOM + ∆VREF /2 VCOM ∆VREF /2 CLK PD, OE, SLEEP, T/B CLK PD, OE, SLEEP, T/B 0.1 VIH = OVDD or VDD (CLK) VIL = 0 5 ISINK = -200µA ISOURCE = 200µA OE = OVDD OE = OVDD 5 OVDD - 0.2 ±10 0.2 ±5 ±5 0.8 ✕ VDD 0.8 ✕ OVDD 0.2 ✕ VDD 0.2 ✕ OVDD kΩ V V V V DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B) Input High Threshold Input Low Threshold Input Hysteresis Input Leakage Input Capacitance Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance VIH VIL VHYST IIH IIL CIN VOL VOH ILEAK COUT V V V µA pF V V µA pF DIGITAL OUTPUTS (D0A/B–D9A/B, A/B) 4 _______________________________________________________________________________________ Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1186 ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k Ω resistor, V IN = 2V P-P (differential w.r.t. COM), C L = 10pF at digital outputs (Note 5), f CLK = 40MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER POWER REQUIREMENTS Analog Supply Voltage Range Output Supply Voltage Range Analog Supply Current VDD OVDD Operating, fINA or B = 20MHz at -0.5dB FS IVDD Sleep mode Shutdown, clock idle, PD = OE = OVDD Operating, CL = 15pF, fINA or B = 20MHz at -0.5dB FS Output Supply Current IOVDD Sleep mode Shutdown, clock idle, PD = OE = OVDD Operating, fINA or B = 20MHz at -0.5dB FS Power Dissipation PDISS Sleep mode Shutdown, clock idle, PD = OE = OVDD Power-Supply Rejection Ratio TIMING CHARACTERISTICS CLK Rise to CHA Output Data Valid CLK Fall to CHB Output Data Valid Clock Rise/Fall to A/B Rise/Fall Time Output Enable Time Output Disable Time CLK Pulse Width High CLK Pulse Width Low Wake-Up Time tDOA tDOB tDA/B tENABLE tDISABLE tCH tCL tWAKE Figure 4 Figure 4 Figure 3, clock period: 25ns Figure 3, clock period: 25ns Wake-up from sleep mode (Note 4) Wake-up from shutdown (Note 4) fINA or B = 20MHz at -0.5dB FS fINA or B = 20MHz at -0.5dB FS fINA or B = 20MHz at -0.5dB FS Figure 3 (Note 3) Figure 3 (Note 3) 5 5 6 10 1.5 12.5 ±3.8 12.5 ±3.8 0.41 1.5 -70 0.02 0.25 ±0.2 8 8 ns ns ns ns ns ns ns µs PSRR Offset Gain 2.7 1.7 3.0 2.5 35 2.8 1 4 100 2 105 8.4 3 ±0.2 ±0.1 45 10 150 15 3.6 3.6 50 V V mA µA mA µA mW µW mV/V %/V SYMBOL CONDITIONS MIN TYP MAX UNITS CHANNEL-TO-CHANNEL MATCHING Crosstalk Gain Matching Phase Matching dB dB degrees Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a 1.024V full-scale input voltage range. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is 6dB or better, if referenced to the two-tone envelope. Note 3: Digital outputs settle to VIH and VIL. Parameter guaranteed by design. Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down. Note 5: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL. _______________________________________________________________________________________ 5 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1186 Typical Operating Characteristics (V DD = 3V, OV DD = 2.5V, V REFIN = 2.048V, differential input at -0.5dB FS, f CLK = 40.00057MHz, C L ≈ 10pF, T A = +25 ° C, unless otherwise noted.) FFT PLOT CHA (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) MAX1186 toc01 FFT PLOT CHB (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) MAX1186 toc02 FFT PLOT CHA (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 HD2 HD3 fCLK = 40.0005678MHz fINA = 19.8879776MHz fINB = 24.9661747MHz AINA = -0.516dB FS CHA MAX1186 toc03 MAX1186 toc09 MAX1186 toc06 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 2 4 6 8 HD2 HD3 CHA fCLK = 40.0005678MHz fINA = 6.1475482MHz fINB = 7.5342866MHz AINA = -0.552dB FS 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 HD2 HD3 CHB fCLK = 40.0005678MHz fINA = 6.1475482MHz fINB = 7.5342866MHz AINB = -0.534dB FS 0 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) FFT PLOT CHB (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) MAX1186 toc04 TWO-TONE IMD PLOT (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 IMD2 fCLK = 40.0005678MHz fIN1 = 11.606610MHz fIN2 = 13.383979MHz AIN = -6.5dB FS TWO-TONE ENVELOPE = -0.471dB FS fIN1 IMD3 IMD3 IMD2 MAX1186 toc05 SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY 61 CHB 60 59 SNR (dB) CHA 58 57 56 55 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 2 4 6 8 HD2 HD3 fCLK = 40.0005678MHz fINA = 19.8879776MHz fINB = 24.9661747MHz AINB = -0.498dB FS CHB 0 fIN2 -80 -90 -100 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 1 10 ANALOG INPUT FREQUENCY (MHz) 100 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUECNY MAX1186 toc07 TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY MAX1186 toc08 SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY 80 CHB 62 CHB 60 SINAD (dB) -60 -64 CHA 76 SFDR (dBc) THD (dBc) -68 72 58 CHA -72 CHB 68 CHA 64 56 -76 54 1 10 ANALOG INPUT FREQUENCY (MHz) 100 -80 1 10 ANALOG INPUT FREQUENCY (MHz) 100 60 1 10 ANALOG INPUT FREQUENCY (MHz) 100 6 _______________________________________________________________________________________ Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs Typical Operating Characteristics (continued) (V DD = 3V, OV DD = 2.5V, V REFIN = 2.048V, differential input at -0.5dB FS, f CLK = 40.00057MHz, C L ≈ 10pF, T A = +25 ° C, unless otherwise noted.) FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED MAX1186 toc10 MAX1186 SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED MAX1186 toc11 SIGNAL-TO-NOISE RATIO vs. INPUT POWER (fIN = 19.8879776MHz) MAX1186 toc12 6 4 2 GAIN (dB) 6 VIN = 100mVP-P 4 2 65 60 55 GAIN (dB) 0 -2 -4 -6 -8 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz) 0 -2 -4 -6 -8 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz) SNR (dB) 50 45 40 35 -20 -16 -12 -8 -4 0 INPUT POWER (dB FS) SIGNAL-TO-NOISE PLUS DISTORTION vs. INPUT POWER (fIN = 19.8879776MHz) MAX1186 toc13 TOTAL HARMONIC DISTORTION vs. INPUT POWER (fIN = 19.8879776MHz) MAX1186 toc14 SPURIOUS-FREE DYNAMIC RANGE vs. INPUT POWER (fIN = 19.8879776MHz) MAX1186 toc15 65 60 55 SINAD (dB) 50 45 40 35 -20 -16 -12 -8 -4 0 INPUT POWER (dB FS) -55 80 -60 75 SFDR (dBc) -20 -16 -12 -8 -4 0 THD (dBc) -65 70 -70 -75 65 -80 INPUT POWER (dB FS) 60 -20 -16 -12 -8 -4 0 INPUT POWER (dB FS) INTEGRAL NONLINEARITY (BEST ENDPOINT FIT) MAX1186 toc16 DIFFERENTIAL NONLINEARITY MAX1186 toc17 GAIN ERROR vs. TEMPERATURE EXTERNAL REFERENCE (VREFIN = 2.048V) MAX1186 toc18 0.3 0.2 0.1 0.3 0.2 0.1 DNL (LSB) 0 -0.1 -0.2 -0.3 0.4 0.3 GAIN ERROR (%FS) 0.2 CHB 0.1 0 -0.1 -0.2 CHA INL (LSB) 0 -0.1 -0.2 -0.3 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 7 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1186 Typical Operating Characteristics (continued) (V DD = 3V, OV DD = 2.5V, V REFIN = 2.048V, differential input at -0.5dB FS, f CLK = 40.00057MHz, C L ≈ 10pF, T A = +25 ° C, unless otherwise noted.) OFFSET ERROR vs. TEMPERATURE EXTERNAL REFERENCE (VREFIN = 2.048V) MAX1186 toc19 ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE MAX1186 toc20 ANALOG SUPPLY CURRENT vs. TEMPERATURE MAX1186 toc21 0.2 0.1 OFFSET ERROR (%FS) 0 45 42 41 40 43 IVDD (mA) IVDD (mA) 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 41 -0.1 -0.2 -0.3 CHA -0.4 -40 -15 10 35 60 85 TEMPERATURE (°C) CHB 39 38 39 37 37 36 -40 -15 10 35 60 85 TEMPERATURE (°C) 35 ANALOG POWER-DOWN CURRENT vs. ANALOG POWER SUPPLY MAX1186 toc22 SFDR, SNR, THD, SINAD vs. CLOCK DUTY CTCLE MAX1186 toc23 INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE MAX1186 toc24 0.40 OE = PD = OVDD 0.32 80 SFDR SFDR, SNR, THD, SINAD (dB) 74 fINA/B = 7.5342866MHz 2.0100 2.0080 VREFOUT (V) IVDD (µA) 0.24 68 SNR 62 THD 2.0060 0.16 2.0040 0.08 56 SINAD 2.0020 0 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 50 20 30 40 50 60 70 80 CLOCK DUTY CYCLE (%) 2.0000 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX1186 toc25 OUTPUT NOISE HISTOGRAM (DC INPUT) 63,000 56,000 49,000 64,515 MAX1186 toc26 2.014 70,000 2.010 VREOUT (V) COUNTS 2.006 42,000 35,000 28,000 21,000 2.002 1.998 14,000 7,000 0 N-2 869 N-1 N 152 N+1 0 N+2 1.994 -40 -15 10 35 60 85 TEMPERATURE (°C) 0 DIGITAL OUTPUT CODE 8 _______________________________________________________________________________________ Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1186 Pin Description PIN 1 2, 6, 11, 14, 15 3, 7, 10, 13, 16 4 5 8 9 12 17 NAME COM VDD GND INA+ INAINBINB+ CLK T/B FUNCTION Common-Mode Voltage Input/Output. Bypass to GND with a ≥0.1µF capacitor. Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. Analog Ground Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+. Channel A Negative Analog Input. For single-ended operation, connect INA- to COM. Channel B Negative Analog Input. For single-ended operation, connect INB- to COM. Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+. Converter Clock Input T/B selects the ADC digital output format. High: Two’s complement. Low: Straight offset binary. Sleep Mode Input. High: Deactivates the two ADCs, but leaves the reference bias circuit active. Low: Normal operation. Power-Down Input. High: Power-down mode. Low: Normal operation. Output Enable Input. High: Digital outputs disabled. Low: Digital outputs enabled. No Connection A/B Data Indicator. This digital output indicates CHA data (A/B = 1) or CHB data (A/B = 0) to be present on the output. A/B follows the external clock signal with typically 6ns delay. Output Driver Ground Output Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2µF in parallel with 0.1µF. Three-State Digital Output, Bit 0 (LSB). Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 1. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 2. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 3. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 4. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 5. Depending on status of A/B, output data reflects channel A or channel B data. 18 SLEEP 19 PD 20 21–29 30 31, 34 32, 33 35 36 37 38 39 40 OE N.C. A/B OGND OVDD D0A/B D1A/B D2A/B D3A/B D4A/B D5A/B _______________________________________________________________________________________ 9 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1186 Pin Description (continued) PIN 41 42 43 44 45 46 47 48 NAME D6A/B D7A/B D8A/B D9A/B REFOUT REFIN REFP REFN FUNCTION Three-State Digital Output, Bit 6. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 7. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 8. Depending on status of A/B, output data reflects channel A or channel B data. Three-State Digital Output, Bit 9 (MSB). Depending on status of A/B, output data reflects channel A or channel B data. Internal Reference Voltage Output. Maybe connected to REFIN through a resistor or a resistordivider. Reference Input. VREFIN = 2 ✕ (VREFP - VREFN). Bypass to GND with a >1nF capacitor. Positive Reference Input/Output. Conversion range is ±(VREFP - VREFN). Bypass to GND with a >0.1µF capacitor. Negative Reference Input/Output. Conversion range is ±(VREFP - VREFN). Bypass to GND with a >0.1µF capacitor. 10 ______________________________________________________________________________________ Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs Detailed Description The MAX1186 uses a nine-stage, fully-differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every one-half clock cycle. Including the delay through the output latch, the total clock-cycle latency is five clock cycles. 1.5-bit (2-comparator) flash ADCs convert the held input voltages into a digital code. The digital-to-analog converters (DACs) convert the digitized results back into analog voltages, which are then subtracted from the original held input signals. The resulting error signals are then multiplied by two and the residues are passed along to the next pipeline stages, where the process is repeated until the signals have been processed by all nine stages. Digital error correction compensates for ADC comparator offsets in each of these pipeline stages and ensures no missing codes. Both input channels are sampled on the rising edge of the clock and the resulting data is multiplexed at the output. CHA data is updated on the rising edge (5 clock cycles later) and CHB data is updated on the falling edge (5.5 clock cycles later) of the clock signal. The A/B indicator follows the clock signal with a typical delay time of 6ns and remains high when CHA data is updated and low when CHB data is updated. MAX1186 Input Track-and-Hold (T/H) Circuits Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuits in both track- and holdmode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully-differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1, sampling the input waveform. Switches S4a and S4b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers are used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1186 to track and sample/hold analog inputs of high frequencies (> Nyquist). Both ADC inputs (INA+, INB+, INA-, and INB-) can be driven either differentially or single-ended. Match the impedance of INA+ and INA-, as well as INB+ and INB-, and set the common-mode voltage to midsupply (VDD/2) for optimum performance. VIN T/H Σ x2 VOUT VIN T/H Σ x2 VOUT FLASH ADC 1.5 BITS DAC FLASH ADC 1.5 BITS DAC 2-BIT FLASH ADC STAGE 1 STAGE 2 STAGE 8 STAGE 9 STAGE 1 STAGE 2 STAGE 8 2-BIT FLASH ADC STAGE 9 DIGITAL CORRECTION LOGIC T/H 10 T/H VINB OUTPUT MULTIPLEXER 10 D0A/B–D9A/B DIGITAL CORRECTION LOGIC 10 VINA Figure 1. Pipelined Architecture—Stage Blocks ______________________________________________________________________________________ 11 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs MAX1186 INTERNAL BIAS S2a C1a S4a INA+ C2a S4c S1 OUT S4b C2b C1b S3b S2b INTERNAL BIAS S5b COM HOLD INTERNAL BIAS S2a C1a S4a INB+ C2a S4c S1 OUT S4b C2b C1b S3b S2b INTERNAL BIAS S5b COM OUT TRACK HOLD TRACK CLK INTERNAL NONOVERLAPPING CLOCK SIGNALS OUT COM S5a S3a INA- COM S5a S3a INB- MAX1186 Figure 2. MAX1186 T/H Amplifiers 12 ______________________________________________________________________________________ Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs Analog Inputs and Reference Configurations The full-scale range of the MAX1186 is determined by the internally generated voltage difference between REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The full-scale range for both on-chip ADCs is adjustable through the REFIN pin, which is provided for this purpose. REFOUT, REFP, COM (VDD/2), and REFN are internally buffered low-impedance outputs. The MAX1186 provides three modes of reference operation: • Internal reference mode • Buffered external reference mode • Unbuffered external reference mode In internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g., 10kΩ) or resistor-divider, if an application requires a reduced full-scale range. For stability and noise filtering purposes, bypass REFIN with a >10nF capacitor to GND. In internal reference mode, REFOUT, COM, REFP, and REFN become low-impedance outputs. In buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accurate voltage at REFIN. In this mode, COM, REFP, and REFN become outputs. REFOUT may be left open or connected to REFIN through a >10kΩ resistor. In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REFP, COM, and REFN. With their buffers shut down, these nodes become high impedance and may be driven through separate, external reference sources. The MAX1186 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50%, must meet the specifications for high and low periods as stated in the Electrical Characteristics. MAX1186 System Timing Requirements Figure 3 shows the relationship between clock and analog input, A/B indicator, and the resulting CHA/CHB data output. CHA and CHB data are sampled on the rising edge of the clock signal. Following the rising edge of the 5th clock cycles, the digitized value of the original CHA sample is presented at the output. This followed one-half clock cycle later by the digitized value of the original CHB sample. A channel selection signal (A/B indicator) allows the user to determine which output data represents which input channel. With A/B = 1, digitized data from CHA is present at the output and with A/B = 0 digitized data from CHB is present. Digital Output Data, Output Data Format Selection (T/B), Output Enable (OE), Channel Selection (A/B) All digital outputs, D0A/B–D9A/B (CHA or CHB data) and A/B are TTL/CMOS logic-compatible. The output coding can be chosen to be either offset binary or two’s complement (Table 1) controlled by a single pin (T/B). Pull T/B low to select offset binary and high to activate two’s complement output coding. The capacitive load on the digital outputs D0A/B–D9A/B should be kept as low as possible (