MAX1192ETI-T

19-2835; Rev 1; 9/03 Ultra-Low-Power, 22Msps, Dual 8-Bit ADC General Description The MAX1192 is an ultra-low-power, dual, 8-bit, 22Msps analog-to-digital converter (ADC). The device features two fully differential wideband track-and-hold (T/H) inputs. These inputs have a 440MHz bandwidth and accept fully differential or single-ended signals. The MAX1192 delivers a typical signal-to-noise and distortion (SINAD) of 48.6dB at an input frequency of 5.5MHz and a sampling rate of 22Msps while consuming only 27.3mW. This ADC operates from a 2.7V to 3.6V analog power supply. A separate 1.8V to 3.6V supply powers the digital output driver. In addition to ultra-low operating power, the MAX1192 features three power-down modes to conserve power during idle periods. Excellent dynamic performance, ultra-low power, and small size make the MAX1192 ideal for applications in imaging, instrumentation, and digital communications. An internal 1.024V precision bandgap reference sets the full-scale range of the ADC to ±0.512V. A flexible reference structure allows the MAX1192 to use its internal reference or accept an externally applied reference for applications requiring increased accuracy. The MAX1192 features parallel, multiplexed, CMOScompatible tri-state outputs. The digital output format is offset binary. A separate digital power input accepts a voltage from 1.8V to 3.6V for flexible interfacing to different logic levels. The MAX1192 is available in a 5mm × 5mm, 28-pin thin QFN package, and is specified for the extended industrial (-40°C to +85°C) temperature range. For higher sampling frequency applications, refer to the MAX1195–MAX1198 dual 8-bit ADCs. Pin-compatible versions of the MAX1192 are also available. Refer to the MAX1191 data sheet for 7.5Msps, and the MAX1193 data sheet for 45Msps. Features o Ultra-Low Power 27.3mW (Normal Operation: 22Msps) 1.8µW (Shutdown Mode) o Excellent Dynamic Performance 48.6dB/47.2dB SNR at fIN = 5.5MHz/125MHz 70dBc/69dBc SFDR at fIN = 5.5MHz/125MHz o 2.7V to 3.6V Single Analog Supply o 1.8V to 3.6V TTL/CMOS-Compatible Digital Outputs o Fully Differential or Single-Ended Analog Inputs o Internal/External Reference Option o Multiplexed CMOS-Compatible Tri-State Outputs o 28-Pin Thin QFN Package o Evaluation Kit Available (Order MAX1193EVKIT) MAX1192 Ordering Information PART MAX1192ETI-T TEMP RANGE -40°C to +85°C PIN-PACKAGE 28 Thin QFN-EP* (5mm x 5mm) *EP = Exposed paddle. Pin Configuration TOP VIEW REFIN REFN REFP COM PD0 PD1 VDD 28 27 26 25 24 23 Applications Ultrasound and Medical Imaging IQ Baseband Sampling Battery-Powered Portable Instruments Low-Power Video WLAN, Mobile DSL, WLL Receiver 22 INAINA+ GND CLK GND INB+ INB- 1 2 3 4 5 6 7 EXPOSED PADDLE 21 20 19 D0 D1 D2 D3 A/B D4 D5 MAX1192 18 17 16 15 12 13 D7 10 11 GND VDD VDD 5mm x 5mm THIN QFN ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. OGND OVDD D6 14 8 9 Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192 ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V INA+, INA-, INB+, INB- to GND .................-0.3V to (VDD + 0.3V) CLK, REFIN, REFP, REFN, COM to GND ...-0.3V to (VDD + 0.3V) PD0, PD1 to OGND .................................-0.3V to (OVDD + 0.3V) Digital Outputs to OGND .........................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 28-Pin Thin QFN (derated 20.8mW/°C above +70°C) ..1667mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range ............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 22MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error DC Gain Matching Gain Temperature Coefficient Power-Supply Rejection ANALOG INPUT Differential Input Voltage Range Common-Mode Input Voltage Range Input Resistance Input Capacitance CONVERSION RATE Clock Frequency Range Data Latency fCLK Channel A Channel B fIN = 1.875MHz SNR fIN = 5.5MHz fIN = 11MHz Signal-to-Noise and Distortion (Note 2) fIN = 1.875MHz SINAD fIN = 5.5MHz fIN = 11MHz 47 47 7.5 5.0 5.5 48.6 48.6 48.6 48.7 48.6 48.6 dB dB 22 MHz Clock cycles VDIFF VCOM RIN CIN Switched capacitor load Differential or single-ended inputs ±0.512 VDD / 2 245 5 V V kΩ pF Offset (VDD ±5%) Gain (VDD ±5%) INL DNL No missing codes over temperature ≥ +25°C < +25°C Excludes REFP - REFN error ±0.01 ±30 ±0.02 ±0.05 8 ±0.15 ±0.14 ±1.00 ±1.00 ±4 ±6 ±2 ±0.2 Bits LSB LSB %FS %FS dB ppm/°C LSB SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT) Signal-to-Noise Ratio (Note 2) 2 _______________________________________________________________________________________ Ultra-Low-Power, 22Msps, Dual 8-Bit ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 22MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Spurious-Free Dynamic Range (Note 2) SYMBOL SFDR fIN = 5.5MHz fIN = 11MHz Third-Harmonic Distortion (Note 2) Intermodulation Distortion Third-Order Intermodulation Total Harmonic Distortion (Note 2) Small-Signal Bandwidth Full-Power Bandwidth Aperture Delay Aperture Jitter Overdrive Recovery Time REFP Output Voltage REFN Output Voltage COM Output Voltage Differential Reference Output Differential Reference Output Temperature Coefficient Maximum REFP/REFN/COM Source Current Maximum REFP/REFN/COM Sink Current VCOM VREF VREFTC ISOURCE ISINK VREFP - VREFN fIN = 1.875MHz HD3 fIN = 5.5MHz fIN = 11MHz IMD IM3 fIN1 = 1MHz at -7dB FS, fIN2 = 1.01MHz at -7dB FS fIN1 = 1MHz at -7dB FS, fIN2 = 1.01MHz at -7dB FS fIN = 1.875MHz THD SSBW FPBW tAD tAJ 1.5 × full-scale input VREFP - VCOM VREFN - VCOM VDD / 2 - 0.15 fIN = 5.5MHz fIN = 11MHz Input at -20dB FS Input at -0.5dB FS CONDITIONS fIN = 1.875MHz 59.0 MIN TYP 70.8 70.0 70.4 75.8 -74.0 -74.8 -64 -67 -71.0 -70.0 -70.2 440 440 1.5 2 2 0.256 -0.256 VDD / 2 0.512 ±30 2 2 VDD / 2 + 0.15 MHz MHz ns psRMS ns V V V V ppm/°C mA mA -57.0 dBc dBc dBc dBc dBc MAX UNITS MAX1192 INTERNAL REFERENCE (REFIN = VDD; VREFP, VREFN, and VCOM are generated internally) BUFFERED EXTERNAL REFERENCE (VREFIN = 1.024V, VREFP, VREFN, and VCOM are generated internally) REFIN Input Voltage COM Output Voltage Differential Reference Output Maximum REFP/REFN/COM Source Current VREFIN VCOM VREF ISOURCE VREFP - VREFN VDD / 2 - 0.15 1.024 VDD / 2 0.512 2 VDD / 2 + 0.15 V V V mA _______________________________________________________________________________________ 3 Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192 ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 22MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Maximum REFP/REFN/COM Sink Current REFIN Input Resistance REFIN Input Current REFP Input Voltage REFN Input Voltage COM Input Voltage Differential Reference Input Voltage REFP Input Resistance REFN Input Resistance DIGITAL INPUTS (CLK, PD0, PD1) CLK Input High Threshold VIH PD0, PD1 CLK Input Low Threshold VIL PD0, PD1 Input Hysteresis Digital Input Leakage Current Digital Input Capacitance DIGITAL OUTPUTS (D7–D0, A/B) Output Voltage Low Output Voltage High Tri-State Leakage Current Tri-State Output Capacitance VOL VOH ILEAK COUT 5 ISINK = 200µA ISOURCE = 200µA 0.8 x OVDD ±5 0.2 x OVDD V V µA pF VHYST DIIN DCIN CLK at GND or VDD PD0 and PD1 at OGND or OVDD 5 0.1 ±5 ±5 0.7 x VDD 0.7 x OVDD 0.3 x VDD 0.3 x OVDD V µA pF VCOM VREF RREFP RREFN VREFP - VREFN Measured between REFP and COM Measured between REFN and COM VREFP - VCOM VREFN - VCOM SYMBOL ISINK CONDITIONS MIN TYP 2 >500 -0.7 0.256 -0.256 VDD / 2 0.512 4 4 MAX UNITS mA kΩ µA V V V V kΩ kΩ UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, VREFP, VREFN, and VCOM are applied externally) V V 4 _______________________________________________________________________________________ Ultra-Low-Power, 22Msps, Dual 8-Bit ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 22MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER POWER REQUIREMENTS Analog Supply Voltage Digital Output Supply Voltage VDD OVDD Normal operating mode, fIN = 1.875MHz at -0.5dB FS, fCLK = 7.5MHz, CLK input from GND to VDD Normal operating mode, fIN = 5.5MHz at -0.5dB FS, fCLK = 22MHz, CLK input from GND to VDD Idle mode (tri-state), fIN = 1.875MHz at 0.5dB FS, fCLK = 7.5MHz, CLK input from GND to VDD Analog Supply Current IDD Idle mode (tri-state), fIN = 5.5MHz at -0.5dB FS, fCLK = 22MHz, CLK input from GND to VDD Standby mode, fCLK = 7.5MHz, CLK input from GND to VDD Standby mode, fCLK = 22MHz, CLK input from GND to VDD Shutdown mode, CLK = GND or VDD, PD0 = PD1 = OGND Normal operating mode, fIN = 1.875MHz at -0.5dB FS, fCLK = 7.5MHz, CL ≈ 10pF Normal operating mode, fIN = 5.5MHz at -0.5dB FS, fCLK = 22MHz, CL ≈ 10pF Digital Output Supply Current (Note 3) IODD Idle mode (tri-state), DC input, CLK = GND or VDD, PD0 = OVDD, PD1 = OGND Standby mode, DC input, CLK = GND or VDD, PD0 = OGND, PD1 = OVDD Shutdown mode, CLK = GND or VDD, PD0 = PD1 = OGND 9.1 2.7 1.8 4.2 3.0 3.6 VDD 5.0 V V SYMBOL CONDITIONS MIN TYP MAX UNITS MAX1192 9.1 10.5 4.2 mA 2.3 4.9 0.6 5.0 µA 1.0 mA 2.9 0.1 5.0 µA 0.1 0.1 5.0 _______________________________________________________________________________________ 5 Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192 ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 22MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER TIMING CHARACTERISTICS CLK Rise to CHA Output Data Valid CLK Fall to CHB Output Data Valid CLK Rise/Fall to A/B Rise/Fall Time PD1 Rise to Output Enable PD1 Fall to Output Disable CLK Duty Cycle CLK Duty Cycle Variation Wake-Up Time from Shutdown Mode Wake-Up Time from Standby Mode Digital Output Rise/Fall Time INTERCHANNEL CHARACTERISTICS Crosstalk Rejection Amplitude Matching Phase Matching fIN,X = 5.5MHz at -0.5dB FS, fIN,Y = 0.3MHz at -0.5dB FS (Note 6) fIN = 5.5MHz at -0.5dB FS (Note 7) fIN = 5.5MHz at -0.5dB FS (Note 7) -75 ±0.03 ±0.1 dB dB Degrees tWAKE, SD (Note 5) tWAKE, ST (Note 5) 20% to 80% tDOA tDOB tDA/B tEN tDIS 50% of CLK to 50% of data, Figure 5 (Note 4) 50% of CLK to 50% of data, Figure 5 (Note 4) 50% of CLK to 50% of A/B, Figure 5 (Note 4) PD0 = OVDD PD0 = OVDD 1 1 1 6 6 6 5 5 50 ±10 20 5.4 2 8.5 8.5 8.5 ns ns ns ns ns % % µs µs ns SYMBOL CONDITIONS MIN TYP MAX UNITS Note 1: Specifications ≥+25°C guaranteed by production test, 0.8 x VDD REFERENCE MODE Internal reference mode. VREF is internally generated to be 0.512V. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Buffered external reference mode. An external 1.024V ±10% reference voltage is applied to REFIN. VREF is internally generated to be VREFIN/2. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor. Unbuffered external reference mode. REFP, REFN, and COM are driven by external reference sources. VREF is the difference between the externally applied VREFP and VREFN. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. 1.024V ±10% Nyquist). Both ADC inputs (INA+, INB+, INA-, and INB-) can be driven either differentially or single ended. Match the impedance of INA+ and INA-, as well as INB+ and INB-, and set the common-mode voltage to midsupply (VDD/2) for optimum performance. 62.5µA MAX1192 4kΩ REFP 1.75V COM 0µA Analog Inputs and Reference Configurations The MAX1192 full-scale analog input range is ±VREF with a common-mode input range of VDD/2 ±0.2V. VREF is the difference between V REFP and V REFN . The MAX1192 provides three modes of reference operation. The voltage at REFIN (VREFIN) sets the reference operation mode (Table 1). In internal reference mode, connect REFIN to VDD or leave REFIN unconnected. VREF is internally generated to be 0.512V ±3%. COM, REFP, and REFN are lowimpedance outputs with VCOM = VDD/2, VREFP = VDD/2 + VREF/2, and VREFN = VDD/2 - VREF/2. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. In buffered external reference mode, apply a 1.024V ±10% at REFIN. In this mode, COM, REFP, and REFN are low-impedance outputs with VCOM = VDD/2, VREFP = V DD /2 + V REFIN /4, and V REFN = V DD /2 - V REFIN /4. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor. In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for COM, REFP, and REFN. With their buffers shut down, these nodes become high-impedance inputs (Figure 4) and can be driven through separate, external reference sources. Drive VCOM to VDD/2 ±10%, drive 1.5V 4kΩ 62.5µA REFN 1.25V Figure 4. Unbuffered External Reference Mode Impedance VREFP to (VDD/2 +0.256V) ±10%, and drive VREFN to (VDD/2 - 0.256V) ±10%. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. For detailed circuit suggestions and how to drive this dual ADC in buffered/unbuffered external reference mode, see the Applications Information section. Clock Input (CLK) CLK accepts a CMOS-compatible signal level. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (