MAX1198ECM

19-2412; Rev 0; 4/02 Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs General Description The MAX1198 is a 3.3V, dual, 8-bit analog-to-digital converter (ADC) featuring fully differential wideband trackand-hold (T/H) inputs, driving two ADCs. The MAX1198 is optimized for low power, small size, and high-dynamic performance for applications in imaging, instrumentation, and digital communications. This ADC operates from a single 2.7V to 3.6V supply, consuming only 264mW, while delivering a typical signal-to-noise and distortion (SINAD) of 48.1dB at an input frequency of 50MHz and a sampling rate of 100Msps. The T/H-driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters may also be operated with singleended inputs. In addition to low operating power, the MAX1198 features a 3.2mA sleep mode, as well as a 0.15µA power-down mode to conserve power during idle periods. An internal 2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of this internal or an externally applied reference, if desired, for applications requiring increased accuracy or a different input voltage range. The MAX1198 features parallel, CMOS-compatible threestate outputs. The digital output format can be set to two’s complement or straight offset binary through a single control pin. The device provides for a separate output power supply of 1.7V to 3.6V for flexible interfacing with various logic families. The MAX1198 is available in a 7mm x 7mm, 48-pin TQFP package, and is specified for the extended industrial (-40°C to +85°C) temperature range. Pin-compatible lower speed versions of the MAX1198 are also available. Refer to the MAX1195 data sheet for 40Msps and the MAX1197 data sheet for 60Msps. In addition to these speed grades, this family includes a multiplexed output version (MAX1196, 40Msps), for which digital data is presented time interleaved and on a single, parallel 8-bit output port. For a 10-bit, pin-compatible upgrade, refer to the MAX1180 data sheet. With the N.C. pins of the MAX1198 internally pulled down to ground, this ADC becomes a drop-in replacement for the MAX1180. o Single 2.7V to 3.6V Operation o Excellent Dynamic Performance 48.1dB/47.6dB SINAD at fIN = 50MHz/200MHz 66dBc/61.5dBc SFDR at fIN = 50MHz/200MHz o -72dB Interchannel Crosstalk at fIN = 50MHz o Low Power 264mW (Normal Operation) 10.6mW (Sleep Mode) 0.5µW (Shutdown Mode) o 0.05dB Gain and ±0.1° Phase Matching o Wide ±1VP-P Differential Analog Input Voltage Range o 400MHz -3dB Input Bandwidth o On-Chip 2.048V Precision Bandgap Reference o User-Selectable Output Format—Two’s Complement or Offset Binary o Pin-Compatible 8-Bit and 10-Bit Upgrades Available Features MAX1198 Ordering Information PART MAX1198ECM TEMP RANGE -40°C to +85°C PIN-PACKAGE 48 TQFP-EP* *EP = Exposed paddle Functional Diagram and Pin Compatible Upgrades table appear at end of data sheet. Pin Configuration REFN REFP REFIN REFOUT D7A D6A D5A D4A D3A D2A D1A D0A 48 47 46 45 44 43 42 41 40 39 38 COM VDD GND INA+ INAVDD GND INBINB+ GND VDD CLK 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 N.C. N.C. OGND OVDD OVDD OGND N.C. N.C. D0B D1B D2B D3B Applications Baseband I/Q Sampling Multichannel IF Sampling Ultrasound and Medical Imaging Battery-Powered Instrumentation WLAN, WWAN, WLL, MMDS Modems Set-Top Boxes VSAT Terminals MAX1198 30 29 28 27 26 25 VDD VDD GND ________________________________________________________________ Maxim Integrated Products T/B SLEEP PD OE D7B D6B D5B D4B GND TQFP-EP 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1198 ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V INA+, INA-, INB+, INB- to GND ...............................-0.3V to VDD REFIN, REFOUT, REFP, REFN, COM, CLK to GND .................................-0.3V to (VDD + 0.3V) OE, PD, SLEEP, T/B, D7A–D0A, D7B–D0B to OGND .............................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 48-Pin TQFP (derate 12.5mW/°C above +70°C).........1000mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3.3V, OVDD = 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 100MHz, TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, Nyquist). Both ADC inputs (INA+, INB+ and INA-, INB-) can be driven either differentially or single ended. ______________________________________________________________________________________ Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1198 5-CLOCK-CYCLE LATENCY N N+1 N+2 N+3 N+4 N+5 N+6 ANALOG INPUT tAD CLOCK INPUT tDO DATA OUTPUT D7A–D0A N-6 N-5 N-4 tCH N-3 tCL N-2 N-1 N N+1 DATA OUTPUT D7B–D0B N-6 N-5 N-4 N-3 N-2 N-1 N N+1 Figure 3. System Timing Diagram Match the impedance of INA+ and INA-, as well as INB+ and INB-, and set the common-mode voltage to mid supply (VDD/2) for optimum performance. Analog Inputs and Reference Configurations The full-scale range of the MAX1198 is determined by the internally generated voltage difference between REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The full-scale range for both on-chip ADCs is adjustable through the REFIN pin, which is provided for this purpose. The MAX1198 provides three modes of reference operation: • Internal reference mode • Buffered external reference mode • Unbuffered external reference mode In internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g., 10kΩ) or resistor-divider, if an application requires a reduced full-scale range. For stability and noise-filtering purposes, bypass REFIN with a >10nF capacitor to GND. In internal reference mode, REFOUT, COM, REFP, and REFN become low-impedance outputs. In buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accurate voltage at REFIN. In this mode, COM, REFP, and REFN are outputs. REFOUT can be left open or connected to REFIN through a >10kΩ resistor. In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REFP, COM, and REFN. With their buffers shut down, these nodes become high-impedance inputs and can be driven through separate, external reference sources. For detailed circuit suggestions and how to drive this dual ADC in buffered/unbuffered external reference mode, see the Applications Information section. Clock Input (CLK) The MAX1198’s CLK input accepts a CMOS-compatible clock signal. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (