MAX1205CMH

19-4794; Rev 0; 11/98 KIT ATION EVALU ABLE AVAIL +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC General Description Features o Monolithic, 14-Bit, 1Msps ADC o +5V Single Supply o SNR of 80dB for fIN = 500kHz o SFDR of 87dB for fIN = 500kHz o Low Power Dissipation: 257mW o On-Demand Self-Calibration o Differential Nonlinearity Error: ±0.3LSB o Integral Nonlinearity Error: ±1.2LSB o Three-State, Two’s Complement Output Data MAX1205 END_CAL The MAX1205 is a 14-bit, monolithic, analog-to-digital converter (ADC) capable of conversion rates up to 1Msps. This integrated circuit, built on a CMOS process, uses a fully differential, pipelined architecture with digital error correction and a short self-calibration procedure that corrects for capacitor and gain mismatches and ensures 14-bit linearity at full sample rates. An on-chip track/hold (T/H) maintains superb dynamic performance up to the Nyquist frequency. The MAX1205 operates from a single +5V supply. The fully differential inputs allow an input swing of ±VREF. The reference is also differential, with the positive reference (RFPF) typically connected to +4.096V and the negative reference (RFNF) connected to analog ground. Additional sensing pins (RFPS, RFNS) are provided to compensate for any resistive-divider action that may occur due to finite internal and external resistances in the reference traces and the on-chip resistance of the reference pins. A single-ended input is also possible using two operational amplifiers. The power dissipation is typically 257mW at +5V, at a sampling rate of 1Msps. The device employs a CMOScompatible, 14-bit parallel, two’s complement output data format. For higher sampling rates, the MAX1201 is a 2.2Msps pin-compatible upgrade to the MAX1205. The MAX1205 is available in an MQFP package, and operates over the commercial (0°C to +70°C) and the extended (-40°C to +85°C) temperature ranges. Ordering Information PART MAX1205CMH MAX1205EMH TEMP. RANGE 0°C to +70°C -40°C to +85°C PIN-PACKAGE 44 MQFP 44 MQFP Pin Configuration TOP VIEW 44 43 42 41 40 39 38 37 36 35 Imaging Communications Medical Scanners Data Acquisition ST_CAL AGND AVDD AGND AGND AVDD DOR D13 D12 D11 D10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 34 Applications TEST0 INP RFNS RFNF RFPS RFPF CM INN N.C. N.C. MAX1205 OE DAV CLK DVDD DGND DGND DVDD TEST1 TEST2 TEST3 D0 DGND D5 D4 D3 D2 D9 D8 ________________________________________________________________ Maxim Integrated Products D7 D6 DRVDD MQFP D1 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC MAX1205 ABSOLUTE MAXIMUM RATINGS AVDD to AGND, DGND ..........................................................+7V DVDD to DGND, AGND..........................................................+7V DRVDD to DGND, AGND .......................................................+7V INP, INN, RFPF, RFPS, RFNF, RFNS, CLK, CM.................................(AGND - 0.3V) to (AVDD + 0.3V) Digital Inputs to DGND ............................-0.3V to (DVDD + 0.3V) Digital Output (DAV) to DGND ..............-0.3V to (DRVDD + 0.3V) Other Digital Outputs to DGND .............-0.3V to (DRVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 44-Pin MQFP (derate 11.11mW/°C above +70°C)........889mW Operating Temperature Ranges (TA) MAX1205CMH .....................................................0°C to +70°C MAX1205EMH ..................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048V, VIN = -0.5dBFS, fCLK= 2.048MHz, digital output load ≤ 20pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER ANALOG INPUT Input Voltage Range (Notes 2, 3) Input Resistance (Note 4) Input Capacitance (Note 3) REFERENCE/EXTERNAL Reference Voltage (Note 3) Reference Input Resistance TRANSFER CHARACTERISTICS Resolution (no missing codes) (Note 5) Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Input-Referred Noise DYNAMIC SPECIFICATIONS (Note 6) Maximum Sampling Rate Conversion Time (Pipeline Delay/Latency) Acquisition Time Overvoltage Recovery Time Aperture Delay Full-Power Bandwidth Small-Signal Bandwidth tACQ tOVR tAD To full-scale step (0.006%) fSAMPLE fSAMPLE = fCLK / 2 1.024 4 100 410 3 3.3 78 Msps fSAMPLE Cycles ns ns ns MHz MHz RES INL DNL -1 -0.2 -5 After calibration, guaranteed 14 ±1.2 ±0.3 ±0.003 -3.0 75 +1 +0.2 +5 Bits LSB LSB %FSR %FSR µVRMS VREF 700 4.096 1000 4.5 V Ω VIN RI CI Per side in track mode Single-ended Differential 4.096 ±4.096 55 21 4.5 ±4.5 V kΩ pF SYMBOL CONDITIONS MIN TYP MAX UNITS 2 _______________________________________________________________________________________ +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC ELECTRICAL CHARACTERISTICS (continued) (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048V, VIN = -0.5dBFS, fCLK= 2.048MHz, digital output load ≤ 20pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Signal-to-Noise Ratio (Note 5) SYMBOL fIN = 99.5kHz SNR fIN = 300.5kHz fIN = 504.5kHz Spurious-Free Dynamic Range (Note 5) fIN = 99.5kHz SFDR fIN = 300.5kHz fIN = 504.5kHz Total Harmonic Distortion (Note 5) fIN = 99.5kHz THD fIN = 300.5kHz fIN = 504.5kHz Signal-to-Noise Ratio plus Distortion (Note 5) POWER REQUIREMENTS Analog Supply Voltage Analog Supply Current Digital Supply Voltage Digital Supply Current Output Drive Supply Voltage Output Drive Supply Current Power Dissipation Warm-Up Time Power-Supply Rejection Ratio PSRR Offset Gain 55 55 AVDD I(AVDD) DVDD I(DVDD) DRVDD I(DRVDD) PDSS 10pF loads on D0–D13 and DAV 3 0.1 257 0.1 3 0.4 4.75 5 51 5.25 70 5.25 1.2 DVDD 0.6 377 V mA V mA V mA mW sec dB fIN = 99.5kHz SINAD fIN = 300.5kHz fIN = 504.5kHz 77 84 CONDITIONS MIN 78 TYP 83 81.5 80 91 88 87 -86 -85 -84 82 79 78 dB -80 dB dB dB MAX UNITS MAX1205 _______________________________________________________________________________________ 3 +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC MAX1205 TIMING CHARACTERISTICS (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, fCLK = 2.048MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Conversion Time Clock Period Clock High Time Clock Low Time Acquisition Time Output Delay DAV Pulse Width CLK-to-DAV Rising Edge Data Access Time Bus Relinquish Time Calibration Time SYMBOL tCONV tCLK tCH tCL tACQ tOD tDAV tS tAC tREL tCAL ST_CAL = 1, Figure 8 CL = 20pF 187 187 CONDITIONS MIN TYP 4 / fSAMPLE 488 244 244 tCLK / 2 70 1 / fCLK 65 16 16 17,400 145 75 75 150 301 301 MAX UNITS ns ns ns ns ns ns ns ns ns ns fCLK cycles DIGITAL INPUTS AND OUTPUTS (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Input Low Voltage Input High Voltage Input Capacitance CLK Input Low Voltage CLK Input High Voltage CLK Input Capacitance Digital Input Current Clock Input Current Output Low Voltage Output High Voltage Three-State Leakage Current Three-State Output Capacitance CLKVIL CLKVIH CCLK IIN_ ICLK VOL VOH ILEAKAGE COUT ISINK = 1.6mA ISOURCE = 200µA DVDD - 0.4 VIN_ = 0 or DVDD -10 AVDD - 0.8 9 ±0.1 ±1 70 DVDD - 0.03 ±0.1 3.5 ±10 ±10 +10 400 SYMBOL VIL VIH DVDD - 0.8 4 0.8 CONDITIONS MIN TYP MAX 0.8 UNITS V V pF V V pF µA µA mV V µA pF Note 1: Reference inputs driven by operational amplifiers for Kelvin-sensed operation. Note 2: For unipolar mode, the analog input voltage VINP must be within 0V and VREF, VINN = VREF / 2; where VREF = VRFPS - VRFNS. For differential mode, the analog inputs INP and INN must be within 0V and VREF; where VREF = VRFPS - VRFNS. The common mode of the inputs INP and INN is VREF / 2. Note 3: Minimum and maximum parameters are not tested. Guaranteed by design. Note 4: RI varies inversely with sample rate. Note 5: Calibration remains valid for temperature changes within ±20°C and power-supply variations ±5%. Note 6: All AC specifications are shown for the differential mode. 4 _______________________________________________________________________________________ +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC Typical Operating Characteristics (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048V, differential input, fCLK= 2.048MHz, calibrated, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. TWO’S COMPLEMENT OUTPUT CODE MAX1205-01 MAX1205 DIFFERENTIAL NONLINEARITY vs. TWO’S COMPLEMENT OUTPUT CODE MAX1205-02 1.00 0.75 0.50 110 100 90 SFDR (dB) dBFS 0.5 DNL (LSB) INL (LSB) 0.25 0 -0.25 -0.50 -0.75 -1.00 -1.25 -8192 -6144 -4096 -2048 0 2048 4096 6144 8192 0 80 70 60 dBc -0.5 50 40 -1.0 -8192 -6144 -4096 -2048 0 30 2048 4096 6144 8192 -80 -70 -60 -50 -40 -30 -20 -10 0 INPUT AMPLITUDE (dBFS) TWO’S COMPLEMENT OUTPUT CODE TWO’S COMPLEMENT OUTPUT CODE SIGNAL-TO-NOISE RATIO PLUS DISTORTION vs. INPUT FREQUENCY MAX1205-04 TOTAL HARMONIC DISTORTION vs. INPUT FREQUENCY MAX1205-05 SIGNAL-TO-NOISE RATIO vs. INPUT FREQUENCY AIN = -0.5dBFS 80 AIN = -6dBFS SNR (dB) 75 MAX1205-06 84 82 80 78 SINAD (dB) 76 74 72 70 68 66 64 1 10 100 AIN = -6dBFS AIN = -0.5dBFS 85 -76 -78 -80 THD (dB) -82 -84 -86 AIN = -20dBFS AIN = -6dBFS 70 65 -88 AIN = -20dBFS 1000 -90 1 10 100 1000 INPUT FREQUENCY (kHz) AIN = -0.5dBFS 60 1 10 100 1000 INPUT FREQUENCY (kHz) AIN = -20dBFS INPUT FREQUENCY (kHz) SIGNAL-TO-NOISE RATIO PLUS DISTORTION vs. SAMPLING RATE (fIN = 99.5kHz) MAX1205-07 TYPICAL FFT (fIN = 99.5kHz, 2048 VALUE RECORD) -15 -30 AMPLITUDE (dBFS) -45 -60 -75 -90 -105 -120 -135 MAX1205-08 85 AIN = -0.5dBFS 84 SINAD (dB) 83 82 81 80 0.1 1 SAMPLE RATE (Msps) 0 0 100 200 300 400 500 600 FREQUENCY (kHz) _______________________________________________________________________________________ MAX1205-03 1.25 1.0 SINGLE-TONE SPURIOUS-FREE DYNAMIC RANGE vs. INPUT AMPLITUDE (fIN = 99.5kHz) 120 5 +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC MAX1205 Typical Operating Characteristics (continued) (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048V, differential input, fCLK= 2.048MHz, calibrated, TA = +25°C, unless otherwise noted.) TYPICAL FFT (fIN = 504.5kHz, 2048 VALUE RECORD) MAX1205-09 EFFECTIVE NUMBER OF BITS vs. INPUT FREQUENCY 13.5 13.0 ENOB (Bits) 12.5 12.0 11.5 11.0 10.5 10.0 AIN = -20dBFS AIN = -6dBFS AIN = -0.5dBFS MAX1205-10 14.0 -15 -30 AMPLITUDE (dBFS) -45 -60 -75 -90 -105 -120 -135 0 0 100 200 300 400 500 600 1 10 100 1000 FREQUENCY (kHz) INPUT FREQUENCY (kHz) Pin Description PIN 1 2, 4, 5 3, 6 7 8 9 10 11 12 13 14 15 16 17, 28, 29 18 19 20 21 22 23 24 NAME ST_CAL AGND AVDD DOR D13 D12 D11 D10 D9 D8 D7 D6 DRVDD DGND D5 D4 D3 D2 D1 D0 TEST3 Digital Input to Start Calibration. ST_CAL = 0: Normal conversion mode. ST_CAL = 1: Start self-calibration. Analog Ground Analog Power Supply, +5V ±5% Data Out-of-Range Bit Bit 13 (MSB) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Digital Power Supply for the Output Drivers, +3V to +5.25V, DRVDD ≤ DVDD Digital Ground Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Test Pin 3. Leave unconnected. FUNCTION 6 _______________________________________________________________________________________ +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC Pin Description (continued) PIN 25 26 27, 30 31 32 NAME TEST2 TEST1 DVDD CLK DAV Test Pin 2. Leave unconnected. Test Pin 1. Leave unconnected. Digital Power Supply, +3V to +5.25V Input Clock. Receives power from AVDD to reduce jitter. Data Valid Clock Output. This clock can be used to transfer the data to a memory or any other data-acquisition system. Output Enable Input. OE = 0: D0-D13 and DOR are high impedance. OE = 1: All bits are active. Test Pin 0. Leave unconnected. Common-Mode Voltage. Analog Input. Drive midway between positive and negative reference voltages. Positive Reference Voltage. Force input. Positive Reference Voltage. Sense input. Negative Reference Voltage. Force input. Negative Reference Voltage. Sense input. Positive Input Voltage Not Connected. No internal connection. Negative Input Voltage Digital Output for End of Calibration. END_CAL = 0: Calibration in progress. END_CAL = 1: Normal conversion mode. FUNCTION MAX1205 33 34 35 36 37 38 39 40 41, 42 43 44 OE TEST0 CM RFPF RFPS RFNF RFNS INP N.C. INN END_CAL _______________Detailed Description Converter Operation The MAX1205 is a 14-bit, monolithic, analog-to-digital converter (ADC) capable of conversion rates up to 1Msps. It uses a multistage, fully differential pipelined architecture with digital error correction and self-calibration to provide typically greater than 91dB spuriousfree dynamic range at a 1Msps sampling rate. Its signal-to-noise ratio, harmonic distortion, and intermodulation products are also consistent with 14-bit accuracy up to the Nyquist frequency. This makes the device suitable for applications such as imaging, scanners, data acquisition, and digital communications. Figure 1 shows the simplified, internal structure of the ADC. A switched-capacitor pipelined architecture is used to digitize the signal at a high throughput rate. The first four stages of the pipeline use a low-resolution quantizer to approximate the input signal. The multiplying digital-to-analog converter (MDAC) stage is used to subtract the quantized analog signal from the input. The residue is then amplified with a fixed gain and passed on to the next stage. The accuracy of the converter is improved by a digital calibration algorithm which corrects for mismatches between the capacitors in the switched capacitor MDAC. Note that the pipeline introduces latency of four sampling periods between the input being sampled and the output appearing at D13–D0. While the device can handle both single-ended and differential inputs (see Requirements for Reference and Analog Signal Inputs), the latter mode of operation will guarantee best THD and SFDR performance. The differential input provides the following advantages compared to a single-ended operation: • Twice as much signal input span • Common-mode noise immunity • Virtual elimination of the even-order harmonics • Less stringent requirements on the input signal processing amplifiers _______________________________________________________________________________________ 7 +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC MAX1205 RFP_ STAGE1 INP INN S/H ADC MDAC 7 8X RFN_ CM STAGE2 AVDD STAGE3 AGND STAGE4 ADC CLK DVDD ST_CAL DGND OE DRVDD CLOCK GENERATOR DAV CORRECTION AND CALIBRATION LOGIC 17 END_CAL MAX1205 OUTPUT DRIVERS DOR D13–D0 Figure 1. Internal Block Diagram Requirements for Reference and Analog Signal Inputs Fully differential switched-capacitor circuits (SC) are used for both the reference and analog inputs (Figure 2). This allows either single-ended or differential signals to be used in the reference and/or analog signal paths. The signal voltage on these pins (INP, INN, RFN_, RFP_) should never exceed the analog supply rail, AVDD, and should not fall below ground. Choice of Reference It is important to choose a low-noise reference, such as the MAX6341, which can provide both excellent load regulation and low temperature drift. The equivalent input circuit for the reference pins is shown in Figure 3. Note that the reference pins drive approximately 1kΩ of resistance on chip. They also drive a switched capacitor of 21pF. To meet the dynamic performance, the reference voltage is required to settle to 0.0015% within one clock cycle. Accomplish this by choosing an appropriate driving circuit (Figure 4). The capacitors at the reference pins (RFPF, RFNF) provide the dynamic charge required during each clock cycle, while the op amps ensure accuracy of the reference signals. These capacitors must have low dielectric-absorption characteristics, such as polystyrene or teflon capacitors. The reference pins can be connected to either singleended or differential voltages within the specified maximum levels. Typically the positive reference pin (RFPF) would be driven to 4.096V, and the negative reference pin (RFNF) connected to analog ground. There are sense pins, RFPS and RFNS, which can be used with CM RFPF INP RFNF INN RFPF CM RFPS RFPF RFNF RFNS Figure 2. Simplified MDAC Architecture Figure 3. Equivalent Input at the Reference Pins. The sense pins should not draw any DC current. 8 _______________________________________________________________________________________ +5V Single-Supply, 1Msps, 14-Bit Self-Calibrating ADC external amplifiers to compensate for any resistive drop on these lines, internal or external to the chip. Ensure a correct reference voltage by using proper Kelvin connections at the sense pins. gle-ended inputs. In this case, convert the singleended signals into differential ones by using the circuit recommended in Figure 5. Use low-noise, wideband amplifiers such as the MAX4108 to maintain the signal purity over the full-power bandwidth of the MAX1205 input. Lowpass or bandpass signals may be required to improve the signal-to-noise-and-distortion ratio of the incoming signal. For low-frequency signals (