MAX1223

19-4010; Rev 1; 12/07 KIT ATION EVALU ILABLE AVA 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports General Description The MAX1221/MAX1223/MAX1343 integrate a multichannel, 12-bit, analog-to-digital converter (ADC) and a 12-bit, digital-to-analog converter (DAC) in a single IC. The devices also include a temperature sensor and configurable general-purpose I/O ports (GPIOs) with a 25MHz SPI™-/QSPI™-/MICROWIRE™-compatible serial interface. The ADC is available in a 12 or an eight input-channel version. The DAC outputs settle within 2.0µs, and the ADC has a 225ksps conversion rate. All devices include an internal reference (2.5V) providing a well-regulated, low-noise reference for both the ADC and DAC. Programmable reference modes for the ADC and DAC allow the use of an internal reference, an external reference, or a combination of both. Features such as an internal ±1°C accurate temperature sensor, FIFO, scan modes, programmable internal or external clock modes, data averaging, and AutoShutdown™ allow users to minimize both power consumption and processor requirements. The low glitch energy (4nV•s) and low digital feedthrough (0.5nV•s) of the integrated DACs make these devices ideal for digital control of fast-response closed-loop systems. The devices are guaranteed to operate with a supply voltage from +2.7V to +5.25V. The devices consume 2.5mA at 225ksps throughput, only 22µA at 1ksps throughput, and under 0.2µA in the shutdown mode. The MAX1221/ MAX1343 offer four GPIOs that can be configured as inputs or outputs. The MAX1221/MAX1223/MAX1343 are available in 36-pin thin QFN packages. All devices are specified over the -40°C to +85°C temperature range. Features ♦ 12-Bit, 225ksps ADC Analog Multiplexer with True-Differential Track/Hold (T/H) 12 Single-Ended Channels or Six Differential Channels (Unipolar or Bipolar) (MAX1223) Eight Single-Ended Channels or Four Differential Channels (Unipolar or Bipolar) (MAX1221/MAX1343) Excellent Accuracy: ±0.5 LSB INL, ±0.5 LSB DNL ♦ 12-Bit, Octal, 2µs Settling DAC (MAX1221/MAX1223) Ultra-Low Glitch Energy (4nV•s) Power-Up Options from Zero Scale or Full Scale Excellent Accuracy: ±0.5 LSB INL ♦ Internal Reference or External Single-Ended/ Differential Reference Internal Reference Voltage 2.5V ♦ Internal ±1°C Accurate Temperature Sensor ♦ On-Chip FIFO Capable of Storing 16 ADC Conversion Results and One Temperature Result ♦ On-Chip Channel-Scan Mode and Internal Data-Averaging Features ♦ Analog Single-Supply Operation +2.7V to +5.25V ♦ 2.7V to AVDD Digital Supply ♦ 25MHz, SPI/QSPI/MICROWIRE Serial Interface ♦ AutoShutdown Between Conversions ♦ Low-Power ADC 2.5mA at 225ksps 22µA at 1ksps 0.2µA at Shutdown ♦ Low-Power DAC: 1.5mA ♦ Evaluation Kit Available (Order MAX1258EVKIT) SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. AutoShutdown is a trademark of Maxim Integrated Products, Inc. Pin Configurations appear at end of data sheet. MAX1221/MAX1223/MAX1343 Applications Closed-Loop Controls for Optical Components and Base Stations System Supervision and Control Data-Acquisition Systems Ordering Information/Selector Guide PART MAX1221BETX MAX1223BETX MAX1343BETX PIN-PACKAGE 36 Thin QFN-EP* 36 Thin QFN-EP* 36 Thin QFN-EP* REF ANALOG RESOLUTION ADC VOLTAGE SUPPLY BITS** CHANNELS (V) VOLTAGE (V) 2.5 2.5 2.5 2.7 to 5.25 2.7 to 5.25 2.7 to 5.25 12 12 12 8 12 8 DAC CHANNELS 8 8 4 GPIOs 4 0 4 PKG CODE T3666-3 T3666-3 T3666-3 Note: All devices are specified over the -40°C to +85°C operating temperature range. *EP = Exposed pad. **Number of resolution bits refers to both DAC and ADC. ________________________________________________________________ Maxim Integrated Products 1 For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 ABSOLUTE MAXIMUM RATINGS AVDD to AGND .........................................................-0.3V to +6V DGND to AGND.....................................................-0.3V to +0.3V DVDD to AVDD .......................................................-3.0V to +0.3V Digital Inputs to DGND.............................................-0.3V to +6V Digital Outputs to DGND .........................-0.3V to (DVDD + 0.3V) Analog Inputs, Analog Outputs and REF_ to AGND...............................................-0.3V to (AVDD + 0.3V) Maximum Current into Any Pin (except AGND, DGND, AVDD, DVDD, and OUT_) ...........................................................50mA Maximum Current into OUT_.............................................100mA Continuous Power Dissipation (TA = +70°C) 36-Pin Thin QFN (6mm x 6mm) (derate 26.3mW/°C above +70°C) ......................2105.3mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-60°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Note: If the package power dissipation is not exceeded, one output at a time may be shorted to AVDD, DVDD, AGND, or DGND indefinitely. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V. TA = +25°C. Outputs are unloaded, unless otherwise noted.) PARAMETER DC ACCURACY (Note 1) Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Gain Temperature Coefficient Channel-to-Channel Offset DYNAMIC SPECIFICATIONS (10kHz sine-wave input, VIN = 2.5VP-P, 225ksps, fCLK = 3.6MHz) Signal-to-Noise Plus Distortion Total Harmonic Distortion (Up to the Fifth Harmonic) Spurious-Free Dynamic Range Intermodulation Distortion Full-Linear Bandwidth Full-Power Bandwidth CONVERSION RATE (Note 3) External reference Power-Up Time tPU Internal reference (Note 4) 0.8 218 µs Conversion clock cycles SINAD THD SFDR IMD fIN1 = 9.9kHz, fIN2 = 10.2kHz SINAD > 70dB -3dB point 70 -76 72 76 100 1 dB dBc dBc dBc kHz MHz (Note 2) INL DNL 12 ±0.5 ±0.5 ±0.5 ±0.5 ±0.8 ±0.1 ±1.0 ±1.0 ±4.0 ±4.0 Bits LSB LSB LSB LSB ppm/°C LSB SYMBOL CONDITIONS ADC MIN TYP MAX UNITS 2 _______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V. TA = +25°C. Outputs are unloaded, unless otherwise noted.) PARAMETER Acquisition Time Conversion Time External-Clock Frequency Duty Cycle Aperture Delay Aperture Jitter ANALOG INPUTS Input Voltage Range (Note 6) Input Leakage Current Input Capacitance INTERNAL TEMPERATURE SENSOR Measurement Error (Notes 5, 7) Temperature Resolution INTERNAL REFERENCE REF1 Output Voltage REF1 Voltage Temperature Coefficient REF1 Output Impedance REF1 Short-Circuit Current EXTERNAL REFERENCE REF1 Input Voltage Range REF2 Input Voltage Range (Note 4) VREF1 REF mode 11 (Note 4) REF mode 01 REF mode 11 1 1 0 AVDD + 0.05 AVDD + 0.05 1 V VREF = 2.5V TCREF (Note 8) 2.482 2.50 ±30 6.5 0.39 2.518 V ppm/°C kΩ mA TA = +25°C TA = TMIN to TMAX ±0.7 ±1.0 1/8 ±2.0 °C °C/LSB Unipolar Bipolar 0 -VREF / 2 ±0.01 24 VREF VREF / 2 ±1 V µA pF SYMBOL tACQ tCONV fCLK (Note 5) Internally clocked Externally clocked Externally clocked conversion (Note 5) 3.6 0.1 40 30 < 50 3.6 60 CONDITIONS MIN 0.6 5.5 TYP MAX UNITS µs µs MHz % ns ps MAX1221/MAX1223/MAX1343 VREF2 V _______________________________________________________________________________________ 3 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V. TA = +25°C. Outputs are unloaded, unless otherwise noted.) PARAMETER REF1 Input Current (Note 9) REF2 Input Current SYMBOL IREF1 IREF2 CONDITIONS VREF = 2.5V, fSAMPLE = 225ksps Acquisition between conversions VREF = 2.5V, fSAMPLE = 225ksps Acquisition between conversions DAC DC ACCURACY (Note 10) Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset-Error Drift Gain Error Gain Temperature Coefficient DAC OUTPUT No load Output Voltage Range 10kΩ load to either rail DC Output Impedance Capacitive Load Resistive Load to AGND RL (Note 11) AVDD = 2.7V, VREF = 2.5V, gain error < 1% 2000 0.1 0.5 1 AVDD 0.1 Ω nF Ω 0.02 AVDD 0.02 V GE (Note 8) INL DNL VOS Guaranteed monotonic (Note 8) ±3 ±10 ±5 ±8 ±10 12 ±0.5 ±4 ±1.0 ±10 Bits LSB LSB mV ppm of FS/°C LSB ppm of FS/°C MIN TYP 25 ±0.01 25 ±0.01 MAX 80 ±1 80 ±1 UNITS µA µA 4 _______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V. TA = +25°C. Outputs are unloaded, unless otherwise noted.) PARAMETER Wake-Up Time (Note 12) 1kΩ Output Termination 100kΩ Output Termination DYNAMIC PERFORMANCE (Notes 5, 13) Output-Voltage Slew Rate Output-Voltage Settling Time Digital Feedthrough Major Code Transition Glitch Impulse Output Noise (0.1Hz to 50MHz) Output Noise (0.1Hz to 500kHz) DAC-to-DAC Transition Crosstalk INTERNAL REFERENCE REF1 Output Voltage REF1 Temperature Coefficient REF1 Short-Circuit Current EXTERNAL-REFERENCE INPUT REF1 Input Voltage Range REF1 Input Impedance VREF1 RREF1 DIGITAL INTERFACE DIGITAL INPUTS (SCLK, DIN, CS, CNVST, LDAC) Input-Voltage High Input-Voltage Low Input Leakage Current Input Capacitance DIGITAL OUTPUT (DOUT) (Note 14) Output-Voltage Low VOL ISINK = 2mA 0.4 V VIH VIL IL CIN DVDD = 2.7V to 5.25V DVDD = 3.6V to 5.25V DVDD = 2.7V to 3.6V ±0.01 15 2.4 0.8 0.6 ±10 V V µA pF REF modes 01, 10, and 11 (Note 4) 0.7 70 100 AVDD 130 V kΩ TCREF VREF = 2.5V 2.482 2.50 ±30 0.39 2.518 V ppm/°C mA SR tS Positive and negative To 1 LSB, 400 - C00 hex (Note 7) Code 0, all digital inputs from 0 to DVDD Between codes 2047 and 2048 From VREF Using internal reference From VREF Using internal reference 3 2 0.5 4 660 720 260 320 0.5 5 V/µs µs nV•s nV•s µVP-P µVP-P nV•s SYMBOL CONDITIONS From power-down mode, AVDD = 5V From power-down mode, AVDD = 2.7V Programmed in power-down mode At wake-up or programmed in power-down mode MIN TYP 25 21 1 100 MAX UNITS µs kΩ kΩ MAX1221/MAX1223/MAX1343 _______________________________________________________________________________________ 5 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V. TA = +25°C. Outputs are unloaded, unless otherwise noted.) PARAMETER Output-Voltage High Tri-State Leakage Current Tri-State Output Capacitance DIGITAL OUTPUT (EOC) (Note 14) Output-Voltage Low Output-Voltage High Tri-State Leakage Current Tri-State Output Capacitance COUT ISINK = 2mA ISINK = 4mA ISOURCE = 2mA ISINK = 15mA ISOURCE = 15mA DVDD 0.8 ±10 COUT DVDD DIDD AVDD Idle, all blocks shut down Analog Positive-Supply Current AIDD Only ADC on, external reference AVDD = 2.7V Output code = FFFhex, AVDD = 2.7V to 5.25V fSAMPLE = 225ksps fSAMPLE = 100ksps Idle, all blocks shut down Only ADC on, external reference 2.70 0.2 2.8 2.6 1.5 -77 ±0.1 ±0.5 4.0 dB mV 2.7 0.2 1 5.25 2 4.2 mA 15 AVDD 4 DVDD 0.5 0.8 15 0.4 0.8 DIGITAL OUTPUTS (GPIO_) (Note 14) GPIOC_ Output-Voltage Low GPIOC_ Output-Voltage High GPIOA_ Output-Voltage Low GPIOA_ Output-Voltage High Tri-State Leakage Current Tri-State Output Capacitance Digital Positive-Supply Voltage Digital Positive-Supply Current Analog Positive-Supply Voltage POWER REQUIREMENTS (Note 15) V µA mA V µA V V V V µA pF VOL VOH ISINK = 2mA ISOURCE = 2mA DVDD 0.5 ±10 0.4 V V µA pF COUT 15 SYMBOL VOH CONDITIONS ISOURCE = 2mA MIN DVDD 0.5 ±10 TYP MAX UNITS V µA pF All DACs on, no load, internal reference REF1 Positive-Supply Rejection DAC Positive-Supply Rejection PSRR PSRD 6 _______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V. TA = +25°C. Outputs are unloaded, unless otherwise noted.) PARAMETER ADC Positive-Supply Rejection SCLK Clock Period SCLK Pulse-Width High SCLK Pulse-Width Low GPIO Output Rise/Fall After CS Rise GPIO Input Setup Before CS Fall LDAC Pulse Width SCLK Fall to DOUT Transition (Note 16) SCLK Rise to DOUT Transition (Notes 16, 17) CS Fall to SCLK Fall Setup Time SCLK Fall to CS Rise Setup Time DIN to SCLK Fall Setup Time DIN to SCLK Fall Hold Time CS Pulse-Width High CS Rise to DOUT Disable CS Fall to DOUT Enable EOC Fall to CS Fall SYMBOL PSRA tCP tCH tCL tGOD tGSU tLDACPWL tDOT tDOT tCSS tCSH tDS tDH tCSPWH tDOD tDOE tRDS CKSEL = 01 (temp sense) or CKSEL = 10 (temp sense), internal reference on CKSEL = 01 (temp sense) or CKSEL = 10 (temp sense), internal reference initially off tDOV CKSEL = 01 (voltage conversion) CKSEL = 10 (voltage conversion), internal reference on CKSEL = 10 (voltage conversion), internal reference initially off CNVST Pulse Width tCSW CKSEL = 00, CKSEL = 01 (temp sense) CKSEL = 01 (voltage conversion) 40 1.4 CLOAD = 20pF CLOAD = 20pF 1.5 30 65 CLOAD = 20pF, SLOW = 0 CLOAD = 20pF, SLOW = 1 CLOAD = 20pF, SLOW = 0 CLOAD = 20pF, SLOW = 1 40/60 duty cycle 60/40 duty cycle CLOAD = 20pF 0 20 1.8 10 1.8 10 10 0 10 0 50 25 25.0 2000 12.0 40 12.0 40 CONDITIONS Full-scale input, AVDD = 2.7V to 5.25V 40 16 16 100 MIN TYP ±0.06 MAX ±0.5 UNITS mV ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MAX1221/MAX1223/MAX1343 TIMING CHARACTERISTICS (Figures 6–13) CS or CNVST Rise to EOC Fall—Internally Clocked Conversion Time 140 9 9 80 ns µs µs _______________________________________________________________________________________ 7 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V. TA = +25°C. Outputs are unloaded, unless otherwise noted.) Note 1: Tested at DVDD = AVDD = +2.7V. Note 2: Offset nulled. Note 3: No bus activity during conversion. Conversion time is defined as the number of conversion clock cycles, multiplied by the clock period. Note 4: See Table 5 for reference-mode details. Note 5: Not production tested. Guaranteed by design. Note 6: See the ADC/DAC References section. Note 7: Fast automated test, excludes self-heating effects. Note 8: Specified over the -40°C to +85°C temperature range. Note 9: REFSEL[1:0] = 00 or when DACs are not powered up. Note 10: DAC linearity, gain, and offset measurements are made between codes 115 and 3981. Note 11: The DAC buffers are guaranteed by design to be stable with a 1nF load. Note 12: Time required by the DAC output to power up and settle within 1 LSB in the external reference mode. Note 13: All DAC dynamic specifications are valid for a load of 100pF and 10kΩ. Note 14: Only one digital output (either DOUT, EOC, or the GPIOs) can be indefinitely shorted to either supply at one time. Note 15: All digital inputs at either DVDD or DGND. DVDD should not exceed AVDD. Note 16: See the Reset Register section and Table 9 for details on programming the SLOW bit. Note 17: Clock mode 11 only. Typical Operating Characteristics (AVDD = DVDD = 3V external VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.) ANALOG SHUTDOWN CURRENT vs. ANALOG SUPPLY VOLTAGE MAX1221 toc01 ANALOG SHUTDOWN CURRENT vs. TEMPERATURE MAX1221 toc02 ADC INTEGRAL NONLINEARITY vs. OUTPUT CODE 0.75 INTEGRAL NONLINEARITY (LSB) 0.50 0.25 0 -0.25 -0.50 -0.75 AVDD = DVDD = 5V EXTERNAL REFERENCE = 4.096V MAX1221 toc03 0.5 ANALOG SHUTDOWN CURRENT (μA) 0.4 ANALOG SHUTDOWN CURRENT (μA) 1.00 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 0 -40 -15 10 35 60 85 TEMPERATURE (°C) -1.00 0 1024 2048 OUTPUT CODE 3072 4096 8 _______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Typical Operating Characteristics (continued) (AVDD = DVDD = 3V external VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.) ADC INTEGRAL NONLINEARITY vs. OUTPUT CODE MAX1221 toc04 MAX1221/MAX1223/MAX1343 ADC DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 AVDD = DVDD = 5V EXTERNAL REFERENCE = 4.096V MAX1221 toc05 ADC DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 MAX1221 toc06 1.00 0.75 INTEGRAL NONLINEARITY (LSB) 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 0 1024 2048 OUTPUT CODE 3072 1.00 DIFFERENTIAL NONLINEARITY (LSB) 1.00 DIFFERENTIAL NONLINEARITY (LSB) 4096 0 1024 2048 OUTPUT CODE 3072 4096 0 1024 2048 OUTPUT CODE 3072 4096 ADC OFFSET ERROR vs. ANALOG SUPPLY VOLTAGE MAX1221 toc07 ADC OFFSET ERROR vs. TEMPERATURE MAX1221 toc08 ADC GAIN ERROR vs. ANALOG SUPPLY VOLTAGE MAX1221 toc09 1.0 2 1.0 0.8 OFFSET ERROR (LSB) OFFSET ERROR (LSB) 1 GAIN ERROR (LSB) -40 -15 10 35 60 85 0.5 0.6 0 0 0.4 -1 0.2 -0.5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) -2 TEMPERATURE (°C) -1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) ADC GAIN ERROR vs. TEMPERATURE ADC EXTERNAL REFERENCE INPUT CURRENT (μA) MAX1221 toc10 ADC EXTERNAL REFERENCE INPUT CURRENT vs. SAMPLING RATE MAX1221 toc11 ANALOG SUPPLY CURRENT vs. SAMPLING RATE MAX1221 toc12 2 60 50 40 30 20 10 0 0 50 100 150 200 250 3.0 ANALOG SUPPLY CURRENT (mA) 2.5 2.0 1.5 1.0 0.5 0 1 GAIN ERROR (LSB) 0 -1 -2 -40 -15 10 35 60 85 TEMPERATURE (°C) 300 0 50 100 150 200 250 300 SAMPLING RATE (ksps) SAMPLING RATE (ksps) _______________________________________________________________________________________ 9 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 Typical Operating Characteristics (continued) (AVDD = DVDD = 3V external VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.) ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE MAX1221 toc13 ANALOG SUPPLY CURRENT vs. TEMPERATURE MAX1221 toc14 DAC INTEGRAL NONLINEARITY vs. OUTPUT CODE AVDD = DVDD = 5V EXTERNAL REFERENCE = 4.096V MAX1221 toc15 2.04 2.02 SUPPLY CURRENT (mA) 2.00 1.98 1.96 1.94 1.92 1.90 2.5 3.0 3.5 4.0 4.5 5.0 2.02 ANALOG SUPPLY CURRENT (mA) 2.00 1.98 1.96 1.94 1.92 1.90 1.88 AVDD = DVDD = 3V AVDD = DVDD = 5V 1.5 INTEGRAL NONLINEARITY (LSB) 1.0 0.5 0 -0.5 -1.0 -1.5 5.5 -40 -15 10 35 60 85 0 1024 2048 OUTPUT CODE 3072 4096 SUPPLY VOLTAGE (V) TEMPERATURE (°C) DAC INTEGRAL NONLINEARITY vs. OUTPUT CODE MAX1221 toc16 DAC DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE AVDD = DVDD = 5V EXTERNAL REFERENCE = 4.096V 0.2 MAX1221 toc17 DAC DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE MAX1221 toc18 1.5 INTEGRAL NONLINEARITY (LSB) 1.0 0.5 0 -0.5 -1.0 -1.5 0 1024 2048 OUTPUT CODE 3072 0.4 DIFFERENTIAL NONLINEARITY (LSB) 0.4 DIFFERENTIAL NONLINEARITY (LSB) 0.2 0 0 -0.2 -0.2 -0.4 4096 2047 2050 2053 2056 2059 2062 OUTPUT CODE -0.4 2047 2050 2053 2056 2059 2062 OUTPUT CODE DAC FULL-SCALE ERROR vs. ANALOG SUPPLY VOLTAGE MAX1221 toc19 DAC FULL-SCALE ERROR vs. TEMPERATURE MAX1221 toc20 DAC FULL-SCALE ERROR vs. TEMPERATURE 8 DAC FULL-SCALE ERROR (LSB) 6 4 2 0 -2 -4 EXTERNAL REFERENCE = 2.5V AVDD = DVDD = 3V -40 -15 10 35 60 85 TEMPERATURE (°C) INTERNAL REFERENCE MAX1221 toc21 1.2 DAC FULL-SCALE ERROR (LSB) 10 8 DAC FULL-SCALE ERROR (LSB) 6 4 2 0 -2 -4 AVDD = DVDD = 5V EXTERNAL REFERENCE = 4.096V 10 1.0 0.8 0.6 0.4 0.2 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) -6 -40 -15 10 35 60 85 TEMPERATURE (°C) -6 10 ______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Typical Operating Characteristics (continued) (AVDD = DVDD = 3V external VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.) DAC FULL-SCALE ERROR vs. REFERENCE VOLTAGE MAX1221 toc22 MAX1221/MAX1223/MAX1343 DAC FULL-SCALE ERROR vs. REFERENCE VOLTAGE MAX1221 toc23 DAC FULL-SCALE ERROR vs. LOAD CURRENT AVDD = DVDD = 5V EXTERNAL REFERENCE = 4.096V DAC FULL-SCALE ERROR (LSB) 0 MAX1221 toc24 1.00 AVDD = DVDD = 5V 0.75 DAC FULL-SCALE ERROR (LSB) 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 0 1 2 3 4 5 REFERENCE VOLTAGE (V) 0 DAC FULL-SCALE ERROR (LSB) -1 -2 -3 -4 -5 -6 -7 0 0.5 1.0 1.5 2.0 2.5 5 -5 -10 -15 3.0 0 5 10 15 20 25 30 REFERENCE VOLTAGE (V) LOAD CURRENT (mA) DAC FULL-SCALE ERROR vs. LOAD CURRENT MAX1221 toc25 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX1221 toc26 ADC REFERENCE SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE ADC REFERENCE SUPPLY CURRENT (μA) MAX1221 toc27 5 DAC FULL-SCALE ERROR (LSB) 2.52 INTERNAL REFERENCE VOLTAGE (V) 25.1 0 2.51 25.0 -5 2.50 24.9 -10 2.49 24.8 -15 0 0.5 1.0 1.5 2.0 2.5 3.0 LOAD CURRENT (mA) 2.48 -40 -15 10 35 60 85 TEMPERATURE (°C) 24.7 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) ADC REFERENCE SUPPLY CURRENT vs. TEMPERATURE MAX1221 toc28 ADC REFERENCE SUPPLY CURRENT vs. TEMPERATURE MAX1221 toc29 ADC FFT PLOT -20 -40 AMPLITUDE (dB) -60 -80 -100 -120 fSAMPLE = 32.768kHz fANALOG_)N = 10.080kHz fCLK = 5.24288MHz SINAD = 71.27dBc SNR = 71.45dBc THD = 85.32dBc SFDR = 87.25dBc MAX1221 toc30 41.0 ADC REFERENCE SUPPLY CURRENT (μA) 25.1 ADC REFERENCE SUPPLY CURRENT (μA) 0 40.9 25.0 40.8 24.9 40.7 40.6 AVDD = DVDD = 5V EXTERNAL REFERENCE = 4.096V 40.5 -40 -15 10 35 60 85 TEMPERATURE (°C) 24.8 AVDD = DVDD = 3V EXTERNAL REFERENCE = 2.5V 24.7 -40 -15 10 35 60 85 TEMPERATURE (°C) -140 -160 0 50 100 150 200 ANALOG INPUT FREQUENCY (kHz) ______________________________________________________________________________________ 11 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 Typical Operating Characteristics (continued) (AVDD = DVDD = 3V external VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.) ADC IMD PLOT MAX1221 toc31 ADC CROSSTALK PLOT MAX1221 toc32 DAC OUTPUT LOAD REGULATION vs. OUTPUT CURRENT 2.07 DAC OUTPUT VOLTAGE (V) 2.06 2.05 2.04 2.03 2.02 2.01 2.00 SINKING SOURCING DAC OUTPUT = MIDSCALE AVDD = DVDD = 5V EXTERNAL REFERENCE = 4.096V MAX1221 toc33 0 -20 -40 AMPLITUDE (dB) -60 -80 -100 -120 -140 -160 0 50 100 AMPLITUDE (dB) fCLK = 5.24288MHz fIN1 = 9.0kHz fIN2 = 11.0kHz AIN = -6dBFS IMD = 82.99dBc 0 -20 -40 -60 -80 -100 -120 -140 -160 fCLK = 5.24288MHz fIN1 = 10.080kHz fIN2 = 8.0801kHz SNR = 72.00dBc THD = 85.24dBc ENOB = 11.65 BITS 2.08 150 200 0 50 100 150 200 -30 0 30 60 90 ANALOG INPUT FREQUENCY (kHz) ANALOG INPUT FREQUENCY (kHz) OUTPUT CURRENT (mA) DAC OUTPUT LOAD REGULATION vs. OUTPUT CURRENT MAX1221 toc34 GPIO OUTPUT VOLTAGE vs. SOURCE CURRENT MAX1221 toc35 1.29 DAC OUTPUT = MIDSCALE 1.28 DAC OUTPUT VOLTAGE (V) 1.27 1.26 1.25 1.24 1.23 1.22 1.21 -30 -20 0 10 -10 OUTPUT CURRENT (mA) 20 SINKING SOURCING 5 GPIO OUTPUT VOLTAGE (V) 4 3 GPIOA0, AGPIOA1 OUTPUTS 2 GPIOC0, GPIOC1 OUTPUTS 1 AVDD = DVDD = 5V EXTERNAL REFERENCE = 4.096V 0 30 0 20 40 60 80 100 SOURCE CURRENT (mA) GPIO OUTPUT VOLTAGE vs. SOURCE CURRENT MAX1221 toc36 GPIO OUTPUT VOLTAGE vs. SINK CURRENT GPIOC0, GPIOC1 OUTPUTS MAX1221 toc37 3.0 2.5 GPIO OUTPUT VOLTAGE (V) 2.0 1.5 1.0 0.5 0 0 20 40 60 80 GPIOC0, GPIOC1 OUTPUTS GPIOA0, GPIOA1 OUTPUTS 1500 GPIO OUTPUT VOLTAGE (mV) 1200 900 600 GPIOA0, GPIOA1 OUTPUTS 300 AVDD = DVDD = 5V EXTERNAL REFERENCE = 4.096V 0 100 0 20 40 60 80 100 SOURCE CURRENT (mA) SINK CURRENT (mA) 12 ______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Typical Operating Characteristics (continued) (AVDD = DVDD = 3V external VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.) GPIO OUTPUT VOLTAGE vs. SINK CURRENT GPIOC0, GPIOC1 OUTPUTS MAX1221 toc38 MAX1221/MAX1223/MAX1343 TEMPERATURE SENSOR ERROR vs. TEMPERATURE 0.75 0.50 0.25 0 MAX1221 toc39 1500 1.00 TEMPERATURE SENSOR ERROR (°C) GPIO OUTPUT VOLTAGE (mV) 1200 900 600 GPIOA0, GPIOA1 OUTPUTS -0.25 -0.50 -0.75 300 0 0 10 20 30 40 50 60 SINK CURRENT (mA) -1.00 -40 -15 10 35 60 85 TEMPERATURE (°C) DAC-TO-DAC CROSSTALK (RLOAD = 10kΩ, CLOAD = 100pF) MAX1221 toc40 DAC-TO-DAC CROSSTALK (RLOAD = 10kΩ, CLOAD = 100pF) MAX1221 toc41 VOUTA 1V/div VOUTA 2V/div VOUTB 10mV/div AC-COUPLED AVDD = DVDD = 5V EXTERNAL REFERENCE = 4.096V 100μs/div 100μs/div VOUTB 10mV/div AC-COUPLED DYNAMIC RESPONSE RISE TIME (RLOAD = 10kΩ, CLOAD = 100pF) MAX1221 toc42 DYNAMIC RESPONSE RISE TIME (RLOAD = 10kΩ, CLOAD = 100pF) MAX1221 toc43 VOUT 1V/div CS 2V/div CS 1V/div AVDD = DVDD = 5V EXTERNAL REFERENCE = 4.096V 1μs/div 1μs/div VOUT 2V/div ______________________________________________________________________________________ 13 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 Typical Operating Characteristics (continued) (AVDD = DVDD = 3V external VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.) DYNAMIC RESPONSE FALL TIME (RLOAD = 10kΩ, CLOAD = 100pF) DYNAMIC RESPONSE FALL TIME (RLOAD = 10kΩ, CLOAD = 100pF) MAX1221 toc44 MAX1221 toc45 VOUT 1V/div CS 2V/div CS 1V/div AVDD = DVDD = 5V EXTERNAL REFERENCE = 4.096V 1μs/div 1μs/div VOUT 2V/div MAJOR CARRY TRANSITION (RLOAD = 10kΩ, CLOAD = 100pF) MAX1221 toc46 MAJOR CARRY TRANSITION (RLOAD = 10kΩ, CLOAD = 100pF) MAX1221 toc47 CS 1V/div CS 2V/div VOUT 10mV/div AC-COUPLED AVDD = DVDD = 5V EXTERNAL REFERENCE = 4.096V 1μs/div 1μs/div VOUT 20mV/div AC-COUPLED DAC DIGITAL FEEDTHROUGH (RLOAD = 10kΩ, CLOAD = 100pF, CS = HIGH, DIN = LOW) MAX1221 toc48 DAC DIGITAL FEEDTHROUGH (RLOAD = 10kΩ, CLOAD = 100pF, CS = HIGH, DIN = LOW) MAX1221 toc49 SCLK 1V/div SCLK 2V/div VOUT 100mV/div AC-COUPLED AVDD = DVDD = 5V EXTERNAL REFERENCE = 4.096V 200ns/div 200ns/div VOUT 100mV/div AC-COUPLED 14 ______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Typical Operating Characteristics (continued) (AVDD = DVDD = 3V external VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.) NEGATIVE FULL-SCALE SETTLING TIME (RLOAD = 10kΩ, CLOAD = 100pF) MAX1340 toc50 MAX1221/MAX1223/MAX1343 NEGATIVE FULL-SCALE SETTLING TIME (RLOAD = 10kΩ, CLOAD = 100pF) MAX1221 toc51 VOUT 1V/div VLDAC 2V/div VOUT_ 2V/div VLDAC 1V/div 1μs/div AVDD = DVDD = 5V EXTERNAL REFERENCE = 4.096V 2μs/div POSITIVE FULL-SCALE SETTLING TIME (RLOAD = 10kΩ, CLOAD = 100pF) MAX1221 toc52 POSITIVE FULL-SCALE SETTLING TIME (RLOAD = 10kΩ, CLOAD = 100pF) MAX1221 toc53 VOUT_ 1V/div VLDAC 2V/div VOUT_ 2V/div VLDAC 1V/div 1μs/div AVDD = DVDD = 5V EXTERNAL REFERENCE = 4.096V 1μs/div ADC REFERENCE FEEDTHROUGH (RLOAD = 10kΩ, CLOAD = 100pF) MAX1221 toc54 ADC REFERENCE FEEDTHROUGH (RLOAD = 10kΩ, CLOAD = 100pF) MAX1221 toc55 VREF2 1V/div VREF2 2V/div VDAC-OUT 10mV/div AC-COUPLED ADC REFERENCE SWITCHING 200μs/div AVDD = DVDD = 5V EXTERNAL REFERENCE = 4.096V ADC REFERENCE SWITCHING 200μs/div VDAC-OUT 2mV/div AC-COUPLED ______________________________________________________________________________________ 15 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 Pin Description PIN MAX1221 1, 2 — 3 4 5 6 MAX1223 — 1 3 4 5 6 MAX1343 1, 2 — 3 4 5 6 NAME GPIOA0, GPIOA1 CNVST/AIN11 EOC DVDD DGND DOUT FUNCTION General-Purpose I/O A0, A1. GPIOA0, A1 can sink and source 15mA. Active-Low Conversion-Start Input/Analog Input 11. See Table 5 for details on programming the setup register. Active-Low End-of-Conversion Output. Data is valid after the falling edge of EOC. Digital Positive-Power Input. Bypass DVDD to DGND with a 0.1µF capacitor. Digital Ground. Connect DGND to AGND. Serial-Data Output. Data is clocked out on the falling edge of the SCLK clock in modes 00, 01, and 10. Data is clocked out on the rising edge of the SCLK clock in mode 11. It is high impedance when CS is high. Serial-Clock Input. Clocks data in and out of the serial interface. (Duty cycle must be 40% to 60%). See Table 5 for details on programming the clock mode. Serial-Data Input. DIN data is latched into the serial interface on the falling edge of SCLK. DAC Outputs DAC Outputs Positive Analog Power Input. Bypass AVDD to AGND with a 0.1µF capacitor. Analog Ground No Connection. Not internally connected. Do Not Connect. Do not connect to this pin. Active-Low Load DAC. LDAC is an asynchronous active-low input that updates the DAC outputs. Drive LDAC low to make the DAC registers transparent. Active-Low Chip-Select Input. When CS is low, the serial interface is enabled. When CS is high, DOUT is high impedance. Reset Select. Select DAC wake-up mode. Set RES_SEL low to wake up the DAC outputs with a 100kΩ resistor to GND or set RES_SEL high to wake up the DAC outputs with a 100kΩ resistor to VREF. The default is the external VREF. 7 7 7 SCLK 8 — 9–12, 16–19 13 14 15, 23, 32, 33 — 20 8 — 9–12, 16–19 13 14 2, 15, 24, 32 — 20 8 9–12 — 13 14 15, 23, 32, 33 16–19 20 DIN OUT0–OUT3 OUT0–OUT7 AVDD AGND N.C. D.C. LDAC 21 21 21 CS 22 22 22 RES_SEL 24, 25 — 24, 25 GPIOC0, GPIOC1 General-Purpose I/O C0, C1. GPIOC0, C1 can sink 4mA and source 2mA. 16 ______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Pin Description (continued) PIN MAX1221 — MAX1223 23, 25, 27–31, 33, 34, 35 MAX1343 — NAME FUNCTION MAX1221/MAX1223/MAX1343 AIN0–AIN9 Analog Inputs 26 26 26 REF1 Reference 1 Input. Reference voltage; leave unconnected to use the internal reference (2.5V). REF1 is the positive reference in ADC differential mode. Bypass REF1 to AGND with a 0.1µF capacitor in external reference mode only. See the ADC/DAC References section. Analog Inputs Reference 2 Input/Analog Input Channel 6. See Table 5 for details on programming the setup register. Active-Low Conversion-Start Input/Analog Input 7. See Table 5 for details on programming the setup register. Reference 2 Input/Analog Input Channel 10. See Table 5 for details on programming the setup register. Exposed Pad. Must be externally connected to AGND. Do not use as a ground connect. 27–31, 34 35 36 — — — — — 36 — 27–31, 34 35 36 — — AIN0–AIN5 REF2/AIN6 CNVST/AIN7 REF2/AIN10 EP ______________________________________________________________________________________ 17 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 Detailed Description The MAX1221/MAX1223/MAX1343 integrate a multichannel 12-bit ADC, and an octal/quad 12-bit DAC in a single IC. The devices also include a temperature sensor and configurable GPIOs with a 25MHz SPI-/QSPI-/ MICROWIRE-compatible serial interface. The ADC is available in a 12 or an eight input-channel version. The DAC outputs settle within 2.0µs, and the ADC has a 225ksps conversion rate. All devices include an internal reference (2.5V) providing a well-regulated, low-noise reference for both the ADC and DAC. Programmable reference modes for the ADC and DAC allow the use of an internal reference, an external reference, or a combination of both. Features such as an internal ±1°C accurate temperature sensor, FIFO, scan modes, programmable internal or external clock modes, data averaging, and AutoShutdown allow users to minimize both power consumption and processor requirements. The low glitch energy (4nV•s) and low digital feedthrough (0.5nV • s) of the integrated DACs make these devices ideal for digital control of fast-response closed-loop systems. The devices are guaranteed to operate with a supply voltage from +2.7V to +5.25V. The devices consume 2.5mA at 225ksps throughput, only 22µA at 1ksps throughput, and under 0.2µA in the shutdown mode. The MAX1221/MAX1343 offer four GPIOs that can be configured as inputs or outputs. Figure 1 shows the MAX1221 functional diagram. The MAX1221/MAX1343 only include the GPIOA0, GPIOA1 and GPIOC0, GPIOC1 blocks. The MAX1223 excludes the GPIOs. The output-conditioning circuitry takes the internal parallel data bus and converts it to a serial data format at DOUT, with the appropriate wake-up timing. The arithmetic logic unit (ALU) performs the averaging function. low to latch any input data at DIN on the falling edge of SCLK. Output data at DOUT is updated on the falling edge of SCLK in clock modes 00, 01, and 10. Output data at DOUT is updated on the rising edge of SCLK in clock mode 11. See Figures 6–11. Bipolar true-differential results and temperature-sensor results are available in two’s complement format, while all other results are in binary. A high-to-low transition on CS initiates the data-input operation. Serial communications to the ADC always begin with an 8-bit command byte (MSB first) loaded from DIN. The command byte and the subsequent data bytes are clocked from DIN into the serial interface on the falling edge of SCLK. The serial-interface and fastinterface circuitry is common to the ADC, DAC, and GPIO sections. The content of the command byte determines whether the SPI port should expect 8, 16, or 24 bits and whether the data is intended for the ADC, DAC, or GPIOs (if applicable). See Table 1. Driving CS high resets the serial interface. The conversion register controls ADC channel selection, ADC scan mode, and temperature-measurement requests. See Table 4 for information on writing to the conversion register. The setup register controls the clock mode, reference, and unipolar/bipolar ADC configuration. Use a second byte, following the first, to write to the unipolar-mode or bipolar-mode registers. See Table 5 for details of the setup register and see Tables 6, 7, and 8 for setting the unipolar- and bipolarmode registers. Hold CS low between the command byte and the second and third byte. The ADC averaging register is specific to the ADC. See Table 9 to address that register. Table 11 shows the details of the reset register. Begin a write to the DAC by writing 0001XXXX as a command byte. The last 4 bits of this command byte are don’t-care bits. Write another 2 bytes (holding CS low) to the DAC interface register following the command byte to select the appropriate DAC and the data to be written to it. See the DAC Serial Interface section and Tables 10, 17, and 18. Write to the GPIOs (if applicable) by issuing a command byte to the appropriate register. Writing to the MAX1221/MAX1343 GPIOs requires 1 additional byte following the command byte. See Tables 12–16 for details on GPIO configuration, writes, and reads. See the GPIO Command section. Command bytes written to the GPIOs on devices without GPIOs are ignored. SPI-Compatible Serial Interface The MAX1221/MAX1223/MAX1343 feature a serial interface that is compatible with SPI and MICROWIRE devices. For SPI, ensure the SPI bus master (typically a microcontroller (µC)) runs in master mode so that it generates the serial clock signal. Select the SCLK frequency of 25MHz or less, and set the clock polarity (CPOL) and phase (CPHA) in the µC control registers to the same value. The MAX1221/MAX1223/MAX1343 operate with SCLK idling high or low, and thus operate with CPOL = CPHA = 0 or CPOL = CPHA = 1. Set CS 18 ______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 GPIOA0, GPIOA1 GPIOC0, GPIOC1 AVDD DVDD MAX1221 USER-PROGRAMMABLE I/O GPIO CONTROL INPUT REGISTER DAC REGISTER 12-BIT DAC BUFFER OUTPUT CONDITIONING OUT0 OSCILLATOR SCLK CS DIN DOUT SPI PORT INPUT REGISTER DAC REGISTER 12-BIT DAC BUFFER OUTPUT CONDITIONING OUT1 INPUT REGISTER DAC REGISTER 12-BIT DAC BUFFER OUTPUT CONDITIONING OUT2 INPUT REGISTER TEMPERATURE SENSOR INPUT REGISTER DAC REGISTER 12-BIT DAC BUFFER OUTPUT CONDITIONING OUT3 DAC REGISTER 12-BIT DAC BUFFER OUTPUT CONDITIONING OUT4 ADDRESS EOC CNVST AIN0 AIN5 REF2/ AIN6 CNVST/ AIN7 T/H LOGIC CONTROL INPUT REGISTER DAC REGISTER 12-BIT DAC BUFFER OUTPUT CONDITIONING OUT5 12-BIT SAR ADC FIFO AND ALU INPUT REGISTER DAC REGISTER 12-BIT DAC BUFFER OUTPUT CONDITIONING OUT6 REF2 INPUT REGISTER DAC REGISTER 12-BIT DAC BUFFER OUTPUT CONDITIONING OUT7 REF1 INTERNAL REFERENCE LDAC AGND DGND RES_SEL Figure 1. MAX1221 Functional Diagram ______________________________________________________________________________________ 19 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 Table 1. Command Byte (MSB First) REGISTER NAME Conversion Setup ADC Averaging DAC Select Reset GPIO Configure* GPIO Write* GPIO Read* No Operation BIT 7 1 0 0 0 0 0 0 0 0 BIT 6 CHSEL3 1 0 0 0 0 0 0 0 BIT 5 CHSEL2 CKSEL1 1 0 0 0 0 0 0 BIT 4 CHSEL1 CKSEL0 AVGON 1 0 0 0 0 0 BIT 3 CHSEL0 REFSEL1 NAVG1 X 1 0 0 0 0 BIT 2 SCAN1 REFSEL0 NAVG0 X RESET 0 0 0 0 BIT 1 SCAN0 DIFFSEL1 NSCAN1 X SLOW 1 1 0 0 BIT 0 TEMP DIFFSEL0 NSCAN0 X FBGON 1 0 1 0 X = Don’t care. *Only applicable on the MAX1221/MAX1343. Power-Up Default State The MAX1221/MAX1223/MAX1343 power up with all blocks in shutdown (including the reference). All registers power up in state 00000000, except for the setup register and the DAC input register. The setup register powers up at 0010 1000 with CKSEL1 = 1 and REFSEL1 = 1. The DAC input register powers up to FFFh when RES_SEL is high and powers up to 000h when RES_SEL is low. 12-Bit ADC The MAX1221/MAX1223/MAX1343 ADCs use a fully differential successive-approximation register (SAR) conversion technique and on-chip track-and-hold (T/H) circuitry to convert temperature and voltage signals into 12-bit digital results. The analog inputs accept both single-ended and differential input signals. Single-ended signals are converted using a unipolar transfer function, and differential signals are converted using a selectable bipolar or unipolar transfer function. See the ADC Transfer Functions section for more data. timed conversions through the serial interface by writing to the conversion register in the default clock mode, 10. Use clock mode 11 with SCLK up to 3.6MHz for externally timed acquisitions to achieve sampling rates up to 225ksps. Clock mode 11 disables scanning and averaging. See Figures 6–9 for timing specifications on how to begin a conversion. These devices feature an active-low, end-of-conversion output. EOC goes low when the ADC completes the last requested operation and is waiting for the next command byte. EOC goes high when CS or CNVST go low. EOC is always high in clock mode 11. ADC Clock Modes When addressing the setup, register bits 5 and 4 of the command byte (CKSEL1 and CKSEL0, respectively) control the ADC clock modes. See Table 5. Choose between four different clock modes for various ways to start a conversion and determine whether the acquisitions are internally or externally timed. Select clock mode 00 to configure CNVST/AIN_ to act as a conversion start and use it to request internally timed conversions, without tying up the serial bus. In clock mode 01, use CNVST to request conversions one channel at a time, thereby controlling the sampling speed without tying up the serial bus. Request and start internally 20 Single-Ended or Differential Conversions The MAX1221/MAX1223/MAX1343 use a fully differential ADC for all conversions. When a pair of inputs are connected as a differential pair, each input is connected to the ADC. When configured in single-ended mode, the positive input is the single-ended channel and the negative input is referred to AGND. See Figure 2. In differential mode, the T/H samples the difference between two analog inputs, eliminating common-mode DC offsets and noise. IN+ and IN- are selected from the following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, AIN6/AIN7, AIN8/AIN9, AIN10/AIN11. AIN0–AIN7 are available on all devices. AIN0–AIN11 are available on the MAX1223. See Tables 5–8 for more details on configuring the inputs. For the inputs that are configurable as CNVST, REF2, and an analog input, only one function can be used at a time. Unipolar or Bipolar Conversions Address the unipolar- and bipolar-mode registers through the setup register (bits 1 and 0). See Table 5 for ______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports the setup register. See Figures 3 and 4 for the transferfunction graphs. Program a pair of analog inputs for differential operation by writing a one to the appropriate bit of the bipolar- or unipolar-mode register. Unipolar mode sets the differential input range from 0 to VREF1. A negative differential analog input in unipolar mode causes the digital output code to be zero. Selecting bipolar mode sets the differential input range to ±VREF1 / 2. The digital output code is binary in unipolar mode and two’s complement in bipolar mode. In single-ended mode, the MAX1221/MAX1223/ MAX1343 always operate in unipolar mode. The analog inputs are internally referenced to AGND with a full-scale input range from 0 to the selected reference voltage. voltages is converted. The input capacitance charging rate determines the time required for the T/H to acquire an input signal. If the input signal’s source impedance is high, the required acquisition time lengthens. Any source impedance below 300Ω does not significantly affect the ADC’s AC performance. A high-impedance source can be accommodated either by lengthening tACQ (only in clock mode 01) or by placing a 1µF capacitor between the positive and negative analog inputs. The combination of the analog-input source impedance and the capacitance at the analog input creates an RC filter that limits the analog input bandwidth. MAX1221/MAX1223/MAX1343 Analog Input (T/H) The equivalent circuit of Figure 2 shows the ADC input architecture of the MAX1223. In track mode, a positive input capacitor is connected to AIN0–AIN11 in singleended mode and AIN0, AIN2, AIN4–AIN10 in differential mode. A negative input capacitor is connected to AGND in single-ended mode or AIN1, AIN3, AIN5–AIN11 in differential mode. The MAX1221/MAX1343 feature eight analog input channels (AIN0–AIN7). In track mode, a positive input capacitor is connected to AIN0–AIN7 in singleended mode and to AIN0, AIN2, AIN4, and AIN6 in differential mode. A negative input capacitor is connected to AGND in single-ended mode or to AIN1, AIN3, AIN5, and AIN7 in differential mode. For external T/H timing, use clock mode 01. After the T/H enters hold mode, the difference between the sampled positive and negative input Input Bandwidth The ADC’s input-tracking circuitry has a 1MHz small-signal bandwidth, making it possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. Anti-alias prefiltering of the input signals is necessary to avoid high-frequency signals aliasing into the frequency band of interest. Analog Input Protection Internal electrostatic-discharge (ESD) protection diodes clamp all analog inputs to AVDD and AGND, allowing the inputs to swing from (AGND - 0.3V) to (AVDD + 0.3V) without damage. However, for accurate conversions near full scale, the inputs must not exceed AVDD by more than 50mV or be lower than AGND by 50mV. If an analog input voltage exceeds the supplies, limit the input current to 2mA. Internal FIFO The MAX1221/MAX1223/MAX1343 contain a firstin/first-out (FIFO) buffer that holds up to 16 ADC results plus one temperature result. The internal FIFO allows the ADC to process and store multiple internally clocked conversions and a temperature measurement without being serviced by the serial bus. AIN0–AIN11 (SINGLE-ENDED), AIN0, AIN2, AIN4–AIN10 (DIFFERENTIAL) REF1 ACQ AGND CIN+ DAC COMPARATOR HOLD CINAGND (SINGLE-ENDED), AIN1, AIN3, AIN5–AIN11 (DIFFERENTIAL) ACQ HOLD ACQ HOLD AVDD / 2 Figure 2. MAX1223 Equivalent Input Circuit If the FIFO is filled and further conversions are requested without reading from the FIFO, the oldest ADC results are overwritten by the new ADC results. Each result contains 2 bytes, with the MSB preceded by four leading zeros. After each falling edge of CS, the oldest available pair of bytes of data is available at DOUT, MSB first. When the FIFO is empty, DOUT is zero. The first 2 bytes of data read out after a temperature measurement always contain the 12-bit temperature result, preceded by four leading zeros, MSB first. If another temperature measurement is performed before the first temperature result is read out, the old measurement is overwritten by the new result. Temperature results are in degrees Celsius (two’s complement), at a resolution of 8 21 ______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 LSB per degree. See the Temperature Measurements section for details on converting the digital code to a temperature. AGND upon power-up to be sure the DAC outputs wake up to a known state. Connect RES_SEL to AGND to wake up all DAC outputs at 000h. While RES_SEL is low, the 100kΩ internal resistor pulls the DAC outputs to AGND and the output buffers are powered down. Connect RES_SEL to AVDD to wake up all DAC outputs at FFFh. While RES_SEL is high, the 100k Ω pullup resistor pulls the DAC outputs to VREF1 and the output buffers are powered down. 12-Bit DAC In addition to the 12-bit ADC, the MAX1221/MAX1223/ MAX1343 also include eight (MAX1221/MAX1223) or four (MAX1343) voltage-output, 12-bit, monotonic DACs with less than 4 LSB integral nonlinearity error and less than 1 LSB differential nonlinearity error. Each DAC has a 2µs settling time and ultra-low glitch energy (4nV•s). The 12-bit DAC code is unipolar binary with 1 LSB = VREF / 4096. DAC Power-Up Modes See Table 18 for a description of the DAC power-up and power-down modes. DAC Digital Interface Figure 1 shows the functional diagram of the MAX1221. The shift register converts a serial 16-bit word to parallel data for each input register operating with a clock rate up to 25MHz. The SPI-compatible digital interface to the shift register consists of CS, SCLK, DIN, and DOUT. Serial data at DIN is loaded on the falling edge of SCLK. Pull CS low to begin a write sequence. Begin a write to the DAC by writing 0001XXXX as a command byte. The last 4 bits of the DAC select register are don’t-care bits. See Table 10. Write another 2 bytes to the DAC interface register following the command byte to select the appropriate DAC and the data to be written to it. See Tables 17 and 18. The double-buffered DACs include an input and a DAC register. The input registers are directly connected to the shift register and hold the result of the most recent write operation. The 12-bit DAC registers hold the current output code for the respective DAC. Data can be transferred from the input registers to the DAC registers by pulling LDAC low or by writing the appropriate DAC command sequence at DIN. See Table 17. The outputs of the DACs are buffered through eight (MAX1221/MAX1223) or four (MAX1343) rail-to-rail op amps. The MAX1221/MAX1223/MAX1343 DAC output-voltage range is based on the internal reference or an external reference. Write to the setup register (see Table 5) to program the reference. If using an external voltage reference, bypass REF1 with a 0.1µF capacitor to AGND. The internal reference is 2.5V. When using an external reference on any of these devices, the voltage range is 0.7V to AVDD. DAC Transfer Function See Table 2 for various analog outputs from the DAC. DAC Power-On Wake-Up Modes The state of the RES_SEL input determines the wake-up state of the DAC outputs. Connect RES_SEL to AVDD or 22 GPIOs In addition to the internal ADC and DAC, the MAX1221/MAX1343 also provide four GPIO channels, GPIOA0, GPIOA1, GPIOC0, GPIOC1. Read and write to the GPIOs as detailed in Table 1 and Tables 12–16. Also, see the GPIO Command section. See Figures 11 and 12 for GPIO timing. Write to the GPIOs by writing a command byte to the GPIO command register. Write a single data byte to the MAX1221/MAX1343 following the command byte. The GPIOs can sink and source current. GPIOA0 and GPIOA1 can sink and source up to 15mA. GPIOC0 and GPIOC1 can sink 4mA and source 2mA. See Table 3. Table 2. DAC Output Code Table DAC CONTENTS MSB 1111 1111 LSB 1111 ANALOG OUTPUT ⎛ 4095 ⎞ + VREF ⎜ ⎟ ⎝ 4096 ⎠ ⎛ 2049 ⎞ + VREF ⎜ ⎟ ⎝ 4096 ⎠ ⎛ 2048 ⎞ ⎛ + VREF ⎞ + VREF ⎜ ⎟=⎜ ⎟ ⎝ 4096 ⎠ ⎝ 2 ⎠ ⎛ 2047 ⎞ + VREF ⎜ ⎟ ⎝ 4096 ⎠ ⎛1⎞ + VREF ⎜ ⎟ ⎝ 4096 ⎠ 0 1000 0000 0001 1000 0000 0000 0111 0111 0111 0000 0000 0000 0000 0001 0000 ______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Clock Modes Internal Clock The MAX1221/MAX1223/MAX1343 can operate from an internal oscillator. The internal oscillator is active in clock modes 00, 01, and 10. Figures 6, 7, and 8 show how to start an ADC conversion in the three internally timed conversion modes. Read out the data at clock speeds up to 25MHz through the SPI interface. External Clock Set CKSEL1 and CKSEL0 in the setup register to 11 to set up the interface for external clock mode 11. See Table 5. Pulse SCLK at speeds from 0.1MHz to 3.6MHz. Write to SCLK with a 40% to 60% duty cycle. The SCLK frequency controls the conversion timing. See Figure 9 for clock mode 11 timing. See the ADC Conversions in Clock Mode 11 section. See Table 4. The MAX1221/MAX1223/MAX1343 perform temperature measurements with an internal diode-connected transistor. The diode bias current changes from 68µA to 4µA to produce a temperature-dependent bias voltage difference. The second conversion result at 4µA is subtracted from the first at 68µA to calculate a digital value that is proportional to absolute temperature. The output data appearing at DOUT is the digital code above, minus an offset to adjust from Kelvin to Celsius. The reference voltage used for the temperature measurements is always derived from the internal reference source to ensure that 1 LSB corresponds to 1/8 of a degree Celsius. On every scan where a temperature measurement is requested, the temperature conversion is carried out first. The first 2 bytes of data read from the FIFO contain the result of the temperature measurement. If another temperature measurement is performed before the first temperature result is read out, the old measurement is overwritten by the new result. Temperature results are in degrees Celsius (two’s complement). See the Applications Information section for information on how to perform temperature measurements in each clock mode. MAX1221/MAX1223/MAX1343 ADC/DAC References Address the reference through the setup register, bits 3 and 2. See Table 5. Following a wake-up delay, set REFSEL[1:0] = 00 to program both the ADC and DAC for internal reference use. Set REFSEL[1:0] = 10 to program the ADC for internal reference use without a wake-up delay. Set REFSEL[1:0] = 10 to program the DAC for external reference, REF1. When using REF1 or REF2/AIN_ in external-reference mode, connect a 0.1µF capacitor to AGND. Set REFSEL[1:0] = 01 to program the ADC and DAC for external-reference mode. The DAC uses REF1 as its external reference, while the ADC uses REF2 as its external reference. Set REFSEL[1:0] = 11 to program the ADC for external differential reference mode. REF1 is the positive reference and REF2 is the negative reference in the ADC external differential mode. When REFSEL[1:0] = 00 or 10, REF2/AIN_ functions as an analog input channel. When REFSEL[1:0] = 01 or 11, REF2/AIN_ functions as the device’s negative reference. Register Descriptions The MAX1221/MAX1223/MAX1343 communicate between the internal registers and the external circuitry through the SPI-compatible serial interface. Table 1 details the command byte, the registers, and the bit names. Tables 4–12 show the various functions within the conversion register, setup register, unipolar-mode register, bipolar-mode register, ADC averaging register, DAC select register, reset register, and GPIO command register, respectively. Temperature Measurements Issue a command byte setting bit 0 of the conversion register to one to take a temperature measurement. Table 3. GPIO Maximum Sink/Source Current MAX1221/MAX1343 CURRENT Sink Source GPIOA0, GPIOA1 (mA) 15 15 GPIOC0, GPIOC1 (mA) 4 2 Conversion Register Select active analog input channels, scan modes, and a single temperature measurement per scan by issuing a command byte to the conversion register. Table 4 details channel selection, the four scan modes, and how to request a temperature measurement. Start a scan by writing to the conversion register when in clock mode 10 or 11, or by applying a low pulse to the CNVST pin when in clock mode 00 or 01. See Figures 6 and 7 for timing specifications for starting a scan with CNVST. A conversion is not performed if it is requested on a channel or one of the channel pairs that has been configured as CNVST or REF2. For channels configured as differential pairs, the CHSEL0 bit is ignored and the two pins are treated as a single differential channel. For the MAX1221/MAX1343, the CHSEL3 bit must be zero. ______________________________________________________________________________________ 23 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 Channels 8–11 are invalid. Any scans or averages on these channles can cause corrupt data. Select scan mode 00 or 01 to return one result per single-ended channel and one result per differential pair within the selected scanning range (set by bits 2 and 1, SCAN1 and SCAN0), plus one temperature result if selected. Select scan mode 10 to scan a single input channel numerous times, depending on NSCAN1 and NSCAN0 in the ADC averaging register (Table 9). Select scan mode 11 to return only one result from a single channel. Table 4. Conversion Register* BIT NAME — CHSEL3 CHSEL2 CHSEL1 CHSEL0 SCAN1 SCAN0 BIT 7 (MSB) 6 5 4 3 2 1 FUNCTION Set to one to select conversion register. Analog input channel select (MAX1223). Set to 0 on the MAX1221/MAX1343. Analog input channel select. Analog input channel select. Analog input channel select. Scan mode select. Scan mode select. Set to one to take a single temperature measurement. The first conversion result of a scan contains temperature information. Setup Register Issue a command byte to the setup register to configure the clock, reference, power-down modes, and ADC single-ended/differential modes. Table 5 details the bits in the setup-register command byte. Bits 5 and 4 (CKSEL1 and CKSEL0) control the clock mode, acquisition and sampling, and the conversion start. Bits 3 and 2 (REFSEL1 and REFSEL0) set the device for either internal or external reference. Bits 1 and 0 (DIFFSEL1 and DIFFSEL0) address the ADC unipolar-mode and bipolar-mode registers and configure the analog input channels for differential operation. The ADC reference is always on if any of the following conditions are true: 1) The FBGON bit is set to one in the reset register. 2) At least one DAC output is powered up and REFSEL[1:0] (in the setup register) = 00. 3) At least one DAC is powered down through the 100kΩ to VREF and REFSEL[1:0] = 00. If any of the above conditions exist, the ADC reference is always on, but there is a 188 clock-cycle delay before temperature-sensor measurements begin, if requested. TEMP 0 (LSB) *See below for bit details. CHSEL3 0 0 0 0 0 0 0 0 1 1 1 1 CHSEL2 0 0 0 0 1 1 1 1 0 0 0 0 CHSEL1 0 0 1 1 0 0 1 1 0 0 1 1 CHSEL0 0 1 0 1 0 1 0 1 0 1 0 1 SELECTED CHANNEL (N) AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 SCAN1 0 0 SCAN0 0 1 SCAN MODE (CHANNEL N IS SELECTED BY BITS CHSEL3–CHSEL0) Scans channels 0 through N. Scans channels N through the highest numbered channel. Scans channel N repeatedly. The ADC averaging register sets the number of results. No scan. Converts channel N once only. 1 1 0 1 24 ______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Table 5. Setup Register* BIT NAME — — CKSEL1 CKSEL0 REFSEL1 REFSEL0 DIFFSEL1 DIFFSEL0 BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) Set to zero to select setup register. Set to one to select setup register. Clock mode and CNVST configuration; resets to one at power-up. Clock mode and CNVST configuration. Reference-mode configuration. Reference-mode configuration. Unipolar-/bipolar-mode register configuration for differential mode. Unipolar-/bipolar-mode register configuration for differential mode. FUNCTION MAX1221/MAX1223/MAX1343 *See below for bit details. Table 5a. Clock Modes (see Clock Modes section) CKSEL1 0 0 1 1 CKSEL0 0 1 0 1 CONVERSION CLOCK Internal Internal Internal External (3.6MHz max) ACQUISITION/SAMPLING Internally timed. Externally timed by CNVST. Internally timed. Externally timed by SCLK. CNVST CONFIGURATION CNVST CNVST AIN11/AIN7 AIN11/AIN7 Table 5b. Clock Modes 00, 01, and 10 REFSEL1 REFSEL0 VOLTAGE REFERENCE OVERRIDE CONDITIONS AIN 0 0 Internal (DAC and ADC) Temperature External singleended (REF1 for DAC and REF2 for ADC) AIN Temperature AUTOSHUTDOWN Internal reference turns off after scan is complete. If internal reference is turned off, there is a programmed delay of 218 internal-conversion clock cycles. AIN10/AIN6 Internal reference required. There is a programmed delay of 244 internal-conversion clock cycles for the internal reference to settle after wake-up. Internal reference not used. Internal reference required. There is a programmed delay of 244 internal-conversion clock cycles for the internal reference to settle after wake-up. Default reference mode. Internal reference turns off after scan is complete. If internal reference is turned off, there is a programmed delay of 218 internalconversion clock cycles. Internal reference required. There is a programmed delay of 244 internal-conversion clock cycles for the internal reference to settle after wake-up. Internal reference not used. Internal reference required. There is a programmed delay of 244 internal-conversion clock cycles for the internal reference to settle after wake-up. REF2 REF2 REF2 CONFIGURATION 0 1 AIN 1 0 Internal (ADC) and external REF1 (DAC) Temperature AIN Temperature AIN10/AIN6 1 1 External differential (ADC), external REF1 (DAC) ______________________________________________________________________________________ 25 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 Table 5c. Clock Mode 11 REFSEL1 REFSEL0 VOLTAGE REFERENCE OVERRIDE CONDITIONS AIN 0 0 Internal (DAC and ADC) Temperature AUTOSHUTDOWN Internal reference turns off after scan is complete. If internal reference is turned off, there is a programmed delay of 218 external-conversion clock cycles. Internal reference required. There is a programmed delay of 244 external-conversion clock cycles for the internal reference. Temperature-sensor output appears at DOUT after 188 further external clock cycles. Internal reference not used. Internal reference required. There is a programmed delay of 244 external-conversion clock cycles for the internal reference. Temperature-sensor output appears at DOUT after 188 further external clock cycles. Default reference mode. Internal reference turns off after scan is complete. If internal reference is turned off, there is a programmed delay of 218 externalconversion clock cycles. AIN10/AIN6 Temperature Internal reference required. There is a programmed delay of 244 external-conversion clock cycles for the internal reference. Temperature-sensor output appears at DOUT after 188 further external clock cycles. Internal reference not used. Internal reference required. There is a programmed delay of 244 external-conversion clock cycles for the internal reference. Temperature-sensor output appears at DOUT after 188 further external clock cycles. REF2 REF2 AIN10/AIN6 REF2 CONFIGURATION AIN 0 1 External singleended (REF1 for DAC and REF2 for ADC) Temperature AIN 1 0 Internal (ADC) and external REF1 (DAC) AIN 1 1 External differential (ADC), external REF1 (DAC) Temperature Table 5d. Differential Select Modes DIFFSEL1 DIFFSEL0 0 0 1 1 0 1 0 1 FUNCTION No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged. No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged. 1 byte of data follows the command setup byte and is written to the unipolar-mode register. 1 byte of data follows the command setup byte and is written to the bipolar-mode register. 26 ______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Table 6. Unipolar-Mode Register (Addressed Through the Setup Register) BIT NAME UCH0/1 UCH2/3 UCH4/5 UCH6/7 UCH8/9 UCH10/11 X X BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) FUNCTION Configure AIN0 and AIN1 for unipolar differential conversion. Configure AIN2 and AIN3 for unipolar differential conversion. Configure AIN4 and AIN5 for unipolar differential conversion. Configure AIN6 and AIN7 for unipolar differential conversion. Configure AIN8 and AIN9 for unipolar differential conversion (MAX1223). Set UCH8/9 to zero on the MAX1221/MAX1343. Configure AIN10 and AIN11 for unipolar differential conversion (MAX1223). Set UCH8/9 to zero on the MAX1221/MAX1343. Don’t care. Don’t care. MAX1221/MAX1223/MAX1343 Table 7. Bipolar-Mode Register (Addressed Through the Setup Register) BIT NAME BCH0/1 BIT 7 (MSB) FUNCTION Set to one to configure AIN0 and AIN1 for bipolar differential conversion. Set the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN0 and AIN1 for unipolar single-ended conversion. Set to one to configure AIN2 and AIN3 for bipolar differential conversion. Set the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN2 and AIN3 for unipolar single-ended conversion. Set to one to configure AIN4 and AIN5 for bipolar differential conversion. Set the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN4 and AIN5 for unipolar single-ended conversion. Set to one to configure AIN6 and AIN7 for bipolar differential conversion. Set the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN6 and AIN7 for unipolar single-ended conversion. Set to one to configure AIN8 and AIN9 for bipolar differential conversion (MAX1223). Set the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN8 and AIN9 for unipolar single-ended conversion. Set BCH8/9 to zero on the MAX1221 and MAX1343. Set to one to configure AIN10 and AIN11 for bipolar differential conversion (MAX1223). Set the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN10 and AIN11 for unipolar single-ended conversion. Set BCH8/9 to zero on the MAX1221 and MAX1343. Don’t care. Don’t care. BCH2/3 6 BCH4/5 5 BCH6/7 4 BCH8/9 3 BCH10/11 X X 2 1 0 (LSB) ______________________________________________________________________________________ 27 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 Unipolar/Bipolar Registers The final 2 bits (LSBs) of the setup register control the unipolar-/bipolar-mode address registers. Set DIFFSEL[1:0] = 10 to write to the unipolar-mode register. Set bits DIFFSEL[1:0] = 11 to write to the bipolarmode register. In both cases, the setup command byte must be followed by 1 byte of data that is written to the unipolar-mode register or bipolar-mode register. Hold CS low and run 16 SCLK cycles before pulling CS high. If the last 2 bits of the setup register are 00 or 01, neither the unipolar-mode register nor the bipolar-mode register is written. Any subsequent byte is recognized as a new command byte. See Tables 6, 7, and 8 to program the unipolar- and bipolar-mode registers. Both registers power up at all zeros to set the inputs as eight unipolar single-ended channels. To configure a channel pair as single-ended unipolar, bipolar differential, or unipolar differential, see Table 8. In unipolar mode, AIN+ can exceed AIN- by up to VREF. The output format in unipolar mode is binary. In bipolar mode, either input can exceed the other by up to VREF / 2. The output format in bipolar mode is two’s complement (see the ADC Transfer Functions section). Table 8. Unipolar/Bipolar Channel Function UNIPOLARMODE REGISTER BIT 0 0 1 1 BIPOLAR-MODE REGISTER BIT 0 1 0 1 CHANNEL PAIR FUNCTION Unipolar single-ended Bipolar differential Unipolar differential Unipolar differential ADC Averaging Register Write a command byte to the ADC averaging register to configure the ADC to average up to 32 samples for each requested result, and to independently control the number of results requested for single-channel scans. Table 9. ADC Averaging Register* BIT NAME — — — AVGON NAVG1 NAVG0 NSCAN1 BIT 7 (MSB) 6 5 4 3 2 1 FUNCTION Set to zero to select ADC averaging register. Set to zero to select ADC averaging register. Set to one to select ADC averaging register. Set to one to turn averaging on. Set to zero to turn averaging off. Configures the number of conversions for single-channel scans. Configures the number of conversions for single-channel scans. Single-channel scan count. (Scan mode 10 only.) Single-channel scan count. (Scan mode 10 only.) NSCAN0 0 (LSB) *See below for bit details. AVGON 0 1 1 1 1 NAVG1 X 0 0 1 1 NAVG0 X 0 1 0 1 FUNCTION Performs one conversion for each requested result. Performs four conversions and returns the average for each requested result. Performs eight conversions and returns the average for each requested result. Performs 16 conversions and returns the average for each requested result. Performs 32 conversions and returns the average for each requested result. NSCAN1 0 0 1 1 NSCAN0 0 1 0 1 FUNCTION (APPLIES ONLY IF SCAN MODE 10 IS SELECTED) Scans channel N and returns four results. Scans channel N and returns eight results. Scans channel N and returns 12 results. Scans channel N and returns 16 results. 28 ______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Table 9 details the four scan modes available in the ADC conversion register. All four scan modes allow averaging as long as the AVGON bit, bit 4 in the averaging register, is set to 1. Select scan mode 10 to scan the same channel multiple times. Clock mode 11 disables averaging. For example, if AVGON = 1, NAVG[1:0] = 00, NSCAN[1:0] = 11 and SCAN[1:0] = 10, 16 results are written to the FIFO, with each result being the average of four conversions of channel N. byte controls the DAC serial interface. See Table 17 and the DAC Serial Interface section. MAX1221/MAX1223/MAX1343 DAC Select Register Write a command byte 0001XXXX to the DAC select register (as shown in Table 9) to set up the DAC interface and indicate that another word will follow. The last 4 bits of the DAC select register are don’t-care bits. The word that follows the DAC select-register command Table 10. DAC Select Register BIT NAME — — — — X X X X BIT FUNCTION Reset Register Write to the reset register (as shown in Table 11) to clear the FIFO or reset all registers (excluding the DAC and GPIO registers) to their default states. When the RESET bit in the reset register is set to 0, the FIFO is cleared. Set the RESET bit to one to return all the device registers to their default power-up state. All registers power up in state 00000000, except for the setup register that powers up in clock mode 10 (CKSEL1 = 1 and REFSEL1 = 1). The DAC and GPIO registers are not reset by writing to the reset register. Set the SLOW bit to one to add a 15ns delay in the DOUT signal path to provide a longer hold time. Writing a one to the SLOW bit also clears the contents of the FIFO. Set the FBGON bit to one to force the bias block and bandgap reference to power up regardless of the state of the DAC and activity of the ADC block. Setting the FBGON bit high also removes the programmed wake-up delay between conversions in clock modes 01 and 11. Setting the FBGON bit high also clears the FIFO. 7 (MSB) Set to zero to select DAC select register. 6 5 4 3 2 1 0 Set to zero to select DAC select register. Set to zero to select DAC select register. Set to one to select DAC select register. Don’t care. Don’t care. Don’t care. Don’t care. Table 12. GPIO Command Register BIT NAME — — — — FUNCTION — — GPIOSEL1 GPIOSEL2 GPIOSEL1 1 BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) GPIOSEL2 1 FUNCTION Set to zero to select GPIO register. Set to zero to select GPIO register. Set to zero to select GPIO register. Set to zero to select GPIO register. Set to zero to select GPIO register. Set to zero to select GPIO register. GPIO configuration bit. GPIO write bit. FUNCTION GPIO configuration; written data is entered in the GPIO configuration register. GPIO write; written data is entered in the GPIO write register. GPIO read; the next 8 SCLK cycles transfer the state of all GPIO drivers into DOUT. Table 11. Reset Register BIT NAME — — — — — RESET SLOW FBGON BIT 7 (MSB) Set to zero to select ADC reset register. 6 5 4 3 2 1 0 (LSB) Set to zero to select ADC reset register. Set to zero to select ADC reset register. Set to zero to select ADC reset register. Set to one to select ADC reset register. Set to zero to clear the FIFO only. Set to one to set the device in its power-on condition. Set to one to turn on slow mode. Set to one to force internal bias block and bandgap reference to be always powered up. 1 0 0 1 ______________________________________________________________________________________ 29 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 GPIO Command Write a command byte to the GPIO command register to configure, write, or read the GPIOs, as detailed in Table 12. Write the command byte 00000011 to configure the GPIOs. The eight SCLK cycles following the command byte load data from DIN to the GPIO configuration register in the MAX1221/MAX1343. See Tables 13 and 14. The register bits are updated after the last CS rising edge. All GPIOs default to inputs upon power-up. The data in the register controls the function of each GPIO, as shown in Tables 13, 14, and 16. GPIO Write Write the command byte 00000010 to indicate a GPIO write operation. The eight SCLK cycles following the command byte load data from DIN into the GPIO write register in the MAX1221/MAX1343. See Tables 14 and 15. The register bits are updated after the last CS rising edge. GPIO Read Write the command byte 00000001 to indicate a GPIO read operation. The eight SCLK cycles following the command byte transfer the state of the GPIOs to DOUT in the MAX1221/MAX1343. See Table 16. DAC Serial Interface Write a command byte 0001XXXX to the DAC select register to indicate the word to follow is written to the DAC serial interface, as detailed in Tables 1, 10, 17, and 18. Write the next 16 bits to the DAC interface register, as shown in Tables 17 and 18. Following the high-to-low transition of CS, the data is shifted synchronously and latched into the input register on each falling edge of SCLK. Each word is 16 bits. The first 4 bits are the control bits followed by 12 data bits (MSB first). See Figures 9–12 for DAC timing specifications. If CS goes high prior to completing 16 SCLK cycles, the command is discarded. To initiate a new transfer, drive CS low again. For example, writing the DAC serial interface word 1111 0000 and 0011 0100 disconnects DAC outputs 2 and 3 Table 13. MAX1221/MAX1343 GPIO Configuration DATA PIN DIN DOUT 0 0 GPIO COMMAND BYTE 0 0 0 0 0 0 0 0 0 0 1 0 1 0 GPIOC1 0 GPIOC0 0 DATA BYTE GPIOA1 0 GPIOA0 0 X 0 X 0 X 0 X 0 Table 14. MAX1221/MAX1343 GPIO Write DATA PIN DIN DOUT 0 0 0 0 GPIO COMMAND BYTE 0 0 0 0 0 0 0 0 1 0 0 0 GPIOC1 0 GPIOC0 0 DATA BYTE GPIOA1 0 GPIOA0 0 X 0 X 0 X 0 X 0 Table 15. GPIO-Mode Control CONFIGURATION BIT 1 1 0 0 WRITE BIT 1 0 1 0 OUTPUT STATE 1 0 Tri-state 0 GPIO FUNCTION Output Output Input Pulldown (open drain) Table 16. MAX1221/MAX1343 GPIO Read DATA PIN DIN DOUT 0 0 GPIO COMMAND BYTE 0 0 0 0 0 0 0 0 0 0 0 0 1 0 X 0 X 0 X 0 X 0 X GPIOC1 DATA BYTE X GPIOC0 X GPIOA1 X GPIOA0 30 ______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Table 17. DAC Serial-Interface Configuration 16-BIT SERIAL WORD MSB CONTROL BITS C3 C2 C1 C0 D11 D10 D9 0 0 0 0 0 0 0 1 X 0 X X X X D8 X X D7 X X DATA BITS D6 X X D5 X X D4 X X D3 X X D2 X X D1 X X D0 X X NOP RESET No operation. Reset all internal registers to 000h and leave output buffers in their present state. Preset all internal registers to FFFh and leave output buffers in their present state. D11–D0 to input register 0, DAC output unchanged. D11–D0 to input register 1, DAC output unchanged. D11–D0 to input register 2, DAC output unchanged. D11–D0 to input register 3, DAC output unchanged. D11–D0 to input register 4, DAC output unchanged (MAX1221/MAX1223). NOP command (MAX1343). D11–D0 to input register 5, DAC output unchanged (MAX1221/MAX1223). NOP command (MAX1343). D11–D0 to input register 6, DAC output unchanged (MAX1221/MAX1223). NOP command (MAX1343). D11–D0 to input register 7, DAC output unchanged (MAX1221/MAX1223). NOP command (MAX1343). D11–D0 to input registers 0–3 and DAC register 0–3. DAC outputs updated (write-through). D11–D0 to input registers 4–7 and DAC register 4–7. DAC outputs updated (write-through) (MAX1221/MAX1223). NOP command (MAX1343). D11–D0 to input registers 0–7 and DAC register 0–7 (MAX1221/MAX1223). D11–D0 to input registers 0–3 and DAC registers 0–3 (MAX1343). DAC outputs updated (write-through). LSB DESCRIPTION FUNCTION MAX1221/MAX1223/MAX1343 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 1 — — — — X — — — — X — — — — X — — — — X — — — — X — — — — X — — — — X — — — — X — — — — X — — — — X — — — — X — — — — Pull-High DAC0 DAC1 DAC2 DAC3 0 1 1 0 — — — — — — — — — — — — DAC4 0 1 1 1 — — — — — — — — — — — — DAC5 1 0 0 0 — — — — — — — — — — — — DAC6 1 0 0 1 — — — — — — — — — — — — DAC7 1 0 1 0 — — — — — — — — — — — — DAC0–3 1 0 1 1 — — — — — — — — — — — — DAC4–7 1 1 0 0 — — — — — — — — — — — — DAC0–7 ______________________________________________________________________________________ 31 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 Table 17. DAC Serial-Interface Configuration (continued) 16-BIT SERIAL WORD MSB CONTROL BITS C3 C2 C1 C0 D11 D10 D9 D8 D7 DATA BITS D6 D5 D4 D3 D2 D1 D0 D11–D0 to input registers 0–7 (MAX1221/MAX1223). D11–D0 to input registers 0–3 (MAX1343). DAC outputs unchanged. Input registers to DAC registers indicated by ones, DAC outputs updated, equivalent to software LDAC. (No effect on DACs indicated by zeros.) DAC7–DAC4 are only valid on the MAX1221/ MAX1223. These are don’t-care bits for the MAX1343. LSB DESCRIPTION FUNCTION 1 1 0 1 — — — — — — — — — — — — DAC0–7 1 1 1 0 DAC DAC DAC DAC DAC DAC DAC DAC X 7 6 5 4 3 2 1 0 X X X DAC0–7 Table 18. DAC Power-Up and Power-Down Commands CONTROL BITS DAC7 DAC6 DAC5 DAC4 C3 C2 C1 C0 DATA BITS DAC3 DAC2 DAC1 DAC0 DESCRIPTION D3 D2 D1 D0 Power up individual DAC buffers indicated by data in DAC0 through DAC3. A one indicates the DAC output is connected and active. A zero does not affect the DAC’s present state. FUNCTION 1 1 1 1 ————————0 0 1 X Power-Up 1 1 1 1 ————————0 1 0 X Power down individual DAC buffers indicated by data in DAC0 through DAC3. A one indicates the Power-Down 1 DAC output is disconnected and high impedance. A zero does not affect the DAC’s present state. Power down individual DAC buffers indicated by data in DAC0 through DAC3. A one indicates the Power-Down 2 DAC output is disconnected and pulled to AGND with a 1kΩ resistor. A zero does not affect the DAC’s present state. Power down individual DAC buffers indicated by data in DAC0 through DAC3. A one indicates the Power-Down 3 DAC output is disconnected and pulled to AGND with a 100kΩ resistor. A zero does not affect the DAC’s present state. Power down individual DAC buffers indicated by data in DAC0 through DAC3. A one indicates the Power-Down 4 DAC output is disconnected and pulled to REF1 with a 100kΩ resistor. A zero does not affect the DAC’s present state. 1 1 1 1 ————————1 0 0 X 1 1 1 1 ————————0 0 0 X 1 1 1 1 ————————1 1 1 X 32 ______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports and forces them to a high-impedance state. DAC outputs 0 and 1 remain in their previous state. Output-Data Format Figures 6–9 illustrate the conversion timing for the MAX1221/MAX1223/MAX1343. All 12-bit conversion results are output in 2-byte format, MSB first, with four leading zeros. Data appears on DOUT on the falling edges of SCLK. Data is binary for unipolar mode and two’s complement for bipolar mode and temperature results. See Figures 3, 4, and 5 for input/output and temperature-transfer functions. second byte is read out partially, the rest of that byte is lost. The remaining data in the FIFO is unaffected and can be read out normally after taking CS low again, as long as the 4 leading bits (normally zeros) are ignored. If CS is pulled low before EOC goes low, a conversion may not be completed and the FIFO data may not be correct. Incorrect writes (pulling CS high before completing eight SCLK cycles) are ignored and the register remains unchanged. MAX1221/MAX1223/MAX1343 ADC Transfer Functions Figure 3 shows the unipolar transfer function for singleended or differential inputs. Figure 4 shows the bipolar transfer function for differential inputs. Code transitions occur halfway between successive-integer LSB values. Output coding is binary, with 1 LSB = VREF1 / 4096 for unipolar and bipolar operation, and 1 LSB = +0.125°C for temperature measurements. Bipolar true-differential results and temperature-sensor results are available in two’s complement format, while all others are in binary. See Tables 6, 7, and 8 for details on which setting (unipolar or bipolar) takes precedence. In unipolar mode, AIN+ can exceed AIN- by up to VREF1. In bipolar mode, either input can exceed the other by up to VREF1 / 2. VREF 011....111 OFFSET BINARY OUTPUT CODE (LSB) 011....110 011....101 FS = VREF / 2 + VCOM ZS = COM -FS = -VREF / 2 1 LSB = VREF / 4096 000....001 000....000 111....111 100....011 100....010 100....001 100....000 -FS VREF = VREF+ - VREFVREF VREF (COM) VREF Partial Reads and Partial Writes If the first byte of an entry in the FIFO is partially read (CS is pulled high after fewer than eight SCLK cycles), the remaining bits are lost for that byte. The next byte of data that is read out contains the next 8 bits. If the first byte of an entry in the FIFO is read out fully, but the -1 0 +1 (COM) INPUT VOLTAGE (LSB) +FS - 1 LSB Figure 4. Bipolar Transfer Function—Full Scale (±FS) = ±VREF / 2 OUTPUT CODE 111....111 OFFSET BINARY OUTPUT CODE (LSB) 111....110 111....101 FS = VREF 1 LSB = VREF / 4096 000....010 000....001 000....000 111....111 000....011 000....010 000....001 000....000 0123 INPUT VOLTAGE (LSB) FS - 3/2 LSB -256 0 TEMPERATURE (°C) +255.5 FS 100....001 100....000 111....110 111....101 FULL-SCALE TRANSITION 011....111 011....110 Figure 3. Unipolar Transfer Function—Full Scale (FS) = VREF Figure 5. Temperature Transfer Function 33 ______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 CNVST (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT MSB1 tRDS EOC LSB1 MSB2 Figure 6. Clock Mode 00—After writing a command byte, set CNVST low for at least 40ns to begin a conversion. tCSW CNVST (CONVERSION 2) (ACQUISITION 1) CS tDOV SCLK (CONVERSION 1) (ACQUISITION 2) DOUT MSB1 EOC LSB1 MSB2 Figure 7. Clock Mode 01—After writing a command byte, request multiple conversions by setting CNVST low for each conversion. Applications Information Internally Timed Acquisitions and Conversions Using CNVST ADC Conversions in Clock Mode 00 In clock mode 00, the wake-up, acquisition, conversion, and shutdown sequence is initiated through CNVST and performed automatically using the internal oscillator. Results are added to the internal FIFO to be read out later. See Figure 6 for clock mode 00 timing after a command byte is issued. See Table 5 for details on programming the clock mode in the setup register. Initiate a scan by setting CNVST low for at least 40ns before pulling it high again. The MAX1221/MAX1223/ MAX1343 then wake up, scan all requested channels, 34 store the results in the FIFO, and shut down. After the scan is complete, EOC is pulled low and the results are available in the FIFO. Wait until EOC goes low before pulling CS low to communicate with the serial interface. EOC stays low until CS or CNVST is pulled low again. A temperature-conversion result, if requested, precedes all other FIFO results. Do not issue a second CNVST signal before EOC goes low; otherwise, the FIFO can be corrupted. Wait until all conversions are complete before reading the FIFO. SPI communications to the DAC and GPIO registers are permitted during conversion. However, coupled noise may result in degraded ADC signal-to-noise ratio (SNR). ______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 DIN (CONVERSION BYTE) (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT tDOV EOC MSB1 LSB1 MSB2 Figure 8. Clock Mode 10—The command byte to the conversion register begins the acquisition (CNVST is not required). Externally Timed Acquisitions and Internally Timed Conversions with CNVST ADC Conversions in Clock Mode 01 In clock mode 01, conversions are requested one at a time using CNVST and performed automatically using the internal oscillator. See Figure 7 for clock mode 01 timing after a command byte is issued. Setting CNVST low begins an acquisition, wakes up the ADC, and places it in track mode. Hold CNVST low for at least 1.4µs to complete the acquisition. If reference mode 00 or 10 is selected, an additional 45µs is required for the internal reference to power up. If a temperature measurement is being requested, reference power-up and temperature measurement is internally timed. In this case, hold CNVST low for at least 40ns. Set CNVST high to begin a conversion. Sampling is completed approximately 500ns after CNVST goes high. After the conversion is complete, the ADC shuts down and pulls EOC low. EOC stays low until CS or CNVST is pulled low again. Wait until EOC goes low before pulling CS or CNVST low. The number of CNVST signals must equal the number of conversions requested by the scan and averaging registers to correctly update the FIFO. Wait until all conversions are complete before reading the FIFO. SPI communications to the DAC and GPIO registers are permitted during conversion. However, coupled noise may result in degraded ADC SNR. If averaging is turned on, multiple CNVST pulses need to be performed before a result is written to the FIFO. Once the proper number of conversions has been performed to generate an averaged FIFO result (as specified to the averaging register), the scan logic automatically switches the analog input multiplexer to the next requested channel. If a temperature measurement is programmed, it is performed after the first rising edge of CNVST following the command byte written to the conversion register. The temperature-conversion result is available on DOUT once EOC has been pulled low. ______________________________________________________________________________________ 35 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 DIN (CONVERSION BYTE) (ACQUISITION1) CS SCLK (CONVERSION1) (ACQUISITION2) DOUT MSB1 EOC LSB1 MSB2 Figure 9. Clock Mode 11—Externally Timed Acquisition, Sampling, and Conversion without CNVST Internally Timed Acquisitions and Conversions Using the Serial Interface ADC Conversions in Clock Mode 10 In clock mode 10, the wake-up, acquisition, conversion, and shutdown sequence is initiated by writing a command byte to the conversion register, and is performed automatically using the internal oscillator. This is the default clock mode upon power-up. See Figure 8 for clock mode 10 timing. Initiate a scan by writing a command byte to the conversion register. The MAX1221/MAX1223/MAX1343 then power up, scan all requested channels, store the results in the FIFO, and shut down. After the scan is complete, EOC is pulled low and the results are available in the FIFO. If a temperature measurement is requested, the temperature result precedes all other FIFO results. EOC stays low until CS is pulled low again. Wait until all conversions are complete before reading the FIFO. SPI communications to the DAC and GPIO registers are permitted during conversion. However, coupled noise may result in degraded ADC SNR. Initiate a conversion by writing a command byte to the conversion register followed by 16 SCLK cycles. If CS is pulsed high between the eighth and ninth cycles, the pulse width must be less than 100µs. To continuously convert at 16 cycles per conversion, alternate 1 byte of zeros (NOP byte) between each conversion byte. If 2 NOP bytes follow a conversion byte, the analog cells power down at the end of the second NOP. Set the FBGON bit to one in the reset register to keep the internal bias block powered. If reference mode 00 is requested, or if an external reference is selected but a temperature measurement is being requested, wait 45µs with CS high after writing the conversion byte to extend the acquisition and allow the internal reference to power up. To perform a temperature measurement, write 24 bytes (192 cycles) of zeros after the conversion byte. The temperature result appears on DOUT during the last 2 bytes of the 192 cycles. Externally Clocked Acquisitions and Conversions Using the Serial Interface ADC Conversions in Clock Mode 11 In clock mode 11, acquisitions and conversions are initiated by writing a command byte to the conversion register and are performed one at a time using the SCLK as the conversion clock. Scanning, averaging and the FIFO are disabled, and the conversion result is available at DOUT during the conversion. Output data is updated on the rising edge of SCLK in clock mode 11. See Figure 9 for clock mode 11 timing. Conversion-Time Calculations The conversion time for each scan is based on a number of different factors: conversion time per sample, samples per result, results per scan, if a temperature measurement is requested, and if the external reference is in use. Use the following formula to calculate the total conversion time for an internally timed conversion in clock mode 00 and 10 (see the E lectrical Characteristics, as applicable): Total conversion time = tCNV x nAVG x nSCAN + tTS + tINT-REF,SU where: tCNV = tDOV (where tDOV is dependent from the clock and reference mode selected.) 36 ______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 tCH tCL SCLK 1 tDH 2 3 4 5 32 16 8 tDS DIN D15 D14 D13 tDOT D12 D11 D1 D0 tDOE D15 D7 tCSS tCSPWH D14 D6 tDOD DOUT D13 D5 D12 D4 D1 D0 tCSH CS Figure 10. DAC/GPIO Serial-Interface Timing (Clock Modes 00, 01, and 10) nAVG = samples per result (amount of averaging) nSCAN = number of times each channel is scanned; set to one unless [SCAN1, SCAN0] = 10 t TS = t ime required for temperature measurement (58.1µs); set to zero if temperature measurement is not requested tINT-REF,SU = tWU (external-reference wake-up); if a conversion using the external reference is requested In clock mode 01, the total conversion time depends on how long CNVST is held low or high. Conversion time in externally clocked mode (CKSEL1, CKSEL0 = 11) depends on the SCLK period and how long CS is held high between each set of eight SCLK cycles. In clock mode 01, the total conversion time does not include the time required to turn on the internal reference. fications for clock modes 00, 01, and 10. Figure 11 shows the timing specifications for clock mode 11. Figure 12 details the timing specifications for the DAC input select register and 2 bytes to follow. Output data is updated on the rising edge of SCLK in clock mode 11. Figure 13 shows the GPIO timing. Figure 14 shows the timing details of a hardware LDAC command DACregister update. For a software-command DAC-register update, tS is valid from the rising edge of CS, which follows the last data bit in the software command word. LDAC Functionality Drive LDAC low to transfer the content of the input registers to the DAC registers. Drive LDAC permanently low to make the DAC register transparent. The DAC output typically settles from zero to full scale within ±1 LSB after 2µs. See Figure 14. DAC/GPIO Timing Figures 10–13 detail the timing diagrams for writing to the DAC and GPIOs. Figure 10 shows the timing speci- ______________________________________________________________________________________ 37 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 tCH tCL SCLK 1 2 3 4 5 32 16 8 tDH tDS DIN D15 D14 D13 D12 D11 D1 D0 tDOE tDOT tDOD DOUT tCSS tCSPWH D15 D7 D14 D6 D13 D5 D12 D4 D1 D0 tCSH CS Figure 11. DAC/GPIO Serial-Interface Timing (Clock Mode 11) SCLK 1 2 8 9 10 24 DIN BIT 7 (MSB) BIT 6 BIT 0 (LSB) BIT 15 BIT 14 BIT 1 BIT 0 DOUT THE COMMAND BYTE INITIALIZES THE DAC SELECT REGISTER CS THE NEXT 16 BITS SELECT THE DAC AND THE DATA WRITTEN TO IT Figure 12. DAC-Select Register Byte and DAC Serial-Interface Word 38 ______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 CS tGOD GPIO INPUT/OUTPUT tGSU Figure 13. GPIO Timing tLDACPWL LDAC tS ±1 LSB OUT_ Figure 14. LDAC Functionality Layout, Grounding, and Bypassing For best performance, use PC boards. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital signals parallel to one another (especially clock signals) or do not run digital lines underneath the MAX1221/MAX1223/MAX1343 package. High-frequency noise in the AVDD power supply may affect performance. Bypass the AVDD supply with a 0.1µF capacitor to AGND, close to the AVDD pin. Bypass the DV DD supply with a 0.1µF capacitor to DGND, close to the DVDD pin. Minimize capacitor lead lengths for best supply-noise rejection. If the power supply is very noisy, connect a 10Ω resistor in series with the supply to improve power-supply filtering. The MAX1221/MAX1223/MAX1343 thin QFN packages contain an exposed pad on the underside of the device. Connect this exposed pad to AGND. Refer to the MAX1258EVKIT for an example of proper layout. Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. INL for the MAX1221/MAX1223/MAX1343 is measured using the end-point method. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. Unipolar ADC Offset Error For an ideal converter, the first transition occurs at 0.5 LSB, above zero. Offset error is the amount of deviation between the measured first transition point and the ideal first transition point. ______________________________________________________________________________________ 39 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 Bipolar ADC Offset Error While in bipolar mode, the ADC’s ideal midscale transition occurs at AGND -0.5 LSB. Bipolar offset error is the measured deviation from this ideal value. Effective Number of Bits Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the ENOB as follows: ENOB = (SINAD - 1.76)/6.02 ADC Gain Error Gain error is defined as the amount of deviation between the ideal transfer function and the measured transfer function, with the offset error removed and with a full-scale analog input voltage applied to the ADC, resulting in all ones at DOUT. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: THD = 20 x log⎡ ⎢ ⎣ DAC Offset Error DAC offset error is determined by loading a code of all zeros into the DAC and measuring the analog output voltage. (V22 + V32 + V42 + V52 + V62) / V1⎤ ⎥ ⎦ DAC Gain Error DAC gain error is defined as the amount of deviation between the ideal transfer function and the measured transfer function, with the offset error removed, when loading a code of all ones into the DAC. where V1 is the fundamental amplitude, and V2 through V6 are the amplitudes of the first five harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest distortion component. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. Aperture Delay Aperture delay (t AD ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. ADC Channel-to-Channel Crosstalk Bias the ON channel to midscale. Apply a full-scale sine wave test tone to all OFF channels. Perform an FFT on the ON channel. ADC channel-to-channel crosstalk is expressed in dB as the amplitude of the FFT spur at the frequency associated with the OFF channel test tone. Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analogto-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR = (6.02 x N + 1.76)dB In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is calculated by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset. Intermodulation Distortion (IMD) IMD is the total power of the intermodulation products relative to the total input power when two tones, f1 and f2, are present at the inputs. The intermodulation products are (f1 ± f2), (2 x f1), (2 x f2), (2 x f1 ± f2), (2 x f2 ± f1). The individual input tone levels are at -7dBFS. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC so the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. Note that the T/H performance is usually the limiting factor for the smallsignal input bandwidth. Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to the RMS equivalent of all other ADC output signals: SINAD(dB) = 20 x log (SignalRMS/NoiseRMS) Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency. 40 ______________________________________________________________________________________ 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports DAC Digital Feedthrough DAC digital feedthrough is the amount of noise that appears on the DAC output when the DAC digital control lines are toggled. Chip Information TRANSISTOR COUNT: 58,141 PROCESS: BiCMOS MAX1221/MAX1223/MAX1343 ADC Power-Supply Rejection ADC power-supply rejection (PSR) is defined as the shift in offset error when the power supply is moved from the minimum operating voltage to the maximum operating voltage. DAC Power-Supply Rejection DAC PSR is the amount of change in the converter’s value at full-scale as the power-supply voltage changes from its nominal value. PSR assumes the converter’s linearity is unaffected by changes in the power-supply voltage. ______________________________________________________________________________________ 41 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 Pin Configurations CNVST/AIN7 REF2/AIN10 REF2/AIN6 AIN5 TOP VIEW N.C. N.C. AIN4 AIN3 AIN2 AIN1 AIN9 AIN8 35 34 36 35 34 33 32 31 30 29 28 36 33 32 31 30 29 GPIOA0 GPIOA1 EOC DVDD DGND DOUT SCLK DIN OUT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 27 26 25 24 23 22 21 20 19 AIN0 REF1 GPIOC1 GPIOC0 N.C. RES_SEL CS LDAC OUT7 28 AIN7 N.C. AIN6 AIN5 AIN4 AIN3 CNVST/AIN11 N.C. EOC DVDD DGND DOUT SCLK DIN OUT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 27 26 25 24 23 22 21 20 19 AIN2 REF1 AIN1 N.C. AIN0 RES_SEL CS LDAC OUT7 MAX1221 MAX1223 OUT1 OUT2 OUT3 AVDD AGND N.C. OUT4 OUT5 OUT6 OUT1 OUT2 OUT3 AVDD AGND N.C. OUT4 OUT5 THIN QFN THIN QFN CNVST/AIN7 TOP VIEW REF2/AIN6 AIN5 AIN4 AIN3 AIN2 36 35 34 33 32 31 30 29 28 GPIOA0 1 GPIOA1 2 EOC 3 DVDD 4 DGND 5 DOUT 6 SCLK 7 DIN 8 OUT0 9 10 11 12 13 14 15 16 17 18 OUT1 OUT2 OUT3 N.C. D.C. D.C. AGND AVDD D.C. 27 AIN0 26 REF1 25 GPIOC1 24 GPIOC0 AIN1 N.C. N.C. MAX1343 23 N.C. 22 RES_SEL 21 CS 20 LDAC 19 D.C. THIN QFN (6mm x 6mm x 0.8mm) 42 ______________________________________________________________________________________ OUT6 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QFN THIN.EPS MAX1221/MAX1223/MAX1343 ______________________________________________________________________________________ 43 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 Revision History REVISION NUMBER 1 REVISION DATE 12/07 DESCRIPTION Changed timing characteristic specification PAGES CHANGED 7 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 44 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.