MAX12553

19-3447; Rev 0; 10/04 KIT ATION EVALU ABLE AVAIL 14-Bit, 95Msps, 3.3V ADC General Description Features ♦ Direct IF Sampling Up to 400MHz ♦ Excellent Dynamic Performance 74.2dB/72.1dB SNR at fIN = 3MHz/175MHz 88.4dBc/74.7dBc SFDR at fIN = 3MHz/175MHz ♦ Low Noise Floor: 74.7dBFS ♦ 3.3V Low-Power Operation 465mW (Single-Ended Clock Mode) 497mW (Differential Clock Mode) 300µW (Power-Down Mode) ♦ Fully Differential or Single-Ended Analog Input ♦ Adjustable Full-Scale Analog Input Range ±0.35V to ±1.10V ♦ Common-Mode Reference ♦ CMOS-Compatible Outputs in Two’s Complement or Gray Code ♦ Data-Valid Indicator Simplifies Digital Interface ♦ Data Out-of-Range Indicator ♦ Miniature, 6mm x 6mm x 0.8mm 40-Pin Thin QFN Package with Exposed Paddle ♦ Evaluation Kit Available (Order MAX12555EVKIT) MAX12555 The MAX12555 is a 3.3V, 14-bit, 95Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input stage accepts singleended or differential signals. The MAX12555 is optimized for high dynamic performance, low power, and small size. Excellent dynamic performance is maintained from baseband to input frequencies of 175MHz and beyond, making the MAX12555 ideal for intermediatefrequency (IF) sampling applications. Powered from a single 3.3V supply, the MAX12555 consumes only 497mW while delivering a typical 72.1dB signal-to-noise ratio (SNR) performance at a 175MHz input frequency. In addition to low operating power, the MAX12555 features a 300µW power-down mode to conserve power during idle periods. A flexible reference structure allows the MAX12555 to use the internal 2.048V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.10V. The MAX12555 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The MAX12555 supports either a single-ended or differential input clock. Wide variations in the clock duty cycle are compensated with the ADC’s internal dutycycle equalizer (DCE). ADC conversion results are available through a 14-bit, parallel, CMOS-compatible output bus. The digital output format is pin selectable to be either two’s complement or Gray code. A data-valid indicator eliminates external components that are normally required for reliable digital interfacing. A separate digital power input accepts a wide 1.7V to 3.6V supply, allowing the MAX12555 to interface with various logic levels. The MAX12555 is available in a 6mm x 6mm x 0.8mm, 40-pin thin QFN package with exposed paddle (EP), and is specified for the extended industrial (-40°C to +85°C) temperature range. See the Pin-Compatible Versions table for a complete family of 14-bit and 12-bit high-speed ADCs. Ordering Information PART* MAX12555ETL MAX12555ETL+ PIN-PACKAGE 40 Thin QFN 40 Thin QFN PKG CODE T4066-3 T4066-3 +Denotes lead-free package. *All devices specified over the -40°C to +85°C operating range. Pin-Compatible Versions PART MAX12555 MAX12554 MAX12553 MAX19538 MAX1209 MAX1211 MAX1208 MAX1207 MAX1206 SAMPLING RATE (Msps) 95 80 65 95 80 65 80 65 40 RESOLUTION (BITS) 14 14 14 12 12 12 12 12 12 TARGET APPLICATION IF/Baseband IF/Baseband IF/Baseband IF/Baseband IF IF Baseband Baseband Baseband Applications IF and Baseband Communication Receivers Cellular, Point-to-Point Microwave, HFC, WLAN Medical Imaging Including Positron Emission Tomography (PET) Video Imaging Portable Instrumentation Low-Power Data Acquisition Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 14-Bit, 95Msps, 3.3V ADC MAX12555 ABSOLUTE MAXIMUM RATINGS VDD to GND ...........................................................-0.3V to +3.6V OVDD to GND........-0.3V to the lower of (VDD + 0.3V) and +3.6V INP, INN to GND ...-0.3V to the lower of (VDD + 0.3V) and +3.6V REFIN, REFOUT, REFP, REFN, COM to GND................-0.3V to the lower of (VDD + 0.3V) and +3.6V CLKP, CLKN, CLKTYP, G/T, DCE, PD to GND ........-0.3V to the lower of (VDD + 0.3V) and +3.6V D13–D0, DAV, DOR to GND....................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 40-Pin Thin QFN 6mm x 6mm x 0.8mm (derated 26.3mW/°C above +70°C)........................2105.3mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering 10s) ..................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 95MHz (50% duty cycle, 1.4VP-P square wave), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER DC ACCURACY (Note 2) Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT (INP, INN) Differential Input Voltage Range Common-Mode Input Voltage Input Capacitance (Figure 3) CONVERSION RATE Maximum Clock Frequency Minimum Clock Frequency Data Latency Figure 6 8.0 fCLK 95 5 MHz MHz Clock cycles dBFS CPAR CSAMPLE Fixed capacitance to ground Switched capacitance VDIFF Differential or single-ended inputs ±1.024 VDD / 2 2 4.5 V V pF INL DNL fIN = 3MHz fIN = 3MHz VREFIN = 2.048V VREFIN = 2.048V 14 ±1.6 ±0.65 ±0.1 ±0.35 ±0.78 ±5.3 Bits LSB LSB %FS %FS SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS (Differential Inputs) (Note 2) Small-Signal Noise Floor SSNF Input at less than -35dBFS fIN = 3MHz at -0.5dBFS (Notes 3, 4) Signal-to-Noise Ratio SNR fIN = 47.5MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS (Notes 3, 4) fIN = 3MHz at -0.5dBFS (Notes 3, 4) Signal-to-Noise and Distortion SINAD fIN = 47.5MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS (Notes 3, 4) 64.0 66.9 66.7 67.6 -74.7 74.2 73.8 73.6 72.1 73.8 73.5 72.5 69.8 dB dB 2 _______________________________________________________________________________________ 14-Bit, 95Msps, 3.3V ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 95MHz (50% duty cycle, 1.4VP-P square wave), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS fIN = 3MHz at -0.5dBFS (Notes 3, 4) Spurious-Free Dynamic Range SFDR fIN = 47.5MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS (Notes 3, 4) fIN = 3MHz at -0.5dBFS Total Harmonic Distortion THD fIN = 47.5MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS fIN = 3MHz at -0.5dBFS Second Harmonic HD2 fIN = 47.5MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS fIN = 3MHz at -0.5dBFS Third Harmonic HD3 fIN = 47.5MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS fIN1 = 68.5MHz at -7dBFS fIN2 = 71.5MHz at -7dBFS fIN1 = 172.5MHz at -7dBFS fIN2 = 177.5MHz at -7dBFS fIN1 = 68.5MHz at -7dBFS fIN2 = 71.5MHz at -7dBFS fIN1 = 172.5MHz at -7dBFS fIN2 = 177.5MHz at -7dBFS Two-Tone Spurious-Free Dynamic Range Aperture Delay Aperture Jitter Output Noise Overdrive Recovery Time fIN1 = 68.5MHz at -7dBFS fIN2 = 71.5MHz at -7dBFS fIN1 = 172.5MHz at -7dBFS fIN2 = 177.5MHz at -7dBFS Figure 4 Figure 4 INP = INN = COM ±10% beyond full scale 67.1 MIN 73.5 TYP 88.4 86.9 80.5 74.7 -85.1 -84.7 -79.0 -73.6 -89 -92 -91 -82 -92 -93 -81 -75 -79 dBc -75 -80 dBc -76 80 dBc 76 1.2 50 VCOM VDD / 2 VREFP - VCOM VREFN - VCOM VREF IREFP IREFN ICOM VREF = VREFP - VREFN = VREFIN x 3/4 VREFP = 2.418V VREFN = 0.882V VCOM = 1.650V 1.65 0.768 -0.768 1.536 1.4 1.0 1.0 13 6 0.8 x VDD 0.2 x VDD 0.2 SYMBOL VREFOUT VCOM VREF VDD / 2 VREF = VREFP - VREFN = VREFIN x 3/4 -1.0mA < IREFOUT < +0.1mA CONDITIONS MIN 1.980 TYP 2.048 1.65 1.536 35 +50 0.24 2.1 2.048 2.418 0.882 1.65 1.70 1.604 MAX 2.066 UNITS V V V mV/mA ppm/°C mA INTERNAL REFERENCE (REFIN = REFOUT; VREFP, VREFN, and VCOM are generated internally) BUFFERED EXTERNAL REFERENCE (REFIN driven externally; VREFIN = 2.048V, VREFP, VREFN, and VCOM are generated internally) REFIN Input Voltage REFP Output Voltage REFN Output Voltage COM Output Voltage Differential-Reference Output Voltage Differential-Reference Temperature Coefficient REFIN Input Resistance UNBUFFERED EXTERNAL REFERENCE (REFIN = GND; VREFP, VREFN, and VCOM are applied externally) COM Input Voltage REFP Input Voltage REFN Input Voltage Differential-Reference Input Voltage REFP Sink Current REFN Source Current COM Sink Current REFP, REFN Capacitance COM Capacitance CLOCK INPUTS (CLKP, CLKN) Single-Ended Input High Threshold Single-Ended Input Low Threshold Minimum Differential Input Voltage Swing VIH VIL CLKTYP = GND, CLKN = GND CLKTYP = GND, CLKN = GND CLKTYP = high V V VP-P V V V V mA mA mA pF pF V V V V V ppm/°C MΩ 4 _______________________________________________________________________________________ 14-Bit, 95Msps, 3.3V ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 95MHz (50% duty cycle, 1.4VP-P square wave), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Differential Input Common-Mode Voltage Input Resistance Input Capacitance RCLK CCLK 0.8 x OVDD 0.2 x OVDD VIH = OVDD VIL = 0 CDIN D13–D0, DOR, ISINK = 200µA DAV, ISINK = 600µA D13–D0, DOR, ISOURCE = 200µA Output-Voltage High VOH DAV, ISOURCE = 600µA Tri-State Leakage Current D13–D0, DOR Tri-State Output Capacitance DAV Tri-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Digital Output Supply Voltage VDD OVDD Normal operating mode, fIN = 175MHz at -0.5dBFS, CLKTYP = GND, single-ended clock Analog Supply Current IVDD Normal operating mode, fIN = 175MHz at -0.5dBFS, CLKTYP = OVDD, differential clock Power-down mode clock idle, PD = OVDD 3.15 1.7 3.3 1.8 3.60 VDD + 0.3V V V ILEAK COUT CDAV (Note 5) (Note 5) (Note 5) 3 6 OVDD 0.2 V OVDD 0.2 ±5 µA pF pF 5 0.2 0.2 ±5 ±5 SYMBOL CONDITIONS CLKTYP = high Figure 5 MIN TYP VDD / 2 5 2 MAX UNITS V kΩ pF MAX12555 DIGITAL INPUTS (CLKTYP, DCE, G/T, PD) Input High Threshold Input Low Threshold Input Leakage Current Input Capacitance VIH VIL V V µA pF DIGITAL OUTPUTS (D13–D0, DAV, DOR) Output-Voltage Low VOL V 141 mA 150.6 0.1 165 _______________________________________________________________________________________ 5 14-Bit, 95Msps, 3.3V ADC MAX12555 ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 95MHz (50% duty cycle, 1.4VP-P square wave), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS Normal operating mode, fIN = 175MHz at -0.5dBFS, CLKTYP = GND, single-ended clock Analog Power Dissipation PDISS Normal operating mode, fIN = 175MHz at -0.5dBFS, CLKTYP = OVDD, differential clock Power-down mode clock idle, PD = OVDD Normal operating mode, fIN = 175MHz at -0.5dBFS, OVDD = 1.8V, CL ≈ 5pF Power-down mode clock idle, PD = OVDD TIMING CHARACTERISTICS (Figure 6) Clock Pulse-Width High Clock Pulse-Width Low Data-Valid Delay Data Setup Time Before Rising Edge of DAV Data Hold Time After Rising Edge of DAV Wake-Up Time from Power-Down tCH tCL tDAV tSETUP tHOLD tWAKE CL = 5pF (Note 6) CL = 5pF (Notes 6, 7) CL = 5pF (Notes 6, 7) VREFIN = 2.048V 5.5 4.0 10 5.2 5.2 5.2 ns ns ns ns ns ms MIN TYP 465 mW 497 0.3 10.2 8 mA µA 545 MAX UNITS Digital Output Supply Current IOVDD Note 1: Specifications ≥+25°C guaranteed by production test; 50MΩ). When driving REFIN through a Table 1. Reference Modes VREFIN REFERENCE MODE Internal Reference Mode. Drive REFIN with REFOUT either through a direct short or a resistive divider. The full-scale analog input range is ±VREFIN / 2: VCOM = VDD / 2 VREFP = VDD / 2 + VREFIN x 3/8 VREFN = VDD / 2 - VREFIN x 3/8 Buffered External Reference Mode. Apply an external 0.7V to 2.2V reference voltage to REFIN. The full-scale analog input range is ±VREFIN / 2: VCOM = VDD / 2 VREFP = VDD / 2 + VREFIN x 3/8 VREFN = VDD / 2 - VREFIN x 3/8 Unbuffered External Reference Mode. Drive REFP, REFN, and COM with external reference sources. The full-scale analog input range is ±(VREFP - VREFN) x 2/3. 35% VREFOUT to 100% VREFOUT 0.7V to 2.2V