MAX13000EEUE

19-3692; Rev 1; 5/11 Ultra-Low-Voltage Level Translators General Description The MAX13000E–MAX13005E 6-channel level translators provide the level shifting necessary to allow data transfer in multivoltage systems. Externally applied voltages, VCC and VL, set the logic levels on either side of the device. Logic signals present on the VL side of the device appear as higher voltage logic signals on the VCC side of the device, and vice-versa. The MAX13000E–MAX13005E feature a low VCC and VL quiescent supply current less than 4µA. The MAX13000E–MAX13005E also have ±15kV ESD protection on the I/O VCC side for greater protection in applications that route signals externally. The ESD protection is specified using the Human Body Model (HBM). The MAX13000E/MAX13001E/MAX13002E operate at a guaranteed 230kbps data rate. The MAX13003E/ MAX13004E/MAX13005E operate at a guaranteed 20Mbps data rate when VCC > +1.65V. The MAX13000E/MAX13003E are bidirectional level translators, allowing data translation in either direction (VL ↔ VCC) on any single data line without a DIRECTION input. The MAX13001E/MAX13002E/MAX13004E/ MAX13005E unidirectional level translators level shift data in one direction (VL → VCC or VCC → VL) on any single data line. The MAX13001E/MAX13002E/ MAX13004E/MAX13005E unidirectional translators’ inputs have the capability to interface with both CMOS and open-drain (OD) outputs. For more information see the Ordering Information, Selector Guide, and the InputDriver Requirements sections. The MAX13000E–MAX13005E operate with +0.9V to +3.6V VL voltages and +1.5V to +3.6V VCC voltages. The MAX13000E–MAX13005E are available in 16-bump UCSP™ and 16-pin TSSOP packages, and are specified over the extended -40°C to +85°C operating temperature range. Features ♦ Guaranteed Data-Rate Options 230kbps (MAX13000E/MAX13001E/MAX13002E) 20Mbps (MAX13003E/MAX13004E/MAX13005E) ♦ Bidirectional Level Translation Without a DIRECTION Input ♦ ♦ ♦ ♦ Operational Down to +0.9V on VL and +1.5V on VCC ±15kV ESD Protection on I/O VCC Lines per HBM Low +1.65V, CI/OVL = 50pF, MAX13003E/MAX13004E/MAX13005E, Figures 2a, 2b Propagation Delay (Driving I/OVCC_) VCC = 1.5V, CI/OVL = 15pF, MAX13003E/MAX13004E/MAX13005E, Figures 2a, 2b CI/OVL = 50pF, MAX13000E/MAX13001E/MAX13002E, Figures 2a, 2b Propagation Delay from I/OVL to I/OVCC_ after EN (Note 5) CI/OVCC = 50pF, CMOS output, Figure 3 tEN-VCC CI/OVCC = 50pF, OD output, Figure 3 6 1000 300 300 MIN TYP MAX 15 UNITS MAX13000E–MAX13005E 15 ns 1200 15 15 ns 1200 20 ns Propagation Delay (Driving I/OVL_) 20 I/OVCC-VL 20 ns 1000 2 µs _______________________________________________________________________________________ 5 Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E TIMING CHARACTERISTICS (continued) (VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4) PARAMETER Propagation Delay from I/OVCC to I/OVL after EN (Note 5) SYMBOL tEN-VL CI/OVL = 50pF, OD output, Figure 4 Each translator equally loaded, MAX13003E/MAX13004E/MAX13005E Channel-to-Channel Skew tSKEW Each translator equally loaded, MAX13000E/MAX13001E/MAX13002E CI/OVL = 15pF, CI/OVCC = 15pF, VL = +1.8V, VCC = +2V, ΔT = +5°C, MAX13003E/MAX13004E/MAX13005E MAX13003E/MAX13004E/MAX13005E VCC > +1.65V, CI/OVL = 50pF, CI/OVCC = 50pF MAX13000E/MAX13001E/MAX13002E CI/OVL = 50pF, CI/OVCC = 50pF 6 ±5 ns ±250 CONDITIONS CI/OVL = 50pF, CMOS output, Figure 4 MIN TYP MAX 2 µs UNITS Part-to-Part Skew (Note 6) tPPSKEW 10 ns 20 Mbps Maximum Data Rate 230 kbps Note 1: All devices are 100% production tested at TA = +25°C. Limits are guaranteed by design over the entire temperature range. Note 2: VL must be less than or equal to VCC during normal operation. However, VL can be greater than VCC during startup and shutdown conditions. Note 3: This consumption is referred to as no signal transmission. Note 4: Guaranteed by design with an input signal full swing, rise/fall time ≤ 3ns, source resistance is 50Ω. Note 5: Enable input signal full swing and rise/fall time ≤ 50ns. Note 6: Guaranteed by design, not production tested. Typical Operating Characteristics (VCC = +3.3V, VL = +0.9V, TA = +25°C, MAX13003E.) VL SUPPLY CURRENT vs. SUPPLY VOLTAGE (DRIVING I/O VL, VL = 0.9V) MAX13000Etoc01 VL SUPPLY CURRENT vs. SUPPLY VOLTAGE (DRIVING I/O VCC, VL = 0.9V) MAX13000Etoc02 VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE (DRIVING I/O VL, VL = 0.9V) DATA RATE = 20Mbps VCC SUPPLY CURRENT (mA) MAX13000Etoc03 1000 1 DATA RATE = 20Mbps VL SUPPLY CURRENT (mA) 0.1 10 VL SUPPLY CURRENT (μA) DATA RATE = 20Mbps 100 1 10 DATA RATE = 230kbps 1 0.01 DATA RATE = 230kbps 0.1 DATA RATE = 230kbps 0.1 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) 0.001 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) 0.01 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) 6 _______________________________________________________________________________________ Ultra-Low-Voltage Level Translators Typical Operating Characteristics (continued) (VCC = +3.3V, VL = +0.9V, TA = +25°C, MAX13003E.) VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE (DRIVING I/OVCC, VL = +0.9V) MAX13000Etoc04 MAX13000E–MAX13005E VL SUPPLY CURRENT vs. TEMPERATURE (DRIVING I/OVCC, VCC = +3.3V, VL = +0.9V) MAX13000E toc05 VCC SUPPLY CURRENT vs. TEMPERATURE (DRIVING I/OVCC, VCC = +3.3V, VL = +0.9V) MAX13000E toc06 10 DATA RATE = 20Mbps VCC SUPPLY CURRENT (mA) 1.0 340 4.10 VCC SUPPLY CURRENT (μA) VCC SUPPLY CURRENT (mA) 330 4.05 DATA RATE = 20Mbps 4.00 320 0.1 310 DATA RATE = 20Mbps 3.95 DATA RATE = 230kbps 0.01 300 3.90 0.001 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) 290 -40 -15 10 35 60 85 TEMPERATURE (°C) 3.85 -40 -15 10 35 60 85 TEMPERATURE (°C) VL SUPPLY CURRENT vs. CAPACITIVE LOAD ON I/O VCC (DRIVING I/OVL, VCC = 3.3V, VL = +0.9V) MAX31000Etoc07 VCC SUPPLY CURRENT vs. CAPACITIVE LOAD ON I/O VCC (DRIVING I/OVL, VCC = 3.3V, VL = +0.9V) MAX31000Etoc08 RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O VCC (DRIVING I/OVL, VCC = 3.3V, VL = +0.9V) 8 7 RISE/FALL TIME (ns) 6 5 4 3 2 tF tR MAX31000Etoc09 140 120 VL SUPPLY CURRENT (μA) 100 80 60 40 20 0 10 20 30 40 50 60 70 80 DATA RATE = 230kbps DATA RATE = 20Mbps 9 8 VCC SUPPLY CURRENT (mA) 7 6 5 4 3 2 1 0 DATA RATE = 230kbps 10 20 30 40 50 60 70 80 DATA RATE = 20Mbps 9 1 0 90 100 10 20 30 40 50 60 70 80 90 100 90 100 CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF) RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O VL (DRIVING I/OVCC, = 3.3V, VL = +0.9V) MAX31000Etoc10 PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O VCC (DRIVING I/OVL, VCC, = 3.3V, VL = +0.9V) MAX31000Etoc11 PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O VL (DRIVING I/OVCC, VCC = 3.3V, VL = +0.9V) 6.0 PROPAGATION DELAY (ns) 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 MAX13000Etoc12 8 7 RISE/FALL TIME (ns) 6 tF 5 4 3 tR 2 1 0 10 20 30 40 50 60 70 80 9.0 8.5 PROPAGATION DELAY (ns) 8.0 7.5 7.0 6.5 6.0 5.5 5.0 6.5 90 100 10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100 CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF) _______________________________________________________________________________________ 7 Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E Typical Operating Characteristics (continued) (VCC = +3.3V, VL = +0.9V, TA = +25°C, MAX13003E.) OD RAIL-TO-RAIL DRIVING (MAX13005E) (DRIVING I/OVL, VCC = +3.3V, VL = +0.9V, CI/OVCC = 56pF, DATA RATE = 230Mbps, RPULLUP = 1kΩ) MAX31000Etoc13 OD RAIL-TO-RAIL DRIVING (MAX13002E) (DRIVING I/OVL, VCC = +3.3V, VL = +0.9V, CI/OVCC = 56pF, DATA RATE = 230kbps, RPULLUP = 15kΩ) MAX31000Etoc14 RAIL-TO-RAIL DRIVING (DRIVING I/OVL, VCC = +3.3V, VL = +0.9V, CI/OVCC = 50pF, DATA RATE = 230kbps) MAX31000Etoc15 I/OVL_ 500mV/div GND I/OVL_ 500mV/div GND I/OVL_ 500mV/div GND I/OVCC 2V/div GND I/OVCC 2V/div GND I/OVCC 2V/div GND 200ns/div 2μs/div 1μs/div RAIL-TO-RAIL DRIVING (DRIVING I/OVL VCC = +3.3V, VL = +0.9V, CI/OVCC = 50pF, DATA RATE = 4Mbps) MAX31000Etoc16 RAIL-TO-RAIL DRIVING (DRIVING I/OVL, VCC = +3.3V, VL = +0.9V, CI/OVCC = 50pF, DATA RATE = 20Mbps) MAX31000Etoc17 VCC + VL SUPPLY CURRENT vs. FREQUENCY (DRIVING I/OVL, VCC = +3.3V, VL = +0.9V) 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100 I/OVL IS DRIVEN WITH A 0.9V SQUARE WAVE MAX31000Etoc18 I/OVL_ 500mV/div GND I/OVL_ 500mV/div GND VCC + VL SUPPLY CURRENT (mA) VCC + VL VCC I/OVCC 2V/div GND I/OVCC 2V/div GND VL 40ns/div 10ns/div 4250 8400 12,550 16,700 20,850 25,000 FREQUENCY (kHz) VCC + VL SUPPLY CURRENT vs. FREQUENCY (DRIVING I/OVCC, VCC = +3.3V, VL = +0.9V) 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100 I/OVCC IS DRIVEN WITH A 3.3V SQUARE WAVE VCC + VL 2.0 VOHL (V) 1.5 1.0 0.5 0 4250 8400 12,550 16,700 20,850 25,000 FREQUENCY (kHz) 0 5 MAX31000Etoc19 VOHL vs. IOHL FOR VL SIDE (VCC = 3.3V) MAX13000Etoc20 VOLL vs. IOLL FOR VL SIDE (VCC = 3.3V) MAX13000Etoc21 3.0 2.5 VL = +2.5V 0.25 VCC + VL SUPPLY CURRENT (mA) 0.20 VL = +2.5V VL = +1.8V VL = +0.9V VOLL (V) VL = +1.8V 0.15 VCC 0.10 VL = +0.9V 0.05 VL 0 10 15 20 25 30 35 40 45 50 IOHL (μA) 0 5 10 15 20 25 30 35 40 45 50 IOLL (μA) 8 _______________________________________________________________________________________ Ultra-Low-Voltage Level Translators Typical Operating Characteristics (continued) (VCC = +3.3V, VL = +0.9V, TA = +25°C, MAX13003E.) VOLC vs. IOLC FOR VCC SIDE MAX13000Etoc22 MAX13000E–MAX13005E VOHC vs. IOHC FOR VCC SIDE VCC = +3.3V 3.0 VCC = +2.5V MAX13000Etoc23 0.25 VCC = +2.5V 0.20 VCC = +3.3V 3.5 0.10 VCC = +1.8V VOHC (V) VOLC (V) 0.15 2.5 2.0 VCC = +1.8V 0.05 1.5 0 0 5 10 15 20 25 30 35 40 45 50 IOLC (μA) 1.0 0 5 10 15 20 25 30 35 40 45 50 IOHC (μA) Pin Descriptions MAX13000E/MAX13003E PIN TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UCSP B1 B2 A1 A2 A3 A4 B3 B4 C4 C3 D4 D3 D2 D1 C2 C1 NAME I/OVL1 I/OVL2 I/OVL3 VL EN I/OVL4 I/OVL5 I/OVL6 I/OVCC6 I/OVCC5 I/OVCC4 GND VCC I/OVCC3 I/OVCC2 I/OVCC1 FUNCTION CMOS Input/Output 1, Referenced to VL CMOS Input/Output 2, Referenced to VL CMOS Input/Output 3, Referenced to VL Logic Input Voltage, +0.9V ≤ VL ≤ VCC. Bypass VL to GND with a 0.1µF capacitor. Enable Input. When EN is pulled low, I/O VCC1 to I/O VCC6 and I/O VL1 to I/O VL6 are tri-stated. Drive EN high (VL) for normal operation. CMOS Input/Output 4, Referenced to VL CMOS Input/Output 5, Referenced to VL CMOS Input/Output 6, Referenced to VL CMOS Input/Output 6, Referenced to VCC CMOS Input/Output 5, Referenced to VCC CMOS Input/Output 4, Referenced to VCC Ground VCC Input Voltage, +1.5V ≤ VCC ≤ 3.6V. Bypass VCC to GND with a 0.1µF capacitor. For full ESD protection, use a 1µF bypass capacitor on VCC. CMOS Input/Output 3, Referenced to VCC CMOS Input/Output 2, Referenced to VCC CMOS Input/Output 1, Referenced to VCC _______________________________________________________________________________________ 9 Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E Pin Descriptions (continued) MAX13001E/MAX13004E PIN TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UCSP B1 B2 A1 A2 A3 A4 B3 B4 C4 C3 D4 D3 D2 D1 C2 C1 NAME OVL1 OVL2 OVL3 VL EN OVL4 OVL5 OVL6 IVCC6 IVCC5 IVCC4 GND VCC IVCC3 IVCC2 IVCC1 CMOS Output 1, Referenced to VL CMOS Output 2, Referenced to VL CMOS Output 3, Referenced to VL Logic Input Voltage, +0.9V ≤ VL ≤ VCC. Bypass VL to GND with a 0.1µF capacitor. Enable Input. When EN is pulled low, OVCC1 to OVCC6 and IVL1 to IVL6 are tri-stated. Drive EN high (VL) for normal operation. CMOS Output 4, Referenced to VL CMOS Output 5, Referenced to VL CMOS Output 6, Referenced to VL Open-Drain-Compatible Input 6, Reference to VCC Open-Drain-Compatible Input 5, Referenced to VCC Open-Drain-Compatible Input 4, Referenced to VCC Ground VCC Input Voltage, +1.5V ≤ VCC ≤ 3.6V. Bypass VCC to GND with a 0.1µF capacitor. For full ESD protection, use a 1µF bypass capacitor on VCC. Open-Drain-Compatible Input 3, Referenced to VCC Open-Drain-Compatible Input 2, Referenced to VCC Open-Drain-Compatible Input 1, Referenced to VCC FUNCTION 10 ______________________________________________________________________________________ Ultra-Low-Voltage Level Translators Pin Descriptions (continued) MAX13002E/MAX13005E PIN TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UCSP B1 B2 A1 A2 A3 A4 B3 B4 C4 C3 D4 D3 D2 D1 C2 C1 NAME IVL1 IVL2 IVL3 VL EN IVL4 IVL5 IVL6 OVCC6 OVCC5 OVCC4 GND VCC OVCC3 OVCC2 OVCC1 FUNCTION Open-Drain-Compatible Input 1, Referenced to VL Open-Drain-Compatible Input 2, Referenced to VL Open-Drain-Compatible Input 3, Referenced to VL Logic Input Voltage, +0.9V ≤ VL ≤ VCC. Bypass VL to GND with a 0.1µF capacitor. Enable Input. When EN is pulled low, OVCC1 to OVCC6 and IVL1 to IVL6 are tri-stated. Drive EN high (VL) for normal operation. Open-Drain-Compatible Input 4, Referenced to VL Open-Drain-Compatible Input 5, Referenced to VL Open-Drain-Compatible Input 6, Referenced to VL CMOS Output 6, Referenced to VCC CMOS Output 5, Referenced to VCC CMOS Output 4, Referenced to VCC Ground VCC Input Voltage, +1.5V ≤ VCC ≤ 3.6V. Bypass VCC to GND with a 0.1µF capacitor. For full ESD protection, use a 1µF bypass capacitor on VCC. CMOS Output 3, Referenced to VCC CMOS Output 2, Referenced to VCC CMOS Output 1, Referenced to VCC MAX13000E–MAX13005E ______________________________________________________________________________________ 11 Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E Test Circuits/Timing Diagrams I/OVL_ 90% VL VCC 50% 10% tRISE/FALL I/OVL-VCC MAX13000E EN I/OVL_ SOURCE RS I/OVCC CI/OVCC I/OVCC_ 90% 50% 10% tFVCC I/OVL-VCC tRVCC UNUSED I/Os ARE GROUNDED. tRISE/FALL < 3ns (MAX13003E/MAX13004E/MAX13005E) tRISE/FALL < 80ns (MAX13000E/MAX13001E/MAX13002E) Figure 1a. Driving I/OVL Figure 1b. Timing for Driving I/OVL tRISE/FALL VL VCC I/OVCC_ 90% 50% 10% I/OVCC-VL I/OVCC-VL MAX13000E EN I/OVL_ I/OVL_ CI/OVL I/OVCC RS 90% 50% 10% tFVL tRVL SOURCE tRISE/FALL < 3ns (MAX13003E/MAX13004E/MAX13005E) UNUSED I/Os ARE GROUNDED. tRISE/FALL < 80ns (MAX13000E/MAX13001E/MAX13002E) Figure 2a. Driving I/OVCC Figure 2b. Timing for Driving I/OVCC 12 ______________________________________________________________________________________ Ultra-Low-Voltage Level Translators Test Circuits/Timing Diagrams (continued) VL EN SOURCE EN t'EN-VCC 0 VL I/OVL_ VL I/OVCC I/OVL_ CI/OVCC VCC / 2 I/OVCC_ 0 VL t"EN-VCC SOURCE EN 0 VCC MAX13000E–MAX13005E MAX13000E MAX13000E EN I/OVL_ 0 VL 0 VCC VCC / 2 0 I/OVL_ I/OVCC CI/OVCC I/OVCC_ tEN-VCC IS WHICH EVER IS LARGER BETWEEN t'EN-VCC AND t"EN-VCC. Figure 3. Propagation Delay from I/OVL to I/OVCC After EN VL VL SOURCE EN EN MAX13000E I/OVCC_ t'EN-VL 0 VCC 0 VL I/OVL_ CI/OVL I/OVCC VCC I/OVL_ VL / 2 0 VL EN VL SOURCE t"EN-VL 0 VCC 0 VL I/OVL_ VL / 2 0 EN MAX13000E I/OVCC_ I/OVL_ CI/OVL I/OVCC tEN-VL IS WHICH EVER IS LARGER BETWEEN t'EN-VL AND t"EN-VL. Figure 4. Propagation Delay from I/OVCC to I/OVL After EN ______________________________________________________________________________________ 13 Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E Detailed Description The MAX13000E–MAX13005E logic-level translators provide the level shifting necessary to allow data transfer in multivoltage systems. Externally applied voltages, VCC and VL, set the logic levels on each side of the device. Logic signals present on the VL side of the device appear as higher voltage logic signals on the VCC side of the device, and vice-versa. The MAX13000E/MAX13003E are bidirectional level translators allowing data translation in either direction (VL ↔ VCC) on any single data line without the use of a DIRECTION input. The MAX13001E/MAX13002E/ MAX13004E/MAX13005E unidirectional level translators level shift data in one direction (VL → VCC or VCC → V L ) on any single data line. The MAX13001E/ MAX13002E/MAX13004E/MAX13005E unidirectional translators’ inputs have the capability to interface with both CMOS and open-drain (OD) outputs. For more information, see the Ordering Information section and the Input Driver Requirements section. The MAX13000E–MAX13005E accept VL from +0.9V to +3.6V. All devices have VCC ranging from +1.5V to +3.6V, making them ideal for data transfer between low-voltage ASICs/PLDs and higher voltage systems. The MAX13000E–MAX13005E feature low VCC quiescent supply current of less than 4µA, and VL quiescent supply current of less than 2µA when in shutdown. The MAX13000E–MAX13005E have ±15kV ESD protection on the VCC side for greater protection in applications that route signals externally. The ESD protection is specified using the Human Body Model (HBM).The MAX13000E/MAX13001E/MAX13002E operate at a guaranteed 230kbps data rate. The MAX13003E/ MAX13004E/MAX13005E operate at a guaranteed 20Mbps data rate when VCC > +1.65V. For normal operation, ensure that +1.5V ≤ VCC ≤ +3.6V, and +0.9V ≤ VL ≤ VCC. During power-up sequencing, VL ≥ VCC does not damage the device whenever VL is within the absolute maximum ratings (see the Absolute Maximum Ratings s ection). During power-supply sequencing, when VCC is floating and VL is powered up, 1mA of current can be sourced to each load on the VL side, yet the device does not latch up. The MAX13000E–MAX13005E are designed to have VCC ≥ VL at all times; however, if VCC is turned off, the part will not be damaged and will not latch up. To prevent excessive leakage currents in either the I/O or supply lines, the I/O on the VL side must be left in the high state. The maximum data rate for the MAX13000E– MAX13005E depends heavily on the load capacitance (see the T ypical Operating Characteristics ), output impedance of the driver, and the operational voltage range (see the Timing Characteristics table). Open-Drain Operation The MAX13001E/MAX13002E/MAX13004E/MAX13005E have input stages specifically designed to accommodate external open-drain drivers. When using opendrain drivers, the MAX13001E/MAX13002E/ MAX13004E/MAX13005E operate in a unidirectionalonly mode, translating from the OD side to the CMOS side. For improved performance, the rise- and fall-time accelerators are present on both the CMOS and the OD side. See the Input-Driver Requirement section. Do not use pullup resistors greater than 15kΩ for proper operation, and smaller pullup resistance may be needed for higher speed operation. Input-Driver Requirements The MAX13000E–MAX13005E feature four different architectures based on the speed of the part, as well as on whether the translator is a CMOS-to-CMOS translator, or whether it is an OD-to-CMOS translator. 20Mbps CMOS-to-CMOS Bidirectional Translator (MAX13003E) The MAX13003E architecture is based on a one-shot accelerator output stage (Figure 5). Accelerator output stages are always in tri-state, except when there is a transition on any of the translators on the input side, either I/OVL or I/OVCC. A short pulse is generated during which the one-shot output stage becomes active and charges/discharges the capacitances at the I/Os. Due to its bidirectional nature, the accelerator stages on both the I/OVCC and the I/OVL become active during an I/O transition from low to high or high to low. This can lead to some current feeding into the external source that is driving the translator. However, this behavior helps speed up the transition on the driven side. The type of devices that drive the inputs of the MAX13003E is usually specified with an output drivecurrent capability (IOUT). When driving the inputs of the MAX13003E, the maximum achievable speed is constrained by the drive current of the external driver. To insure the maximum possible throughput of 20Mbps, the external driver should meet the following requirement: IOUT ≥ 1.67 × 108 × V × (CIN + CP) Level Translation 14 ______________________________________________________________________________________ Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E VL P ONE-SHOT 5kΩ I/OVL INVERTER 2 INVERTER 1 N ONE-SHOT VCC I/OVCC P ONE-SHOT 5kΩ INVERTER 4 N ONE-SHOT INVERTER 3 Figure 5. Architecture of 20Mbps, CMOS-to-CMOS Bidirectional Translators where, CP is the parasitic capacitance of the traces, V is the supply voltage of the driven side (i.e., VL or VCC), and CIN is the input capacitance of the driven side (CIN = 10pF for VL side, CIN = 20pF for VCC side). 20Mbps OD-to-CMOS Unidirectional Translators (MAX13004E/MAX13005E) The MAX13004E/MAX13005E architecture is virtually the same as that for the bidirectional CMOS-to-CMOS translators, the only difference being that the output inverter (inverter 4) at the driving side accommodates the driving capabilities of an open-drain output (Figure 6). For proper operation, a pullup resistor needs to be connected from the open-drain output to the power supply of the driving side. Use pullup resistors no larger than 15kΩ. 230kbps CMOS-to-CMOS Bidirectional Translator (MAX13000E) The architecture of the MAX13000E lacks the one-shot accelerator output stages since the transitions that this device handles are limited by its data rate, 230kbps (Figure 7). For proper operation, the driver must meet the following conditions: 1kΩ maximum output impedance and 1mA minimum output current. 230kbps OD-to-CMOS Unidirectional Translators (MAX13001E/MAX13002E) The architecture of the MAX13001E/MAX13002E is similar to that of the 230kbps CMOS-to-CMOS part, with the difference that it accommodates the driving capability of an open-drain output on the driving side, and also that it has only a single one-shot output stage (Figure 8). For proper operation, a pullup resistor needs to be connected from the open-drain output to the power supply of the driving side. Use pullup resistors no larger than 15kΩ. Figure 9 shows a graph of the typical input current versus input voltage for all of the above configurations. Enable Output Mode (EN) The MAX13000E–MAX13005E feature an enable (EN) input. Drive EN low to set the MAX13000E–MAX13005E I/Os in tri-state mode. Drive EN high (VL) for normal operation. ±15kV ESD Protection As with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. The I/OV CC lines have extra protection against static discharge. Maxim’s engineers have developed state-of-the-art structures to protect these pins against ESD of ±15kV without damage. The ESD 15 ______________________________________________________________________________________ Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E 20Mbps OPEN-DRAIN-TO-CMOS UNIDIRECTIONAL LEVEL TRANSLATOR VCC/VL P ONE-SHOT 5kΩ IVCC/IVL INVERTER 2 OPEN-DRAIN COMPATIBLE INPUT INVERTER 1 N ONE-SHOT CMOSCOMPATIBLE INPUT OVL/OVCC VL/VCC P ONE-SHOT 5kΩ INVERTER 3 75kΩ INVERTER 4 N ONE-SHOT Figure 6. Architecture of 20Mbps, OD-to-CMOS Unidirectional Translators 230kbps Bidirectional CMOS-TO-CMOS Level Translator VL VCC 5kΩ I/OVL INVERTER 1 INVERTER 2 I/OVCC 5kΩ INVERTER 4 INVERTER 3 Figure 7. Architecture of 230kbps, CMOS-to-CMOS Bidirectional Translator 16 ______________________________________________________________________________________ Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E 230kbps OPEN-DRAIN-TO-CMOS UNIDIRECTIONAL LEVEL TRANSLATOR VCC/VL VL/VCC 5kΩ IVCC/IVL OPEN-DRAIN COMPATIBLE INPUT INVERTER 1 INVERTER 2 OVL/OVCC CMOSCOMPATIBLE INPUT 5kΩ INVERTER 3 75kΩ INVERTER 4 5kΩ N ONE-SHOT Figure 8. Architecture of 230kbps, OD-to-CMOS Unidirectional Translator IIN VTH_IN / RIN1 structures withstand high ESD in all states: normal operation, tri-state output mode, and power-down. After an ESD event, Maxim’s E-versions keep working without latchup, whereas competing products can latch and must be powered-down to remove latchup. ESD protection can be tested in various ways. The I/OVCC lines of the MAX13000E–MAX13005E are characterized for protection to ±15kV using the Human Body Model. ESD Test Conditions 0 VTH_IN VIN ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. (VS - VTH_IN) / RIN2 VS WHERE, VS = VCC OR VL Human Body Model Figure 10 shows the Human Body Model and Figure 11 shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a 1.5kΩ resistor. RIN1 = RIN2 = 5kΩ FOR CMOS-TO-CMOS TRANSLATORS RIN1 = 75kΩ FOR OD-TO-CMOS TRANSLATORS Figure 9. Typical IIN vs. VIN ______________________________________________________________________________________ 17 Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E RC 1MΩ CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF RD 1500Ω DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST HIGHVOLTAGE DC SOURCE RC 50Ω TO 100Ω CHARGE-CURRENTLIMIT RESISTOR RD 330Ω DISCHARGE RESISTANCE DEVICE UNDER TEST Cs 150pF STORAGE CAPACITOR Figure 10. Human Body ESD Test Model Figure 12. IEC 61000-4-2 Contact Discharge Test Model IP 100% 90% AMPERES 36.8% 10% 0 0 tRL Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) UCSP Package Considerations For general UCSP package information and PC layout considerations, please refer to Maxim application note: Wafer-Level Chip-Scale Package. TIME tDL CURRENT WAVEFORM UCSP Reliability The chip-scale package (UCSP) represents a unique packaging form factor that may not perform equally to a packaged product through traditional mechanical reliability tests. UCSP reliability is integrally linked to the user’s assembly methods, circuit board material, and usage environment. The user should closely review these areas when considering use of a UCSP package. Performance through Operating Life Test and Moisture Resistance remains uncompromised as it is primarily determined by the wafer-fabrication process. Mechanical stress performance is a greater consideration for a UCSP package. UCSPs are attached through direct solder contact to the user’s PC board, foregoing the inherent stress relief of a packaged product lead frame. Solder joint contact integrity must be considered. Information on Maxim’s qualification plan, test data, and recommendations are detailed in the UCSP application note, which can be found on Maxim’s website at www.maxim-ic.com. Figure 11. Human Body Current Waveform IEC 61000-4-2 Standard ESD Protection The IEC 61000-4-2 standard (Figure 12) specifies ESD tolerance for electronic systems. The IEC61000-4-2 model specifies a 150pF capacitor that is discharged into the device through a 330 Ω resistor. The MAX13000E–MAX13005E’s I/O on the V CC side are rated for IEC 61000-4-2 standard, (8kV Contact Discharge and ±10kV Air-Gap Discharge). The IEC 61000-4-2 model discharges higher peak current and more energy than the HBM due to the lower series resistance and larger capacitor. Applications Information Power-Supply Decoupling To reduce ripple and the chance of transmitting incorrect data, bypass VL and VCC to ground with a 0.1µF capacitor. To ensure full ±15kV ESD protection, bypass VCC to ground with a 1µF capacitor. Place all capacitors as close to the power-supply inputs as possible. 18 ______________________________________________________________________________________ Ultra-Low-Voltage Level Translators Functional Diagram VL VCC MAX13000E–MAX13005E EN MAX13000E–MAX13005E I/OVL1 I/OVCC1 I/OVL2 I/OVCC2 I/OVL3 I/OVCC3 I/OVL4 I/OVCC4 I/OVL5 I/OVCC5 I/OVL6 I/OVCC6 GND ______________________________________________________________________________________ 19 Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E Typical Operating Circuits +0.9V +2.8V 0.1μF 1μF +0.9V SYSTEM CONTROLLER DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 VL VCC +2.8V SYSTEM EN MAX13004E OVL_1 IVCC_1 OVL_2 IVCC_2 OVL_3 OVL_4 OVL_5 OVL_6 GND IVCC_3 IVCC_4 IVCC_5 IVCC_6 MAX13001E DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 +0.9V +2.8V 0.1μF 1μF +0.9V SYSTEM CONTROLLER DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 VL VCC +2.8V SYSTEM EN MAX13005E IVL_1 OVCC_1 IVL_2 OVCC_2 IVL_3 IVL_4 IVL_5 IVL_6 GND OVCC_3 OVCC_4 OVCC_5 OVCC_6 MAX13002E DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 20 ______________________________________________________________________________________ Ultra-Low-Voltage Level Translators Typical Operating Circuits (continued) +0.9V +2.8V MAX13000E–MAX13005E 0.1μF 1μF +0.9V SYSTEM CONTROLLER DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 VL VCC +2.8V SYSTEM MAX13000E EN MAX13003E I/OVL_1 I/OVCC_1 I/OVL_2 I/OVL_3 I/OVL_4 I/OVL_5 I/OVL_6 GND I/OVCC_2 I/OVCC_3 I/OVCC_4 I/OVCC_5 I/OVCC_6 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 Selector Guide PART MAX13000E MAX13001E MAX13002E MAX13003E MAX13004E MAX13005E DATA RATE (bps) 230k 230k 230k 20M 20M 20M NUMBER OF BIDIRECTIONAL TRANSLATORS 6 — — 6 — — NUMBER OF VL → VCC TRANSLATORS — — 6 — — 6 NUMBER OF VCC → VL TRANSLATORS — 6 — — 6 — TRANSLATOR CONFIGURATION CMOS-to-CMOS OD-to-CMOS OD-to-CMOS CMOS-to-CMOS OD-to-CMOS OD-to-CMOS ______________________________________________________________________________________ 21 Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E Pin Configurations (continued) BOTTOM VIEW MAX13001E/MAX13004E IVCC3 D IVCC1 C OVL1 B OVL3 A VL EN OVL4 A OVL2 OVL5 OVL6 B IVL3 VL EN IVL4 IVCC2 IVCC5 IVCC6 C IVL1 IVL2 IVL5 IVL6 VCC GND IVCC4 D OVCC1 OVCC2 OVCC5 OVCC6 MAX13002E/MAX13005E OVCC3 VCC GND OVCC4 1 2 3 4 1 2 3 4 4 X 4 UCSP 4 X 4 UCSP TOP VIEW I/OVL1 1 I/OVL2 2 I/OVL3 3 VL 4 EN 5 I/OVL4 6 I/OVL5 7 I/OVL6 8 16 I/OVCC1 15 I/OVCC2 14 I/OVCC3 13 VCC OVL1 1 OVL2 2 OVL3 3 VL 4 EN 5 OVL4 6 OVL5 7 OVL6 8 16 IVCC1 15 IVCC2 14 IVCC3 13 VCC IVL1 1 IVL2 2 IVL3 3 VL 4 EN 5 IVL4 6 IVL5 7 IVL6 8 16 OVCC1 15 OVCC2 14 OVCC3 13 VCC MAX13000E MAX13003E 12 GND 11 I/OVCC4 10 I/OVCC5 9 I/OVCC6 MAX13001E MAX13004E 12 GND 11 IVCC4 10 IVCC5 9 IVCC6 MAX13002E MAX13005E 12 GND 11 OVCC4 10 OVCC5 9 OVCC6 TSSOP TSSOP TSSOP 22 ______________________________________________________________________________________ Ultra-Low-Voltage Level Translators Ordering Information (continued) PART MAX13000EEBE+T* MAX13001EEUE+ MAX13001EEBE+T* MAX13002EEUE+ MAX13002EEBE+T* MAX13003EEUE+ MAX13003EEBE+T* MAX13004EEUE+ MAX13004EEBE+T* MAX13005EEUE+ MAX13005EEBE+T* TEMP RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C PINPACKAGE 16 UCSP (4mm × 4mm) 16 TSSOP 16 UCSP (4mm × 4mm) 16 TSSOP 16 UCSP (4mm × 4mm) 16 TSSOP 16 UCSP (4mm × 4mm) 16 TSSOP 16 UCSP (4mm × 4mm) 16 TSSOP MAX13000E–MAX13005E Chip Information PROCESS: BiCMOS 16 UCSP (4mm × 4mm) *Future Product—contact factory for availability. +Denotes a lead(Pb)-free/RoHS-compliant package. T =Tape and reel. ______________________________________________________________________________________ 23 Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 16 TSSOP 16 UCSP PACKAGE CODE U16+2 B16+1 OUTLINE NO. 21-0066 21-0101 LAND PATTERN NO. 90-0117 Refer to Application Note 1891 24 ______________________________________________________________________________________ Ultra-Low-Voltage Level Translators Revision History REVISION NUMBER 0 1 REVISION DATE 6/05 5/11 Initial release Added lead-free information to the Ordering Information DESCRIPTION PAGES CHANGED — 1, 23 MAX13000E–MAX13005E Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.