MAX13301

19-5955; Rev 0; 6/11 TION_KIT EVALUA BLE ILA AVA 4-Channel, Automotive Class D Audio Amplifier General Description The MAX13301 combines four high-efficiency Class D amplifiers with integrated diagnostic hardware for reliable automotive audio systems, and delivers up to 80W at 10% THD+N per channel into 4I when operating from a 24V supply. The internal diagnostics evaluate each channel’s output impedance to check for shorts across the outputs, to the battery, or to ground. The I2C interface allows the system to query critical device parameters such as device temperature and output clipping. The device is programmable to four different I2C addresses. The audio amplifiers feature single-ended analog inputs with a common negative input. The MAX13301 has a fixed gain of 26dB. The Class D amplifier has 10 programmable switching frequencies between 300kHz and 750kHz. The BTL outputs are protected against short circuits and thermal overload. The outputs can be configured as a 2-, 3-, or 4-channel amplifier. The device provides 50V load-dump protection, and is offered in the thermally enhanced, 48-pin TSSOP-EPR package operating over the -40NC to +125NC temperature range. S High_Output_Power_(10%_THD+N)  2_x_160W_into_2I_at_24V  4_x_80W_into_4I_at_24V S 2_Channels_Can_Be_Paralleled S Feedback_After_the_Filter  Improves_THD+N  Low_Output_Impedance  High-Frequency_Response  Improved_Damping_of_Complex_Loads  Enables_Low-Cost_Inductors S 102dB_SNR S Low_0.04%_THD+N S 70dB_PSRR S On-Board_Diagnostics  Short-to-Battery/GND  Open/Shorted_Load  Tweeter_Detect S Protection_and_Monitoring_Functions:  Short-Circuit_Protection  50V_Load-Dump_Protection  Programmable_Clip_Detection  DC_Offset_Detection  Open_Battery/GND_Tolerant  Thermal-Overload_Protection  Thermal_Warning_Indication S Four-Address_I2C_Control_Interface S Low-Power_Shutdown_Mode S Up_to_90.5%_Efficiency S -40°C_to_+125°C_Ambient_Operating_Temperature S 48-Pin_TSSOP-EPR_(Top_Side_Exposed_Pad)_Package S AEC-Q100_Qualified Features MAX13301 Applications Car Stereo Rear-Seat Entertainment Units Discrete Amplifier Modules Active Loudspeaker Systems Radio Head Units Mobile Surround Systems Ordering Information PART Typical Operating Circuit appears at end of data sheet. PIN-PACKAGE 48 TSSOP-EPR* SUPPLY_VOLTAGE_ RANGE_(V) 6 to 25.5 MAX13301AUM/V+ Note: The device operates over the -40°C to +125°C operating temperature range. /V denotes an automotive qualified part. +Denotes a lead(Pb)-free/RoHS-compliant package. *EPR = Top side exposed pad. ________________________________________________________________ _Maxim Integrated Products_ _ 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 4-Channel, Automotive Class D Audio Amplifier MAX13301 ABSOLUTE_MAXIMUM_RATINGS PVDD to PGND...................................................... -0.3V to +30V PVDD to PGND (t < 200ms) .................................. -0.3V to +50V PVDD Ramp Rate ........................................................... 25V/ms VDD5, CM to PGND ................................................. -0.3V to +6V CP to PGND ........................ (VPVDD - 0.3V) to (VCHOLD + 0.3V) CHOLD to PVDD ..................................................... -0.3V to +6V OUT_ to PGND, FB_ to PGND ..............-0.3V to (VPVDD + 0.3V) VDD to GND ............................................................ -0.3V to +6V REF to GND ............................................................. -0.3V to +6V SCL, SDA, SYNC to GND........................................ -0.3V to +6V MUTE_CL1, CL0, FLT_OT, EN to GND ................... -0.3V to +6V IN_ to GND .............................................................. -0.3V to +6V GND to PGND ...................................................... -0.3V to +0.3V Continuous Power Dissipation (Notes 1 and 2) TSSOP (derate 16.7mW/NC above 70NC) ............... 1333.3mW Operating Temperature Range ........................ -40NC to +125NC Junction Temperature Range........................... -40NC to +150NC Storage Temperature Range............................ -65NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+240NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE_THERMAL_CHARACTERISTICS_(Notes_1_and_2) TSSOP Junction-to-Ambient Thermal Resistance (BJA) .......... 60NC/W Junction-to-Case Thermal Resistance (BJC) ................. 1NC/W Note_1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Note_2: The 48-pin TSSOP-EPR package has a top side exposed pad for enhanced thermal management. Connect this exposed pad to an external heatsink to ensure the device is adequately cooled. The maximum power dissipation in the device is a function of this external heatsink and other system parameters. See the Thermal Information section for more information. ELECTRICAL_CHARACTERISTICS (VPVDD = 14.4V, VDD = VDD5 = 5V, VGND = VPGND = 0V, fSW = 500kHz, MAP.COMP[2:0] = (see Table 20 for applicable setting), TA = -40NC to +125NC; typical values are at TA = +25NC, unless otherwise noted.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN 8 Operational 6 4.75 4.5 Falling Rising Rising OV active Falling Rising 0.1 IPVDD Quiescent Supply Current IVDD5 IVDD 2 RL = J, play mode (CTRL2 = 0x0F) 5.2 26 4 5 5 5.35 27 14 VPVDD/2 4.2 4.5 0.2 1 70 60 50 72 75 4.35 4.6 5.5 5.5 5.6 30 55 V V Fs V V V Fs FA mA TYP MAX 25.5 V UNITS AMPLIFIER_DC_CHARACTERISTICS VPVDD Supply Voltage Range VDD5 VDD PVDD UVLO Threshold PVDD OVLO Threshold PVDD OVLO Response Timing OUT_ and FB_ Voltage VDD UV Threshold VDD UV Threshold Hysteresis VDD UV Threshold Deglitch 4-Channel, Automotive Class D Audio Amplifier ELECTRICAL_CHARACTERISTICS_(continued) (VPVDD = 14.4V, VDD = VDD5 = 5V, VGND = VPGND = 0V, fSW = 500kHz, MAP.COMP[2:0] = (see Table 20 for applicable setting), TA = -40NC to +125NC; typical values are at TA = +25NC, unless otherwise noted.) (Note 3) PARAMETER PVDD Shutdown Supply Current VDD5 Shutdown Supply Current VDD Shutdown Supply Current Standby Supply Current Output Leakage Output Discharge Current RDS(ON) per Output FB_ Resistance Output Offset OUT_ Output Impedance AMPLIFIER_AC_CHARACTERISTICS THD+N = 1%, RL = 4I, VPVDD = 24V Output Power POUT THD+N = 10%, RL = 4I, VPVDD = 24V THD+N = 10%, RL = 2I, VPVDD = 24V, parallel mode 66 80 160 26 -1 IN0+, IN1+, IN2+, IN3+ INGuaranteed by design, test is functional only CTRL1.PRE = 1 VDD = 4.5V to 5.5V Power-Supply Rejection Ratio REF Voltage REF Output Impedance Input Voltage Range VPVDD = 1VP-P ripple, 100Hz to 10kHz VPVDD = 8V to 25.5V CREF(MIN) = 1µF DC AC-coupled ININ_+ 90 5 1 +0.1 20 5 100 10 2 70 60 68 2.224 800 1.2 V I VRMS dB +1 dB dB kI dB mA W VOS TA = +25NC, mute mode (CTRL2 = 0x00), no input signal TA = TMIN to TMAX 100 SYMBOL IPVDD_ SHDN MAX13301 CONDITIONS TA = +25NC, VEN = 0V TA = TMIN to +85NC, VEN = 0V TA = +25NC, VEN = 0V TA = TMIN to +85NC, VEN = 0V TA = +25NC, VEN = 0V TA = TMIN to +85NC, VEN = 0V CTRL2 = 0x20, VEN = 5V VOUT_ = 14.4V VOUT_ = 0V CTRL3.DIS = 1 Excluding wire bond resistance MIN TYP 7 MAX 17 UNITS FA FA FA mA IVDD5_ SHDN 0.1 2 0.1 2 1 10 200 1 8 70 310 15 100 IVDD_SHDN IVDD5 IVDD FA mA mI kI mV mI Signal-Path Gain Channel-to-Channel Gain Tracking Input Resistance Mute Attenuation Precharge Current 3 4-Channel, Automotive Class D Audio Amplifier MAX13301 ELECTRICAL_CHARACTERISTICS_(continued) (VPVDD = 14.4V, VDD = VDD5 = 5V, VGND = VPGND = 0V, fSW = 500kHz, MAP.COMP[2:0] = (see Table 20 for applicable setting), TA = -40NC to +125NC; typical values are at TA = +25NC, unless otherwise noted.) (Note 3) PARAMETER Total Harmonic Distortion Plus Noise SYMBOL CONDITIONS POUT = 10W, RL = 4I, BW = 22Hz to 20kHz AES17 filter, f = 1kHz POUT = 1W to 10W, RL = 4I, BW = 22Hz to 20kHz AES17 filter, f = 1kHz A-weighted, VPVDD = 24V Noise N 22Hz to 22kHz, VPVDD = 24V A-weighted, CTRL5.SS[2:0] = 110, SSEN = 1, VPVDD = 24V POUT_ = 4W, f = 1kHz to 10kHz E RL = 4I, POUT = 20W/channel, VDD5, VDD supplied from a switching power supply 6 to 15 clock-divider range 300 MIN TYP 0.04 0.1 100 140 100 60 88 dB % FVRMS MAX 0.14 % UNITS THD+N Crosstalk Efficiency Internal Switching Frequency Adjust Range ONE-TIME_DIAGNOSTICS Short-to-Ground Detection Short-to-PVDD Detection Threshold Open-Load Detection 750 kHz CTRL2.STBY = 0, CTRL3.SDET = 1 CTRL2.STBY = 1, CTRL3.SDET = 1 CTRL3.LDM = 1, power amplifier mode CTRL3.LDM = 0, line-driver mode 15kHz < f < 25kHz, TA = +25NC, CTRL3.TW = 1 f < 20Hz, CTRL3.TW = 0 CTRL3.HCL = 0 CTRL3.HCL = 1 CTRL3.HCL = 0 CTRL3.HCL = 1 70 200 160 200 0.65 0.9 75 6 100 300 291 364 1.15 1.65 500 625 1.85 2.15 I V I Low-Current Threshold mA High-Current Threshold CONTINUOUS_DIAGNOSTICS Differential Output Offset Voltage Threshold A No audio in play mode CTRL1.CLVL[1:0] = 11 CTRL1.CLVL[1:0] = 01 CTRL1.CLVL[1:0] = 10 CTRL1.CLVL[1:0] = 00 0.56 1.04 1 3 1.6 V Clip-Detect Threshold RL = 4I %THDN 5 10 4 4-Channel, Automotive Class D Audio Amplifier ELECTRICAL_CHARACTERISTICS_(continued) (VPVDD = 14.4V, VDD = VDD5 = 5V, VGND = VPGND = 0V, fSW = 500kHz, MAP.COMP[2:0] = (see Table 20 for applicable setting), TA = -40NC to +125NC; typical values are at TA = +25NC, unless otherwise noted.) (Note 3) PARAMETER SYMBOL CONDITIONS OUT__ shorted to ground/PVDD, CTRL1.CL_TH = 1 OUT__ shorted to ground/PVDD, CTRL1.CL_TH = 0 ILIM1 ILIM2 CTRL3.HCL = 0 CTRL3.HCL = 1 Guaranteed monotonic Guaranteed monotonic Guaranteed monotonic Guaranteed monotonic Guaranteed monotonic 150 15 fCP = fSW Guaranteed by FET RDS(ON) measurement 300 100 1.8 VPVDD + 5 2x switching frequency Spread-spectrum disabled CTRL1.CM[1:0] = 01, ISOURCE = 3mA CTRL1.CM[1:0] = 01, ISINK = 3mA VINH VINL 300 SDA, SCL, CL0, MUTE_CL1, FLT_OT SDA, CL0, MUTE_CL1, ISINK = 3mA, FLT_OT MUTE_CL1 EN 5 10 Q10 0.4 13 18 2.0 0.8 0.6 17.1 4.5 0.4 18 1.5 18.9 750 CTRL3.HCL = 0 CTRL3.HCL = 1 CTRL3.HCL = 0 CTRL3.HCL = 1 5.5 7 MIN TYP 1.03 1.28 3.09 3.86 7 8.75 110 120 130 140 165 5 A A NC NC NC NC NC NC NC kHz Fs I V MHz MHz V V V V mV FA V FA A MAX UNITS MAX13301 Short-to-Ground/PVDD Level 1 Output Current Limit Level 2 Output Current Limit THERMAL_PROTECTION Thermal Warning Range 1 Thermal Warning Range 2 Thermal Warning Range 3 Thermal Warning Range 4 Thermal Shutdown Level Thermal Warning Hysteresis Thermal Shutdown Hysteresis CHARGE_PUMP Switching Frequency Soft-Start Time Charge-Pump Output Impedance Output Voltage INTERNAL_OSCILLATOR SYNC I/O Frequency Range Frequency SYNC High SYNC Low Input Voltage High Input Voltage Low Input Voltage Hysteresis Input Leakage Current Output Low Voltage Pulldown Current DIGITAL_INTERFACE_(SCL,_SDA,_ADDR,_CL0,_MUTE_CL1,_EN,_SYNC,_FLT_OT) 5 4-Channel, Automotive Class D Audio Amplifier MAX13301 ELECTRICAL_CHARACTERISTICS_(continued) (VPVDD = 14.4V, VDD = VDD5 = 5V, VGND = VPGND = 0V, fSW = 500kHz, MAP.COMP[2:0] = (see Table 20 for applicable setting), TA = -40NC to +125NC; typical values are at TA = +25NC, unless otherwise noted.) (Note 3) PARAMETER I2C_TIMING Output Fall Time Pin Capacitance Clock Frequency SCL Low Time SCL High Time START Condition Hold Time START Condition Setup Time Data Hold Time Data Setup Time Input Rise Time Input Fall Time STOP Condition Setup Time Bus Free Time Maximum Bus Capacitance fSCL tLOW tHIGH tHD:STA tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tBUF CBUS Between START and STOP conditions Per bus line SCL, SDA SCL, SDA 0.6 1.3 400 Repeated START condition Repeated START condition 1.3 0.6 0.6 0.6 0 100 300 300 900 tOF CBUS = 10pF to 400pF 250 10 400 ns pF kHz Fs Fs Fs Fs ns ns ns ns Fs Fs pF SYMBOL CONDITIONS MIN TYP MAX UNITS Note_3: All units are 100% production tested at TA = +25NC. All temperature limits are guaranteed by design. 6 4-Channel, Automotive Class D Audio Amplifier Typical Operating Characteristics (VPVDD = 24V, VDD = VDD5 = 5V, VGND = VPGND = 0V, fSW = 500kHz, MAP.COMP[2:0] = 011, see Table 32 for LC filter value, TA = +25NC, unless otherwise noted.) THD+N vs. OUTPUT POWER MAX13301 toc01 MAX13301 THD+N vs. OUTPUT POWER f = 1kHz BW = 22Hz TO 20kHz AES17 PARALLEL MODE 1 THD+N (%) RL = 2I RL = 4I 0.1 MAX13301 toc02 EFFICIENCY vs. OUTPUT POWER PER CHANNEL 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 fIN = 1kHz 10% THD+N BW = 22Hz TO 20kHz AES17 0 10 20 30 40 50 60 70 80 90 100 OUTPUT POWER PER CHANNEL (W) RL = 2I RL = 4I 2-CHANNEL PARALLEL MODE RL = 1I MAX13301 toc03 10 f = 1kHz BW = 22Hz TO 20kHz AES17 RL = 4I 10 100 1 THD+N (%) 0.1 0.01 0 20 40 OUTPUT POWER (W) 60 80 0.01 0 20 40 60 80 100 120 140 160 OUTPUT POWER (W) 0 EFFICIENCY vs. OUTPUT POWER PER CHANNEL MAX13301 toc04 POWER DISSIPATION vs. OUTPUT POWER PER CHANNEL MAX13301 toc05 POWER DISSIPATION vs. OUTPUT POWER PER CHANNEL 45 POWER DISSIPATION (W) 40 35 30 25 20 15 10 5 0 0 10 20 30 fIN = 1kHz RL = 4I 10% THD+N BW = 22Hz TO 20kHz AES17 40 50 60 70 80 90 OUTPUT POWER PER CHANNEL (W) MAX13301 toc06 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 fIN = 1kHz RL = 4I 10% THD+N BW = 22Hz TO 20kHz AES1 40 35 POWER DISSIPATION (W) 30 25 20 15 10 5 0 RL = 2I fIN = 1kHz 10% THD+N BW = 22Hz TO 20kHz AES17 0 5 50 90 10 15 20 25 30 35 40 45 50 OUTPUT POWER PER CHANNEL (W) OUTPUT POWER PER CHANNEL (W) OUTPUT POWER vs. SUPPLY VOLTAGE MAX13301 toc07 CROSSTALK MAX13301 toc08 OUTPUT FREQUENCY SPECTRUM MUTE MODE RL = 4I MAX13301 toc09 100 OUTPUT POWER PER CHANNEL(W) 90 80 70 60 50 40 30 20 10 0 5 10 15 20 25 1% THD+N 10% THD+N RL = 4I fIN = 1kHz -40 -50 CROSSTALK (dB) -60 -70 -80 -90 OUT0 TO OUT1 -100 0.01 0.1 1 FREQUENCY (kHz) 10 OUT0 TO OUT3 OUT0 TO OUT2 POUT = 4W RL = 4I 0 -20 AMPLITUDE (dBV) -40 -60 -80 -100 -120 30 100 0 5 10 FREQUENCY (kHz) 15 20 VPVDD (V) 7 4-Channel, Automotive Class D Audio Amplifier MAX13301 Typical Operating Characteristics (continued) (VPVDD = 24V, VDD = VDD5 = 5V, VGND = VPGND = 0V, fSW = 500kHz, MAP.COMP[2:0] = 011, see Table 32 for LC filter value, TA = +25NC, unless otherwise noted.) FREQUENCY RESPONSE MAX13301 toc10 FIXED-FREQUENCY MODULATION WIDEBAND OUTPUT SPECTRUM -10 -20 AMPLITUDE (dBV) -30 -40 -50 -60 -70 -80 -90 100 0.1 1 10 100 2 RESPONSE (dB) 1 0 -1 -2 -3 0.01 0.1 1 FREQUENCY (kHz) 10 POUT = 30W RL = 2I C2 = 1µF POUT = 1W AND 10W RL = 4I MEASURED AT OUT__ WITH -20dB ATTENUATION FREQUENCY (MHz) SPREAD-SPECTRUM MODULATION WIDEBAND OUTPUT SPECTRUM MAX13301 toc12 SPREAD-SPECTRUM MODULATION WIDEBAND OUTPUT SPECTRUM -10 -20 AMPLITUDE (dBV) -30 -40 -50 -60 -70 -80 -90 -10 -20 AMPLITUDE (dBV) -30 -40 -50 -60 -70 -80 -90 0.1 1 CTRL5 = 0x09 MEASURED AT OUT__ WITH -20dB ATTENUATION CTRL5 = 0xB9 MEASURED AT OUT__ WITH -20dB ATTENUATION 10 100 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) 8 MAX13301 toc13 0 0 MAX13301 toc11 3 0 4-Channel, Automotive Class D Audio Amplifier Pin Configuration TOP VIEW PVDD 1 FB2+ 2 FB2- 3 FB3+ 4 FB3- 5 CL0 6 OUT3+ 7 OUT3- 8 PGND 9 PGND 10 PGND 11 PGND 12 OUT2+ 13 OUT2- 14 MUTE_CL1 15 IN- 16 GND 17 VDD 18 IN0+ 19 IN1+ 20 REF 21 IN2+ 22 IN3+ 23 PVDD 24 EPR MAX13301 + 48 PVDD 47 CP 46 CHOLD 45 CM 44 VDD5 43 PGND 42 OUT1+ 41 OUT140 PGND 39 PGND MAX13301 38 PGND 37 PGND 36 OUT0+ 35 OUT034 FLT_OT 33 FB0+ 32 FB031 FB1+ 30 FB129 SDA 28 SCL 27 EN 26 SYNC 25 PVDD TSSOP Pin Description PIN NAME FUNCTION Audio Output Power-Supply Input. Bypass each PVDD to its PGND pair locally with 0.1FF and 4.7FF ceramic capacitors. Each PVDD/PGND pair consists of one PVDD and two PGNDs. The PVDD/ PGND pairs are 1 and 9-10, 48 and 39-40, 24 and 11-12, and 25 and 37-38. Bypassing PVDD locally minimizes the area of di/dt loops. An additional 1000FF, low-ESR electrolytic capacitor should be placed from 1 and 48 to PGND and 24 and 25 to PGND. Output 2 Positive Feedback. Connect to the LC filter’s positive output through a 150I ±1% resistor. Output 2 Negative Feedback. Connect to the LC filter’s negative output through a 150I ±1% resistor. 9 1, 24, 25, 48 PVDD 2 3 FB2+ FB2- 4-Channel, Automotive Class D Audio Amplifier MAX13301 Pin Description (continued) PIN 4 5 6 7 8 9–12, 37–40, 43 13 14 NAME FB3+ FB3CL0 OUT3+ OUT3PGND OUT2+ OUT2FUNCTION Output 3 Positive Feedback. Connect to the LC filter’s positive output through a 150I ±1% resistor. Output 3 Negative Feedback. Connect to the LC filter’s negative output through a 150I ±1% resistor. Active-Low Open-Drain Clip 0 Output. CL0 is configurable to provide clipping indication for outputs 0 and 1 or for all four outputs. Channel 3 Power Amplifier Positive Output Channel 3 Power Amplifier Negative Output Audio Output Power Ground Channel 2 Power Amplifier Positive Output Channel 2 Power Amplifier Negative Output Mute Input or Active-Low Open-Drain Clip 1 Output. MUTE_CL1 is configurable as a mute input or as an open-drain clip indicator output. When configured as an input, drive MUTE_CL1 low to mute all four outputs. As an output, MUTE_CL1 provides clipping indication for outputs 2 and 3. This pin also selects the low bit of the I2C address and is latched upon the rising edge of the EN pin. MUTE_CL1 has an internal 5FA pulldown. Common Audio Negative Input. IN- has 5kI of input resistance. Bypass to analog ground with 2µF or 4 x CIN_+. Analog Ground 5V Analog Power-Supply Input. Bypass with a 2.2FF or larger ceramic capacitor to GND. VDD provides power to the analog and digital circuitry. Channel 0 Audio Input. IN0+ has 20kI of input resistance. Connect a series capacitor of at least 0.47FF to IN0+. Channel 1 Audio Input. IN1+ has 20kI of input resistance. Connect a series capacitor of at least 0.47FF to IN1+. 2.2V Reference Output. Bypass REF to GND with a 1FF ceramic capacitor. Channel 2 Audio Input. IN2+ has 20kI of input resistance. Connect a series capacitor of at least 0.47FF to IN2+. Channel 3 Audio Input. IN3+ has 20kI of input resistance. Connect a series capacitor of at least 0.47FF to IN3+. Sync I/O. In master mode, SYNC outputs a clock signal that is synchronized to that of the modulator. In slave mode, SYNC is a clock input and serves as the clock source for the modulator. Enable Input. Connect EN to VDD for normal operation. Connect EN to GND to place the device in a low-power mode. There is an internal 10µA pulldown on EN. I2C Serial-Clock Input I2C Serial-Data Input and Output Output 1 Negative Feedback. Connect to the LC filter’s negative output through a 150I ±1% resistor. Output 1 Positive Feedback. Connect to the LC filter’s positive output through a 150I ±1% resistor. Output 0 Negative Feedback. Connect to the LC filter’s negative output through a 150I ±1% resistor. Output 0 Positive Feedback. Connect to the LC filter’s positive output through a 150I ±1% resistor. 15 MUTE_CL1 16 17 18 19 20 21 22 23 26 27 28 29 30 31 32 33 INGND VDD IN0+ IN1+ REF IN2+ IN3+ SYNC EN SCL SDA FB1FB1+ FB0FB0+ 10 4-Channel, Automotive Class D Audio Amplifier MAX13301 Pin Description (continued) PIN 34 35 36 41 42 44 45 46 47 NAME FLT_OT OUT0OUT0+ OUT1OUT1+ VDD5 CM CHOLD CP FUNCTION Active-Low Open-Drain Fault and Overtemperature Output. FLT_OT provides indication of faults, overtemperature, and thermal shutdown status. Channel 0 Power Amplifier Negative Output Channel 0 Power Amplifier Positive Output Channel 1 Power Amplifier Negative Output Channel 1 Power Amplifier Positive Output 5V Power-Supply Input. Bypass with a 0.1FF capacitor to PGND. VDD5 provides power to the gate drivers and charge pump. Charge-Pump Capacitor Negative Terminal Charge-Pump Output. Connect a 1FF capacitor from CHOLD to PVDD. Charge-Pump Capacitor Positive Terminal Top Side Exposed Pad. Connect this exposed pad to an external heatsink to ensure the device is adequately cooled. The maximum power dissipation in the device is a function of this external heatsink and other system parameters. See the Thermal Information section for more information. The top side exposed pad is electrically isolated from the die. — EPR Functional Diagram VDD5 PGND IN_+ INVDD GND REF SCL SDA ANALOG MODULATOR AND DIAGNOSTICS FB3+ FB3PVDD VDD5 CLO MUTE_CL1 EN FLT_OT SYNC REGISTERS AND SYSTEM CONTROL GATE DRIVER 3 CLASS D OUTPUT STAGE 3 AND DIAGS OUT3+ OUT3PGND CP ANALOG AUDIO INTERFACE OSC VDD5 GATE DRIVER 0 CLASS D OUTPUT STAGE 0 AND DIAGS PVDD OUT0+ OUT0PGND FB0+ FB0- LPF FEEDBACK DIFF. AMP I2C CONTROL INTERFACE LPF FEEDBACK DIFF. AMP MAX13301 CHARGE PUMP CM CHOLD 11 4-Channel, Automotive Class D Audio Amplifier MAX13301 I2C COMP TRIANGLE WAVE OSC PWM LOGIC PWM COMPARATOR I2C COMP REF REF 3-BIT ADC FEEDFORWARD PVDD REF REF ERROR AMPLIFIER AUDIO IN REF PREAMPLIFIER Figure 1. Detailed Block Diagram of the MAX13301 Audio Path Detailed Description The MAX13301 4-channel, Class D audio power amplifiers is specifically designed for automotive applications. Integrated feedback from the LC filter’s output improves the THD+N by reducing the distortion, providing Class AB performance while achieving efficiency up to 90.5%. The devices also support spread-spectrum modulation for AM radio compatibility. The device emulates current-mode controllers with digital feed-forward (Figure 1). The internal oscillator creates an 18MHz square wave. The I2C controls a clock divider that divides down this high-frequency clock to a usable frequency. The resulting square wave is integrated to create 12 a triangle wave. A 3-bit ADC converts the PVDD voltage into a code that adjusts the resistors used in the trianglewave integrator. The triangle-wave amplitude becomes progressively larger as PVDD increases. The triangle wave is fed into the PWM comparator. The two differential amplifiers provide both analog and digital feedback. The feedback is summed with the output of the preamplifier at the error amplifier. The output of the error amplifier is an AC replica of the inductor current (emulated current mode) and the triangle wave is therefore the slope compensation. The PWM comparator controls the full-bridge operation, turning on and off each FET pair (double-edge modulation). To ensure that the devices switch at the desired frequency, it is important to ensure that the triangle wave is greater than the error- Description of Operation 4-Channel, Automotive Class D Audio Amplifier amplifier ramp. The design equation that must be met to ensure constant frequency is as follows: Error-Amplifier Ramp < 2/3 Triangle-Wave Ramp The error-amplifier ramp is fixed by the gain of the differential amplifiers used in the feedback loop and by the error-amplifier compensation capacitor programmed through I2C. To ensure the design equation for fixed frequency is met, the error-amplifier compensation capacitor tracks the integrator capacitor used to generate the triangle wave. For optimal noise shaping, the error-amplifier capacitor should be set to a small value. This results in a broadband spectrum where the error amplifier pushes the noise created by the clock jitter and PWM sampling above the audio range. However, there is a limit. Because the triangle-wave capacitor tracks the erroramplifier capacitor, small capacitor values can clip the triangle wave as it runs out of supply. This effect is aggravated at high PVDD voltages by the ADC action that decreases the integrator resistor at higher supply voltages. Tables 20 and 21 are lookup tables to facilitate choosing the optimal setting for the error-amplifier capacitance (MAP.COMP[2:0]). It is possible to change this setting instantaneously while playing music, but if there is no music, a slight audible click is heard at the speakers. Systems that monitor the input voltage can take advantage of this instantaneous programmability and use a smaller error-amplifier capacitor at lower PVDD voltages. Higher switching frequencies also allow the use of a smaller integrator capacitor, and thus help improve the noise performance of the amplifier. Do not set the error-amplifier capacitor to a value less than 18pF. Doing so results in extreme distortion, as the triangle wave clips. The MAP.COMP[2:0] settings that result in this behavior are listed as reserved (Table 19). High-fidelity audio amplifiers require very low output impedance. The device achieves this by using a dualfeedback approach. The digital feedback (feedback from OUT__ outputs) emulates current-mode enabling on chip compensation. The analog feedback (FB__ inputs) significantly reduces the output impedance of the amplifier and at the same time, compensates for the nonideal characteristics of the output filter. If the characteristics of the speaker and/or output filter change with age or temperature, the analog feedback compensates accordingly. Further inductor matching is less critical because the inductors are inside the feedback loop. Because the inductors are inside the feedback loop, the loop can dampen out any LC ringing that might occur when the amplifier is used as a line driver. The analog feedback is differential so it does not help with common-mode ringing. Thus, the Zobel (RC) networks are required on each speaker connection to damp any common-mode ringing associated with the LC output filter and speaker. Configure the device for one of three states of activity: normal, standby, or shutdown. Normal In normal mode, the device is ready for play. Placing the device in standby reduces power consumption while keeping fault monitors and the I2C interface on to communicate fault conditions. In shutdown, the device is completely disabled and draws minimal current from the battery. To reset the device and clear all register contents to their reset values, set CTRL5.RST to 1. After reset, this bit is automatically cleared back to 0. Standby In standby, all circuitry is disabled except the fault monitors and the I2C interface. The I2C registers retain their content and are still interactive. To place the device in standby, set the CTRL2.STBY bit to 1. In standby, the device draws 11mA from all power-supply inputs. Before exiting standby, always set the CTRL1.CL_TH (current-limit threshold setting) bit to 1. After exiting standby, clear CTRL1.CL_TH back to 0. MAX13301 Operating Modes Advantage of Feedback After the Filter Table_1._Operating_Modes MODE Normal Standby Shutdown X = Don’t care EN High High Low CTRL2.STBY 0 1 X I2C Enabled Enabled Off FAULT_MONITORS On On Off ALL_OTHER_CIRCUITRY On Off Off 13 4-Channel, Automotive Class D Audio Amplifier MAX13301 Shutdown In shutdown, all circuitry including the fault monitors and I2C interface is disabled to reduce power consumption and extend battery life. Connect EN to logic-high for normal operation. Connect EN to GND to place the device in a low-power shutdown mode. In shutdown, the devices draw 17mA (typ) from the battery. The device supports fixed-frequency modulation with an internal or external clock. The modulation mode is selected through CTRL1.CM[1:0] (operating mode select bits). Master Configuration In master mode, 10 modulation frequencies are available in fixed-frequency modulation mode. Program CTRL0.MDIV[3:0] (master clock-divide ratio bits) for the desired frequency. Slave Configuration Configuring the device as a slave allows an external clock source to provide the switching frequency. In this case, apply the external clock signal at SYNC at double the desired switching frequency. Fixed-Frequency Modulation Mode The devices supports a fixed-frequency modulation mode with 10 different selectable frequencies between 300kHz and 750kHz. The frequency is selectable through the I2C interface. The frequency spectrum consists of the fundamental switching frequency and its associated harmonics (see the wideband output spectrum graphs in the Typical Operating Characteristics). For applications where exact spectrum placement of the switching fundamental is important, program the switching frequency so that the harmonics do not fall within a sensitive frequency band. Spread Spectrum The device features a unique spread-sprectrum mode that flattens the wideband spectral components, improving EMI emissions that can be radiated by the speaker and cables. This feature is only available in master clock mode and is enabled by setting the CTRL5.SS[2:0] and CTRL5.SSEN bits. In spread-spectrum mode, the switching frequency vaies linearly by up to 7% depending on CTRL5.SS[2:0] setting. The modulation scheme remains the same, but the period of the triangle waveform changes from cycle to cycle. Instead of a large amount of spectral energy present at multiples of the switching frequency, the energy is now spread over a bandwidth that increases with frequency. Above a few megahertz, the wideband spectrum looks like white noise for EMI 14 purposes. A proprietary amplifier topology ensures this does not significantly increase the noise floor in the audio bandwidth. The high efficiency of a Class D amplifier is due to the switching operation of the output stage transistors. In a Class D amplifier, the output transistors act as currentsteering switches and consume negligible additional power. Any power loss associated with the Class D output stage is mostly due to the I2R loss of the MOSFET on-resistance and quiescent current overhead. The theoretical best efficiency of a linear amplifier is 78% at peak output power. Under normal operating levels (typical music reproduction levels), the efficiency falls below 30%, whereas the device exhibits > 80% efficiency under the same conditions (Figure 2). The current limit of the outputs is selectable between 7A (typ) and 8.75A (typ) through the CTRL3.HCL bit. Efficiency Clock Source Current Limit When the current limit is exceeded, the affected output is latched off and its corresponding overcurrent indicator bit OSTAT0.OC[3:0] is set to 0. The device does not attempt to activate the output until instructed by the microcontroller to do so. After eliminating the cause of the current limit, reactivate the output by setting OSTAT0.OC[3:0] to 1. Short to either ground or battery causes the output to be latched off and its corresponding OSTAT0.OC[3:0] bit to be set to 0. After removing the short, reactivate the output by setting OSTAT0.OC[3:0] to 1. MAX13301 EFFICIENCY vs. IDEAL CLASS AB AMPLIFIER EFFICIENCY 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 5 10 15 VPVDD = 14.4V RL = 4I 20 25 OUTPUT POWER PER CHANNEL (W) MAX13301 IDEAL CLASS AB AMPLIFIER Figure 2. Efficiency vs. Output Power of Class AB Amplifier and the MAX13301 4-Channel, Automotive Class D Audio Amplifier The device has real-time current limit for shorted outputs, outputs shorted to battery, outputs shorted to ground, and outputs shorted to adjacent channels. For shorted outputs, the devices enter cycle-by-cycle current limit. In a BTL configuration, current flows diagonally through two of the four FETs at any instant in time. If the current in either of these FETs reaches the current-limit threshold, then both turn off and the other pair of diagonal FETs turns on for a fixed time. This creates distortion, as the music clips. The internal logic of the device counts the cycle-by-cycle currentlimit events, and if too many happen in a fixed amount of time, the devices latch off the faulted channel. Current limit is programmable with the I2C. When CTRL3.HCL = 1, the peak current is limited to 8.75A (typ). With CTRL3.HCL = 0, peak current is limited to 7A (typ). Short-to-battery and short-to-ground take advantage of the diagonal flow of current in a full bridge to detect fault conditions. The load current during normal operation should be equal in the two diagonal FETs that are actively conducting current. When an output is shorted to battery or ground, the current is no longer equal and the degree of mismatch is a measure of the severity of the fault. If the mismatch threshold is exceeded in any channel, that channel is immediately shut down and an overcurrent fault is reported. The level of mismatch is programmable through I2C. When CTRL1.CL_TH = 0, the mismatch threshold is 3.09A with CTRL3.HCL = 0 and 3.86A with CTRL3.HCL = 1. When CTRL1.CL_TH = 1, the mismatch threshold is 1.03A with CTRL3.HCL = 0 and 1.28A with CTRL3.HCL = 1. The lower setting is preferred in that it can detect a misconfigured speaker. For example, the lower setting issues a fault if a 4I speaker is incorrectly connected between one of the outputs and ground. At startup, when a large snubber capacitor is present, the higher setting is sometimes required to avoid false trips. When the bridge starts switching, both snubber capacitors must be charged to half the battery. The charging current mimics a short to ground. Following the startup procedure is the best way to avoid issues with overcurrent faults. The device features a clickless/popless mute mode. When muted, the volume at the speaker is reduced to an inaudible level. To mute the device, configure MUTE_CL1 as a mute input by setting MAP.MCLP (clip output mapping bit) to 0. Then drive the mute input low. Use the mute function during system power-up and power-down to ensure optimum click-and-pop performance. It is also advisable to set CTRL1.PRE (precharge bit) to 1 after taking the device out of standby mode to precharge the input DC-blocking capacitors. This action should be part of any startup routine. Precharging the DC-blocking capacitors enhances click-and-pop performance. Capacitors that are 0.47µF/2µF in series with the inputs take about 1ms to be charged. The four FETs forming the full-bridge output of each channel can be programmed into one of four states: high-impedance (default), forced overvoltage, mute, and play through the CTRL2.MD01_[1:0] (channels 0 and 1 output mode) and CTRL2.MD23_[1:0] (channels 2 and 3 output mode) bits. Channels 0 and 1 and channels 2 and 3 always share the same configuration. In high-impedance mode, all four FETs are turned off. In forced overvoltage state, each half-bridge output is regulated to 1/2 VPVDD. In mute mode, the outputs continue to switch but the volume is kept to an inaudible level. In play mode, the FETs switch normally. The device features an 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the device and the master at clock rates up to 400kHz. When the device is used on an I2C bus with multiple devices, the VDD supply must stay powered on to ensure proper I2C bus operation. The master, typically a microcontroller, generates SCL and initiates data transfer on the bus. Figure 3 shows the 2-wire interface timing diagram. A master device communicates to the IC by transmitting the proper address followed by the data word. Each transmit sequence is framed by a START (S) or repeated START (Sr) condition, and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse. The SDA line operates as both an input and an opendrain output. A pullup resistor, greater than 500I, is required on the SDA bus. The SCL line operates as an input only. A pullup resistor, greater than 500I, is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an opendrain SCL output. Series resistors in line with SDA and SCL are optional. The SCL and SDA inputs suppress noise spikes to ensure proper device operation even on a noisy bus. I2C, MAX13301 Output Configuration I2C Interface Mute/Precharging 15 4-Channel, Automotive Class D Audio Amplifier MAX13301 SDA tSU:DAT tLOW SCL tHD:STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD:DAT tSU:STA tBUF tHD:STA tSP tSU:STO Figure 3. 2-Wire Serial-Interface Timing Diagram S SDA Sr P Early STOP Condition The device recognizes a STOP condition at any point during data transmission, except if the STOP condition occurs in the same high pulse as a START condition. Slave Address Each time the device is enabled, the state of the MUTE_CL1 input is latched and determines the device’s slave address. Table 2 shows the two possible hardware-defined slave addresses of the devices. Once the device is enabled, it is programmable to one of four I2C slave addresses through CTRL4.ADDR[1:0] (I2C slave address setting bits), as shown in Table 3. When initially setting the slave address, use the default slave address as discussed in the previous paragraph and shown in Table 2. After setting the slave address, set the CTRL5.ADDR_DEF (I2C slave address definition bit) to 1. For subsequent reads and writes, use the new softwaredefined address. These slave addresses are unique device IDs. The address is defined as the 7 most significant bits (MSBs) followed by the R/W bit. Set the R/W bit to 1 to configure the device to read mode. Set the R/W bit to 0 to configure the device to write mode. The address is the first byte of information sent to the device after the START condition. SCL Figure 4. START, STOP, and Repeated START Conditions Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). SDA and SCL idle high when the I2C bus is not busy. STOP and START Conditions A master device initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 4). A START condition from the master signals the beginning of a transmission to the device. The master terminates transmission and frees the bus by issuing a STOP condition. The bus remains active if a repeated START condition is generated instead of a STOP condition. 16 4-Channel, Automotive Class D Audio Amplifier Table_2._Default_Slave_Address MUTE_CL1 Low High A6 1 1 A5 1 1 A4 0 0 A3 1 1 A2 1 1 A1 0 0 A0 1 0 R/W X X WRITE 0xDA 0xD8 READ 0xDB 0xD9 MAX13301 Table_3._I2C_Programmable_Slave_Address CTRL4._ ADDR[1:0] 00 01 10 11 A6 1 1 1 1 A5 1 1 1 1 A4 0 0 0 0 A3 1 1 1 1 A2 1 1 1 1 A1 0 1 0 1 A0 0 0 1 1 R/W X X X X WRITE 0xD8 0xDC 0xDA 0xDE READ 0xD9 0xDD 0xDB 0xDF Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the device uses to handshake receipt each byte of data (Figure 5). The device pulls down SDA during the master-generated 9th clock pulse. The SDA line must remain stable and low during the high period of the acknowledge clock pulse. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master can reattempt communication. Write Data Format A write to the device includes transmission of a START condition, the slave address with the write bit set to 0, one byte of data to register address, one byte of data to the command register, and a STOP condition. Figure 6 illustrates the proper format for one frame. Read Data Format A read from the device includes transmission of a START condition, the slave address with the write bit set to 0, one byte of data to register address, restart condition, the slave address with read bit set to 1, one byte of data to the command register, and a STOP condition. Figure 6 illustrates the proper format for one frame. S SDA ACKNOWLEDGE SCL 1 2 8 9 Figure 5. Acknowledge Condition S SLAVE ADDRESS (WRITE ADDRESS) A REGISTER ADDRESS A DATA A P S SLAVE ADDRESS (WRITE ADDRESS) A REGISTER ADDRESS A Sr SLAVE ADDRESS (READ ADDRESS) A DATA NA P S = START CONDITION, A = ACKNOWLEDGE, NA = NOT ACKNOWLEDGE Sr = REPEATED START CONDITION, P = STOP CONDITION Figure 6. Data Format of I2C Interface Write Mode Read Mode 17 4-Channel, Automotive Class D Audio Amplifier MAX13301 Register Map Table_4._Register_Map REGISTER CTRL0 CTRL1 CTRL2 CTRL3 CTRL4 CTRL5 MAP STAT OSTAT0 OSTAT1 OSTAT2 OSTAT3 BIT_7 — — — TW — SSEN — OC3 LDOK3 SBAT3 — BIT_6 — CL_TH — RDET — RST OT OC2 LDOK2 SBAT2 — BIT_5 MDIV3 CLVL1 STBY SDET ADDR1 SS2 COMP0 OTW OC1 LDOK1 SBAT1 — BIT_4 MDIV2 CLVL0 — DIS ADDR0 SS1 OTWM OV OC0 LDOK0 SBAT0 VER BIT_3 MDIV1 — — — SS0 LCTM UV CLIP3 LOAD3 SGND3 VOS3 BIT_2 MDIV0 PRE HCL — PAR1 MCLP OC CLIP2 LOAD2 VOS2 BIT_1 TW1 CM1 — — PAR0 OTM CPUV CLIP1 LOAD1 VOS1 BIT_0 TW0 CM0 MD01_0 LDM — ADDR_DEF FLTM CLIP CLIP0 LOAD0 SGND0 VOS0 ADDRESS 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B R/W R/W R/W R/W R/W R/W R/W R/W R R R R R POWER-ON_ RESET_(POR) 0x24 0x00 0x20 0x00 0xC0 0x01 0x40 — — — — — MD23_1 MD23_0 MD01_1 COMP2 COMP1 SGND2 SGND1 Table_5._Control_Register_0 CTRL0 BIT_# NAME POR 7 — 0 6 — 0 5 MDIV3 1 4 MDIV2 0 3 MDIV1 0 2 MDIV0 1 1 TW1 0 0 TW0 0 Table_6._Control_Register_0_Bit_Description BIT BIT_DESCRIPTION Master Clock-Divide Ratio. In master mode, the modulation and charge-pump frequencies are each set to 4.5MHz/(MDIV[3:0]). The device is in standby mode for MDIV[3:0] ≤ 3. The valid operating frequencies are 750kHz, 642.9kHz, 562.5kHz, 500kHz, 450kHz, 409.1kHz, 375kHz, 346.2kHz, 321.4kHz, and 300kHz. Switching frequencies below 450kHz compromises noise, as a larger integrator and triangle-wave capacitor trim setting is required. In slave mode, the modulation and charge-pump frequency are always set to fSYNC/2, where fSYNC is the frequency of the clock signal applied to the SYNC input. Thermal Warning Threshold. This threshold determines the temperature at which the status bit STAT.OTW asserts. 00 = Junction temperature exceeds 110NC. 01 = Junction temperature exceeds 120NC. 10 = Junction temperature exceeds 130NC. 11 = Junction temperature exceeds 140NC. MDIV[3:0] TW[1:0] 18 4-Channel, Automotive Class D Audio Amplifier Table_7._Control_Register_1 CTRL1 BIT_# NAME POR 7 — 0 6 CL_TH 0 5 CLVL1 0 4 CLVL0 0 3 — 0 2 PRE 0 1 CM1 0 0 CM0 0 MAX13301 Table_8._Control_Register_1_Bit_Description BIT BIT_DESCRIPTION Selects the current threshold for the real-time short-to-ground and short-to-battery detection diagnostics. Set this bit to 0 before exiting high-Z mode to prevent false triggering of short-to-ground and short-to-battery faults during startup. Set this bit to 1 after the device has entered mute or play mode. 0 = High threshold 1 = Normal threshold Clip Level. The clip level provides an indication of the amount of total harmonic distortion in the output signal. 00 = THD exceeds 10% 10 = THD exceeds 5% 01 = THD exceeds 3% 11 = THD exceeds 1% Precharge. Use PRE to precharge the input DC-blocking capacitors. Set this bit to 1 as part of the startup procedure. A 2FF capacitor for IN- and 0.47FF input blocking capacitors require a 1ms precharge to avoid startup pop. 0 = Disable precharging 1 = Enable precharging Clock Mode. Before selecting the operating mode, three-state all outputs. 00 = Master fixed frequency, switching frequency set by the master clock-divide ratio (CTRL0.MDIV[3:0]) bits, SYNC output disabled 01 = Master fixed frequency, switching frequency set by the master clock-divide ratio (CTRL0.MDIV[3:0]) bits, SYNC output enabled 10 = Reserved 11 = Slave fixed frequency, SYNC input enabled CL_TH CLVL[1:0] PRE CM[1:0] 19 4-Channel, Automotive Class D Audio Amplifier MAX13301 Table_9._Control_Register_2 CTRL2 BIT_# NAME POR 7 — 0 6 — 0 5 STBY 1 4 — 0 3 MD23_1 0 2 MD23_0 0 1 MD01_1 0 0 MD01_0 0 Table_10._Control_Register_2_Bit_Description BIT BIT_DESCRIPTION Standby Mode. Wait 50ms after exiting standby mode to allow the charge pump and reference to stabilize before entering mute or play mode. 0 = Normal mode 1 = Standby mode. The charge pump, preamplifier, and modulator are disabled. Fault monitors and I2C are still active. Channels 2 and 3 Output Mode. Channels 2 and 3 are always in the same configuration. MD23_[1:0] determines the state of outputs 2 and 3. 00 = High-Z 01 = Mute 10 = Forced overvoltage. In this state, both differential outputs are charged to 1/2 VPVDD. 11 = Play Channels 0 and 1 Output Mode. Channels 0 and 1 are always in the same mode. MD01_[1:0] determines the state of outputs 0 and 1. 00 = High-Z 01 = Mute 10 = Force overvoltage. In this state, both differential outputs are charged to 1/2 VPVDD. 11 = Play STBY MD23_[1:0] MD01_[1:0] 20 4-Channel, Automotive Class D Audio Amplifier Table_11._Control_Register_3 CTRL3 BIT_# NAME POR 7 TW 0 6 RDET 0 5 SDET 0 4 DIS 0 3 — 0 2 HCL 0 1 — 0 0 LDM 0 MAX13301 Table_12._Control_Register_3_Bit_Description BIT BIT_DESCRIPTION Tweeter-Detect Current Threshold Setting 0 = The current threshold at which OSTAT1.LOAD[3:0] (load indicator bit) asserts is set equal to the shortedload current threshold (see the Electrical Characteristics table). Use this setting when running shorted-load diagnostic. 1 = The current threshold at which OSTAT1.LOAD[3:0] asserts is set equal to the tweeter detect current threshold. This threshold is approximately 25% of the default value to facilitate tweeter detection. Use this setting when the running tweeter diagnostic or for detecting the presence of a speaker. Open-Load Diagnostic Enable. Upon detecting an open load on any of the outputs, the corresponding OSTAT1.LDOK[3:0] (load OK indicator bit) asserts. Always perform short-to-ground and short-to-battery diagnosis before entering RDET mode. If a short-to-battery is detected, do not enter RDET mode. After performing the short-to-battery test, discharge both outputs by setting CTRL3.DIS to 1 for 200µs, then reset CTRL3.DIS back to 0. Failure to follow this procedure can result in a loud pop at the speaker. Because the results are not latched, read LDOK[3:0] before clearing RDET. Wait a minimum of 200µs before reading these status bits. RDET can only be set after three-stating all four outputs. When performing the open-load diagnostic, set the CTRL3.SDET (short-to-ground/battery enable) bit to 0. 0 = Disable open-load diagnostic 1 = Enable open-load diagnostic Short-to-Ground/Battery Diagnostic Enable. Upon detecting a short-to-ground or battery on any of the outputs, the corresponding OSTAT2.SBAT[3:0] (short-to-battery) and OSTAT2.SGND[3:0] (short-to-ground) bits assert. Because the results are not latched, read OSTAT2.SBAT[3:0] and OSTAT2.SGND[3:0] before clearing SDET. Wait a minimum of 200µs before reading these status bits. Before setting SDET to 1, three-state all four outputs and set the CTRL3.DIS (discharge output enable) bit to 1 and then reset back to 0. Before performing the short-to-ground/battery diagnostic, set the CTRL3.RDET (open-load diagnostic enable) bit to 0. To test for short-to-ground, set CTRL2.STBY to 0, and to test for short-to-battery, set CTRL2.STBY to 1. 0 = Disable short-to-ground/battery diagnostic 1 = Enable short-to-ground/battery diagnostic Discharge Output Enable. Set DIS to 1 to discharge all outputs with 15mA current sources. Use DIS to discharge all outputs before performing the short-to-ground/battery diagnostic (SDET) to avoid a loud pop on the speaker. DIS can only be set to 1 after three-stating all four outputs. 0 = Output discharge is disabled. 1 = Output discharge is enabled. Current-Limit Level. HCL sets the current-limit threshold of the outputs during normal operation. 0 = 7A (typ) current limit 1 = 8.75A (typ) current limit Line-Driver Mode. Use LDM to set the load resistance threshold required to assert the OSTAT1.LDOK[3:0] (load-okay indicator bit). Any load with a resistance greater than the threshold is interpreted as an open output. 0 = Line-driver mode, OSTAT1.LDOK[3:0] = 1 if RL > 300I 1 = Power amplifier mode, OSTAT1.LDOK[3:0] = 1 if RL > 100I 21 TW RDET SDET DIS HCL LDM 4-Channel, Automotive Class D Audio Amplifier MAX13301 Table_13._Control_Register_4 CTRL4 BIT_# NAME POR 7 — 1 6 — 1 5 ADDR1 0 4 ADDR0 0 3 — X 2 — X 1 — X 0 — X Table_14._Control_Register_4_Bit_Description BIT BIT_DESCRIPTION I2C Slave Address Setting. Use ADDR[1:0] to set the slave address of the device. After setting the slave address, set CTRL5.ADDR_DEF (I2C slave address definition bit) to 1 to make the new address effective. 00 = Slave address set to 1101100 R/W 01 = Slave address set to 1101110 R/W 10 = Slave address set to 1101101 R/W 11 = Slave address set to 1101111 R/W ADDR[1:0] 22 4-Channel, Automotive Class D Audio Amplifier Table_15._Control_Register_5 CTRL5 BIT_# NAME POR 7 SSEN 0 6 RST 0 5 SS2 0 4 SS1 0 3 SS0 0 2 PAR1 0 1 PAR0 0 0 ADDR_DEF 1 MAX13301 Table_16._Control_Register_5_Bit_Description BIT SSEN BIT_DESCRIPTION Spread-Spectrum Modulation Enable. 0: Spread-spectrum disabled; SSEN = 1 and SS[2:0] > 0: Spread-spectrum enabled Reset. Setting RST to 1 resets the device. In reset, all register bits are reset to their POR values. RST is automatically cleared back to 0 after device reset. 0 = Not in reset 1 = Reset Spread-Spectrum Modulation Control. Spread-spectrum modulation is enabled when SSEN = 1 and SS[2:0] > 0, once enabled the switching frequency varies from +2% to +7% (see Table 17). Parallel Mode. The four outputs can be paralleled in one of four ways. To parallel outputs, connect the positive outputs together and connect the negative outputs together. In parallel mode, only the feedback inputs corresponding to the slaved input IN0+ or IN2+ are used. Connect the other feedback inputs to ground. 00 = 4-channel output 01 = 2.1-channel output. Outputs 0 and 1 are paralleled and slaved to input IN0+. Channels 2 and 3 are unaffected. 10 = 2.1-channel output. Outputs 2 and 3 are paralleled and slaved to input IN2+. Channels 0 and 1 are unaffected. 11 = 2-channel output. Outputs 0 and 1 are paralleled and slaved to input IN0+. Outputs 2 and 3 are paralleled and slaved to input IN2+. I2C Slave Address Definition. This bit determines whether the I2C slave address is hardware or softwaredefined. 0 = Slave address is defined by CTRL4.ADDR[1:0] (I2C slave address setting bits). 1 = Slave address is set to the default address as defined by the state of the MUTE_CL1 input when the enable input EN is pulled high. RST SS[2:0] PAR[1:0] ADDR_DEF Table_17._Spread-Spectrum_Modulation_Table SSEN 0 1 1 1 1 1 1 1 1 SS2 X 0 0 0 0 1 1 1 1 SS1 X 0 0 1 1 0 0 1 1 SS0 X 0 1 0 1 0 1 0 1 SPREAD_(%) Disabled 0 2 3 4 5 6 7 Reserved 23 4-Channel, Automotive Class D Audio Amplifier MAX13301 Table_18._Mapping_Register MAP BIT_# NAME POR 7 COMP2 0 6 COMP1 1 5 COMP0 0 4 OTWM 0 3 LCTM 0 2 MCLP 0 1 OTM 0 0 FLTM 0 Table_19._Mapping_Register_Bit_Description BIT BIT_DESCRIPTION Integrator and Triangle-Wave Capacitor Trim. A smaller integrator capacitor pushes noise out of the audio band yielding the lowest noise. If distortion rises at high output powers, lower switching frequencies, or higher PVDD voltages then use a larger capacitor setting. See Table 20 for choosing minimum capacitor settings based on PVDD and the switching frequency. Larger capacitor values can be used. If all 4 channels of the amplifier are used to drive subwoofers, the capacitor settings can be relaxed because a smaller capacitor setting helps to eliminate high-frequency noise (greater than 10kHz). Systems with multiple tweeters benefit the most from proper COMP[2:0] selection. Lower switching frequencies are possible when this high-frequency noise is not a concern as with systems that lack tweeters. 000 001 010 011 100 101 110 111 = = = = = = = = 43pF 37pF 31pF 25pF 18pF Reserved Reserved Reserved COMP[2:0] OTWM Overtemperature Warning Mapping Bit 0 = STAT.OTW (overtemperature warning bit) is unmapped to the FLT_OT open-drain output. 1 = STAT.OTW is mapped to FLT_OT when MAP.OTM = 1. Low-Current Threshold Mapping Bit. The current thresholds used in tweeter and shorted load diagnostics are lower than the current limit. When the threshold is exceeded in running either diagnostic, OSTAT1.LOAD[3:0] (load indicator bit) asserts. Hardware indication is also possible by using LCTM to map OSTAT1.LOAD[3:0] to the CL0 and MUTE_CL1 outputs. 0 = OSTAT1.LOAD[3:0] (load indicator bit used for tweeter and shorted load diagnostics) is unmapped to the CL0 and MUTE_CL1 outputs. 1 = OSTAT1.LOAD[3:0] is mapped to the CL0 and MUTE_CL1 outputs. Use this setting only when running tweeter or shorted load diagnostic. Clip Output Mapping. MCLP determines which open-drain outputs (CL0 and MUTE_CL1) are used to indicate clipping on an audio output. CL0 is always used as a clip indicator, while MUTE_CL1 is configurable as a clip indicator output or as a mute input. 0 = CL0 provides clip indication for all audio outputs; MUTE_CL1 is configured as a mute input. 1 = CL0 provides clip indication for audio outputs 0 and 1; MUTE_CL1 is configured as a clip indicator output for audio outputs 2 and 3. Overtemperature Shutdown Map 0 = STAT.OT (overtemperature shutdown bit) is unmapped to the open-drain FLT_OT output. 1 = STAT.OT is mapped to the FLT_OT output. Fault Mapping Bit 0 = Faults are unmapped to the open-drain FLT_OT output. 1 = Any fault condition (as indicated by the status bits OV, UV, OC) causes FLT_OT to assert low. LCTM MCLP OTM FLTM 24 4-Channel, Automotive Class D Audio Amplifier Table_20._COMP[2:0]_Setting_Lookup_Table fSW/VPVDD 300k 320k 346k 375k 409k 450k 475k 500k 530k 562k 600k 643k 675k 700k 725k 750k _21.1V 001 010 010 010 011 011 011 011 011 100 100 100 100 100 100 100 MAX13301 Table_21._Status_Register STAT BIT_# NAME 7 — 6 OT 5 OTW 4 OV 3 UV 2 OC 1 CPUV 0 CLIP Table_22._Status_Register_Bit_Description BIT OT BIT_DESCRIPTION Overtemperature Shutdown. The device goes into thermal shutdown when the junction temperature exceeds +150NC. 0 = Device is in thermal shutdown. 1 = Device is not in thermal shutdown. Overtemperature Warning. OTW asserts when the junction temperature exceeds the thermal warning threshold programmed in CTRL0.TW[1:0]. 0 = Junction temperature is greater than the programmed thermal warning threshold. 1 = Junction temperature is less than the programmed thermal warning threshold. Overvoltage Indicator 0 = VPVDD is greater than the PVDD overvoltage lockout (OVLO) threshold as defined in the Electrical Characteristics table. 1 = VPVDD is less than the OVLO threshold. Undervoltage Indicator 0 = VPVDD is less than the PVDD undervoltage lockout (UVLO) threshold as defined in the Electrical Characteristics table. 1 = VPVDD is greater than the UVLO threshold. OTW OV UV 25 4-Channel, Automotive Class D Audio Amplifier MAX13301 Table_22._Status_Register_Bit_Description_(continued) BIT BIT_DESCRIPTION General Overcurrent Indicator. OC asserts when there is an overcurrent condition on any of the outputs such as a short-to-ground/battery. To identify which output(s) is experiencing an overcurrent condition, read the OSTAT0.OC[3:0] (overcurrent indicator bit). 0 = An overcurrent condition exists on one or more of the outputs. 1 = No overcurrent condition. Charge-Pump Undervoltage Indicator. CPUV asserts when the voltage on the hold capacitor of the charge pump (CHOLD) falls below 3.87V. It deasserts once the voltage rises above 4.1V. 0 = Undervoltage on CHOLD 1 = Adequate voltage on CHOLD General Clip Indicator. CLIP asserts when any of the outputs is clipping. To identify which output(s) is clipping, read the OSTAT0.CLIP[3:0] (clip indicator) bits. 0 = One or more outputs are clipping. 1 = None of the outputs are clipping. OC CPUV CLIP Table_23._Status_Register_0 OSTAT0 BIT_# NAME 7 OC3 6 OC2 5 OC1 4 OC0 3 CLIP3 2 CLIP2 1 CLIP1 0 CLIP0 Table_24._Status_Register_0_Bit_Description BIT BIT_DESCRIPTION Overcurrent Indicator. An overcurrent condition such as a short-to-ground/battery on any of the outputs causes the corresponding OC[3:0] bit to latch to 0. Write a 1 to this bit to clear it. Reset also clears this bit. An overcurrent indicator is available for each output: OC3 is for output 3, OC2 is for output 2, etc. 0 = There is an overcurrent condition on the output. 1 = There is no overcurrent condition on the output. Clip Indicator. CLIP[3:0] is a real-time clip indicator for each output. This bit asserts only during the times when an overdriven output is actually clipping. A clip indictor is available for each output: CLIP3 is for output 3, CLIP2 is for output 2, etc. 0 = Output is clipping. 1 = Output is not clipping. OC[3:0] CLIP[3:0] 26 4-Channel, Automotive Class D Audio Amplifier Table_25._Status_Register_1 OSTAT1 BIT_# NAME 7 LDOK3 6 LDOK2 5 LDOK1 4 LDOK0 3 LOAD3 2 LOAD2 1 LOAD1 0 LOAD0 MAX13301 Table_26._Status_Register_1_Bit_Description BIT BIT_DESCRIPTION Load Okay Indicator. When running the open-load diagnostic, LDOK[3:0] = 1 if the load resistance is greater than the resistance threshold set by CTRL3.LDM (line driver mode bit), indicating that the output is properly loaded and not open. A load okay indicator is available for each output: LDOK3 is for output 3, LDOK2 is for output 2, etc. 0 = Output is loaded. 1 = Output is open. Load Indicator. When running shorted load or tweeter diagnostic, LOAD[3:0] asserts if there is a short across the load or if a tweeter is connected. See the Shorted-Load Diagnostic and Tweeter Diagnostic sections for information on the use of LOAD[3:0] in performing load diagnostics. LOAD[3:0] is available for each output: LOAD3 is for output 3, LOAD2 is for output 2, etc. 0 = Load threshold exceeded. 1 = Load threshold not exceeded. LDOK[3:0] LOAD[3:0] Table_27._Status_Register_2 OSTAT2 BIT_# NAME 7 SBAT3 6 SBAT2 5 SBAT1 4 SBAT0 3 SGND3 2 SGND2 1 SGND1 0 SGND0 Table_28._Status_Register_2_Bit_Description BIT BIT_DESCRIPTION Short-to-Battery Indicator. When running a short-to-ground/battery diagnostic, SBAT[3:0] provides indication of any short-to-battery for each output. Use SBAT[3:0] to ensure that there is no short-to-battery before turning on the device. This indicator is available for each output: SBAT3 is for output 3, SBAT2 is for output 2, etc. 0 = Output is shorted to the battery. 1 = Output is not shorted to the battery. Short-to-Ground Indicator. When running a short-to-ground/battery diagnostic, SGND[3:0] provides indication of any short-to-ground for each output. Use SGND[3:0] to ensure that there is no short-to-ground before turning on the device. This indicator is available for each output: SGND3 is for output 3, SGND2 is for output 2, etc. 0 = Output is shorted to ground. 1 = Output is not shorted to ground. SBAT[3:0] SGND[3:0] 27 4-Channel, Automotive Class D Audio Amplifier MAX13301 Table_29._Status_Register_3 OSTAT3 BIT_# NAME 7 — 6 — 5 — 4 VER 3 VOS3 2 VOS2 1 VOS1 0 VOS0 Table_30._Status_Register_3_Bit_Description BIT VER Version Indicator. 0 = Reserved 1 = MAX13301 Offset Voltage Indicator. VOS[3:0] indicates whether an offset voltage exists between the differential outputs. Read this bit in play mode after precharge with no signal on the input. This bit is not latched and is not a valid indicator of offset when an input signal is present. An offset voltage indicator is available for each output: VOS3 is for output 3, VOS2 is for output 2, etc. 0 = The differential offset voltage between OUT_+ and OUT_- exceeds Q1V (typ). 1 = The differential offset voltage between OUT_+ and OUT_- is within Q1V (typ). BIT_DESCRIPTION VOS[3:0] Table_31._Fault_Conditions FAULT Overvoltage Undervoltage (PVDD) Charge-Pump Undervoltage Overtemperature Shutdown Overtemperature Warning Open Load Shorted Load Short-to-Ground/Battery Clip Output Overcurrent DC Offset MONITORING_STATE All Normal, Standby Normal Normal, Standby Normal Normal Normal Normal Normal Normal Normal, No Music REPORTING_METHOD I2C, FLT_OT I2C, FLT_OT I2C I2C, FLT_OT I2C, FLT_OT I2C I2C I2C, FLT_OT I2C, CL0, MUTE_CL1 I2C, FLT_OT I2C ACTION OUT_ to 1/2 VPVDD High-Z All High-Z All High-Z All None None High-Z Channel High-Z Channel None High-Z Channel None LATCHED No No No No No No Yes Yes No Yes No The device integrates fault detection and protection circuitry. Table 31 lists all fault events that each device can encounter, the modes in which they are detected, the method with which they are reported, the devices' response to them, and whether they cause the outputs to latch into a high-impedance state. The device incorporates built-in diagnostics to detect external wire harness faults that can occur during installation or over time. Load diagnostics include short circuit to ground or battery, shorted or open speaker, and open tweeter. Load diagnostics can be run at any time 28 Fault Detection when the device is in normal mode (i.e., not in standby mode) with the outputs three-stated. The presence of any of these faults is indicated by software through the status registers and by hardware through the CL0 and MUTE_CL1 open-drain outputs if the status bits have been mapped to the outputs. Short-to-Ground/Battery Diagnostic The diagnostic for short-to-battery and ground is done with CTRL3.SDET = 1. None of the results are latched so the OSTAT2 register must be read while running this diagnostic to get a valid status. If the load is present, a short on either of the differential outputs results in a short on the other output. Therefore, Load Diagnostics 4-Channel, Automotive Class D Audio Amplifier the status register only indicates which channel’s output is shorted and not which of its differential outputs is shorted. The I2C status register can indicate, for example, that output 1 is shorted to battery, but it cannot differentiate between an OUT1+ and OUT1- short-to-battery. Before running the short-to-ground/battery diagnostic, perform steps 1 to 3 of the shutdown procedure outlined in the Startup and Shutdown section. Before setting CTRL3.SDET to 1, discharge the output by setting CTRL3.DIS to 1 for 200µs and reset CTRL3.DIS to 0. Run the short-to-ground/battery diagnostic by setting CTRL3.SDET (short-to-ground/battery diagnostic enable bit) to 1. To test for short-to-ground, set CTRL2.STBY to 0; to test short-to-battery, set CTRL2.STBY to 1. With CTRL2.STBY = 0, 6V is developed at each output. An output voltage >_ 6V is interpreted as a short-to-battery. An output voltage < 150mV is interpreted as a short to ground. Results of the diagnostic are reported in the OSTAT2.SBAT[3:0] (short-to-battery indicator) and OSTAT2.SGND[3:0] (short-to-ground indicator) bits. Wait a minimum of 200Fs after setting CTRL3.SDET for valid results. After running the short-toground/battery diagnostic, clear the CTRL3.SDET bit to 0. Because no latch is set, a short-to-ground or battery does not prevent the device from powering up. Therefore, the microcontroller can enable the device into a short although it is discouraged. Should the device be enabled into a short, the real-time overcurrent latches the shorted channel off. The device offers real-time protection for short-to-battery, short-to-ground, and shorted load to prevent damage to the device. Open-Load Diagnostic This diagnostic detects an open between OUT_+ and OUT_- of > 100I or > 300I, depending on the value of CTRL3.LDM (line driver mode bit). Before running the open-load diagnostic, perform steps 1 to 3 of the shutdown procedure outlined in the Startup and Shutdown section. Run the open-load diagnostic test by setting CTRL3.RDET (open-load diagnostic enable bit) to 1, and in the same command, discharge the output capacitors by setting CTRL3.DIS (discharge bit) to 1. During the diagnostic, all low-side FETs of the negative outputs (OUT_-) are turned on, while all other FETs are turned off. The device sources a 2mA current from OUT_+ to OUT_-. If a load is not present, OUT_+ swings high and is interpreted as an open output. Results of the diagnostic are reported in OSTAT1.LDOK[3:0] (load OK indicator bit). Wait a minimum of 200Fs for valid results after setting CTRL3.RDET. After running the open-load diagnostic, clear CTRL3.RDET and CTRL3.DIS to 0. Shorted-Load Diagnostic This diagnostic detects shorted loads on any of the outputs. To detect shorted loads, the device should be in play mode. Set CTRL3.TW (tweeter-detect current threshold setting bit) to 0 and apply a low-frequency (typically < 20Hz) sinusoidal signal to all the inputs. The device compares the load current to the shortedload current threshold. If the load current exceeds the threshold, the corresponding OSTAT1.LOAD[3:0] (load indicator bit) is set to 1, indicating that there is a shorted load. The shorted-load current threshold depends on the programmed current limit as set by the CTRL3.HCL. See the High-Current Threshold parameter in the Electrical Characteristics table. Note that the OSTAT1.LOAD[3:0] bits do not latch high upon detecting a short. During zero crossings, the load current does not exceed the threshold and the OSTAT1.LOAD[3:0] bits are cleared to 0. There are two ways to obtain the results of the shorted load diagnostic: 1) Continuously read the OSTAT1.LOAD[3:0] bits to determine if any have been set high. 2) The open-drain CL0 output can also be monitored if MAP.LCTM (low-current threshold map bit) is set to 1 (setting this bit to 1 maps the OSTAT1.LOAD[3:0] bits to the CL0 output). Because CL0 is the NORed function of the OSTAT1.LOAD[3:0] bits, CL0 pulls low if a short exists on any of the outputs. After running the diagnostic, clear MAP.LCTM to 0 to unmap OSTAT1.LOAD[3:0] to the CL0 output. Doing so prevents CL0 from being asserted when the shortedload current threshold is exceeded during play. Shorted-load diagnostic is done on all outputs. A shorted load is traceable to the output on which it exists by examining the OSTAT1.LOAD[3:0] bits. A shorted load on output 3 causes LOAD3 to go low, a shorted load on output 2 causes LOAD2 to go low, etc. Using the same technique outlined above, it is possible to detect the absence of a speaker. Set CTRL3.TW to 1 to decrease the shorted-load current threshold by a factor of 4. Apply a low-frequency sine wave (< 20Hz) to the inputs and monitor the load indicator either through the I2C registers or the CL0 output. By using the appropriate input signal, a 2I, 4I, or 8I speaker can be detected. MAX13301 Missing Speaker Diagnostic 29 4-Channel, Automotive Class D Audio Amplifier Tweeter Diagnostic This diagnostic detects whether a tweeter is properly connected when a passive crossover is used. To detect the presence of a tweeter load, the device should be in play mode. Set CTRL3.TW (tweeter-detect current threshold setting bit) to 1 and apply a 15kHz to 25kHz sinusoidal signal to all the inputs. The devices compare the load current to the tweeter-detect current threshold. If the load current exceeds the threshold, the corresponding OSTAT1.LOAD[3:0] (load indicator bit) is set to 1, indicating that there is a tweeter. The amplitude of the input signal depends on the impedance vs. frequency characteristics of the tweeter. Correct tweeter detection requires that the amplitude be large enough to trip the tweeter-detect current threshold when a tweeter is present. The tweeter-detect current threshold depends on the programmed current limit as set by CTRL3.HCL bit. See the Low-Current Threshold parameter in the Electrical Characteristics table. Note that the OSTAT1.LOAD[3:0] bits do not latch high upon detecting a tweeter. During zero crossings, the load current does not exceed the threshold and the OSTAT1.LOAD[3:0] bits are cleared to 0. There are two ways to obtain the results of the tweeter diagnostic: 1) Continuously read the OSTAT1.LOAD[3:0] bits to determine if any have been set high. 2) The open-drain CL0 output can also be monitored if MAP.LCTM (low-current threshold map bit) is set to 1 (setting this bit to 1 maps OSTAT1.LOAD[3:0] to the CL0 output). Because CL0 is the NORed function of the OSTAT1.LOAD[3:0] bits, CL0 pulls low if a short exists on any of the outputs. After running the diagnostic, clear CTRL3.TW to 0 to disable tweeter diagnostic and clear MAP.LCTM to 0 to unmap the OSTAT1.LOAD[3:0] bits to the CL0 output. Doing so prevents CL0 from being asserted when the tweeter-detect current threshold is exceeded during play. Tweeter diagnostic is done on all outputs. The presence of a tweeter is traceable to any output by examining the OSTAT1.LOAD[3:0] bits. The presence of a tweeter on output 3 causes LOAD3 to go high, the presence of a tweeter on output 2 causes LOAD2 to go high, etc. The device constantly monitors critical performance and safety parameters such as output offset voltages, output clipping, thermal faults, and undervoltage and overvoltage conditions. The results are reported and continuously updated in the status registers (STAT and OSTAT[3:0]). 30 MAX13301 Offset Diagnostic Run the offset diagnostic to determine if there is an offset between the differential outputs. To do so, place the device in play mode and apply no input signals. The results of this diagnostic are reported in OSTAT3.VOS[3:0] (offset voltage indicator bits). OSTAT3.VOS[3:0] indicates whether the offset voltage is less than or greater than the offset voltage threshold. The differential offset threshold is Q1V (typ) for the MAX13301. Clipping Diagnostic Use the clipping diagnostic to detect clipping outputs. Program CTRL1.CLVL[1:0] (clip level bit) for a threshold of either 1%, 3%, 5%, or 10% THD+N. Clip indication is provided by OSTAT0.CLIP[3:0] (clip indicator bit). These bits are set to 0 only during the times when an overdriven output is actually clipping. A clipping output indicator is available for each output: CLIP3 is for output 3, CLIP2 is for output 2, etc. The open-drain outputs, CL0 and MUTE_CL1, also provide clip indication. Thermal Warning Diagnostic and Thermal Shutdown If the junction temperature exceeds the programmed temperature limit, then a temperature warning is set immediately (i.e., STAT.OTW goes low). The device does not act upon a temperature fault to the programmed limit. The temperature fault self clears when the temperature drops below the threshold. The programmed temperature limit is set by CTRL0.TW[1:0] (thermal warning threshold bits) from +110NC to +140NC in 10NC increments. Overtemperature warning by the hardware is also possible by setting both the MAP.OTWM (overtemperature warning map) and MAP.OTM (overtemperature shutdown mask) to 1 to map the STAT.OTW (overtemperature warning) bit to the FLT_OT output. If the junction temperature exceeds +150NC, the device disables all channels and the STAT.OT (overtemperature shutdown) bit asserts low. The digital interface remains active and the contents of the registers are unchanged. When the die temperature drops below +140NC, normal operation is restored. Thermal shutdown indication by hardware is also possible by setting MAP.OTM (overtemperature shutdown map bit) to 1 to map the STAT.OT (overtemperature shutdown bit) to the FLT_OT output. Charge-Pump Undervoltage Diagnostic The device drives the high-side FETs with the aid of a charge pump. The charge pump charges the hold capacitor CHOLD to 5V at the end of each switching cycle. When the voltage on CHOLD falls below 3.87V, the devices assert STAT.CPUV (charge-pump undervoltage indicator bit) and three-state all outputs. The Continuous Diagnostics 4-Channel, Automotive Class D Audio Amplifier device deasserts the bit only after the voltage on the hold capacitor rises above 4.1V. Undervoltage Diagnostic An undervoltage monitor detects low voltages on PVDD (< 6V). During an undervoltage condition, the devices three-state all outputs, set the STAT.UV (undervoltage indicator) bit to 0, and assert the open-drain output FLT_OT. Overvoltage Diagnostic The device detects overvoltage and load-dump conditions on PVDD and protect the DMOS outputs from damage. During an overvoltage condition, the devices set STAT.OV (overvoltage indicator bit) to 0, assert the open-drain output FLT_OT, and are latched into standby mode. All differential outputs are regulated to 1/2 VPVDD to minimize the drain-source voltage of the low- and high-side FETs. Once the overvoltage condition is removed, bring the devices out of standby mode by clearing CTRL2.STBY (standby bit). The device can withstand 50V load-dump voltage spikes. Battery charger voltages from 26V to 35V can be withstood for up to 1 hour. Figure 7 illustrates the behavior of the device during a load dump. Faults discovered during load diagnostic and continuous diagnostic are indicated through software and hardware. The appropriate status indicator bits (found in the STAT and OSTAT[3:0] registers) assert upon detection of a fault. The host is made aware of the fault through the fault indicator outputs—CL0, MUTE_CL1, and FLT_OT. The host then reads the appropriate status registers to determine which specific fault has occurred. CL0, MUTE_CL1 CL0 is an open-drain output that indicates clipping on the audio outputs. MUTE_CL1 can be configured as an open-drain output that also indicates clipping on the audio outputs. CL0 also finds use in shorted load and tweeter diagnostics. FLT_OT The device asserts the FLT_OT open-drain output upon detecting a fault. A fault is any of the following events: overvoltage, undervoltage, temperature exceeds the programmed overtemperature warning threshold, overtemperature shutdown, and overcurrent. Fault Indication MAX13301 VPVDD 50V 200ms MAX MAX RAMP RATE 25V/ms OVERVOLTAGE PROTECTION UP TO 50V STANDBY MODE HIGH-Z ALL CHANNELS 28.8V 26V READY TO EXIT STANDBY MODE 14.4V OPERATING RANGE 6V TO 25.5V TIME Figure 7. Behavior During Load Dump 31 4-Channel, Automotive Class D Audio Amplifier MAX13301 Fault Mapping The MAP register contains the compensation capacitor, clip output mapping, overtemperature mapping, lowcurrent threshold mapping, and fault mapping bits. The MAP.COMP[2:0] bits set the internal integrator and triangle-wave capacitor. The value of MAP.MCLP (clip output mapping bit) determines whether MUTE_CL1 is a mute input or clip indicator output. MAP.OTWM and MAP.OTM map the overtemperature warning bit STAT.OTW and overtemperature shutdown bit STAT.OT to the FLT_OT output. MAP.LCTM enables the low-current threshold mapping when running tweeter and shorted load diagnositics. The fault map is enabled by setting MAP.FLTM to 1, this maps the status register bits STAT.OV, STAT.UV, and STAT.OC to the FLT_OT output. 12) Set CTRL2.MD23_[1:0] = CTRL2.MD01_[1:0] = 11 to set the outputs to play mode. For shutdown: 1) Set CTRL2.MD23_[1:0] = CTRL2.MD01_[1:0] = 01 to mute the outputs. 2) Wait at least 25ms to ensure that there is no click-andpop noise from a 20Hz signal. 3) Set CTRL2.MD23_[1:0] = CTRL2.MD01_[1:0] = 00 to three-state the output. 4) Set CTRL2.STBY = 1 to go into standby mode. 5) Pull the enable input EN low. Before running open-load diagnostic or short-to-ground/ battery diagnostic, follow steps 1 to 3 of the shutdown procedure to prevent click-and-pop noise. Class D amplifiers differ from analog amplifiers such as Class AB in that their output waveform is composed of high-frequency pulses from ground to the supply rail. When viewed with an oscilloscope, the audio signal is not seen; instead, the high-frequency pulses dominate. To evaluate the output of a Class D amplifier requires taking the difference from the positive and negative outputs, then lowpass filtering the difference to recover the amplified audio signal. The gain for all 4 channels on the device is fixed at 26dB. The device offers flexible output configurations for either 4-channel, 2.1 or high-power, 2-channel sound systems. The configurations are selected using CTRL5.PAR[1:0] (parallel mode bit). In a 2.1 configuration, either outputs 0 and 1 are paralleled together and slaved to input 0, or outputs 2 and 3 are paralleled together and slaved to input 2. In a high-power, 2-channel configuration, outputs 0 and 1 are paralleled and slaved to input 0, while outputs 2 and 3 are paralleled and slaved to input 2. See the Control Register 5 Bit Description table (Table 16) for more information about programming the desired output configuration. Connect the speaker inputs to the feedback inputs through 150I Q1% resistors as shown in the Typical Operating Circuit. Integrated feedback from the LC filter’s output improves the THD+N by reducing distortion. Applications Information Follow these procedures for starting up and shutting down the device. For startup: 1) Set the state of MUTE_CL1 to select the I2C slave address (see Table 2). 2) Pull the enable input EN high. 3) Release MUTE_CL1. 4) If more than two I2C addresses are needed, then write to CTRL4.ADDR[1:0] to set the new address. The new address can be set to one of the four addresses shown in Table 3. 5) Write CTRL5.ADDR_DEF = 0 to enable the new address, if more than two I2C addresses are needed. 6) Set CTRL0, CTRL1.CLVL[1:0], CTRL1.CM[1:0], CTRL3.HCL, CTRL3.LDM, CTRL4, and CTRL5 to the desired values based on application requirements. 7) Set CTRL1.CL_TH = 1. 8) Set CTRL2.STBY = 0 to enable the device. 9) Wait 50ms for the charge pump and reference to stabilize. 10) Set CTRL2.MD23_[1:0] = CTRL2.MD01_[1:0] = 01 to mute the outputs. Delay at least 50Fs before proceeding. 11) Wait 200Fs and then clear CTRL1.CL_TH back to 0. Class D Operation Startup and Shutdown Gain Output Configuration Feedback 32 4-Channel, Automotive Class D Audio Amplifier The Class D amplifiers work with external filters. The filter requirement is due to the unshielded wiring harness. This is common for longer speaker lead lengths, and to gain increased margin to EMC limits. See Figure 8 for the correct connections of these components. The component selection is based on the load impedance of the speaker. Table 32 lists suggested values for a variety of load impedances. Inductors L1 and L2 and capacitor C2 form the primary output filter. In addition to these primary filter components, other components in the filter improve its functionality. RC networks R1-C4 and R2-C5 form Zobels at the output. A Zobel corrects the output loading to compensate for the rising impedance of the loudspeaker. Without a Zobel, the filter has a peak in its response near the cutoff frequency. Capacitors C1 and C3 provide additional high-frequency bypass to reduce radiated emissions. The devices use different supplies for each portion of the device, allowing for the optimum combination of headroom, power dissipation, and noise immunity. The C4 24V C1 MAX13301 External Filters speaker amplifiers are powered from PVDD and can range from 6V to 25.5V. The remainder of the device is powered by VDD (analog and digital blocks) and VDD5 (gate drivers and charge-pump circuit). Power supplies are independent of each other so sequencing is not necessary. Power can be supplied by separate sources or derived from a single higher source using a linear regulator to reduce the voltage, as shown in Figure 9. MAX13301 Component Selection Input Filter The device has four positive inputs and one common negative input. The input resistance of each positive input is 20kI, while the input resistance of the negative input is 5kI. An input capacitor, CIN, in conjunction with the input resistance forms a highpass filter that removes the DC bias from an incoming signal. The DC-blocking capacitor allows the amplifier to automatically bias the signal to an optimum DC level. Assuming zero-source impedance, the -3dB point of the highpass filter is given by: f0 = 1/2GRINCIN Power Supplies R1 SHDN IN OUT 5V 2I VDD C5 GND 22µF GND PGND VDD5 0.1µF PVDD 4.7µF OUT_+ OUT_- L1 L2 C2 RL 1µF MAX16910 MAX13301 C3 R2 Figure 8. Output Filter Figure 9. Using a Linear Regulator to Produce 5V from a 24V Power Supply Table_32._Suggested_Values_for_LC_Filters RL_(I) 8 4 2* 1* L1,_L2_(µH) 10 10 10 10 C1,_C3_(µF) 0.15 0.15 0.15 0.15 C2_(µF) 0.47 0.47 0.68 1 C4,_C5_(nF) 220 220 220 220 R1,_R2_(I) 10 10 10 10 *Parallel channel operation: at 14.4V (for RL = 1I), at 24V (for RL = 2I). 33 4-Channel, Automotive Class D Audio Amplifier MAX13301 Use capacitors with an ESR less than 100mI for optimum performance. Low-ESR ceramic capacitors minimize the output resistance of the charge pump. For best performance over the extended temperature range, select capacitors with an X7R dielectric. The typical value is 1FF. Flying Capacitor (CFLY) The value of the flying capacitor (CFLY) affects the load regulation and output resistance of the charge pump. A CFLY value that is too small degrades the device’s ability to provide sufficient current drive. Increasing the value of CFLY improves load regulation and reduces the chargepump output resistance to an extent. Use a 50V, 1FF ceramic capacitor for CFLY. Proper layout and grounding are essential for optimum performance. Use large traces for the power-supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Large traces also aid in moving heat away from the package. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any switching noise from coupling into the audio signal. Connect PGND and GND together at a single point on the PCB. Route all traces that carry switching transients away from GND and the traces/components in the audio signal path. Bypass VDD to GND with a 10FF ceramic capacitor and VDD5 to PGND with a 0.1FF ceramic capacitor. Each PVDD is paired with two PGNDs for local supply bypassing. Bypass each PVDD-PGND pair with 0.1FF and 4.7FF ceramic capacitors. Table 35 shows the four PVDD-PGND pairs. Place an additional 1000FF low-ESR electrolytic capacitor from pins 1 and 48 to PGND and from pins 24 and 25 to PGND. Use large, low-resistance output traces. Current drawn from the outputs increases as load impedance decreases. High output trace resistance decreases the power delivered to the load. Large output, supply, and PGND traces allow more heat to move from the device to the air, decreasing the thermal impedance of the circuit. Charge-Pump Capacitor Selection Table_33._PVDD_and_PGND_Pairs PVDD_PIN_NUMBER 1 48 24 25 PGND_PIN_NUMBER 9 and 10 39 and 40 11 and 12 37 and 38 The feedback connections are sensitive to inductor magnetic field interference, so route these traces away from the inductors and noisy traces connected to OUT_ and the charge pump. Refer to the MAX13301 Evaluation Kit for a PCB layout example. The device requires external heatsinking for applications that dissipate more than 1333.3mW. The top side exposed pad is the primary heat conduction path on the device. The thermal resistance of the heatsink is calculated from the following equation:  T - TA  θ HS ≤  J  − θ JC − θ CH  PDISS  where: TJ = +150°C TA = Ambient Operating Temperature BJC = 1°C/W BCH = Thermal resistance of the thermal interface used between the top side exposed pad and the heatsink PDISS = Estimated power dissipation of the device The estimated power dissipation can be calculated from the following equation based on the desired continuous output power, POUT, of the application, the typical efficiency, E, and the number of output channels used, N. 1  PDISS ≤  − 1 × N × POUT η  Supply Bypassing, Layout, and Grounding Thermal Information 34 4-Channel, Automotive Class D Audio Amplifier Typical Operating Circuit CHOLD VBAT PVDD PVDD 1000µF 0.1µF 4.7µF 4.7µF PGND PGND PGND PGND CP 1µF 4 x 0.47µF SINGLEENDED ANALOG AUDIO INPUTS CM IN0+ IN1+ IN2+ IN3+ IN2.0µF REF 2.2µF VL VL FB1+ 150I, ±1% FB1CLO I/O CONTROL AND STATUS FLT_OT MUTE_CL1 EN SYNC VL VL 1.5kI 1.5kI SCL SDA 5V SUPPLY 0.1µF PGND 5V SUPPLY 10µF GND VDD VDD5 OUT32I 1nF FB22I 1nF 10µH 0.68µF 10µH 150nF 10I 0.22µF 150I, ±1% FB3+ 150I, ±1% FB3150nF FB2+ 150I, ±1% OUT2OUT2+ 2I 1nF 10µH 0.68µF 2I 1nF 10µH 150nF 10I 0.22µF 150I, ±1% 150nF OUT12I 1nF 10µH 150nF 10I 0.22µF 150I, ±1% OUT1+ OUT0- MAX13301 MAX13301 PVDD PVDD PGND PGND PGND PGND 1µF VBAT 4.7µF 4.7µF 0.1µF 1000µF 2I OUT0+ 1nF 10µH 150nF 0.68µF 10µH 150nF 10I 0.22µF 2I 1nF 10I 0.22µF 150I, ±1% FB0+ 150I, ±1% FB02I 1nF 10µH 0.68µF 150nF 10I 0.22µF 10I 0.22µF OUT3+ 10I 0.22µF 35 4-Channel, Automotive Class D Audio Amplifier MAX13301 Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE_ TYPE 48 TSSOP-EPR PACKAGE_ CODE U48ER+1 OUTLINE_ LAND_ NO. PATTERN_NO. 21-0444 90-0273 36 4-Channel, Automotive Class D Audio Amplifier Revision History REVISION NUMBER 0 REVISION DATE 6/11 Initial release DESCRIPTION PAGES CHANGED — MAX13301 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 37 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.