MAX1395MTB

19-3709; Rev 0; 5/05 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs General Description The MAX1392/MAX1395 micropower, serial-output, 10-bit, analog-to-digital converters (ADCs) operate with a single power supply from +1.5V to +3.6V. These ADCs feature automatic shutdown, fast wake-up, and a high-speed 3-wire interface. Power consumption is only 0.740mW (VDD = +1.5V) at the maximum conversion rate of 357ksps. AutoShutdown™ between conversions reduces power consumption at slower throughput rates. The MAX1392/MAX1395 require an external reference V REF that has a wide range from 0.6V to V DD . The MAX1392 provides one true-differential analog input that accepts signals ranging from 0 to VREF (unipolar mode) or ±VREF/2 (bipolar mode). The MAX1395 provides two single-ended inputs that accept signals ranging from 0 to V REF . Analog conversion results are available through a 5MHz, 3-wire SPI™-/QSPI™/MICROWIRE™-/digital signal processor (DSP)-compatible serial interface. Excellent dynamic performance, low voltage, low power, ease of use, and small package sizes make these converters ideal for portable battery-powered data-acquisition applications, and for other applications that demand low power consumption and minimal space. The MAX1392/MAX1395 are available in a space-saving (3mm x 3mm) 10-pin TDFN package or 10-pin µMAX® package. The parts operate over the extended (-40°C to +85°C) and military (-55°C to +125°C) temperature ranges. Features ♦ 357ksps 10-Bit Successive-Approximation Register (SAR) ADCs ♦ Single True-Differential Analog Input Channel with Unipolar-/Bipolar-Selected Input (MAX1392) ♦ Dual Single-Ended Input Channel with ChannelSelected Input (MAX1395) ♦ ±0.5 LSB INL, ±0.5 LSB DNL, No Missing Codes ♦ ±1 LSB Total Unadjusted Error ♦ 61dB SINAD at 85kHz Input Frequency ♦ Single Supply Voltage (+1.5V to +3.6V) ♦ 0.945mW at 350ksps, 1.8V ♦ 0.27mW at 100ksps, 1.8V ♦ 3.1µW at 1ksps, 1.8V ♦ 59dB MAX1392 MAX1395 VREF = VDD = 1.6 to 3.6V VREF = VDD = 1.6 to 3.6V 61 61 -83 -84 -75 -70 4 200 150 -73 -74 dB dB dBc dBc dB dB MHz kHz CMR MAX1395 only MAX1395 only VCM = 0 to VDD, MAX1392 only TUE ±0.001 ±0.00025 ±0.1 ±0.1 ±0.1 Offset nulled INL DNL No missing code overtemperature 0.25 0.25 10 ±0.5 ±0.5 ±0.5 ±0.5 ±1 Bits LSB LSB LSB LSB LSB LSB/°C LSB/°C LSB LSB mV/V SYMBOL CONDITIONS MIN TYP MAX UNITS 2 _______________________________________________________________________________________ 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs ELECTRICAL CHARACTERISTICS (continued) (VDD = +1.5V to +3.6V, VREF = VDD, CREF = 0.1µF, fSCLK = 5MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER CONVERSION RATE Conversion Time Throughput Rate Power-Up and Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency tACQ tAD tAJ fCLK Unipolar Bipolar, MAX1392 only (AIN+ - AIN-) Bipolar, MAX1392 only [(AIN+) + (AIN-)] / 2 Channel not selected, or conversion stopped, or in shutdown mode 16 VDD + 0.05 24 0.025 357ksps 20 ±2.5 60 0.3 x VDD 0.7 x VDD 0.06 x VDD IIL CIN Inputs at GND or VDD CS, OE CH1/CH2, UNI/BIP 1 12.5 0.1 x VDD 0.9 x VDD ±1 0.1 0 -VREF/2 0 tCONV 11 clock cycles 14 clocks per conversion; includes powerup, acquisition, and conversion time Three SCLK cycles 600 8 30 5.0 VREF +VREF/2 VDD ±1 2.2 357 µs ksps ns ns ps MHz SYMBOL CONDITIONS MIN TYP MAX UNITS MAX1392/MAX1395 ANALOG INPUTS (AIN+, AIN-, AIN1, AIN2) Input Voltage Range Common-Mode Input Voltage Range Input Leakage Current Input Capacitance REFERENCE INPUT (REF) REF Input Voltage Range REF Input Capacitance REF DC Leakage Current REF Input Dynamic Current DIGITAL INPUTS (SCLK, CS, OE, CH1/CH2, UNI/BIP) Input-Voltage Low Input-Voltage High Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUT (DOUT) Output-Voltage Low Output-Voltage High VOL VOH ISINK = 2mA ISOURCE = 2mA V V VIL VIH V V V µA pF VREF 0.6 V pF µA µA VIN VCM V V µA pF _______________________________________________________________________________________ 3 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs MAX1392/MAX1395 ELECTRICAL CHARACTERISTICS (continued) (VDD = +1.5V to +3.6V, VREF = VDD, CREF = 0.1µF, fSCLK = 5MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Tri-State Leakage Current Tri-State Output Capacitance POWER SUPPLY Positive Supply Voltage VDD fSAMPLE = 100ksps Positive Supply Current (Note 3) IDD fSAMPLE = 357ksps Power-down mode (Note 4) Power-down mode (Note 5) Power-Supply Rejection (Note 6) PSR VDD = 1.5V to 3.6V, full-scale input VDD = 1.6V VDD = 3V VDD = 1.6V VDD = 3V 1.5 150 200 520 710 5 0.2 ±150 3.6 140 225 600 800 10 ±2.5 ±1000 µV/V µA V SYMBOL ILT COUT OE = VDD OE = VDD 10 CONDITIONS MIN TYP MAX ±1 UNITS µA pF TIMING CHARACTERISTICS (VDD = +1.5V to +3.6V, VREF = VDD, CREF = 0.1µF, fSCLK = 5MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Figure 1) PARAMETER SCLK Clock Period SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Rise Setup SCLK Rise to CS Fall Ignore SCLK Fall to DOUT Valid OE Rise to DOUT Disable OE Fall to DOUT Enable CS Pulse-Width High or Low OE Pulse-Width High or Low CH1/CH2 Setup Time (to the First SCLK) CH1/CH2 Hold Time (to the First SCLK) UNI/BIP Setup Time (to the First SCLK) UNI/BIP Hold Time (to the First SCLK) SYMBOL tCP tCH tCL tCSS tCSO tDOV tDOD tDOE tCSW tOEW tCHS tCHH tUBS tUBH MAX1395 only MAX1395 only MAX1392 only MAX1392 only 80 80 10 0 10 0 CLOAD = 0 to 30pF CONDITIONS MIN 200 90 90 80 0 10 6 9 80 20 20 TYP MAX 10000 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: VDD = 1.5V, VREF = 1.5V, and VAIN = 1.5V. VDD = 1.5V, VREF = 1.5V, VAIN = 1.5VP-P, fSCLK = 5MHz, fSAMPLE = 357ksps, and fIN (sine-wave) = 85kHz. All digital inputs swing between VDD and GND. VREF = VDD, fIN = 85kHz sine-wave, VAIN = VREFP-P, CLOAD = 30pF on DOUT. CS = VDD, OE = UNI/BIP = CH1/CH2 = VDD or GND, SCLK is active. CS = VDD, OE = UNI/BIP = CH1/CH2 = VDD or GND, SCLK is inactive. Change in VAIN at code boundary 1022.5. 4 _______________________________________________________________________________________ 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs MAX1392/MAX1395 UNI/BIP OR CH1/CH2 tCHS OE tUBS tCHH tUBH tOEW CS tCSO SCLK tDOE tCP tDOV DOUT HIGH-Z tDOD HIGH-Z tCSS tCL tCH tCSW Figure 1. Detailed Serial-Interface Timing Diagram VDD 10mA DOUT DOUT 10mA 50pF GND 50pF GND b) HIGH IMPEDANCE TO VOL, VOH TO VOL, AND VOL TO HIGH IMPEDANCE a) HIGH IMPEDANCE TO VOH, VOL TO VOH, AND VOH TO HIGH IMPEDANCE Figure 2. Load Circuits for Enable/Disable Times _______________________________________________________________________________________ 5 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs MAX1392/MAX1395 Typical Operating Characteristics (VDD = +1.5V, VREF = +1.5V, CREF = 0.1µF, CL = 30pF, fSCLK = 5MHz. TA = +25°C, unless otherwise noted.) INL vs. CODE MAX1392/95 toc01 INL ERROR vs. REFERENCE VOLTAGE MAX1392/95 toc02 DNL vs. CODE 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 MAX1392/95 toc03 1.0 0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1.0 0.8 0.6 INL ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 MIN INL MAX INL VDD = 3.6V 1.0 128 256 384 512 640 768 896 1024 CODE 0.6 1.1 1.6 2.1 2.6 3.1 3.6 0 128 256 384 512 640 768 896 1024 CODE REFERENCE VOLTAGE (V) DNL ERROR vs. REFERENCE VOLTAGE MAX1392/95 toc04 OFFSET ERROR vs. SUPPLY VOLTAGE MAX1392/95 toc05 OFFSET ERROR vs. TEMPERATURE VDD = 3.6V 300 OFFSET ERROR (µV) 200 100 0 -100 -200 -300 -400 AIN1 AIN2 MAX1392/95 toc06 1.0 0.8 0.6 DNL ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0.6 1.1 1.6 2.1 2.6 3.1 MIN DNL MAX DNL VDD = 3.6V 400 300 OFFSET ERROR (µV) 200 100 0 -100 -200 -300 -400 AIN1 VREF = 1.5V TEMPERATURE = +25°C AIN2 400 3.6 1.5 1.8 REFERENCE VOLTAGE (V) 2.1 2.4 2.7 3.0 SUPPLY VOLTAGE (V) 3.3 3.6 -55 -25 5 35 65 95 125 TEMPERATURE (°C) OFFSET ERROR vs. REFERENCE VOLTAGE MAX1392/95 toc07 GAIN ERROR vs. SUPPLY VOLTAGE MAX1392/95 toc08 GAIN ERROR vs. TEMPERATURE VDD = 3.6V 300 200 GAIN ERROR (µV) 100 0 -100 -200 -300 -400 AIN1 AIN2 MAX1392/95 toc09 400 VDD = 3.6V 300 OFFSET ERROR (µV) 200 100 0 -100 -200 -300 -400 0.6 1.1 1.6 2.1 2.6 3.1 400 300 200 GAIN ERROR (µV) 100 0 -100 -200 -300 -400 1.5 1.8 2.1 2.4 2.7 3.0 3.3 AIN1 VREF = 1.5V TEMPERATURE = +25°C AIN2 400 3.6 3.6 -55 -25 5 35 65 95 125 REFERENCE VOLTAGE (V) SUPPLY VOLTAGE (V) TEMPERATURE (°C) 6 _______________________________________________________________________________________ 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs MAX1392/MAX1395 Typical Operating Characteristics (continued) (VDD = +1.5V, VREF = +1.5V, CREF = 0.1µF, CL = 30pF, fSCLK = 5MHz. TA = +25°C, unless otherwise noted.) GAIN ERROR vs. REFERENCE VOLTAGE MAX1392/95 toc10 SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX1392/95 toc11 SUPPLY CURRENT vs. TEMPERATURE VREF = 1.5V, CL = 33pF fSCLK = 5MHz, fSAMPLE = 357ksps AIN = FULL SCALE, 10kHz SINE WAVE SUPPLY CURRENT (µA) 550 MAX1392/95 toc12 400 VDD = 3.6V 300 200 GAIN ERROR (µV) 100 0 -100 -200 -300 -400 0.6 1.1 1.6 2.1 2.6 3.1 800 600 SUPPLY CURRENT (µA) 700 600 500 500 450 VREF = 1.5V, CL = 33pF fSCLK = 5MHz, fSAMPLE = 357ksps AIN = FULL SCALE, 10kHz SINE WAVE 400 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 -55 -25 5 35 65 95 125 SUPPLY VOLTAGE (V) TEMPERATURE (°C) 400 3.6 REFERENCE VOLTAGE (V) SUPPLY CURRENT vs. CONVERSION RATE MAX1392/95 toc13 SHUTDOWN CURRENT vs. SUPPLY VOLTAGE MAX1392/95 toc14 SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE SHUTDOWN SUPPLY CURRENT (µA) MAX1392/95 toc15 800 SUPPLY CURRENT (µA) 600 VDD = VREF = 3.0V 400 SHUTDOWN CURRENT (µA) fSCLK = 5MHz, fSAMPLE = 357ksps AIN = FULL SCALE, 85kHz SINE WAVE CL = 30pF 0.5 2.0 0.4 1.6 0.3 1.2 0.2 0.8 VDD = 3.6V VDD = 1.8V 200 VDD = VREF = 1.6V 0.1 0.4 0 0 50 100 150 200 250 300 350 fSAMPLE (ksps) 0 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) 0 -55 -25 5 35 65 95 125 TEMPERATURE (°C) SCLK-TO-DOUT TIMING MAX1392/95 toc16 FFT MAX1392/95 toc17 SAMPLING ERROR vs. SOURCE IMPEDANCE 0.8 0.6 SAMPLING ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 AIN LOW-TO-HIGH FS TRANSITION MAX1392/95 toc18 100 90 80 DOUT DELAY (ns) 70 60 50 40 30 20 10 0 0 100 200 300 CLOAD (pF) 400 500 VDD = 3.6V VDD = 1.5V 0 -20 MAGNITUDE (dB) -40 -60 -80 -100 -120 VDD = 1.6V VREF = 1.6V fS = 357ksps fIN = 85kHz THD = -82.7dB SINAD = 61.3dB SFDR = -83.8dB 1.0 AIN HIGH-TO-LOW FS TRANSITION -1.0 0 20 40 60 80 100 120 140 160 180 0 500 1000 1500 2000 2500 FREQUENCY (kHz) SOURCE IMPEDENCE (Ω) 600 _______________________________________________________________________________________ 7 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs MAX1392/MAX1395 Pin Description PIN MAX1392 1 2 — 3 — 4 5 MAX1395 1 — 2 — 3 4 5 NAME VDD AINAIN2 AIN+ AIN1 GND REF FUNCTION Positive Supply Voltage. Connect VDD to a 1.5V to 3.6V power supply. Bypass VDD to GND with a 0.1µF capacitor as close to the device as possible. Negative Analog Input Analog Input Channel 2 Positive Analog Input Analog Input Channel 1 Ground External Reference Voltage Input. VREF = 0.6V to (VDD + 0.05V). Bypass REF to GND with a 0.1µF capacitor as close to the device as possible. Input-Mode Select. Drive UNI/BIP high to select unipolar input mode. Pull UNI/BIP low to select bipolar input mode. In unipolar mode, the output data is in straight binary format. In bipolar mode, the output data is in two’s-complement format. Channel-Select Input. Pull CH1/CH2 low to select channel 1. Drive CH1/CH2 high to select channel 2. Active-Low Output Enable. Pull OE low to enable DOUT. Drive OE high to disable DOUT. Connect to CS to interface with SPI, QSPI, and MICROWIRE devices or set low to interface with DSP devices. Active-Low Chip-Select Input. A falling edge on CS initiates power-up and acquisition. Serial-Data Output. DOUT changes state on the falling edge of SCLK. DOUT is high impedance when OE is high. Serial-Clock Input. SCLK drives the conversion process and clocks data out. Acquisition ends on the 3rd falling edge after the CS falling edge. The LSB is clocked out on the SCLK 13th falling edge and the device enters AutoShutdown mode (see Figures 8, 9, and 10). Exposed Pad. Not internally connected. Connect the exposed pad to GND or leave floating. 6 — UNI/BIP — 6 CH1/CH2 7 8 9 7 8 9 OE CS DOUT 10 — 10 — SCLK EP Detailed Description The MAX1392/MAX1395 use an input track and hold (T/H) circuit along with a SAR to convert an analog input signal to a serial 10-bit digital output data stream. The serial interface provides easy interfacing to microprocessors and DSPs. Figure 3 shows the simplified functional diagram for the MAX1392 (1 channel, true differential) and the MAX1395 (2 channels, single ended). VDD CONTROL LOGIC AND TIMING CS SCLK OE AIN+ (AIN1)* AIN- (AIN2)* True-Differential Analog Input T/H The equivalent input circuit of Figure 4 shows the MAX1392/MAX1395 input architecture, which is composed of a T/H, a comparator, and a switched-capacitor DAC. The T/H enters its tracking mode on the falling edge of CS (while OE is held low). The positive input capacitor is connected to AIN+ (MAX1392), or to AIN1 or AIN2 (MAX1395). The negative input capacitor is connected to AIN- (MAX1392) or GND (MAX1395). The T/H enters its hold mode on the 3rd falling edge of SCLK 8 INPUT MUX AND T/H 10-BIT SAR ADC OUTPUT SHIFT REGISTER DOUT REF UNI/BIP (CH1/CH2)* MAX1392 MAX1395 GND *INDICATES THE MAX1395 Figure 3. Simplified Functional Diagram _______________________________________________________________________________________ 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs and the difference between the sampled positive and negative input voltages is converted. The time required for the T/H to acquire an input signal is determined by how quickly its input capacitance is charged. The required acquisition time lengthens as the input signal’s source impedance increases. The acquisition time, tACQ, is the minimum time needed for the signal to be acquired. It is calculated by the following equation: tACQ ≥ 7.4 x (RSOURCE + RIN) x CIN + tPU where: RSOURCE is the source impedance of the input signal. RIN = 500Ω, which is the equivalent differential analog input resistance. CIN = 16pF, which is the equivalent differential analog input capacitance. tPU = 400ns. Note: tACQ is never less than 600ns and any source impedance below 400Ω does not significantly affect the ADC’s AC performance. Analog Input Bandwidth The ADC’s input-tracking circuitry has a 4MHz fullpower bandwidth, making it possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. Use anti-alias filtering to avoid high-frequency signals being aliased into the frequency band of interest. MAX1392/MAX1395 Analog Input Range and Protection The MAX1392/MAX1395 produce a digital output that corresponds to the analog input voltage as long as the analog inputs are within their specified range. When operating the MAX1392 in unipolar mode (UNI/BIP = 1), the specified differential analog input range is from 0 to VREF. When operating in bipolar mode (UNI/BIP = 0), the differential analog input range is from -VREF/2 to +VREF/2 with a common mode range of 0 to VDD. The MAX1395 has an input range from 0 to VREF. Internal protection diodes confine the analog input voltage within the region of the analog power input rails (VDD, GND) and allow the analog input voltage to swing from GND - 0.3V to VDD + 0.3V without damage. Input voltages beyond GND - 0.3V and VDD + 0.3V forward bias the internal protection diodes. In this situation, limit the forward diode current to less than 50mA to avoid damage to the MAX1392/MAX1395. RSOURCE REF GND AIN2 AIN1 (AIN+)* CIN+ DAC MAX1392 MAX1395 COMPARATOR + - Output Data Format Figures 8, 9, and 10 illustrate the conversion timing for the MAX1392/MAX1395. Fourteen SCLK cycles are required to read the conversion result and data on DOUT transitions on the falling edge of SCLK. The conversion result contains 4 zeros, followed by 10 data bits with the data in MSB-first format. For the MAX1392, data is straight binary for unipolar mode and two’s complement for bipolar mode. For the MAX1395, data is always straight binary. ANALOG SIGNAL SOURCE HOLD GND- (AIN-)* CINRINHOLD VDD/2 TRACK RIN+ HOLD Transfer Function Figure 5 shows the unipolar transfer function for the MAX1392/MAX1395. Figure 6 shows the bipolar transfer function for the MAX1392. Code transitions occur halfway between successive-integer LSB values. *INDICATES THE MAX1392 Figure 4. Equivalent Input Circuit _______________________________________________________________________________________ 9 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs MAX1392/MAX1395 3FF 3FE 3FD OUTPUT CODE (hex) 3FC 3FB FS = VREF ZS = 0 1 LSB = VREF 1024 OUTPUT CODE (hex) FULL-SCALE TRANSITION 1FF 1FE +FS = VREF 2 ZS = 0 -VREF 2 V 1 LSB = REF 1024 -FS = FULL-SCALE TRANSITION 001 000 3FF 3FE 004 003 002 001 000 0 1 2 3 FS - 1.5 LSB INPUT VOLTAGE (LSB) 4 FS 201 200 -FS 0 -FS + 0.5 LSB +FS - 1.5 LSB INPUT VOLTAGE (LSB) +FS Figure 5. Unipolar Transfer Function Figure 6. Bipolar Transfer Function Applications Information Starting a Conversion A falling edge on CS initiates the power-up sequence and begins acquiring the analog input as long as OE is also asserted low. On the 3rd SCLK falling edge, the analog input is held for conversion. The most significant bit (MSB) decision is made and clocked onto DOUT on the 4th SCLK falling edge. Valid DOUT data is available to be clocked into the master (microcontroller (µC)) on the following SCLK rising edge. The rest of the bits are decided and clocked out to DOUT on each successive SCLK falling edge. See Figures 8 and 9 for conversion timing diagrams. Once a conversion has been initiated, CS can go high at any time. Further falling edges of CS do not reinitiate an acquisition cycle until the current conversion completes. Once a conversion completes, the first falling edge of CS begins another acquisition/conversion cycle. Selecting Unipolar or Bipolar Mode (MAX1392 Only) Drive UNI/ BIP high to select unipolar mode or pull UNI/BIP low to select bipolar mode. UNI/BIP can be connected to VDD for logic high, to GND for logic low, or actively driven. UNI/BIP needs to be stable for tUBS prior to the first rising edge of SCLK after the CS falling edge (see Figure 1) for a valid conversion result when being actively driven. Selecting Analog Input AIN1 or AIN2 (MAX1395 Only) Pull CH1/CH2 low to select AIN1 or drive CH1/CH2 high to select AIN2 for conversion. CH1/CH2 can be connected to VDD for logic high, to GND for logic low, or actively driven. CH1/CH2 needs to be stable for tCHS prior to the first rising edge of SCLK after the CS falling edge (see Figure 1) for a valid conversion result when being actively driven. 10 ______________________________________________________________________________________ 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs AutoShutdown Mode The ADC automatically powers down on the SCLK falling edge that clocks out the LSB. This is the falling edge after the 13th SCLK. DOUT goes low when the LSB has been clocked into the master (µC) on the 16th rising SCLK edge. Alternatively, drive O E high to force the MAX1392/ MAX1395 into power-down. Whenever OE goes high, the ADC powers down and disables DOUT regardless of CS, SCLK, or the state of the ADC. DOUT enters a high-impedance state after tDOD. 0.1µF capacitor to GND for best performance (see the Typical Operating Circuit). MAX1392/MAX1395 Serial Interface The MAX1392/MAX1395 serial interface is fully compatible with SPI, QSPI, and MICROWIRE (see Figure 7). If a serial interface is available, set the µC’s serial interface in master mode so the µC generates the serial clock. Choose a clock frequency between 100kHz and 5MHz. CS and O E can be connected together and driven simultaneously. OE can also be connected to GND if the DOUT bus is not shared and driven independently. SPI and MICROWIRE When using SPI or MICROWIRE, make the µC the bus master and set CPOL = 0 and CPHA = 0 or CPOL = 1 and CPHA = 1. (These are the bits in the SPI or MICROWIRE control register.) Two consecutive 1-byte reads are required to get the entire 10-bit result from the ADC. The MAX1392/MAX1395 shut down after clocking the LSB and DOUT becomes high impedance. DOUT transitions on SCLK’s falling edge and is clocked into the µC on the SCLK’s rising edge. See Figure 7 for connections and Figures 8 and 9 for timing diagrams. The conversion result contains 4 zeros, followed by the 10 data bits with the data in MSB-first format. When using CPOL = 0 and CPHA = 0 or CPOL = 1 and CPHA = 1, the MSB of the data is clocked into the µC on the SCLK’s fifth rising edge. To be compatible with SPI and MICROWIRE, connect CS and OE together and drive simultaneously. QSPI Unlike SPI, which requires two 1-byte reads to acquire the 10 bits of data from the ADC, QSPI allows the minimum number of clock cycles necessary to clock in the data. The MAX1392/MAX1395 require a minimum of 14 clock cycles from the µC to clock out the 10 bits of data. See Figure 7 for connections and Figures 8 and 9 for timing diagrams. The conversion result contains 4 zeros, followed by the 10 data bits with the data in MSB-first format. The MAX1392/MAX1395 shut down after clocking out the LSB. DOUT then becomes high impedance. When using CPOL = 0 and CPHA = 0 or CPOL = 1 and CPHA = 1, the MSB of the data is clocked into the µC on the SCLK’s fifth rising edge. To be compatible with QSPI, connect CS and OE together and drive simultaneously. External Reference The MAX1392/MAX1395 use an external reference between 0.6V and (VDD + 50mV). Bypass REF with a I/O SCK OE CS SCLK MAX1392 MAX1395 MISO I/O DOUT UNI/BIP (CH1/CH2)* a) SPI CS SCK OE CS SCLK MAX1392 MAX1395 MISO I/O DOUT UNI/BIP (CH1/CH2)* b) QSPI I/O SK OE CS SCLK MAX1392 MAX1395 SI I/O DOUT UNI/BIP (CH1/CH2)* DSP Interface c) MICROWIRE *INDICATES THE MAX1395 Figure 10 shows the timing for DSP operation. Figure 11 shows the connections between the MAX1392/ MAX1395 and several common DSPs. Figure 7. Common Serial-Interface Connections to the MAX1392/MAX1395 ______________________________________________________________________________________ 11 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs MAX1392/MAX1395 SAMPLING INSTANT ADC STATE UNI/BIP (CH1/CH2)* POWERDOWN POWER-UP AND ACQUIRE (tACQ) BIPOLAR (AIN1)* HOLD AND CONVERT (tCONV) POWER-DOWN UNI (AIN2)* CS = OE 1 SCLK HIGH-Z HIGH-Z 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 DOUT D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 *INDICATES THE MAX1395 Figure 8. Serial-Interface Timing for SPI/QSPI (CPOL = CPHA = 1) and MICROWIRE (G6 = 0, G5 = 1) SAMPLING INSTANT ADC STATE UNI/BIP (CH1/CH2)* POWERDOWN POWER-UP AND ACQUIRE (tACQ) BIPOLAR (AIN1)* HOLD AND CONVERT (tCONV) POWER-DOWN UNI (AIN2)* CS = OE 1 SCLK HIGH-Z HIGH-Z 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 DOUT D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 *INDICATES THE MAX1395 Figure 9. Serial-Interface Timing for SPI/QSPI (CPOL = CPHA = 0) and MICROWIRE (G6 = 0, G5 = 0) 12 ______________________________________________________________________________________ 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs MAX1392/MAX1395 SAMPLING INSTANT ADC STATE OE POWERDOWN POWER-UP AND ACQUIRE (tACQ) HOLD AND CONVERT (tCONV) POWERDOWN UNI/BIP (CH1/CH2)* CS 16 SCLK 1 BIPOLAR (AIN1)* UNI (AIN2)* FS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 DOUT D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 *INDICATES THE MAX1395 Figure 10. DSP Serial-Timing Diagram As shown in Figure 11, drive the MAX1392/MAX1395 chip-select input (CS) with the DSP’s frame-sync signal. OE may be connected to GND or driven independently. For continuous conversion operation, keep OE low and make the C S falling edge coincident with the 14th falling edge of the SCLK. Fourteen-bit data transfers can also be performed with compatible DSPs. Unregulated Two-Cell or Single Lithium LiMnO2 Cell Operation Low operating voltage (1.5V to 3.6V) and ultra-low-power consumption make the MAX1392/MAX1395 ideal for low cost, unregulated, battery-powered applications without the need for a DC-DC converter. Power the MAX1392/ MAX1395 directly from two alkaline/NiMH/NiCd cells in series or a single lithium coin cell as shown in the Typical Operating Circuit. Fresh alkaline cells have a voltage of approximately 1.5V per cell (3V with 2 cells in series) and approach end of life at 0.8V (1.6V with 2 cells in series). A typical 2xAA alkaline discharge curve is shown in Figure 12a. A typical CR2032 lithium (LiMnO2) coin cell discharge curve is shown in Figure 12b. Figure 13 shows the recommended system ground connections. Establish a single-point analog ground (star ground point) at the MAX1392/MAX1395s’ GND pin or use the ground plane. High-frequency noise in the power supply (V DD ) degrades the ADC’s performance. Bypass VDD to GND with a 0.1µF capacitor as close to the device as possible. Minimize capacitor lead lengths for best supply noise rejection. To reduce the effects of supply noise, a 10Ω resistor can be connected as a lowpass filter to attenuate supply noise. Exposed Pad The MAX1392/MAX1395 TDFN package has an exposed pad on the bottom of the package. This pad is not internally connected. Connect the exposed pad to the GND pin on the MAX1392/MAX1395 or leave floating for proper electrical performance. Definitions Integral Nonlinearity (INL) INL is the deviation of the values on an actual transfer function from a straight line. For the MAX1392/ MAX1395, this straight line is between the end points of the transfer function once offset and gain errors have been nullified. INL deviations are measured at every step and the worst-case deviation is reported in the Electrical Characteristics section. Layout, Grounding, and Bypassing For best performance, use PC boards. Board layout must ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. ______________________________________________________________________________________ 13 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs MAX1392/MAX1395 I/O FSX FSR CLKX CLKR DR I/O DOUT UNI/BIP (CH1/CH2)* SCLK OE CS 3.0 2.8 MAX1392 MAX1395 VOLTAGE (V) 2.6 2.4 2.2 2.0 1.8 a) TMS320C541 CONNECTION DIAGRAM I/O TFS RFS SCLK DR I/O OE CS TA = +25°C 1.6 0 100 200 300 400 500 600 700 DAYS MAX1392 SCLK MAX1395 DOUT UNI/BIP (CH1/CH2)* Figure 12a. Typical 2xAA Discharge Curve at 100ksps 3.0 b) ADSP218x CONNECTION DIAGRAM 2.8 I/O SC2 SLK SDR I/O OE CS SCLK DOUT 2.6 VOLTAGE (V) 2.4 2.2 2.0 MAX1392 MAX1395 UNI/BIP (CH1/CH2)* 1.8 TA = +25°C 1.6 c) DSP563xx CONNECTION DIAGRAM *INDICATES THE MAX1395 0 10 20 DAYS 30 40 50 Figure 11. Common DSP Connections to the MAX1392/MAX1395 Figure 12b. Typical CR2032 Discharge Curve at 100ksps Differential Nonlinearity (DNL) DNL is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than ±1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX1392/ MAX1395, DNL deviations are measured at every step and the worst-case deviation is reported in the Electrical Characteristics section. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus the RMS distortion. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics (HD2–HD5), and the DC offset. RMS distortion includes the first five harmonics (HD2–HD5).   SIGNALRMS SINAD = 20 × log   2 2  NOISE  RMS + DISTORTIONRMS       14 ______________________________________________________________________________________ 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs where V1 is the fundamental amplitude, and V2 through V6 are the amplitudes of the 2nd- through 6th-order harmonics. POWER SUPPLY MAX1392/MAX1395 Spurious-Free Dynamic Range (SFDR) VDD 10Ω (OPTIONAL) STAR GROUND POINT VDD GND SFDR is a dynamic figure of merit that indicates the lowest usable input signal amplitude. SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious component, excluding DC offset. SFDR is specified in decibels relative to the carrier (dBc). Intermodulation Distortion (IMD) VDD GND DATA DVDD DGND MAX1392/MAX1395 DIGITAL CIRCUITRY IMD is the ratio of the RMS sum of the intermodulation products to the RMS sum of the two fundamental input tones. This is expressed as:  VIM12 + VIM22 + ..... + VIM32 + VIMN2 IMD = 20 × log   V12 + V22      Figure 13. Power-Supply Grounding Connections Signal-to-Noise Ratio (SNR) SNR is a dynamic figure of merit that indicates the converter’s noise performance. For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNRdB[max] = 6.02dB x N + 1.76dB In reality, there are other noise sources such as thermal noise, reference noise, and clock jitter that also degrade SNR. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset. The fundamental input tone amplitudes (V1 and V2) are at -6.5dBFS. Fourteen intermodulation products (VIM_) are used in the MAX1392/MAX1395 IMD calculation. The intermodulation products are the amplitudes of the output spectrum at the following frequencies, where fIN1 and fIN2 are the fundamental input tone frequencies: • 2nd-order intermodulation products: fIN1 + fIN2, fIN2 - fIN1 • 3rd-order intermodulation products: 2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1 • 4th-order intermodulation products: 3 x fIN1 - fIN2, 3 x fIN2 - fIN1, 3 x fIN1 + fIN2, 3 x fIN2 + fIN1 • 5th-order intermodulation products: 3 x f IN1 - 2 x f IN2 , 3 x f IN2 - 2 x f IN1 , 3 x f IN1 + 2 x f IN2 , 3 x f IN2 + 2 x fIN1 Channel-to-Channel Crosstalk Channel-to-channel crosstalk indicates how well each analog input is isolated from the others. The channel-tochannel crosstalk for the MAX1395 is measured by applying DC to channel 2 while an AC sine wave is applied to channel 1. An FFT is taken for channel 1 and channel 2 and the difference (in dB) is reported as the channel-to-channel crosstalk. Total Harmonic Distortion (THD) THD is a dynamic figure of merit that indicates how much harmonic distortion the converter adds to the signal. THD is the ratio of the RMS sum of the first five harmonics of the fundamental signal to the fundamental itself. This is expressed as:  2 2 2 2 2  V2 + V3 + V4 + V5 + V6 THD = 20 × log  V1          ______________________________________________________________________________________ 15 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs MAX1392/MAX1395 Aperture Delay The MAX1392/MAX1395 sample data on the falling edge of its third SCLK cycle (Figure 14). In actuality, there is a small delay between the falling edge of the sampling clock and the actual sampling instant. Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken. THIRD FALLING EDGE SCLK tAD ANALOG INPUT tAJ SAMPLED DATA T/H (INTERNAL SIGNAL) Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in the aperture delay (Figure 14). DC Power-Supply Rejection Ratio (PSRR) DC PSRR is defined as the change in the positive fullscale transfer function point caused by a full range variation in the analog power-supply voltage (VDD). TRACK HOLD Figure 14. T/H Aperture Timing Chip Information TRANSISTOR COUNT: 9106 PROCESS: BiCMOS 2 x AA CELLS REF INPUT VOLTAGE Typical Operating Circuit 0.1µF VDD REF 0.1µF + MAX1392 MAX1395 AIN+ (AIN1)* AIN- (AIN2)* OE CS SCLK DOUT UNI/BIP (CH1/CH2)* SS SCL MISO CPU INPUT VOLTAGE GND *INDICATES THE MAX1395 ONLY 16 ______________________________________________________________________________________ 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs MAX1392/MAX1395 Pin Configurations DOUT SCLK TOP VIEW UNI/BIP TOP VIEW CS 8 10 9 OE 7 6 VDD 1 AIN- 2 10 SCLK 9 DOUT MAX1392 AIN+ 3 GND 4 REF 5 MAX1392 8 CS 7 OE 6 UNI/BIP 1 VDD 2 AIN- 3 AIN+ 4 GND 5 REF µMAX 3mm x 3mm TDFN CH1/CH2 DOUT SCLK TOP VIEW TOP VIEW CS 8 10 9 OE 7 6 VDD 1 AIN2 2 10 SCLK 9 DOUT MAX1395 AIN1 3 GND 4 REF 5 MAX1395 8 CS 7 OE 6 CH1/CH2 1 VDD 2 AIN2 3 AIN1 4 GND 5 REF µMAX 3mm x 3mm TDFN ______________________________________________________________________________________ 17 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs MAX1392/MAX1395 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 6, 8, &10L, DFN THIN.EPS 2 D2 D A2 N PIN 1 ID 0.35x0.35 b PIN 1 INDEX AREA E DETAIL A E2 e [(N/2)-1] x e REF. A1 k C L C L A L e e L PACKAGE OUTLINE, 6,8,10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm -DRAWING NOT TO SCALE- 21-0137 G 1 COMMON DIMENSIONS SYMBOL A D E A1 L k A2 MIN. 0.70 2.90 2.90 0.00 MAX. 0.80 3.10 3.10 0.05 0.20 0.40 0.25 MIN. 0.20 REF. PACKAGE VARIATIONS PKG. CODE T633-1 T633-2 T833-1 T833-2 T833-3 T1033-1 T1433-1 T1433-2 N 6 6 8 8 8 10 14 14 D2 1.50±0.10 1.50±0.10 1.50±0.10 1.50±0.10 1.50±0.10 1.50±0.10 1.70±0.10 1.70±0.10 E2 2.30±0.10 2.30±0.10 2.30±0.10 2.30±0.10 2.30±0.10 2.30±0.10 2.30±0.10 2.30±0.10 e 0.95 BSC 0.95 BSC 0.65 BSC 0.65 BSC 0.65 BSC 0.50 BSC 0.40 BSC 0.40 BSC JEDEC SPEC MO229 / WEEA MO229 / WEEA MO229 / WEEC MO229 / WEEC MO229 / WEEC MO229 / WEED-3 ------b 0.40±0.05 0.40±0.05 0.30±0.05 0.30±0.05 0.30±0.05 0.25±0.05 0.20±0.05 0.20±0.05 [(N/2)-1] x e 1.90 REF 1.90 REF 1.95 REF 1.95 REF 1.95 REF 2.00 REF 2.40 REF 2.40 REF DOWNBONDS ALLOWED NO NO NO NO YES NO YES NO PACKAGE OUTLINE, 6,8,10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm -DRAWING NOT TO SCALE- 21-0137 G 2 2 18 ______________________________________________________________________________________ 1.5V to 3.6V, 357ksps, 1-Channel True-Differential/ 2-Channel Single-Ended, 10-Bit, SAR ADCs Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 10LUMAX.EPS MAX1392/MAX1395 e 10 4X S 10 INCHES MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 0.120 D1 0.116 0.118 D2 0.114 E1 0.116 0.120 0.118 E2 0.114 0.199 H 0.187 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S α 0° 6° MILLIMETERS MAX MIN 1.10 0.05 0.15 0.75 0.95 2.95 3.05 2.89 3.00 2.95 3.05 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0° 6° H Ø0.50±0.1 0.6±0.1 1 1 0.6±0.1 TOP VIEW BOTTOM VIEW D2 GAGE PLANE A2 A b A1 D1 E2 c α E1 L1 L FRONT VIEW SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 10L uMAX/uSOP APPROVAL DOCUMENT CONTROL NO. REV. 21-0061 1 1 I Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 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