MAX1438

19-0523; Rev 1; 2/11 KIT ATION EVALU ABLE AVAIL Octal, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs General Description Features o Excellent Dynamic Performance 69.9dB SNR at 5.3MHz 96dBc SFDR at 5.3MHz 95dB Channel Isolation o Ultra-Low Power 93mW per Channel (Normal Operation) Fast 200μs Wake-Up Time from Standby o Serial LVDS Outputs o Pin-Selectable LVDS/SLVS (Scalable Low-Voltage Signal) Mode o LVDS Outputs Support Up to 30 Inches FR-4 Backplane Connections o Test Mode for Digital Signal Integrity o Fully Differential Analog Inputs o Wide Differential Input Voltage Range (1.4VP-P) o On-Chip 1.24V Precision Bandgap Reference o Clock Duty-Cycle Equalizer o Compact, 100-Pin TQFP Package with Exposed Pad o Evaluation Kit Available (Order MAX1436BEVKIT) MAX1436B The MAX1436B octal, 12-bit analog-to-digital converter (ADC) features fully differential inputs, a pipelined architecture, and digital error correction incorporating a fully differential signal path. This ADC is optimized for low-power and high-dynamic performance in medical imaging instrumentation and digital communications applications. The MAX1436B operates from a 1.8V single supply and consumes only 743mW (93mW per channel) while delivering a 69.9dB (typ) signal-to-noise ratio (SNR) at a 5.3MHz input frequency. In addition to low operating power, the MAX1436B features a lowpower standby mode for idle periods. An internal 1.24V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of an external reference for applications requiring increased accuracy or a different input voltage range. The reference architecture is optimized for low noise. A single-ended clock controls the data-conversion process. An internal duty-cycle equalizer compensates for wide variations in clock duty cycle. An on-chip PLL generates the high-speed serial low-voltage differential signal (LVDS) clock. The MAX1436B has self-aligned serial LVDS outputs for data, clock, and frame-alignment signals. The output data is presented in two’s complement or binary format. The MAX1436B offers a maximum sample rate of 40Msps. See the Pin-Compatible Versions table below for higher-speed versions. This device is available in a small, 14mm x 14mm x 1mm, 100-pin TQFP package with exposed pad and is specified for the extended industrial (-40°C to +85°C) temperature range. Ordering Information PART MAX1436BECQ+D TEMP RANGE PIN-PACKAGE 100 TQFP-EP* -40°C to +85°C (14mm x 14mm x 1mm) Applications Ultrasound and Medical Imaging Instrumentation Multichannel Communications +Denotes a lead(Pb)-free/RoHS-compliant package. D = Dry pack. *EP = Exposed pad. Pin-Compatible Versions PART MAX1434 MAX1436 MAX1436B MAX1437 MAX1438 SAMPLING RATE (Msps) 50 40 40 50 65 RESOLUTION (Bits) 10 12 12 12 12 POWERSAVE MODE Power-down Power-down Standby Power-down Power-down Pin Configuration appears at the end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Octal, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1436B ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND) AVDD.....................................................................-0.3V to +2.0V CVDD.....................................................................-0.3V to +3.6V OVDD ....................................................................-0.3V to +2.0V IN_P, IN_N ..............................................-0.3V to (VAVDD + 0.3V) CLK ........................................................-0.3V to (VCVDD + 0.3V) OUT_P, OUT_N, FRAME_, CLKOUT_ ......-0.3V to (VOVDD + 0.3V) DT, SLVS/LVDS, LVDSTEST, PLL_, T/B, STBY, REFIO, REFADJ, CMOUT...................-0.3V to (VAVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) TQFP (derate 47.6mW/°C above +70°C) ................3809.5mW Operating Temperature Range ...........................-40°C to +85°C Maximum Junction Temperature .....................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) TQFP Junction-to-Ambient Thermal Resistance (θJA) ...........21°C/W Junction-to-Case Thermal Resistance (θJC) ..................2°C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 3.3V, VGND = 0V, external VREFIO = 1.24V, CREFIO = 0.1µF, CREFP = 10µF, CREFN = 10µF, fCLK = 40MHz (50% duty cycle), VDT = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 2, 3) PARAMETER DC ACCURACY (Note 4) Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUTS (IN_P, IN_N) Input Differential Range Common-Mode Voltage Range Common-Mode Voltage Range Tolerance Differential Input Impedance Differential Input Capacitance CONVERSION RATE Maximum Conversion Rate Minimum Conversion Rate Data Latency fSMAX fSMIN 40 4.0 6.5 MHz MHz Cycles RIN CIN VID VCMO (Note 5) Switched capacitor load Differential input 1.4 0.76 ±50 2 12.5 VP-P V mV kΩ pF N INL DNL No missing codes over temperature 12 ±0.4 ±0.25 ±3 ±1 ±0.5 ±2.4 Bits LSB LSB %FS %FS SYMBOL CONDITIONS MIN TYP MAX UNITS 2 _______________________________________________________________________________________ Octal, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs ELECTRICAL CHARACTERISTICS (continued) (VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 3.3V, VGND = 0V, external VREFIO = 1.24V, CREFIO = 0.1µF, CREFP = 10µF, CREFN = 10µF, fCLK = 40MHz (50% duty cycle), VDT = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 2, 3) PARAMETER SYMBOL CONDITIONS fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS fIN = 5.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS f1 = 5.3MHz at -6.5dBFS f2 = 6.3MHz at -6.5dBFS f1 = 5.3MHz at -6.5dBFS f2 = 6.3MHz at -6.5dBFS Figure 11 Figure 11 Input at -20dBFS Input at -0.5dBFS IN_P = IN_N tOR RS = 25Ω, CS = 50pF 79 66.5 66.5 MIN TYP 69.9 69.6 69.9 69.6 11.3 11.3 96 90 -96 -92 89.8 96.6 < 0.4 1 100 100 0.44 1 -79 MAX UNITS MAX1436B DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT) (Note 4) Signal-to-Noise Ratio Signal-to-Noise and Distortion (First 4 Harmonics) Effective Number of Bits Spurious-Free Dynamic Range Total Harmonic Distortion Intermodulation Distortion Third-Order Intermodulation Aperture Jitter Aperture Delay Small-Signal Bandwidth Full-Power Bandwidth Output Noise Over-Range Recovery Time INTERNAL REFERENCE REFADJ Internal Reference-Mode Enable Voltage REFADJ Low-Leakage Current REFIO Output Voltage Reference Temperature Coefficient EXTERNAL REFERENCE REFADJ External ReferenceMode Enable Voltage REFADJ High-Leakage Current REFIO Input Voltage REFIO Input Voltage Tolerance REFIO Input Current IREFIO (Note 6) VAVDD 0.1 200 1.24 ±5 1MΩ. Clock Input (CLK) The MAX1436B accepts a CMOS-compatible clock signal with a wide 20% to 80% input clock duty cycle. Drive CLK with an external single-ended clock signal. Figure 2 shows the simplified clock input diagram. Low clock jitter is required for the specified SNR performance of the MAX1436B. Analog input sampling occurs on the rising edge of CLK, requiring this edge to provide the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship: ⎛ ⎞ 1 SNR = 20 × log ⎜ ⎟ ⎝ 2 × π × fIN × t J ⎠ where fIN represents the analog input frequency and tJ is the total system clock jitter. System Timing Requirements Figure 3 shows the relationship between the analog inputs, input clock, frame-alignment output, serial-clock output, and serial-data output. The differential analog input (IN_P and IN_N) is sampled on the rising edge of the CLK signal and the resulting data appears at the digital outputs 6.5 clock cycles later. Figure 4 provides a detailed, two-conversion timing diagram of the relationship between the inputs and the outputs. PLL Inputs (PLL1, PLL2, PLL3) The MAX1436B features a PLL that generates an output clock signal with 6 times the frequency of the input clock. The output clock signal is used to clock data out of the MAX1436B (see the System Timing Requirements section). Set the PLL1, PLL2, and PLL3 bits according to the input clock range provided in Table 1. Clock Output (CLKOUTP, CLKOUTN) The MAX1436B provides a differential clock output that consists of CLKOUTP and CLKOUTN. As shown in Figure 4, the serial output data is clocked out of the MAX1436B on both edges of the clock output. The frequency of the output clock is 6 times the frequency of CLK. Frame-Alignment Output (FRAMEP, FRAMEN) The MAX1436B provides a differential frame-alignment signal that consists of FRAMEP and FRAMEN. As shown in Figure 4, the rising edge of the frame-alignment signal corresponds to the first bit (D0) of the 12bit serial data stream. The frequency of the framealignment signal is identical to the frequency of the input clock. Serial Output Data (OUT_P, OUT_N) The MAX1436B provides its conversion results through individual differential outputs consisting of OUT_P and OUT_N. The results are valid 6.5 input clock cycles after the sample is taken. As shown in Figure 3, the output data is clocked out on both edges of the output clock, LSB (D0) first. Figure 5 provides the detailed serial-output timing diagram. AVDD MAX1436B CVDD CLK GND DUTY-CYCLE EQUALIZER Figure 2. Clock Input Circuitry ______________________________________________________________________________________ 15 Octal, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1436B N+2 N (VIN_P VIN_N) N+1 tSAMPLE N+3 N+5 N+4 N+7 N+6 N+8 N+9 CLK 6.5 CLOCK-CYCLE DATA LATENCY (VFRAMEP VFRAMEN)* (VCLKOUTP VCLKOUTN) (VOUT_P VOUT_N) OUTPUT DATA FOR SAMPLE N-6 *DUTY CYCLE VARIES DEPENDING ON INPUT CLOCK FREQUENCY. OUTPUT DATA FOR SAMPLE N Figure 3. Global Timing Diagram N+2 N (VIN_P - VIN_N) tSAMPLE CLK (VFRAMEP VFRAMEN)* (VCLKOUTP VCLKOUTN) (VOUT_P VOUT_N) D5N-7 D6N-7 D7N-7 D8N-7 D9N-7 D10N-7 D11N-7 D0N-6 D1N-6 D2N-6 D3N-6 D4N-6 D5N-6 D6N-6 D7N-6 D8N-6 D9N-6 D10N-6 D11N-6 D0N-5 D1N-5 D2N-5 D3N-5 D4N-5 D5N-5 D6N-5 *DUTY CYCLE DEPENDS ON INPUT CLOCK FREQUENCY. N+1 tSF tCF Figure 4. Detailed Two-Conversion Timing Diagram tCH (VCLKOUTP VCLKOUTN) (VOUT_P VOUT_N) tCL tOD D0 D1 D2 tOD D3 Figure 5. Serialized-Output Detailed Timing Diagram 16 ______________________________________________________________________________________ Octal, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1436B Table 2. Output Code Table (VREFIO = 1.24V) TWO’S-COMPLEMENT DIGITAL OUTPUT CODE (T/B = 0) BINARY D11 → D0 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1000 0000 0001 1000 0000 0000 HEXADECIMAL EQUIVALENT OF D11 → D0 0x7FF 0x7FE 0x001 0x000 0xFFF 0x801 0x800 DECIMAL EQUIVALENT OF D11 → D0 +2047 +2046 +1 0 -1 -2047 -2048 OFFSET BINARY DIGITAL OUTPUT CODE (T/B = 1) BINARY D11 → D0 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000 HEXADECIMAL EQUIVALENT OF D11 → D0 0xFFF 0xFFE 0x801 0x800 0x7FF 0x001 0x000 DECIMAL EQUIVALENT OF D11 → D0 +4095 +4094 +2049 +2048 +2047 +1 0 VIN_P - VIN_N (mV) (VREFIO = 1.24V) +699.66 +699.32 +0.34 0 -0.34 -699.66 -700.00 1 LSB = 2 x FSR 4096 FSR TWO'S-COMPLEMENT OUTPUT CODE (LSB) 0x7FF 0x7FE 0x7FD FSR = 700mV x VREFIO 1.24V FSR OFFSET BINARY OUTPUT CODE (LSB) 0xFFF 0xFFE 0xFFD 1 LSB = 2 x FSR 4096 FSR FSR = 700mV x VREFIO 1.24V FSR 0x001 0x000 0xFFF 0x801 0x800 0x7FF 0x803 0x802 0x801 0x800 -2047 -2045 -1 0 +1 +2045 +2047 0x003 0x002 0x800 0x000 -2047 -2045 -1 0 +1 +2045 +2047 DIFFERENTIAL INPUT VOLTAGE (LSB) DIFFERENTIAL INPUT VOLTAGE (LSB) Figure 6. Two’s-Complement Transfer Function (T/B = 0) Figure 7. Binary Transfer Function (T/B = 1) Output Data Format (T/B) Transfer Functions The MAX1436B output data format is either offset binary or two’s complement, depending on the logic-input T/B. With T/B low, the output data format is two’s complement. With T/B high, the output data format is offset binary. The following equations, Table 2, and Figures 6 and 7 define the relationship between the digital output and the analog input. For two’s complement (T/B = 0): VIN _ P − VIN _ N = FSR × 2 × CODE10 4096 and for offset binary (T/B = 1): VIN _ P − VIN _ N = FSR × 2 × CODE10 − 2048 4096 where CODE10 is the decimal equivalent of the digital output code as shown in Table 2. Keep the capacitive load on the MAX1436B digital outputs as low as possible. ______________________________________________________________________________________ 17 Octal, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1436B LVDS and SLVS Signals (SLVS/LVDS) Drive SLVS/LVDS low for LVDS or drive SLVS/LVDS high for SLVS levels at the MAX1436B outputs (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, and FRAMEN). For SLVS levels, enable double-termination by driving DT high. See the Electrical Characteristics table for LVDS and SLVS output voltage levels. DT OUT_P/ CLKOUTP/ FRAMEP Z0 = 50Ω LVDS Test Pattern (LVDSTEST) Drive LVDSTEST high to enable the output test pattern on all LVDS or SLVS output channels. The output test pattern is 0000 1011 1101. Drive LVDSTEST low for normal operation (test pattern disabled). 100Ω 100Ω Common-Mode Output (CMOUT) CMOUT provides a common-mode reference for DCcoupled analog inputs. If the input is DC-coupled, match the output common-mode voltage of the circuit driving the MAX1436B to the output voltage at VCMOUT to within ±50mV. It is recommended that the output common-mode voltage of the driving circuit be derived from CMOUT. The MAX1436B offers an optional, internal 100Ω termination between the differential output pairs (OUT_P and OUT_N, CLKOUTP and CLKOUTN, FRAMEP and FRAMEN). In addition to the termination at the end of the line, a second termination directly at the outputs helps eliminate unwanted reflections down the line. This feature is useful in applications where trace lengths are long (> 5in) or with mismatched impedance. Drive DT high to select doubletermination, or drive DT low to disconnect the internal termination resistor (single-termination). Selecting double-termination increases the OVDD supply current (see Figure 8). MAX1436B OUT_N/ CLKOUTN/ FRAMEN Z0 = 50Ω SWITCHES ARE CLOSED WHEN DT IS HIGH. SWITCHES ARE OPEN WHEN DT IS LOW. Figure 8. Double-Termination Double-Termination (DT) • OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, and FRAMEN have approximately 342Ω between the output pairs when DT is low. When DT is high, the differential output pairs have 100Ω between each pair. When operating in internal reference mode, the MAX1436B requires 200µs to power up and settle when the converter exits standby mode. To exit standby mode, STBY, the applied control signal must transition from high to low. When using an external reference, the wakeup time is dependent on the external reference drivers. Applications Information Full-Scale Range Adjustments Using the Internal Reference The MAX1436B supports a full-scale adjustment range of 10% (±5%). To decrease the full-scale range, add a 25kΩ to 250kΩ external resistor or potentiometer (RADJ) between REFADJ and GND. To increase the fullscale range, add a 25kΩ to 250kΩ resistor between REFADJ and REFIO. Figure 9 shows the two possible configurations. The following equations provide the relationship between RADJ and the change in the analog full-scale range: ⎛ 1.25kΩ ⎞ FSR = 0.7V ⎜1 + RADJ ⎟ ⎝ ⎠ for RADJ connected between REFADJ and REFIO, and: Standby Mode The MAX1436B offers a standby mode to efficiently use power by transitioning to a low-power state when conversions are not required. STBY controls the standby mode of all channels and the internal reference circuitry. The reference does not power down in standby mode. Drive STBY high to enable standby. In standby mode, the output impedance of all of the LVDS/SLVS outputs is approximately 342Ω, if DT is low. The output impedance of the differential LVDS/SLVS outputs is 100Ω when DT is high. See the Electrical Characteristics table for typical supply currents during standby. The following list shows the state of the analog inputs and digital outputs in standby mode: • IN_P, IN_N analog inputs are disconnected from the internal input amplifier • 18 Reference circuit remains active ______________________________________________________________________________________ Octal, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1436B ADC FULL-SCALE = REFT - REFB REFERENCESCALING AMPLIFIER 0.1μF VIN N.C. 1 T1 2 5 6 10Ω IN_P 39pF REFT REFB REFERENCE BUFFER G MAX1436B 0.1μF REFIO 1V REFADJ CONTROL LINE TO DISABLE REFERENCE BUFFER 0.1μF 25kΩ 250kΩ 4 3 MINICIRCUITS ADT1-1WT 10Ω IN_N 39pF 25kΩ 250kΩ Figure 10. Transformer-Coupled Input Drive MAX1436B AVDD AVDD/2 Figure 9. Circuit Suggestions to Adjust the ADC’s Full-Scale Range ⎛ 1.25kΩ ⎞ FSR = 0.7V ⎜1 − RADJ ⎟ ⎝ ⎠ for RADJ connected between REFADJ and GND. Using Transformer Coupling An RF transformer (Figure 10) provides an excellent solution to convert a single-ended input source signal to a fully differential signal. The MAX1436B input common-mode voltage is internally biased to 0.76V (typ) with f CLK = 40MHz. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. Multilayer boards with ample ground and power planes produce the highest level of signal integrity. Connect MAX1436B ground pins and the exposed pad to the same ground plane. The MAX1436B relies on the exposed-backside-pad connection for a low-inductance ground connection. Isolate the ground plane from any noisy digital system ground planes. Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 90° turns. Ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equally. Refer to the MAX1434/MAX1436/MAX1436B/MAX1437/ MAX1438 EV kit data sheet for an example of symmetric input layout. Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. For the MAX1436B, this straight line is between the end points of the transfer function, once offset and gain errors have been nullified. INL deviations are measured at every step and the worst-case deviation is reported in the Electrical Characteristics table. Grounding, Bypassing, and Board Layout The MAX1436B requires high-speed board layout design techniques. Refer to the MAX1434/MAX1436/ MAX1436B/MAX1437/MAX1438 EV kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass AVDD to GND with a 0.1µF ceramic capacitor in parallel with a 0.1µF ceramic capacitor. Bypass OVDD to GND with a 0.1µF ceramic capacitor in parallel with a ≥ 2.2µF ceramic capacitor. Bypass CVDD to GND with a 0.1µF ceramic capacitor in parallel with a ≥ 2.2µF ceramic capacitor. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX1436B, DNL deviations are measured at every step and the worst-case deviation is reported in the Electrical Characteristics table. ______________________________________________________________________________________ 19 Octal, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1436B Offset Error Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. For the MAX1436B, the ideal midscale digital output transition occurs when there is -1/2 LSBs across the analog inputs (Figures 6 and 7). Bipolar offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point. CLK tAD ANALOG INPUT tAJ SAMPLED DATA Gain Error Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. For the MAX1436B the gain error is the difference of the measured full-scale and zero-scale transition points minus the difference of the ideal full-scale and zero-scale transition points. For the bipolar devices (MAX1436B), the full-scale transition point is from 0x7FE to 0x7FF for two’s-complement output format (0xFFE to 0xFFF for offset binary) and the zero-scale transition point is from 0x800 to 0x801 for two’s complement (0x000 to 0x001 for offset binary). T/H HOLD TRACK HOLD Figure 11. Aperture Jitter/Delay Specifications For the MAX1436B, SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2–HD7), and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency, excluding the fundamental and the DC offset. Crosstalk Crosstalk indicates how well each analog input is isolated from the others. For the MAX1436B, a 5.3MHz, -0.5dBFS analog signal is applied to one channel while a 19.3MHz, -0.5dBFS analog signal is applied to another channel. An FFT is taken on the channel with the 5.3MHz analog signal. From this FFT, the crosstalk is measured as the difference in the 5.3MHz and 19.3MHz amplitudes. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: ⎛ SINAD − 1.76 ⎞ ENOB = ⎜ ⎟ ⎝ ⎠ 6.02 Aperture Delay Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken. See Figure 11. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in the aperture delay. See Figure 11. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is expressed as: ⎛ V22 + V32 + V4 2 + V52 + V62 + V72 THD = 20 × log ⎜ ⎜ V1 ⎝ ⎞ ⎟ ⎟ ⎠ Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNRdB[max] = 6.02dB x N x 1.76dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. 20 Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious ______________________________________________________________________________________ Octal, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs component, excluding DC offset. SFDR is specified in decibels relative to the carrier (dBc). Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency. MAX1436B Intermodulation Distortion (IMD) IMD is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones f1 and f2. The individual input tone levels are at -6.5dBFS. The intermodulation products are as follows: • 2nd-order intermodulation products (IM2): f1 + f2, f2 - f1 • • • 3rd-order intermodulation products (IM3): 2 x f1 - f2, 2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1 4th-order intermodulation products (IM4): 3 x f1 - f2, 3 x f2 - f1, 3 x f1 + f2, 3 x f2 + f1 5th-order intermodulation products (IM5): 3 x f1 - 2 x f2, 3 x f2 - 2 x f1, 3 x f1 + 2 x f2, 3 x f2 + 2 x f1 Gain Matching Gain matching is a figure of merit that indicates how well the gain of all eight ADC channels is matched to each other. For the MAX1436B, gain matching is measured by applying the same 5.3MHz, -0.5dBFS analog signal to all analog input channels. These analog inputs are sampled at 40Msps and the maximum deviation in amplitude is reported in dB as gain matching in the Electrical Characteristics table. Phase Matching Phase matching is a figure of merit that indicates how well the phases of all eight ADC channels are matched to each other. For the MAX1436B, phase matching is measured by applying the same 5.3MHz, -0.5dBFS analog signal to all analog input channels. These analog inputs are sampled at 40Msps and the maximum deviation in phase is reported in degrees as phase matching in the Electrical Characteristics table. Third-Order Intermodulation (IM3) IM3 is the total power of the 3rd-order intermodulation product to the Nyquist frequency relative to the total input power of the two input tones f1 and f2. The individual input tone levels are at -6.5dBFS. The 3rd-order intermodulation products are 2 x f1 - f2, 2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1. Small-Signal Bandwidth A small -20.5dBFS analog input signal is applied to an ADC so that the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. ______________________________________________________________________________________ 21 Octal, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1436B Pin Configuration GND AVDD AVDD AVDD T/B PLL1 PLL2 GND GND IN0N N.C. PLL3 STBY LVDSTEST OUT0P OUT0N OVDD IN0P GND CMOUT TOP VIEW 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 + GND IN1P IN1N GND IN2P IN2N GND IN3P IN3N GND AVDD AVDD AVDD N.C. AVDD GND IN4P IN4N GND IN5P IN5N GND IN6P IN6N GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 REFADJ REFIO GND REFP REFN N.C. OVDD OUT1P OUT1N OVDD N.C. OUT2P OUT2N OVDD OUT3P OUT3N OVDD OVDD CLKOUTP CLKOUTN OVDD FRAMEP FRAMEN OVDD OUT4P OUT4N OVDD OUT5P OUT5N N.C. MAX1436B *EP 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 OVDD OUT7N OUT7P OVDD OUT6N OUT6P AVDD CVDD CLK GND AVDD AVDD AVDD AVDD SLVS/LVDS *CONNECT EP TO GND TQFP 14mm x 14mm x 1mm Chip Information PROCESS: BiCMOS 22 ______________________________________________________________________________________ AVDD 0VDD N.C. IN7N GND N.C. DT GND GND IN7P Octal, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 100 TQFP-EP PACKAGE CODE C100E+2 OUTLINE NO. 21-0116 LAND PATTERN NO. 90-0153 MAX1436B ______________________________________________________________________________________ 23 Octal, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs MAX1436B Revision History REVISION NUMBER 0 1 REVISION DATE 3/06 2/11 Initial release Updated Ordering Information, added new Package Thermal Characteristics section, and fixed errors in Electrical Characteristics table DESCRIPTION PAGES CHANGED — 1–5 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 24 © 2011 Maxim Integrated Products Springer Maxim is a registered trademark of Maxim Integrated Products, Inc.