MAX1444EHJ

19-1745; Rev 1; 11/03 KIT ATION EVALU BLE AVAILA 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference General Description Features o Single 3.0V Operation o Excellent Dynamic Performance 59.5dB SNR at fIN = 20MHz 74dBc SFDR at fIN = 20MHz o Low Power 19mA (Normal Operation) 5µA (Shutdown Mode) o Fully Differential Analog Input o Wide 2Vp-p Differential Input Voltage Range o 400MHz -3dB Input Bandwidth o On-Chip 2.048V Precision Bandgap Reference o CMOS-Compatible Three-State Outputs o 32-Pin TQFP Package o Evaluation Kit Available MAX1444 The MAX1444 10-bit, 3V analog-to-digital converter (ADC) features a pipelined 10-stage ADC architecture with fully differential wideband track-and-hold (T/H) input and digital error correction incorporating a fully differential signal path. This ADC is optimized for lowpower, high dynamic performance applications in imaging and digital communications. The MAX1444 operates from a single 2.7V to 3.6V supply, consuming only 57mW while delivering a 59.5dB signal-to-noise ratio (SNR) at a 20MHz input frequency. The fully differential input stage has a 400MHz -3dB bandwidth and may be operated with single-ended inputs. In addition to low operating power, the MAX1444 features a 5µA power-down mode for idle periods. An internal 2.048V precision bandgap reference is used to set the ADC full-scale range. A flexible reference structure allows the user to supply a buffered, direct, or externally derived reference for applications requiring increased accuracy or a different input voltage range. Higher speed, pin-compatible versions of the MAX1444 are also available. Please refer to the MAX1446 data sheet (60Msps) and the MAX1448 data sheet (80Msps). The MAX1444 has parallel, offset binary, CMOS-compatible three-state outputs that can be operated from 1.7V to 3.6V to allow flexible interfacing. The device is available in a 5x5mm 32-pin TQFP package and is specified over the extended industrial (-40°C to +85°C) temperature range. Ordering Information PART MAX1444EHJ TEMP RANGE -40°C to +85°C PIN-PACKAGE 32 TQFP Pin Configuration REFOUT TOP VIEW REFIN REFP GND D0 D1 D2 26 ________________________Applications Ultrasound Imaging CCD Imaging Baseband and IF Digitization Digital Set-Top Boxes Video Digitizing Applications REFN COM VDD GND GND IN+ INGND 1 2 3 4 5 6 7 8 32 31 30 29 28 27 D3 25 24 D4 23 OGND 22 T.P. 21 OVDD 20 D5 19 D6 18 D7 17 D8 16 D9 MAX1444 9 VDD 10 VDD 11 GND 12 CLK 13 PD 14 GND 15 OE Functional Diagram appears at end of data sheet. TQFP 1 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference MAX1444 ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V IN+, IN- to GND........................................................-0.3V to VDD REFIN, REFOUT, REFP, REFN, and COM to GND.........................-0.3V to (VDD + 0.3V) OE, PD, CLK to GND..................................-0.3V to (VDD + 0.3V) D9–D0 to GND.........................................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 32-Pin TQFP (derate 18.7mW/°C above +70°C)......1495.3mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3V; OVDD = 2.7V; 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V; REFOUT connected to REFIN through a 10kΩ resistor; VIN = 2VP-P (differential with respect to COM); CL = 10pF at digital outputs; fCLK = 40MHz; TA = TMIN to TMAX, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical values are at TA = +25°C.) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT Input Differential Range Common-Mode Voltage Range Input Resistance Input Capacitance CONVERSION RATE Maximum Clock Frequency Data Latency DYNAMIC CHARACTERISTICS (fCLK = 40MHz, 4096-point FFT) fIN = 7.51MHz Signal-to-Noise Ratio SNR fIN = 19.91MHz fIN = 39.9MHz (Note 1) Signal-to-Noise and Distortion (Up to 5th harmonic) fIN = 7.51MHz SINAD fIN = 19.91MHz fIN = 39.9MHz (Note 1) fIN = 7.51MHz Spurious-Free Dynamic Range SFDR fIN = 19.91MHz fIN = 39.9 MHz (Note 1) 67 66 57 56.1 57.5 56.3 59.5 59.5 58.5 59.4 59 58.3 75 74 72.5 dBc dB dB fCLK 40 5.5 MHz Cycles VDIFF VCOM RIN CIN Switched capacitor load Differential or single-ended inputs ±1.0 VDD/2 ±0.5 50 5 V V kΩ pF TA ≥ +25°C INL DNL fIN = 7.51MHz, TA ≥ +25°C fIN = 7.51MHz, no missing codes guaranteed 10 ±0.6 ±0.4 50 1.07 V V V V V MΩ REFOUT TCREF 2.048 ±1% 60 1.25 V ppm/°C mV/mA IN+ = IN- = COM FPBW tAD tAJ For 1.5 × full-scale input Input at -20dBFS, differential inputs Input at -0.5dBFS, differential inputs MIN TYP -75 -74 -72.5 -76 dBc dBc MAX UNITS Third-Order Intermodulation Distortion IM3 -76 -73.8 -72.2 -70 500 400 1 2 2 ±1 ±0.25 0.2 -65 -65 dBc Total Harmonic Distortion (First 4 Harmonics) dBc MHz MHz ns psRMS ns % Degrees LSBRMS _______________________________________________________________________________________ 3 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference MAX1444 ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V; OVDD = 2.7V; 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V; REFOUT connected to REFIN through a 10kΩ resistor; VIN = 2VP-P (differential with respect to COM); CL = 10pF at digital outputs; fCLK = 40MHz; TA = TMIN to TMAX, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical values are at TA = +25°C.) PARAMETER Maximum REFP, COM Source Current Maximum REFP, COM Sink Current Maximum REFN Source Current Maximum REFN Sink Current SYMBOL ISOURCE ISINK ISOURCE ISINK RREFP, RREFN CIN ∆VREF VCOM ∆VREF = VREFP - VREFN Measured between REFP and COM and REFN and COM CONDITIONS MIN TYP 5 -250 250 -5 MAX UNITS mA µA µA mA UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM) REFP, REFN Input Resistance REFP, REFN, COM Input Capacitance Differential Reference Input Voltage Range COM Input Voltage Range 4 15 1.024 ±10% VDD / 2 ±10% VCOM + ∆VREF / 2 VCOM ∆VREF / 2 0.8 × VDD 0.8 × OVDD 0.2 × VDD 0.2 × OVDD kΩ pF V V REFP Input Voltage VREFP V REFN Input Voltage DIGITAL INPUTS (CLK, PD, OE) VREFN V CLK Input High Threshold VIH PD, OE CLK Input Low Threshold VIL PD, OE V V 4 _______________________________________________________________________________________ 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference MAX1444 ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V; OVDD = 2.7V; 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V; REFOUT connected to REFIN through a 10kΩ resistor; VIN = 2VP-P (differential with respect to COM); CL = 10pF at digital outputs; fCLK = 40MHz; TA = TMIN to TMAX, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical values are at TA = +25°C.) PARAMETER Input Hysteresis Input Leakage Input Capacitance DIGITAL OUTPUTS (D9–D0) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Output Supply Voltage Analog Supply Current Output Supply Current Power-Supply Rejection TIMING CHARACTERISTICS CLK Rise to Output Data Valid OE Fall to Output Enable OE Rise to Output Disable CLK Pulse Width High CLK Pulse Width Low Wake-up Time tDO tENABLE tDISABLE tCH tCL tWAKE Figure 6 (Note 3) Figure 5 Figure 5 Figure 6, clock period 25ns Figure 6, clock period 25ns (Note 4) 5 10 15 12.5 ±3.8 12.5 ±3.8 1.7 8 ns ns ns ns ns µs VDD OVDD IVDD IOVDD PSRR Operating, fIN = 19.91MHz at -0.5dBFS Shutdown, clock idle, PD = OE = OVDD Operating, fIN = 19.91MHz at -0.5dBFS Shutdown, clock idle, PD = OE = OVDD Offset Gain 2.7 1.7 3.0 3.0 19 4 4.5 1 ±0.1 ±0.1 20 3.6 3.6 27 15 V V mA µA mA µA mV/V %/V VOL VOH ILEAK COUT ISINK = 200µA ISOURCE = 200µA OE = OVDD OE = OVDD 5 OVDD 0.2 ±10 0.2 V V µA pF SYMBOL VHYST IIH IIL CIN VIH = VDD = OVDD VIL = 0 5 CONDITIONS MIN TYP 0.1 ±5 ±5 MAX UNITS V µA pF Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a +1.024V full-scale input voltage range. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is 6dB better if referenced to the two-tone envelope. Note 3: Digital outputs settle to VIH / VIL. Note 4: REFIN is driven externally. REFP, COM, and REFN are left floating while powered down. _______________________________________________________________________________________ 5 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference MAX1444 Typical Operating Characteristics (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dB FS, fCLK = 40MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) FFT PLOT (fIN = 7.51MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) MAX1444-01 FFT PLOT (fIN = 19.91MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) MAX1444-02 FFT PLOT (fIN = 47MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 3RD HARMONIC 2ND HARMONIC SINAD = 58.1dB SNR = 58.4dB THD = -69.7dBc SFDR = 72.4dBc MAX1444-03 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 2 4 6 8 SINAD = 59dB SNR = 59.3dB THD = -71.6dBc SFDR = 73dBc 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 SINAD = 58.9dB SNR = 59.1dB THD = -72.8dBc SFDR = 75.2dBc 0 3RD HARMONIC 2ND HARMONIC 3RD HARMONIC 2ND HARMONIC 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) FFT PLOT (fIN = 7.51MHz, 8192-POINT FFT, SINGLE-ENDED INPUT) MAX1444-04 FFT PLOT (fIN = 19.91MHz, 8192-POINT FFT, SINGLE-ENDED INPUT) MAX1444-05 FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY (SINGLE ENDED) MAX1444-06 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 2 4 6 8 SINAD = 59.7dB SNR = 60dB THD = -71.8dBc SFDR = 75dBc 0 -10 -20 AMPLITUDE (dB) -30 SINAD = 59.1dB SNR = 59.2dB THD = -74.6dBc SFDR = 77.6dBc 6 4 2 GAIN (dB) 0 -2 -4 -6 -8 3RD HARMONIC 2ND HARMONIC -40 -50 -60 -70 -80 -90 -100 2ND HARMONIC 3RD HARMONIC 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY (SINGLE ENDED) MAX1444-07 TWO-TONE INTERMODULATION 8192-POINT IMD (DIFFERENTIAL INPUT) MAX1444-08 SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY 75 70 SFDR (dBc) 65 60 55 50 45 40 SINGLE ENDED DIFFERENTIAL MAX1444-09 6 4 2 GAIN (dB) 0 -2 -4 -6 -8 1 VIN = 100mVp-p 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 f1 = 11.5MHz AT -6.5dB FS f2 = 13.5MHz AT -6.5dB FS IMD = -76dBc 80 10 100 1000 0 5 10 15 20 25 1 10 ANALOG INPUT FREQUENCY (MHz) 100 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) 6 _______________________________________________________________________________________ 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference MAX1444 Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dB FS, fCLK = 40MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY MAX1444-10 TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY MAX1444-11 SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUENCY MAX1444-12 62 61 60 -45 -50 SINGLE ENDED -55 65 61 SINAD (dB) THD (dBc) SNR (dB) 59 58 57 56 55 54 1 10 ANALOG INPUT FREQUENCY (MHz) 100 SINGLE ENDED DIFFERENTIAL 57 DIFFERENTIAL 53 -60 -65 DIFFERENTIAL -70 -75 1 10 ANALOG INPUT FREQUENCY (MHz) 100 49 SINGLE ENDED 45 1 10 ANALOG INPUT FREQUENCY (MHz) 100 SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER MAX1444-13 SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER MAX1444-14 TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER fIN = 19.91MHz MAX1444-15 80 75 70 SFDR (dBc) fIN = 19.91MHz 65 fIN = 19.91MHz -50 -55 -60 THD (dBc) 60 SNR (dB) 55 65 60 55 50 -15 -12 -9 -6 -3 0 ANALOG INPUT POWER (dB FS) -65 -70 50 45 -75 -80 -15 -12 -9 -6 -3 0 -15 -12 -9 -6 -3 0 ANALOG INPUT POWER (dB FS) ANALOG INPUT POWER (dB FS) 40 SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT POWER MAX1444-16 SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE MAX1444-17 SIGNAL-TO-NOISE RATIO vs. TEMPERATURE fIN = 19.91MHz MAX1444-18 65 fIN = 19.91MHz 84 fIN = 19.91MHz 70 60 80 66 SINAD (dB) SFDR (dBc) SNR (dB) 55 76 62 50 72 58 45 68 54 40 -15 -12 -9 -6 -3 0 ANALOG INPUT POWER (dB FS) 64 -40 -15 10 35 60 85 TEMPERATURE (°C) 50 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 7 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference MAX1444 Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dB FS, fCLK = 40MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) TOTAL HARMONIC DISTORTION vs. TEMPERATURE MAX1444-19 SIGNAL-TO-NOISE PLUS DISTORTION vs. TEMPERATURE MAX1444-20 INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE (BEST STRAIGHT LINE) 0.3 0.2 MAX1444-21 -60 fIN = 19.91MHz 70 fIN = 19.91MHz 0.4 -64 66 0.1 0 -0.1 -0.2 -0.3 SINAD (dB) THD (dBc) -72 58 -76 54 -80 -40 -15 10 35 60 85 TEMPERATURE (°C) 50 -40 -15 10 35 60 85 TEMPERATURE (°C) INL (LSB) -68 62 -0.4 0 200 400 600 800 1000 1200 DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE MAX1444-22 GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = 2.048V) MAX1444-23 OFFSET ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = 2.048V) MAX1444-24 0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 0 200 400 600 800 1000 0.05 0.04 0.03 10 8 OFFSET ERROR (LSB) -40 -15 10 35 60 85 GAIN ERROR (LSB) 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 6 4 2 0 -40 -15 10 35 60 85 TEMPERATURE (°C) TEMPERATURE (°C) 1200 DIGITAL OUTPUT CODE ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE MAX1444-25 ANALOG SUPPLY CURRENT vs. TEMPERATURE MAX1444-26 DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE fIN = 7.51MHz MAX1444-27 24 24 6 5 4 22 22 IOVDD (mA) IVDD (mA) IVDD (mA) 20 20 3 2 1 0 18 18 16 16 14 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 14 -40 -15 10 35 60 85 TEMPERATURE (°C) 1.6 2.0 2.4 2.8 3.2 3.6 OVDD (V) 8 _______________________________________________________________________________________ 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference MAX1444 Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dB FS, fCLK = 40MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) DIGITAL SUPPLY CURRENT vs. TEMPERATURE MAX1444-28 ANALOG POWER-DOWN CURRENT vs. ANALOG POWER SUPPLY MAX1444-29 DIGITAL POWER-DOWN CURRENT vs. DIGITAL POWER SUPPLY PD = VDD OE = OVDD MAX1444-30 5 fIN = 7.51MHz 5.0 4.5 4.0 OE = OVDD PD = VDD 10 4 8 IOVDD (mA) IVDD (µA) 3.5 3.0 2 IOVDD (µA) 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 3 6 4 1 2.5 2.0 -40 -15 10 35 60 85 TEMPERATURE (°C) 2 0 0 1.2 1.8 2.4 OVDD (V) 3.0 3.6 SNR/SINAD, THD/SFDR vs. CLOCK FREQUENCY (OVER-CLOCKING) MAX1444-31 INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE MAX1444-32 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX1444-33 80 SNR/SINAD, THD/SFDR (dB, dBc) 75 70 65 60 55 50 30 fIN = 13.24MHz 2.10 2.10 SFDR 2.08 THD VREFOUT (V) SNR 2.08 VREFOUT (V) 2.70 2.85 3.00 3.15 3.30 VDD (V) 3.45 3.60 2.06 2.06 2.04 2.04 SINAD 2.02 2.02 2.00 34 38 42 fCLK (MHz) 46 50 2.00 -40 -15 10 35 60 85 TEMPERATURE (°C) OUTPUT NOISE HISTOGRAM (DC INPUT) 64515 63000 56000 49000 COUNTS 42000 35000 28000 21000 14000 7000 0 N-2 N-1 N N+1 N+2 DIGITAL OUTPUT CODE 0 869 152 0 MAX1444-34 70000 _______________________________________________________________________________________ 9 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference MAX1444 Pin Description PIN 1 2 3, 9, 10 4, 5, 8, 11, 14, 30 6 7 12 13 15 16–20 21 22 23 24–28 29 31 32 NAME REFN COM VDD GND IN+ INCLK PD OE D9–D5 OVDD T.P. OGND D4–D0 REFOUT REFIN REFP FUNCTION Lower Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. Common-Mode Voltage Output. Bypass to GND with a >0.1µF capacitor. Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. Analog Ground Positive Analog Input. For single-ended operation, connect signal source to IN+. Negative Analog Input. For single-ended operation, connect IN- to COM. Conversion Clock Input Power Down Input. High: Power-down mode. Low: Normal operation. Output Enable Input. High: Digital outputs disabled. Low: Digital outputs enabled. Three-State Digital Outputs D9–D5. D9 is the MSB. Output Driver Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. Test Point. Do not connect. Output Driver Ground Three-State Digital Outputs D4–D0. D0 is the LSB. Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor-divider. Reference Input. VREFIN = 2 × (VREFP - VREFN). Bypass to GND with a >0.1µF capacitor. Upper Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a >0.1µF capacitor. 10 ______________________________________________________________________________________ 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference Detailed Description The MAX1444 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage every half-clock cycle. Counting the delay through the output latch, the clock-cycle latency is 5.5. A 1.5-bit (2-comparator) flash ADC converts the held input voltage into a digital code. The following digitalto-analog converter (DAC) converts the digitized result back into an analog voltage, which is then subtracted from the original held input signal. The resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage where the process is repeated until the signal has been processed by all 10 stages. Each stage provides a 1-bit resolution. voltage is held on C2a and C2b. Switches S4a, S4b, S5a, S5b, S1, S2a, and S2b are then opened before S3a, S3b, and S4c are closed, connecting capacitors C1a and C1b to the amplifier output. This charges C1a and C1b to the same values originally held on C2a and C2b. This value is then presented to the first-stage quantizer and isolates the pipeline from the fast-changing input. The wide-input-bandwidth T/H amplifier allows the MAX1444 to track and sample/hold analog inputs of high frequencies beyond Nyquist. The analog inputs (IN+ and IN-) can be driven either differentially or single-ended. It is recommended to match the impedance of IN+ and IN- and set the common-mode voltage to midsupply (VDD/2) for optimum performance. MAX1444 Analog Input and Reference Configuration The MAX1444 full-scale range is determined by the internally generated voltage difference between REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The ADC’s full-scale range is user-adjustable through the REFIN pin, which provides a high input impedance for this purpose. REFOUT, REFP, COM (VDD/2), and REFN are internally buffered, low-impedance outputs. Input Track-and-Hold Circuit Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuit in both track and hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuit samples the input signal onto the two capacitors (C2a and C2b). Switches S2a and S2b set the common mode for the amplifier input. The resulting differential INTERNAL BIAS S2a C1a COM S5a S3a MDAC VIN T/H Σ x2 VOUT IN+ FLASH ADC 1.5 BITS C2a DAC S4c S1 OUT S4b C2b C1b S3b VIN STAGE 1 STAGE 2 STAGE 10 S2b INTERNAL BIAS DIGITAL ALIGNMENT LOGIC 10 D9–D0 VIN = INPUT VOLTAGE BETWEEN IN+ AND IN- (DIFFERENTIAL OR SINGLE-ENDED) TRACK HOLD TRACK HOLD CLK INTERNAL NON-OVERLAPPING CLOCK SIGNALS S5b COM S4a OUT IN- Figure 1. Pipelined Architecture—Stage Blocks Figure 2. Internal T/H Circuit 11 ______________________________________________________________________________________ 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference MAX1444 The MAX1444 provides three modes of reference operation: • Internal reference mode • Buffered external reference mode • Unbuffered external reference mode In internal reference mode, the internal reference output (REFOUT) can be tied to the REFIN pin through a resistor (e.g., 10kΩ) or resistor-divider if an application requires a reduced full-scale range. For stability purposes, it is recommended to bypass REFIN with a >10nF capacitor to GND. In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a stable and accurate voltage at REFIN. In this mode, REFOUT may be left open or connected to REFIN through a >10kΩ resistor. In unbuffered external reference mode, REFIN is connected to GND, thereby deactivating the on-chip buffers of REFP, COM, and REFN. With their buffers shut down, these pins become high impedance inputs and can be driven by external reference sources. Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines. The MAX1444 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50% must meet the specifications for high and low periods as stated in the Electrical Characteristics. See Figures 3a, 3b, 4a, and 4b for the relationship between spurious-free dynamic range (SFDR), signal-to-noise ratio (SNR), total harmonic distortion (THD), or signal-to-noise plus distortion (SINAD) versus clock duty cycle. Output Enable (OE), Power Down (PD), and Output Data (D0–D9) All data outputs, D0 (LSB) through D9 (MSB), are TTL/CMOS-logic compatible. There is a 5.5 clock-cycle latency between any particular sample and its valid output data. The output coding is straight offset binary (Table 1). With OE and PD (power down) high, the digital output enters a high-impedance state. If OE is held low with PD high, the outputs are latched at the last value prior to the power down. The capacitive load on the digital outputs D0 – D9 should be kept as low as possible (