MAX1446

19-1729; Rev 1; 7/03 KIT ATION EVALU ILABLE AVA 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference General Description Features o Single 3.0V Operation o Excellent Dynamic Performance 59.5dB SNR at fIN = 20MHz 73dB SFDR at fIN = 20MHz o Low Power: 30mA (Normal Operation) 5µA (Shutdown Mode) o Fully Differential Analog Input o Wide 2Vp-p Differential Input Voltage Range o 400MHz -3dB Input Bandwidth o On-Chip 2.048V Precision Bandgap Reference o CMOS-Compatible Three-State Outputs o 32-Pin TQFP Package MAX1446 The MAX1446 10-bit, 3V analog-to-digital converter (ADC) features a fully differential input, a pipelined 10stage ADC architecture with digital error correction and wideband track and hold (T/H) incorporating a fully differential signal path. This ADC is optimized for lowpower, high dynamic performance applications in imaging and digital communications. The MAX1446 operates from a single 2.7V to 3.6V supply, consuming only 90mW while delivering a 59.5dB signal-to-noise ratio (SNR) at a 20MHz input frequency. The fully differential input stage has a 400MHz, -3dB bandwidth and may be operated with single-ended inputs. In addition to low operating power, the MAX1446 features a 5µA power-down mode for idle periods. An internal 2.048V precision bandgap reference is used to set the ADC full-scale range. A flexible reference structure allows the user to supply a buffered, direct or externally derived reference for applications requiring increased accuracy or a different input voltage range. Lower and higher speed, pin-compatible versions of the MAX1446 are also available. Refer to the MAX1444 data sheet for a 40Msps version and the MAX1448 data sheet for a 80Msps version. The MAX1446 has parallel, offset binary, three-state outputs that can be operated from 1.7V to 3.3V to allow flexible interfacing. The device is available in a 5x5mm, 32-pin TQFP package and is specified over the extended industrial (-40°C to +85°C) temperature range. Ordering Information PART MAX1446EHJ TEMP RANGE -40°C to +85°C PIN-PACKAGE 32 TQFP Functional Diagram ________________________Applications Ultrasound Imaging CCD Imaging Baseband and IF Digitization Digital Set-Top Boxes Video Digitizing Applications CLK MAX1446 CONTROL VDD GND IN+ T/H INPIPELINE ADC D E C 10 OUTPUT DRIVERS D9–D0 PD REF REF SYSTEM + BIAS OVDD OGND REFOUT REFIN REFP COM REFN OE ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446 ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V IN+, IN- to GND........................................................-0.3V to VDD REFIN, REFOUT, REFP, REFN, and COM to GND.........................-0.3V to (VDD + 0.3V) OE, PD, CLK to GND..................................-0.3V to (VDD + 0.3V) D9–D0 to GND.........................................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 32-Pin TQFP (derate 11.1mW/°C above +70°C)...........889mW Operating Temperature Range ..........................-40°C to +85°C Storage Temperature Range ............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3.0V, OVDD = 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 62.5MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, 0.01µF capacitor. Upper Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a >0.1µF capacitor. MAX1446 15 16–20 21 22 23 24–28 29 31 32 OE D9–D5 OVDD T.P. OGND D4–D0 REFOUT REFIN REFP _______________________________________________________________________________________ 9 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446 Detailed Description The MAX1446 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage every half-clock cycle. Counting the delay through the output latch, the clock-cycle latency is 5.5. A 1.5-bit (2-comparator) flash ADC converts the held input voltage into a digital code. The following digitalto-analog converter (DAC) converts the digitized result back into an analog voltage, which is then subtracted from the original held input signal. The resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage where the process is repeated until the signal has been processed by all 10 stages. Each stage provides a 1-bit resolution. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. input. The resulting differential voltage is held on C2a and C2b. S4a, S4b, S5a, S5b, S1, S2a, and S2b are then opened before S3a, S3b and S4c are closed, connecting capacitors C1a and C1b to the amplifier output, and S4c is closed. This charges C1a and C1b to the same values originally held on C2a and C2b. This value is then presented to the first stage quantizer and isolates the pipeline from the fast-changing input. The wide-input-bandwidth T/H amplifier allows the MAX1446 to track and sample/hold analog inputs of high frequencies beyond Nyquist. The analog inputs (IN+ and IN-) can be driven either differentially or single ended. It is recommended to match the impedance of IN+ and IN- and set the common-mode voltage to midsupply (VDD/2) for optimum performance. Analog Input and Reference Configuration The MAX1446 full-scale range is determined by the internally generated voltage difference between REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The ADC’s full-scale range is user adjustable through the REFIN pin, which provides a high input impedance for this purpose. REFOUT, REFP, COM (VDD/2), and REFN are internally buffered, low-impedance outputs. INTERNAL BIAS S2a C1a COM S5a S3a Input Track-and-Hold Circuit Figure 2 displays a simplified functional diagram of the input T/H circuit in both track and hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuit samples the input signal onto the two capacitors (C2a and C2b). S2a and S2b set the common mode for the amplifier MDAC VIN T/H Σ x2 VOUT S4a IN+ OUT C2a S4c S1 OUT S4b C2b C1b S3b S2b INTERNAL BIAS S5b COM FLASH ADC 1.5 bits DAC IN- VIN STAGE 1 STAGE 2 STAGE 10 DIGITAL CORRECTION LOGIC 10 D9–D0 VIN = INPUT VOLTAGE BETWEEN IN+ AND IN- (DIFFERENTIAL OR SINGLE ENDED) TRACK HOLD TRACK CLK INTERNAL HOLD NON-OVERLAPPING CLOCK SIGNALS Figure 1. Pipelined Architecture—Stage Blocks 10 Figure 2. Internal T/H Circuit ______________________________________________________________________________________ 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference The MAX1446 provides three modes of reference operation: • Internal reference mode • Buffered external reference mode • Unbuffered external reference mode In internal reference mode, the internal reference output (REFOUT) can be tied to the REFIN pin through a resistor (e.g., 10kΩ) or resistor-divider if an application requires a reduced full-scale range. For stability purposes, it is recommended to bypass REFIN with a >10nF capacitor to GND. In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a stable and accurate voltage at REFIN. In this mode, REFOUT may be left open or connected to REFIN through a >10kΩ resistor. In unbuffered external reference mode, REFIN is connected to GND, thereby deactivating the on-chip buffers of REFP, COM, and REFN. With their buffers shut down, these pins become high impedance and can be driven by external reference sources. The MAX1446 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50% must meet the specifications for high and low periods as stated in the Electrical Characteristics. See Figures 3a, 3b, 4a, and 4b for the relationship between spurious-free dynamic range (SFDR), signal-to-noise ratio (SNR), total harmonic distortion (THD), or signal-to-noise plus distortion (SINAD) versus duty cycle. MAX1446 Output Enable (OE), Power-Down (PD), and Output Data (D0–D9) All data outputs, D0 (LSB) through D9 (MSB), are TTL/CMOS-logic compatible. There is a 5.5 clock-cycle latency between any particular sample and its valid output data. The output coding is straight offset binary (Table 1). With OE and PD (power-down) high, the digital output enters a high-impedance state. If OE is held low with PD high, the outputs are latched at the last value prior to the power-down. The capacitive load on the digital outputs D0 – D9 should be kept as low as possible (