MAX1446_08

19-1729; Rev 4; 11/08 KIT ATION EVALU ABLE AVAIL 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference General Description Features o Single 3.0V Operation o Excellent Dynamic Performance 59.5dB SNR at fIN = 20MHz 73dB SFDR at fIN = 20MHz o Low Power: 30mA (Normal Operation) 5µA (Shutdown Mode) o Fully Differential Analog Input o Wide 2VP-P Differential Input Voltage Range o 400MHz -3dB Input Bandwidth o On-Chip 2.048V Precision Bandgap Reference o CMOS-Compatible Three-State Outputs o 32-Pin TQFP Package o Evaluation Kit Available (MAX1448 EV Kit) MAX1446 The MAX1446 10-bit, 3V analog-to-digital converter (ADC) features a fully differential input, a pipelined 10stage ADC architecture with digital error correction and wideband track and hold (T/H) incorporating a fully differential signal path. This ADC is optimized for lowpower, high dynamic performance applications in imaging and digital communications. The MAX1446 operates from a single 2.7V to 3.6V supply, consuming only 90mW while delivering a 59.5dB signal-to-noise ratio (SNR) at a 20MHz input frequency. The fully differential input stage has a 400MHz, -3dB bandwidth and may be operated with single-ended inputs. In addition to low operating power, the MAX1446 features a 5µA power-down mode for idle periods. An internal 2.048V precision bandgap reference is used to set the ADC full-scale range. A flexible reference structure allows the user to supply a buffered, direct or externally derived reference for applications requiring increased accuracy or a different input voltage range. Lower and higher speed, pin-compatible versions of the MAX1446 are also available. Refer to the MAX1444 data sheet for a 40Msps version, the MAX1448 data sheet for an 80Msps version, and the MAX1449 data sheet for a 105Msps version. The MAX1446 has parallel, offset binary, three-state outputs that can be operated from 1.7V to 3.3V to allow flexible interfacing. The device is available in a 5mm x 5mm, 32-pin TQFP package and is specified over the extended industrial (-40°C to +85°C) and automotive (-40°C to +105°C) temperature ranges. Ordering Information PART MAX1446EHJ+ MAX1446GHJ+ TEMP RANGE -40°C to +85°C -40°C to +105°C PINPACKAGE 32 TQFP 32 TQFP +Denotes a lead(Pb)-free/RoHS-compliant package. ________________________Applications Ultrasound Imaging CCD Imaging Baseband and IF Digitization Digital Set-Top Boxes Video Digitizing Applications IN+ T/H INCLK Functional Diagram MAX1446 CONTROL VDD GND PIPELINE ADC D E C 10 OUTPUT DRIVERS D9–D0 Pin-Compatible, Lower/Higher Speed Versions PART MAX1444 MAX1448 MAX1449 SAMPLING SPEED (Msps) 40 80 105 PD REF REF SYSTEM + BIAS OVDD OGND REFOUT REFIN REFP COM REFN OE ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446 ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V IN+, IN- to GND........................................................-0.3V to VDD REFIN, REFOUT, REFP, REFN, and COM to GND.........................-0.3V to (VDD + 0.3V) OE, PD, CLK to GND..................................-0.3V to (VDD + 0.3V) D9–D0 to GND.........................................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 32-Pin TQFP (derate 18.7mW/°C above +70°C)......1495.3mW Operating Temperature Ranges: MAX1446EHJ+ .................................................-40°C to +85°C MAX1446GHJ+...............................................-40°C to +105°C Storage Temperature Range ............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3.0V, OVDD = 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 62.5MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT Input Differential Range Common-Mode Voltage Range Input Resistance Input Capacitance CONVERSION RATE Maximum Clock Frequency Data Latency DYNAMIC CHARACTERISTICS fIN = 7.492MHz Signal-to-Noise Ratio SNR fIN = 19.943MHz fIN = 39.9MHz (Note 1) Signal-to-Noise + Distortion (Up to 5th Harmonic) fIN = 7.492MHz SINAD fIN = 19.943MHz fIN = 39.9MHz (Note 1) Spurious-Free Dynamic Range fIN = 7.492MHz SFDR fIN = 19.943MHz fIN = 39.9MHz (Note 1) 65 63 56.6 56.2 57 56.5 59.5 59.5 59 59.4 59 58.5 74 73 71 dBc dB dB fCLK 60 5.5 MHz Cycles VDIFF VCOM RIN CIN Switched capacitor load Differential or single-ended inputs ±1.0 VDD/2 ± 0.5 33 5 V V kΩ pF TA ≥ +25°C INL DNL fIN = 7.492MHz, TA ≥ +25°C No missing codes, fIN = 7.492MHz -1.6 10 ±0.6 ±0.4 < ±0.1 0 ±1.9 ±1.0 ±1.9 ±2.0 Bits LSB LSB % FS % FS SYMBOL CONDITIONS MIN TYP MAX UNITS 2 _______________________________________________________________________________________ 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 62.5MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER Third-Harmonic Distortion Two-Tone Intermodulation Distortion Third-Order Intermodulation Distortion Total Harmonic Distortion (First 5 Harmonics) Small-Signal Bandwidth Full-Power Bandwidth Aperture Delay Aperture Jitter Overdrive Recovery Time Differential Gain Differential Phase Output Noise INTERNAL REFERENCE Reference Output Voltage Reference Temperature Coefficient Load Regulation REFIN Input Voltage Positive Reference Output Voltage Negative Reference Output Voltage Common-Mode Level Differential Reference Output Voltage Range REFIN Resistance Maximum REFP, COM Source Current Maximum REFP, COM Sink Current REFOUT TCREF 2.048 ±1% 60 1.25 VREFIN VREFP VREFN VCOM ΔVREF RREFIN ISOURCE ISINK ΔVREF = VREFP - VREFN, TA ≥ +25°C 0.98 2.048 2.012 0.988 VDD/2 1.024 > 50 5 -250 1.07 V V V V MΩ mA µA V ppm/°C mV/mA IN+ = IN- = COM FPBW tAD tAJ For 1.5 × full-scale input SYMBOL HD3 CONDITIONS fIN = 7.492MHz fIN = 19.943MHz fIN = 39.9MHz (Note 1) IMDTT IM3 f1 = 19MHz at -6.5dBFS, f2 = 21MHz at -6.5dBFS (Note 2) f1 = 19MHz at -6.5dBFS f2 = 21MHz at -6.5dBFS (Note 2) fIN = 7.492MHz THD fIN = 19.943MHz fIN = 39.9MHz (Note 1) Input at -20dBFS, differential inputs Input at -0.5dBFS, differential inputs MIN TYP -74 -73 -71 -75 -75 -70 -70 -69 500 400 1 2 2 ±1 ±0.25 0.2 MHz MHz ns psrms ns % ° LSBrms -64 -63 dBc dBc dBc dBc MAX UNITS MAX1446 BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V) _______________________________________________________________________________________ 3 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446 ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 62.5MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER Maximum REFN Source Current Maximum REFN Sink Current SYMBOL ISOURCE ISINK RREFP, RREFN CIN ΔVREF VCOM VREFP VREFN ΔVREF = VREFP - VREFN Measured between REFP and COM and REFN and COM CONDITIONS MIN TYP 250 -5 MAX UNITS µA mA UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM) REFP, REFN Input Resistance REFP, REFN, COM Input Capacitance Differential Reference Input Voltage Range COM Input Voltage Range REFP Input Voltage REFN Input Voltage DIGITAL OUTPUTS (CLK, PD, OE) CLK Input High Threshold VIH PD, OE CLK Input Low Threshold VIL PD, OE Input Hysteresis Input Leakage Input Capacitance DIGITAL OUTPUTS (D9–D0) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance VOL VOH ILEAK COUT ISINK = 200µA ISOURCE = 200µA OE = OVDD OE = OVDD 5 OVDD 0.2 ±10 0.2 V V µA pF VHYST IIH IIL CIN VIH = VDD = OVDD VIL = 0 5 0.1 ±5 ±5 0.8 x VDD 0.8 x OVDD 0.2 x VDD 0.2 x OVDD V µA pF 4 15 1.024 ±10% VDD/2 ±10% VCOM+ ΔVREF/2 VCOM ΔVREF/2 KΩ pF V V V V V V 4 _______________________________________________________________________________________ 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 62.5MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER POWER REQUIREMENTS Analog Supply Voltage Output Supply Voltage Analog Supply Current VDD OVDD IVDD CL = 10pF Operating, fIN = 19.943MHz at -0.5dBFS Shutdown, clock idle, PD = OE = OVDD Operating, CL = 15pF, fIN = 19.943MHz at -0.5dBFS Shutdown, clock idle, PD = OE = OVDD Power-Supply Rejection TIMING CHARACTERISTICS CLK Rise to Output Data Valid OE Fall to Output Enable OE Rise to Output Disable Clock Duty Cycle Wake-Up Time tWAKE tDO tENABLE tDISABLE Figure 5 (Notes 3, 6) Figure 5 Figure 5 Figure 6, clock period 16ns (Notes 5, 6) (Notes 4, 6) 45 366 2 5 10 1.5 55 520 8 ns ns ns % µs PSRR Offset Gain 2.7 1.7 3.0 3.0 30 4 7 1 ± 0.1 ± 0.1 20 3.6 3.6 37 15 V V mA µA mA µA mV/V %/V SYMBOL CONDITIONS MIN TYP MAX UNITS MAX1446 Output Supply Current IOVDD Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a 1.024V full-scale input voltage range. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is 6dB better, if referenced to the two-tone envelope. Note 3: Digital outputs settle to VIH, VIL. Note 4: Wake-up time is defined as the time from complete reference power-down until the ADC performs within 0.3 ENOB of the final performance for fIN = 10MHz at -0.5dBFS input amplitude. VREFIN = 2.048V, REFP, REFN, and CML decoupled with 2.3µF. Note 5: Dynamic characteristics guaranteed at fIN = 19.943MHz for the specified duty-cycle range. Note 6: Guaranteed by design and engineering characterization. _______________________________________________________________________________________ 5 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446 Typical Operating Characteristics (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dBFS, fCLK = 62.35MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) FFT PLOT (fIN = 7.5MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) MAX1446 toc01 FFT PLOT (fIN = 13.3MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) MAX1446 toc02 FFT PLOT (fIN = 20MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 HD3 HD2 SINAD = 59.3dB SNR = 59.6dB THD = -70.7dBc SFDR = 72.2dBc MAX1446 toc03 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 HD2 SFDR = 72.2dBc SNR = 60.1dB THD = -71.5dBc SINAD = 59.8dB 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 HD3 SINAD = 59.3dB SNR = 59.5dB THD = -72.9dBc SFDR = 74.3dBc 0 HD3 HD2 25 30 35 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) FFT PLOT (fIN = 26.8MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) MAX1446 toc04 FFT PLOT (fIN = 50MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) MAX1446 toc05 FFT PLOT (fIN = 7.5MHz, 8192-POINT FFT, SINGLE-ENDED INPUT) -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 HD2 HD3 SINAD = 59.5dB SNR = 59.7dB THD = -73.0dBc SFDR = 73.6dBc MAX1446 toc06 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 SINAD = 59.0dB SNR = 59.4dB THD = -70.5dBc SFDR = 72.9dBc 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 HD2 SFDR = 70dBc SNR = 59.1dB THD = -67.1dBc SINAD = 58.5dB 0 HD2 HD3 HD3 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) FFT PLOT (fIN = 20MHz, 8192-POINT FFT, SINGLE-ENDED INPUT) MAX1446 toc07 TWO-TONE INTERMODULATION (8192-POINT IMD, DIFFERENTIAL INPUT) -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 SFDR (dBc) f1 = 19MHz AT -6.5dBFS f2 = 21MHz AT -6.5dBFS 3RD IMD = -76dBc MAX1446 toc08 SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY (AIN = -0.5dBFS) DIFFERENTIAL 75 70 65 60 55 50 SINGLE-ENDED MAX1446 toc09 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 HD3 SINAD = 59.2dB SNR = 59.5dB THD = -70.7dBc SFDR = 71.1dBc 0 80 HD2 25 30 35 0 5 10 15 20 25 30 35 0 10 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) 20 30 40 50 60 70 80 ANALOG INPUT FREQUENCY (MHz) 90 6 _______________________________________________________________________________________ 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dBFS, fCLK = 62.35MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY (AIN = -0.5dBFS) MAX1446 toc10 MAX1446 TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY (AIN = -0.5dBFS) MAX1446 toc11 SIGNAL-TO-NOISE AND DISTORTION vs. ANALOG INPUT FREQUENCY (AIN = -0.5dBFS) DIFFERENTIAL 59 58 SINAD (dB) 57 56 55 54 SINGLE-ENDED MAX1446 toc12 60 DIFFERENTIAL 59 -50 -55 -60 THD (dBc) 60 SINGLE-ENDED SNR (dB) 58 -65 -70 -75 -80 57 SINGLE-ENDED 56 DIFFERENTIAL 53 52 0 10 20 30 40 50 60 70 80 ANALOG INPUT FREQUENCY (MHz) 90 55 0 10 20 30 40 50 60 70 80 ANALOG INPUT FREQUENCY (MHz) 90 0 10 20 30 40 50 60 70 80 ANALOG INPUT FREQUENCY (MHz) 90 SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER (fIN = 19.943MHz) MAX1446 toc13 SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER (fIN = 19.943MHz) MAX1446 toc14 TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER (fIN = 19.943MHz) MAX1446 toc15 80 75 70 SFDR (dBc) 66 60 54 -50 -55 -60 THD (dBc) -65 -70 -75 -80 SNR (dB) 65 60 55 50 -20 -16 -12 -8 -4 ANALOG INPUT POWER (dBFS) 0 48 42 36 30 -20 -16 -12 -8 -4 ANALOG INPUT POWER (dBFS) 0 -20 -16 -12 -8 -4 ANALOG INPUT POWER (dBFS) 0 SIGNAL-TO-NOISE AND DISTORTION vs. ANALOG INPUT POWER (fIN = 19.943MHz) MAX1446 toc16 SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE MAX1446 toc17 SIGNAL-TO-NOISE RATIO vs. TEMPERATURE fIN = 19.943MHz, AIN = -0.5dBFS 66 MAX1446 toc18 65 60 55 SINAD (dB) 80 fIN = 19.943MHz, AIN = -0.5dBFS 76 70 45 40 35 30 -20 -16 -12 -8 -4 ANALOG INPUT POWER (dBFS) 0 68 SNR (dB) -40 -15 10 35 TEMPERATURE (°C) 60 85 50 SFDR (dBc) 72 62 58 64 54 60 50 -40 -15 10 35 TEMPERATURE (°C) 60 85 _______________________________________________________________________________________ 7 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446 Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dBFS, fCLK = 62.35MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) TOTAL HARMONIC DISTORTION vs. TEMPERATURE MAX1446 toc19 SIGNAL-TO-NOISE AND DISTORTION vs. TEMPERATURE fIN = 19.943MHz, AIN = -0.5dBFS 66 MAX1446 toc20 INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE (BEST STRAIGHT LINE) 0.4 0.3 INL (LSB) 0.2 0.1 0 fIN = 7.5MHz MAX1446 toc21 -60 fIN = 19.943MHz, AIN = -0.5dBFS -64 70 0.5 -72 TA = +105°C SINAD (dB) THD (dBc) -68 62 58 TA = +105°C -0.1 -0.2 -76 54 -80 -40 -15 10 35 60 TEMPERATURE (°C) 85 110 50 -40 -15 10 35 60 TEMPERATURE (°C) 85 110 -0.3 0 200 400 600 800 1000 1200 DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE MAX1446 toc22 GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = 2.048V) MAX1446 toc23 OFFSET ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = 2.048V) 8 6 OFFSET ERROR (%FS) 4 2 0 -2 -4 -6 -8 -10 TA = +105°C MAX1446 toc24 0.3 0.2 0.1 DNL (LSB) 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 200 400 600 800 1000 fIN = 7.5MHz 10 8 6 GAIN ERROR (%FS) 4 2 0 -2 -4 -6 -8 -10 TA = +105°C 10 1200 -40 -15 DIGITAL OUTPUT CODE 10 35 60 TEMPERATURE (°C) 85 110 -40 -15 10 35 60 TEMPERATURE (°C) 85 110 ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE MAX1446 toc25 ANALOG SUPPLY CURRENT vs. TEMPERATURE MAX1446 toc26 DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE fIN = 7.5MHz 7 6 IOVDD (mA) 5 4 3 2 MAX1446 toc27 35 50 46 42 38 TA = +105°C 8 33 IVDD (mA) IVDD (mA) 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 31 34 30 26 22 29 27 18 14 25 2.70 10 -40 -15 10 35 60 TEMPERATURE (°C) 85 110 1.2 1.8 2.4 OVDD (V) 3.0 3.6 8 _______________________________________________________________________________________ 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446 Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dBFS, fCLK = 62.35MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) DIGITAL SUPPLY CURRENT vs. TEMPERATURE MAX1446 toc28 ANALOG POWER-DOWN CURRENT vs. ANALOG POWER SUPPLY MAX1446 toc29 DIGITAL POWER-DOWN CURRENT vs. DIGITAL POWER SUPPLY PD = VDD, OE = OVDD 8 MAX1446 toc30 20 fIN = 7.5MHz 16 TA = +105°C IOVDD (mA) 5.0 4.5 4.0 IVDD (μA) 3.5 3.0 10 OE = OVDD, PD = VDD 12 IOVDD (μA) 6 8 4 4 2 2.5 0 -40 -15 10 35 60 TEMPERATURE (°C) 85 110 0 2.0 2.70 1.2 1.8 2.4 OVDD (V) 3.0 3.6 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 SNR/SINAD, -THD/SFDR vs. CLOCK FREQUENCY MAX1446 toc31 INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE MAX1446 toc32 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX1446 toc33 80 SFDR SNR/SINAD, -THD/SFDR (dB, dBc) 74 2.10 2.10 2.08 VREFOUT (V) 2.08 SNR 62 VREFOUT (V) 68 -THD 2.06 2.06 2.04 2.04 56 fIN = 20MHz, AIN = -0.5dBFS 50 50 54 58 62 66 CLOCK FREQUENCY (MHz) 70 SINAD 2.02 2.02 TA = +105°C 2.00 2.70 2.00 2.85 3.00 3.15 3.30 VDD (V) 3.45 3.60 -40 -15 10 35 60 TEMPERATURE (°C) 85 110 OUTPUT NOISE HISTOGRAM (DC INPUT) 140000 120000 100000 COUNT 80000 60000 40000 20000 0 0 N-2 N-1 N N+1 N+2 DIGITAL OUTPUT CODE 926 725 0 MAX1446 toc34 160000 129421 _______________________________________________________________________________________ 9 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446 Pin Description PIN 1 2 3, 9, 10 4, 5, 8, 11, 14, 30 6 7 12 13 NAME REFN COM VDD GND IN+ INCLK PD FUNCTION Lower Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. Common-Mode Voltage Output. Bypass to GND with a > 0.1µF capacitor. Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. Analog Ground Positive Analog Input. For single-ended operation, connect signal source to IN+. Negative Analog Input. For single-ended operation, connect IN- to COM. Conversion Clock Input Power-Down Input High: power-down mode Low: normal operation Output Enable Input High: digital outputs disabled Low: digital outputs enabled Three-State Digital Outputs D9–D5. D9 is the MSB. Output Driver Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. Test Point. Do not connect. Output Driver Ground Three-State Digital Outputs D4–D0. D0 is the LSB. Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor-divider. Reference Input. VREFIN = 2 × (VREFP - VREFN). Bypass to GND with a > 0.01µF capacitor. Upper Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. 15 16–20 21 22 23 24–28 29 31 32 OE D9–D5 OVDD T.P. OGND D4–D0 REFOUT REFIN REFP 10 ______________________________________________________________________________________ 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference Detailed Description The MAX1446 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage every half-clock cycle. Counting the delay through the output latch, the clock-cycle latency is 5.5. A 1.5-bit (2-comparator) flash ADC converts the held input voltage into a digital code. The following digitalto-analog converter (DAC) converts the digitized result back into an analog voltage, which is then subtracted from the original held input signal. The resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage where the process is repeated until the signal has been processed by all 10 stages. Each stage provides a 1-bit resolution. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. input. The resulting differential voltage is held on C2a and C2b. S4a, S4b, S5a, S5b, S1, S2a, and S2b are then opened before S3a, S3b and S4c are closed, connecting capacitors C1a and C1b to the amplifier output, and S4c is closed. This charges C1a and C1b to the same values originally held on C2a and C2b. This value is then presented to the first stage quantizer and isolates the pipeline from the fast-changing input. The wide-input-bandwidth T/H amplifier allows the MAX1446 to track and sample/hold analog inputs of high frequencies beyond Nyquist. The analog inputs (IN+ and IN-) can be driven either differentially or single ended. It is recommended to match the impedance of IN+ and IN- and set the common-mode voltage to midsupply (VDD/2) for optimum performance. MAX1446 Analog Input and Reference Configuration The MAX1446 full-scale range is determined by the internally generated voltage difference between REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The ADC’s full-scale range is user adjustable through the REFIN pin, which provides a high input impedance for this purpose. REFOUT, REFP, COM (VDD/2), and REFN are internally buffered, low-impedance outputs. INTERNAL BIAS S2a C1a COM S5a S3a Input Track-and-Hold Circuit Figure 2 displays a simplified functional diagram of the input T/H circuit in both track and hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuit samples the input signal onto the two capacitors (C2a and C2b). S2a and S2b set the common mode for the amplifier MDAC VIN T/H Σ x2 VOUT S4a IN+ OUT C2a S4c S1 OUT S4b C2b C1b S3b S2b INTERNAL BIAS S5b COM FLASH ADC 1.5 bits DAC IN- VIN STAGE 1 STAGE 2 STAGE 10 DIGITAL CORRECTION LOGIC 10 D9–D0 VIN = INPUT VOLTAGE BETWEEN IN+ AND IN- (DIFFERENTIAL OR SINGLE ENDED) TRACK HOLD TRACK CLK INTERNAL HOLD NONOVERLAPPING CLOCK SIGNALS Figure 1. Pipelined Architecture—Stage Blocks Figure 2. Internal T/H Circuit 11 ______________________________________________________________________________________ 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446 The MAX1446 provides three modes of reference operation: • Internal reference mode • Buffered external reference mode • Unbuffered external reference mode In internal reference mode, the internal reference output (REFOUT) can be tied to the REFIN pin through a resistor (e.g., 10kΩ) or resistor-divider if an application requires a reduced full-scale range. For stability purposes, it is recommended to bypass REFIN with a > 10nF capacitor to GND. In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a stable and accurate voltage at REFIN. In this mode, REFOUT may be left open or connected to REFIN through a > 10kΩ resistor. In unbuffered external reference mode, REFIN is connected to GND, thereby deactivating the on-chip buffers of REFP, COM, and REFN. With their buffers shut down, these pins become high impedance and can be driven by external reference sources. Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines. The MAX1446 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50% must meet the specifications for high and low periods as stated in the Electrical Characteristics. See Figures 3a, 3b, 4a, and 4b for the relationship between spurious-free dynamic range (SFDR), signal-to-noise ratio (SNR), total harmonic distortion (THD), or signal-to-noise plus distortion (SINAD) vs. duty cycle. Output Enable (OE), Power-Down (PD), and Output Data (D0–D9) All data outputs, D0 (LSB) through D9 (MSB), are TTL/CMOS-logic compatible. There is a 5.5 clock-cycle latency between any particular sample and its valid output data. The output coding is straight offset binary (Table 1). With OE and PD (power-down) high, the digital output enters a high-impedance state. If OE is held low with PD high, the outputs are latched at the last value prior to the power-down. The capacitive load on the digital outputs D0–D9 should be kept as low as possible (< 15pF) to avoid large digital currents that could feed back into the analog portion of the MAX1446, degrading its dynamic performance. The use of buffers on the ADC’s digital outputs can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1446 small series resistors (e.g., 100Ω) may be added to the digital output paths, close to the ADC. Figure 5 displays the timing relationship between output enable and data output valid, as well as powerdown/wake-up and data output valid. Clock Input (CLK) The MAX1446 CLK input accepts CMOS-compatible clock signals. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). In particular, sampling occurs on the falling edge of the clock signal, mandating this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the ADC as follows: ⎛ ⎞ 1 SNR = 20 × log⎜ ⎟ ⎝ 2 × π × fIN × t AJ ⎠ where fIN represents the analog input frequency, and tAJ is the time of the aperture jitter. System Timing Requirements Figure 6 shows the relationship between the clock input, analog input, and data output. The MAX1446 Table 1. MAX1446 Output Code for Differential Inputs DIFFERENTIAL INPUT VOLTAGE* VREF × 511/512 VREF × 510/512 VREF × 1/512 0 - VREF × 1/512 - VREF × 511/512 - VREF × 512/512 DIFFERENTIAL INPUT +Full Scale -1LSB +Full Scale -2LSB +1LSB Bipolar Zero -1LSB Negative Full Scale + 1LSB Negative Full Scale STRAIGHT OFFSET BINARY 11 1111 1111 11 1111 1110 10 0000 0001 10 0000 0000 01 1111 1111 00 0000 0001 00 0000 0000 *VREFIN = VREFP = VREFN 12 ______________________________________________________________________________________ 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446 80 fIN = 12.5MHz AT -0.5dBFS 70 SFDR (dBc) THD (dBc) -50 -40 fIN = 12.5MHz AT -0.5dBFS 60 -60 50 -70 40 20 30 40 50 60 70 CLOCK DUTY CYCLE (%) -80 20 30 40 50 60 70 CLOCK DUTY CYCLE (%) Figure 3a. SFDR vs. Clock Duty Cycle (Differential Input) Figure 4a. THD vs. Clock Duty Cycle (Differential Input) 70 fIN = 12.5MHz AT -0.5dBFS 65 60 SINAD (dB) SNR (dB) 55 50 45 40 20 30 40 50 60 70 CLOCK DUTY CYCLE (%) 70 fIN = 12.5MHz AT -0.5dBFS 65 60 55 50 45 40 20 30 40 50 60 70 CLOCK DUTY CYCLE (%) Figure 3b. SNR vs. Clock Duty Cycle (Differential Input) Figure 4b. SINAD vs. Clock Duty Cycle (Differential Input) OE tENABLE OUTPUT DATA D9–D0 HIGH-Z tDISABLE HIGH-Z VALID DATA Figure 5. Output Enable Timing ______________________________________________________________________________________ 13 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446 samples at the falling edge of the input clock. Output data is valid on the rising edge of the input clock. The output data has an internal latency of 5.5 clock cycles. Figure 6 also shows the relationship between the input clock parameters and the valid output data. driver, such as an op amp, may also improve the overall distortion. In general, the MAX1446 provides better SFDR and THD with fully differential input signals than singleended drive, especially for very high input frequencies. In differential input mode, even-order harmonics are lower since both inputs (IN+, IN-) are balanced, and each of the inputs only requires half the signal swing compared to single-ended mode. Applications Information Figure 7 shows a typical application circuit containing a single-ended to differential converter. The internal reference provides a VDD/2 output voltage for level shifting purposes. The input is buffered and then split to a voltage follower and inverter. A lowpass filter follows the op amps to suppress some of the wideband noise associated with high-speed op amps. The user may select the RISO and CIN values to optimize the filter performance to suit a particular application. For the application in Figure 7, an RISO of 50Ω is placed before the capacitive load to prevent ringing and oscillation. The 22pF CIN capacitor acts as a small bypassing capacitor. Single-Ended AC-Coupled Input Signal Figure 9 shows an AC-coupled, single-ended application. The MAX4108 op amp provides high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal. Buffered External Reference Drives Multiple ADCs Multiple-converter systems based on the MAX1446 are well suited for use with a common reference voltage. The REFIN pin of those converters can be connected directly to an external reference source. A precision bandgap reference like the MAX6062 generates an external DC level of 2.048V (Figure 10), and exhibits a noise voltage density of 150n√Hz. Its output passes through a 1-pole lowpass filter (with 10Hz cutoff frequency) to the MAX4250, which buffers the reference before its output is applied to a second 10Hz lowpass Using Transformer Coupling An RF transformer (Figure 8) provides an excellent solution for converting a single-ended source signal to a fully differential signal, required by the MAX1446 for optimum performance. Connecting the transformer’s center tap to COM provides a VDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a stepup transformer may be selected to reduce the drive requirements. A reduced signal swing from the input 5.5 CLOCK-CYCLE LATENCY N N+1 N+2 N+3 N+4 N+5 N+6 ANALOG INPUT CLOCK INPUT tDO N-6 N-5 N-4 N-3 N-2 N-1 N N+1 DATA OUTPUT Figure 6. System and Output Timing Diagram 14 ______________________________________________________________________________________ 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446 5V 0.1μF LOWPASS FILTER IN+ RISO 50Ω CIN 22pF MAX4108 300Ω 0.1μF -5V 0.1μF MAX1446 600Ω 300Ω 600Ω COM 0.1μF 5V 5V 0.1μF INPUT MAX4108 600Ω 0.1μF 300Ω 0.1μF LOWPASS FILTER INRISO 50Ω 0.1μF CIN 22pF MAX4108 -5V 300Ω -5V 300Ω 300Ω 600Ω Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion 25Ω IN+ 22pF 0.1μF VIN 3 N.C. 5 1 T1 MAX1446 4 MAX4108 VIN 0.1μF 1kΩ RISO IN+ 100Ω 1kΩ CIN REFP 2 6 2.2μF 0.1μF COM MAX1446 COM 0.1μF RISO REFN MINI-CIRCUITS ADT1–1WT 25Ω IN22pF RISO = 50Ω CIN = 22pF 100Ω INCIN Figure 8. Using a Transformer for AC-Coupling Figure 9. Single-Ended AC-Coupled Input 15 ______________________________________________________________________________________ 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446 3.3V 0.1μF 0.1μF 1 2 16.2kΩ 1μF 3 10Hz LOWPASS FILTER 3 3.3V N.C. 2.048V 0.1μF 5 MAX4250 2 1 100μF 10Hz LOWPASS FILTER 0.1μF 0.1μF 0.1μF 29 31 32 1 162Ω 2 REFOUT REFIN REFP MAX1446 N=1 REFN COM MAX6062 4 0.1μF N.C. 29 31 32 1 0.1μF 0.1μF 0.1μF 2 0.1μF 2.2μF 10V REFOUT REFIN REFP MAX1446 N = 1000 REFN COM NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs. Figure 10. Buffered External Reference Drives Up to 1000 ADCs filter. The MAX4250 provides a low offset voltage (for high-gain accuracy) and a low noise level. The passive 10Hz filter following the buffer attenuates noise produced in the voltage reference and buffer stages. This filtered noise density, which decreases for higher frequencies, meets the noise levels specified for precision ADC operation. Unbuffered External Reference Drives Multiple ADCs Connecting each REFIN to analog ground disables the internal reference of each device, allowing the internal reference ladders to be driven directly by a set of external reference sources. Followed by a 10Hz lowpass filter and precision voltage-divider (Figure 11), the MAX6066 generates a DC level of 2.500V. The buffered outputs of this divider are set to 2.0V, 1.5V, and 1.0V, with an accuracy that depends on the tolerance of the divider resistors. The three voltages are buffered by the 16 MAX4252, which provides low noise and low DC offset. The individual voltage followers are connected to 10Hz lowpass filters, which filter both the reference voltage and amplifier noise to a level of 3n√Hz. The 2.0V and 1.0V reference voltages set the differential full-scale range of the associated ADCs at 2VP-P. The 2.0V and 1.0V buffers drive the ADC’s internal ladder resistances between them. Note that the common power supply for all active components removes any concern regarding power-supply sequencing when powering up or down. With the outputs of the MAX4252 matching better than 0.1%, the buffers and subsequent lowpass filters can be replicated to support as many as 32 ADCs. For applications that require more than 32 matched ADCs, a voltage reference and divider string common to all converters is highly recommended. ______________________________________________________________________________________ 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446 3.3V 0.1μF N.C. 29 31 1 2 21.5kΩ 2.0V 3 4 1 1/4 MAX4252 REFOUT REFIN REFP MAX1446 3.3V 2.0V AT 8mA 47Ω 32 1 2 N=1 REFN COM MAX6066 3 21.5kΩ 2 11 10μF 6V 1.47kΩ 330μF 6V 0.1μF 0.1μF 0.1μF 1μF 1.5V 5 4 7 1/4 MAX4252 3.3V 1.5V AT 0mA 47Ω 3.3V 0.1μF 21.5kΩ MAX4254 POWER-SUPPLY BYPASSING. PLACE CAPACITOR AS CLOSE AS POSSIBLE TO THE OP AMP. 6 11 10μF 6V 1.47kΩ 330μF 6V 1.0V 10 4 8 1/4 MAX4252 3.3V 1.0V AT -8mA 47Ω 0.1μF 330μF 6V N.C. 29 31 32 1 2 0.1μF 0.1μF 0.1μF 2.2μF 10V 21.5kΩ 9 11 10μF 6V 1.47kΩ REFOUT REFIN REFP MAX1446 21.5kΩ N = 32 REFN COM NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 32 ADCs. Figure 11. Unbuffered External Reference Drives Up to 32 ADCs Grounding, Bypassing, __________________and Board Layout The MAX1446 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass VDD, REFP, REFN, and COM with two parallel 0.1µF ceramic capacitors and a 2.2µF bipolar capacitor to GND. Follow the same rules to bypass the digital supply (OVDD) to OGND. Multilayer boards with separated ground and power planes pro- duce the highest level of signal integrity. Consider using a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADC's package. The two ground planes should be joined at a single point so that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes that produces optimum results. Make this connection with a low-value, surface-mount resistor (1Ω to 5Ω), a ferrite bead, or a direct short. Alternatively, all 17 ______________________________________________________________________________________ 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446 ground pins could share the same ground plane if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from sensitive analog traces. Keep all signal lines short and free of 90° turns. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB is computed from: ENOB = (SINAD − 1.76) 6.02 Static Parameter Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function once offset and gain errors have been nullified. The MAX1446’s static linearity parameters are measured using the best-straight-line fit method. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. Total Harmonic Distortion (THD) THD is typically the ratio of the rms sum of the input signal’s first four harmonics to the fundamental itself. This is expressed as: ⎛ V 2 +V 2 +V 2 +V 2 2 3 4 5 THD = 20 × log ⎜ ⎜ V1 ⎝ ⎞ ⎟ ⎟ ⎠ where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Dynamic Parameter Definitions Aperture Jitter Figure 12 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Aperture Delay Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 12). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). The ideal, theoretical minimum A/D noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR(MAX) = 6.02 x N + 1.76 In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal component) to the rms value of the next largest spurious component, excluding DC offset. Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -6.5dB full scale. CLK ANALOG INPUT tAD tAJ SAMPLED DATA (T/H) Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the rms signal to all spectral components minus the fundamental and the DC offset. T/H TRACK HOLD TRACK Figure 12. T/H Aperture Timing 18 ______________________________________________________________________________________ 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference Pin Configurations (continued) REFOUT MAX1446 TOP VIEW REFIN REFP GND D0 D1 D2 26 32 REFN COM VDD GND GND IN+ INGND 1 2 3 4 5 6 7 8 9 VDD 31 30 29 28 27 D3 25 24 D4 23 OGND 22 T.P. 21 OVDD 20 D5 19 D6 18 D7 17 D8 16 D9 MAX1446 10 VDD 11 GND 12 CLK 13 PD 14 GND 15 OE TQFP Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 32 TQFP PACKAGE CODE H32-2F DOCUMENT NO. 21-0110 ______________________________________________________________________________________ 19 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446 Revision History REVISION NUMBER 3 4 REVISION DATE 11/07 11/08 DESCRIPTION Various corrections; updated to extended temperature range for automotive applications; replaced TOCs 9–20, 23, 24, 26, 30, 31, 33; updated package outlines. Updates to the Electrical Characteristics table and notes section. PAGES CHANGED 1–9, 15, 18, 20, 21 5, 14 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2008 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.