MAX1448

19-5400; Rev 2; 5/04 KIT ATION EVALU ILABLE AVA 10-Bit, 80Msps, Single 3.0V, Low-Power ADC with Internal Reference General Description The MAX1448 3V, 10-bit analog-to-digital converter (ADC) features a fully differential input, a pipelined 10stage ADC architecture with wideband track-and-hold (T/H), and digital error correction incorporating a fully differential signal path. The ADC is optimized for lowpower, high dynamic performance in imaging and digital communications applications. The converter operates from a single 2.7V to 3.6V supply, consuming only 120mW while delivering a 59dB (typ) signal-tonoise ratio (SNR) at a 20MHz input frequency. The fully differential input stage has a -3dB 400MHz bandwidth and may be operated with single-ended inputs. In addition to low operating power, the MAX1448 features a 5µA power-down mode for idle periods. An internal 2.048V precision bandgap reference is used to set the ADC full-scale range. A flexible reference structure allows the user to supply a buffered, direct, or externally derived reference for applications requiring increased accuracy or a different input voltage range. Lower speed, pin-compatible versions of the MAX1448 are also available. Refer to the MAX1444 data sheet for a 40Msps version and to the MAX1446 data sheet for a 60Msps version. The MAX1448 has parallel, offset binary, CMOS-compatible three-state outputs that can be operated from 1.7V to 3.6V to allow flexible interfacing. The device is available in a 5mm x 5mm 32-pin TQFP package and is specified over the extended industrial (-40°C to +85°C) temperature range. o Single 3.0V Operation o Excellent Dynamic Performance 59dB SNR at fIN = 20MHz 74dBc SFDR at fIN = 20MHz o Low Power 40mA (Normal Operation) 5µA (Shutdown Mode) o Fully Differential Analog Input o Wide 2VP-P Differential Input Voltage Range o 400MHz -3dB Input Bandwidth o On-Chip 2.048V Precision Bandgap Reference o CMOS-Compatible Three-State Outputs o 32-Pin TQFP Package o Evaluation Kit Available (MAX1448 EV Kit) Features MAX1448 Ordering Information PART MAX1448EHJ TEMP RANGE -40°C to +85°C PIN-PACKAGE 32 TQFP Functional Diagram ________________________Applications Ultrasound Imaging CCD Imaging Baseband and IF Digitization Digital Set-Top Boxes Video Digitizing Applications CLK MAX1448 CONTROL VDD GND IN+ T/H INPIPELINEADC D E C 10 OUTPUT DRIVERS D9–D0 PD REF REFSYSTEM+ BIAS OVDD OGND REFOUT REFIN REFP COM REFN OE Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 10-Bit, 80Msps, Single 3.0V, Low-Power ADC with Internal Reference MAX1448 ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V IN+, IN- to GND........................................................-0.3V to VDD REFIN, REFOUT, REFP, REFN, and COM to GND..........................-0.3V to (VDD + 0.3V) OE, PD, CLK to GND..................................-0.3V to (VDD + 0.3V) D9–D0 to GND.........................................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 32-Pin TQFP (derate 18.7mW/°C above +70°C)......1495.3mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range ............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3.0V, OVDD = 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND, VREFIN = 2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 83.3MHz, TA = TMIN to TMAX, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical values are at TA = +25°C.) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT Input Differential Range Common-Mode Voltage Range Input Resistance Input Capacitance CONVERSION RATE Maximum Clock Frequency Data Latency DYNAMIC CHARACTERISTICS (fCLK = 83.3MHz, 4096-point FFT) fIN = 7.47MHz Signal-to-Noise Ratio SNR fIN = 20MHz fIN = 39.9MHz (Note 1) Signal-to-Noise + Distortion (Up to 5th Harmonic) fIN = 7.47MHz SINAD fIN = 20MHz fIN = 39.9MHz (Note 1) 55.8 55.3 56.5 56 59.1 59 58.5 59 58.8 58 dB dB fCLK 80 5.5 MHz Cycles VDIFF VCOM RIN CIN Switched capacitor load Differential or single-ended inputs ±1.0 VDD/2 ± 0.5 25 5 V V kΩ pF TA ≥ +25°C INL DNL fIN = 7.47MHz, TA ≥ +25°C fIN = 7.47MHz, no missing codes 10 ±0.7 ±0.4 50 5 1.07 V V V V MΩ mA V ppm/°C mV/mA IN+ = IN- = COM FPBW tAD tAJ For 1.5 × full-scale input HD3 fIN = 20MHz fIN = 39.9MHz (Note 1) IMDTT IM3 f1 = 24MHz at -6.5dB FS, f2 = 26MHz at -6.5dB FS (Note 2) f1 = 24MHz at -6.5dB FS, f2 = 26MHz at -6.5dB FS (Note 2) fIN = 7.47MHz THD fIN = 20MHz fIN = 39.9MHz (Note 1) Input at -20dB FS, differential inputs Input at -0.5dB FS, differential inputs CONDITIONS MIN 61 61 TYP 74 74 73 -74 -74 -73 -74 -74 -72 -70 -69 500 400 1 2 2 ±1 ±0.25 0.2 MHz MHz ns psRMS ns % Degrees LSBRMS -60 -60 dBc dBc dBc dBc dBc MAX UNITS MAX1448 BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V) _______________________________________________________________________________________ 3 10-Bit, 80Msps, Single 3.0V, Low-Power ADC with Internal Reference MAX1448 ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND, VREFIN = 2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 83.3MHz, TA = TMIN to TMAX, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical values are at TA = +25°C.) PARAMETER Maximum REFP, COM Sink Current Maximum REFN Source Current Maximum REFN Sink Current SYMBOL ISINK ISOURCE ISINK RREFP, RREFN CIN ∆VREF VCOM VREFP VREFN ∆VREF = VREFP - VREFN Measured between REFP and COM and REFN and COM CONDITIONS MIN TYP -250 250 -5 MAX UNITS µA µA mA UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM ) REFP, REFN Input Resistance REFP, REFN, COM Input Capacitance Differential Reference Input Voltage Range COM Input Voltage Range REFP Input Voltage REFN Input Voltage DIGITAL INPUTS (CLK, PD, OE) CLK Input High Threshold VIH PD, OE CLK Input Low Threshold VIL PD, OE Input Hysteresis Input Leakage VHYST IIH IIL VIH = VDD = OVDD VIL = 0 CLK Input Low Threshold VIL PD, OE Input Hysteresis Input Leakage Input Capacitance VHYST IIH IIL CIN VIH = VDD = OVDD VIL = 0 5 0.1 ±5 ±5 0.1 ±5 ±5 0.2 x VDD 0.2 x OVDD V µA pF 0.8 x VDD 0.8 x OVDD 0.2 x VDD 0.2 x OVDD V µA 4 15 1.024 ± 10% VDD / 2 ± 10% VCOM+ ∆VREF / 2 VCOM ∆VREF / 2 kΩ pF V V V V V V V 4 _______________________________________________________________________________________ 10-Bit, 80Msps, Single 3.0V, Low-Power ADC with Internal Reference MAX1448 ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND, VREFIN = 2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 83.3MHz, TA = TMIN to TMAX, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical values are at TA = +25°C.) PARAMETER DIGITAL OUTPUTS (D9–D0) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Output Supply Voltage Analog Supply Current VDD OVDD IVDD Operating, fIN = 20MHz at -0.5dB FS Shutdown, clock idle, PD = OE = OVDD Operating, CL = 15pF, fIN = 20MHz at -0.5dB FS Shutdown, clock idle, PD = OE = OVDD Power-Supply Rejection TIMING CHARACTERISTICS CLK Rise to Output Data Valid OE Fall to Output Enable OE Rise to Output Disable CLK Pulse Width High CLK Pulse Width Low Wake-Up Time tDO tENABLE tDISABLE tCH tCL tWAKE Figure 6 (Note 3) Figure 5 Figure 5 Figure 6, clock period 12ns Figure 6, clock period 12ns (Note 4) 5 10 15 6±1 6±1 1.5 8 ns ns ns ns ns µs PSRR Offset Gain 2.7 1.7 3.0 3.0 40 4 8 1 ±0.2 ±0.1 20 3.6 3.6 47 15 V V mA µA mA µA mV/V %/V VOL VOH ILEAK COUT ISINK = 200µA ISOURCE = 200µA OE = OVDD OE = OVDD 5 OVDD 0.2 ±10 0.2 V V µA pF SYMBOL CONDITIONS MIN TYP MAX UNITS Output Supply Current IOVDD Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a 1.024V full-scale input voltage range. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is 6dB better if referenced to the two-tone envelope. Note 3: Digital outputs settle to VIH,VIL. Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down. _______________________________________________________________________________________ 5 10-Bit, 80Msps, Single 3.0V, Low-Power ADC with Internal Reference MAX1448 Typical Operating Characteristics (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dB FS, fCLK = 83.3MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) FFT PLOT (fIN = 7.5MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) MAX1448-01 FFT PLOT (fIN = 20MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) MAX1448-02 UNDERSAMPLING FFT PLOT (fIN = 50MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 2ND HARMONIC 3RD HARMONIC SFDR = 65.8dBc SNR = 58dB THD = -65.1dBc SINAD = 57.2dB MAX1448-03 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 25 SFDR = 75.5dBc SNR = 59.3dB THD = -73.9dBc SINAD = 59.2dB 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 CARRIER 0 SFDR = 75.2dBc SNR = 59dB THD = -71.8dBc SINAD = 58.7dB 2ND HARMONIC 3RD HARMONIC 2ND HARMONIC 3RD HARMONIC 30 35 40 45 0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 35 40 45 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) FFT PLOT (fIN = 7.5MHz, 8192-POINT FFT, SINGLE-ENDED INPUT) MAX1448-04 FFT PLOT (fIN = 20MHz, 8192-POINT FFT, SINGLE-ENDED INPUT) MAX1448-05 TWO-TONE INTERMODULATION (8192-POINT IMD, DIFFERENTIAL INPUT) -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 f1 = 24MHz AT -6.5dB FS f2 = 26MHz AT -6.5dB FS 3RD IMD = -74dBc MAX1448-06 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 25 SFDR = 72.2dBc SNR = 58.7dB THD = -70.8dBc SINAD = 58.4dB 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 CARRIER SFDR = 67.2dBc SNR = 58.6dB THD = -66.5dBc SINAD = 58dB 0 2ND HARMONIC 3RD HARMONIC 2ND HARMONIC 3RD HARMONIC 30 35 40 45 0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 35 40 45 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY MAX1448-07 SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY 61 60 THD (dBc) SNR (dB) 59 58 57 56 55 54 -75 -80 1 10 ANALOG INPUT FREQUENCY (MHz) 100 1 SINGLE ENDED DIFFERENTIAL -60 -65 MAX1448-08 TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY MAX1448-09 80 75 70 SFDR (dBc) 65 60 55 50 45 40 1 10 ANALOG INPUT FREQUENCY (MHz) SINGLE ENDED DIFFERENTIAL 62 -50 -55 SINGLE ENDED -70 DIFFERENTIAL 100 10 ANALOG INPUT FREQUENCY (MHz) 100 6 _______________________________________________________________________________________ 10-Bit, 80Msps, Single 3.0V, Low-Power ADC with Internal Reference Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dB FS, fCLK = 83.3MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) FULL-POWER INPUT BANDWIDTH SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY vs. ANALOG INPUT FREQUENCY SIGNAL-TO-NOISE + DISTORTION vs. ANALOG INPUT FREQUENCY (SINGLE-ENDED) (SINGLE-ENDED) MAX1448-11 MAX1448-10 MAX1448 VIN = 100mVp-p 4 2 AMPLITUDE (dB) 4 2 AMPLITUDE (dB) 0 -2 -4 -6 -8 62 SINAD (dB) 59 DIFFERENTIAL SINGLE ENDED 0 -2 -4 56 53 -6 50 1 10 ANALOG INPUT FREQUENCY (MHz) 100 -8 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz) 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz) SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER (fIN = 20MHz) MAX1448-13 SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER (fIN = 20MHz) MAX1448-14 TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER (fIN = 20MHz) MAX1448-15 80 75 70 SFDR (dBc) 65 -50 -55 -60 60 SNR (dB) 55 THD (dBc) 65 60 55 50 -15 -12 -9 -6 -3 0 ANALOG INPUT POWER (dB FS) -65 -70 50 45 -75 -80 -15 -12 -9 -6 -3 0 -15 -12 -9 -6 -3 0 ANALOG INPUT POWER (dB FS) ANALOG INPUT POWER (dB FS) 40 SIGNAL-TO-NOISE + DISTORTION vs. ANALOG INPUT POWER (fIN = 20MHz) MAX1448-16 SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE MAX1448-17 SIGNAL-TO-NOISE RATIO vs. TEMPERATURE fIN = 20MHz MAX1448-18 65 84 fIN = 20MHz 70 60 SINAD (dB) SFDR (dBc) 80 66 50 72 SNR (dB) 55 76 62 58 45 68 54 40 -15 -12 -9 -6 -3 0 ANALOG INPUT POWER (dB FS) 64 -40 -15 10 35 60 85 TEMPERATURE (°C) 50 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 7 MAX1448-12 65 6 6 10-Bit, 80Msps, Single 3.0V, Low-Power ADC with Internal Reference MAX1448 Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dB FS, fCLK = 83.3MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY TOTAL HARMONIC DISTORTION SIGNAL-TO-NOISE + DISTORTION vs. DIGITAL OUTPUT CODE vs. TEMPERATURE vs. TEMPERATURE (BEST STRAIGHT LINE) MAX1448-19 MAX1448-20 fIN = 20MHz fIN = 20MHz 0.6 0.4 -64 SINAD (dB) 66 THD (dBc) INL (LSB) -68 62 0.2 0 -0.2 -72 58 -76 54 -0.4 -80 -40 -15 10 35 60 85 TEMPERATURE (°C) 50 -40 -15 10 35 60 85 TEMPERATURE (°C) -0.6 0 200 400 600 800 1000 1200 DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE MAX1448-22 GAIN ERROR vs. TEMPERATURE EXTERNAL REFERENCE (VREFIN = 2.048V) MAX1448-23 OFFSET ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = 2.048V) MAX1448-24 0.4 0.3 0.2 0.05 0.04 0.03 GAIN ERROR (LSB) 0.02 0.01 0 -0.01 -0.02 3 2 OFFSET ERROR (LSB) 1 0 -1 -2 -3 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 0 200 400 600 800 1000 1200 DIGITAL OUTPUT CODE -0.03 -0.04 -0.05 -40 -15 10 35 60 85 TEMPERATURE (°C) -40 -15 10 35 60 85 TEMPERATURE (°C) ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE MAX1448-25 ANALOG SUPPLY CURRENT vs. TEMPERATURE MAX1448-26 DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE fIN = 7.5MHz MAX1448-27 47 47 12 45 44 10 IVDD (mA) IVDD (mA) 43 41 IOVDD (mA) 8 41 38 6 39 35 4 37 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 32 -40 -15 10 35 60 85 TEMPERATURE (°C) 2 1.6 2.0 2.4 2.8 3.2 3.6 OVDD (V) 8 _______________________________________________________________________________________ MAX1448-21 -60 70 0.8 10-Bit, 80Msps, Single 3.0V, Low-Power ADC with Internal Reference MAX1448 Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dB FS, fCLK = 83.3MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) DIGITAL SUPPLY CURRENT vs. TEMPERATURE MAX1448-28 ANALOG POWER-DOWN CURRENT vs. ANALOG POWER SUPPLY MAX1448-29 DIGITAL POWER-DOWN CURRENT vs. DIGITAL POWER SUPPLY PD = VDD, OE = OVDD MAX1448-30 12 fIN = 7.5MHz 6 OE = OVDD, PD = VDD 10 10 5 8 IOVDD (mA) IOVDD (µA) 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 IVDD (µA) 8 4 6 6 3 4 4 2 2 2 -40 -15 10 35 60 85 TEMPERATURE (°C) 1 0 1.2 1.8 2.4 OVDD (V) 3.0 3.6 SNR/SINAD, THD/SFDR vs. CLOCK FREQUENCY MAX1448-31 INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE MAX1448-32 85 SNR/SINAD, THD/SFDR (dB, dBc) 80 75 fIN = 25.12MHz 2.10 2.08 VREFOUT (V) SNR SINAD 2.02 90 95 100 SFDR THD 70 65 60 55 50 70 2.06 2.04 2.00 75 80 85 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 CLOCK FREQUENCY (MHz) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX1448-33 OUTPUT NOISE HISTOGRAM (DC INPUT) 129377 MAX1448-34 2.10 140000 120000 100000 2.08 VREFOUT (V) COUNTS 2.06 80000 60000 40000 2.04 2.02 20000 2.00 -40 -15 10 35 60 85 TEMPERATURE (°C) 0 0 N-2 965 N-1 N 730 N+1 0 N+2 DIGITAL OUTPUT NOISE _______________________________________________________________________________________ 9 10-Bit, 80Msps, Single 3.0V, Low-Power ADC with Internal Reference MAX1448 Pin Description PIN 1 2 3, 9, 10 4, 5, 8, 11, 14, 30 6 7 12 13 NAME REFN COM VDD GND IN+ INCLK PD FUNCTION Lower Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a >0.1µF capacitor. Common-Mode Voltage Output. Bypass to GND with a >0.1µF capacitor. Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. Analog Ground Positive Analog Input. For single-ended operation, connect signal source to IN+. Negative Analog Input. For single-ended operation, connect IN- to COM. Conversion Clock Input Power-Down Input High: power-down mode Low: normal operation Output Enable Input High: digital outputs disabled Low: digital outputs enabled Three-State Digital Outputs D9–D5. D9 is the MSB. Output Driver Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. Test Point. Do not connect. Output Driver Ground Three-State Digital Outputs D4–D0. D0 is the LSB. Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor-divider. Reference Input. VREFIN = 2 × (VREFP - VREFN). Bypass to GND with a >0.1µF capacitor. Upper Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a >0.1µF capacitor. 15 16–20 21 22 23 24–28 29 31 32 OE D9–D5 OVDD T.P. OGND D4–D0 REFOUT REFIN REFP 10 ______________________________________________________________________________________ 10-Bit, 80Msps, Single 3.0V, Low-Power ADC with Internal Reference _______________Detailed Description The MAX1448 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage every half clock-cycle. Counting the delay through the output latch, the clock-cycle latency is 5.5. A 1.5-bit (2-comparator) flash ADC converts the held input voltage into a digital code. The following digitalto-analog converter (DAC) converts the digitized result back into an analog voltage, which is then subtracted from the original held input signal. The resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage where the process is repeated. Each stage provides a 1-bit resolution. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. neously with S1, sampling the input waveform. S4a and S4b are then opened before S3a and S3b connect capacitors C1a and C1b to the amplifier output, and S4c is closed. The resulting differential voltage is held on C2a and C2b. The amplifier is used to charge C1a and C1b to the same values originally held on C2a and C2b. This value is then presented to the first-stage quantizer and isolates the pipeline from the fast-changing input. The wide-input-bandwidth T/H amplifier allows the MAX1448 to track and sample/hold analog inputs of high frequencies beyond Nyquist. Analog inputs (IN+ and IN-) can be driven either differentially or single-ended. It is recommended to match the impedance of IN+ and IN- and set the common-mode voltage to midsupply (VDD/2) for optimum performance. MAX1448 Analog Input and Reference Configuration The MAX1448 full-scale range is determined by the internally generated voltage difference between REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The ADC’s full-scale range is user-adjustable through the REFIN pin, which provides a high input impedance for this purpose. REFOUT, REFP, COM (VDD/2), and REFN are internally buffered, low-impedance outputs. INTERNAL BIAS S2a C1a Input Track-and-Hold Circuit Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuit in both track and hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuit samples the input signal onto the two capacitors (C2a and C2b) through S4a and S4b. S2a and S2b set the common mode for the amplifier input and open simultaMDAC VIN T/H Σ x2 VOUT COM S5a S3a S4a IN+ OUT C2a S4c S1 OUT S4b C2b C1b FLASH ADC 1.5 BITS DAC IN- VIN STAGE 1 STAGE 2 STAGE 10 S2b INTERNAL BIAS TRACK HOLD TRACK HOLD CLK INTERNAL NON OVERLAPPING CLOCK SIGNALS S5b COM S3b DIGITAL CORRECTION LOGIC 10 D9–D0 VIN = INPUT VOLTAGE BETWEEN IN+ AND IN- (DIFFERENTIAL OR SINGLE ENDED) Figure 1. Pipelined Architecture—Stage Blocks Figure 2. Internal Track-and-Hold Circuit 11 ______________________________________________________________________________________ 10-Bit, 80Msps, Single 3.0V, Low-Power ADC with Internal Reference MAX1448 The MAX1448 provides three modes of reference operation: • Internal reference mode • Buffered external reference mode • Unbuffered external reference mode In internal reference mode, the internal reference output (REFOUT) can be tied to the REFIN pin through a resistor (e.g., 10kΩ) or resistor-divider if an application requires a reduced full-scale range. For stability purposes, it is recommended to bypass REFIN with a >10nF capacitor to GND. In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a stable and accurate voltage at REFIN. In this mode, REFOUT may be left open or connected to REFIN through a >10kΩ resistor. In unbuffered external reference mode, REFIN is connected to GND, thereby deactivating the on-chip buffers of REFP, COM, and REFN. With their buffers shut down, these pins become high impedance and can be driven by external reference sources. Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines. The MAX1448 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50% must meet the specifications for high and low periods as stated in the Electrical Characteristics. See Figures 3a, 3b, 4a, and 4b for the relationship between spurious-free dynamic range (SFDR), signal-to-noise ratio (SNR), total harmonic distortion (THD), or signal-to-noise plus distortion (SINAD) versus duty cycle. Output Enable (OE), Power Down (PD), and Output Data (D0–D9) All data outputs, D0 (LSB) through D9 (MSB), are TTL/CMOS-logic compatible. There is a 5.5 clock-cycle latency between any particular sample and its valid output data. The output coding is straight offset binary (Table 1). With OE and PD high, the digital outputs enter a high-impedance state. If OE is held low with PD high, the outputs are latched at the last value prior to the power down. The capacitive load on the digital outputs D0 – D9 should be kept as low as possible (