MAX1449

19-4802; Rev 0; 10/00 ILABLE N KIT AVA EVALUATIO 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference General Description The MAX1449 +3.3V, 10-bit analog-to-digital converter (ADC) features a fully differential input, a pipelined 10stage ADC architecture with wideband track-and-hold (T/H), and digital error correction incorporating a fully differential signal path. The ADC is optimized for lowpower, high-dynamic performance in imaging and digital communications applications. The converter operates from a single +2.7V to +3.6V supply, consuming only 186mW while delivering a 58.5dB (typ) signalto-noise ratio (SNR) at a 20MHz input frequency. The fully differential input stage has a -3dB 400MHz bandwidth and may be operated with single-ended inputs. In addition to low operating power, the MAX1449 features a 5µA power-down mode for idle periods. An internal +2.048V precision bandgap reference is used to set the ADC’s full-scale range. A flexible reference structure allow’s the user to supply a buffered, direct, or externally derived reference for applications requiring increased accuracy or a different input voltage range. Lower speed, pin-compatible versions of the MAX1449 are also available. Refer to the MAX1444 data sheet for a 40Msps version, the MAX1446 data sheet for a 60Msps version, and the MAX1448 data sheet for 80Msps. The MAX1449 has parallel, offset binary, CMOS-compatible, three-state outputs that can be operated from +1.7V to +3.6V to allow flexible interfacing. The device is available in a 5mm x 5mm 32-pin TQFP package and is specified over the extended industrial (-40°C to +85°C) temperature range. o Single +3.3V Operation o Excellent Dynamic Performance 58.5dB SNR at fIN = 20MHz 72dBc SFDR at fIN = 20MHz o Low Power 62mA (Normal Operation) 5µA (Shutdown Mode) o Fully Differential Analog Input o Wide 2Vp-p Differential Input Voltage Range o 400MHz -3dB Input Bandwidth o On-Chip +2.048V Precision Bandgap Reference o CMOS-Compatible Three-State Outputs o 32-Pin TQFP Package o Evaluation Kit Available Features MAX1449 Ordering Information PART MAX1449EHJ TEMP. RANGE -40°C to +85°C PIN-PACKAGE 32 TQFP Pin-Compatible, Lower Speed Selection Table PART NUMBER MAX1444 MAX1446 MAX1448 SAMPLING SPEED 40Msps 60Msps 80Msps ________________________Applications Ultrasound Imaging CCD Imaging Baseband and IF Digitization Digital Set-Top Boxes Video Digitizing Applications IN+ CLK Functional Diagram MAX1449 CONTROL VDD GND T/H IN- PIPELINE ADC D E C 10 OUTPUT DRIVERS D9–D0 PD REF REF SYSTEM + BIAS OVDD OGND Pin Configuration appears at end of data sheet. REFOUT REFIN REFP COM REFN OE ________________________________________________________________ Maxim Integrated Products 1 For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference MAX1449 ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V IN+, IN- to GND........................................................-0.3V to VDD REFIN, REFOUT, REFP, REFN, and COM to GND..........................-0.3V to (VDD + 0.3V) OE, PD, CLK to GND..................................-0.3V to (VDD + 0.3V) D9–D0 to GND.........................................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 32-Pin TQFP (derate 11.1mW/°C above +70°C)...........889mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range ............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +3.3V, OVDD = +2.0V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = +2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 105MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT Input Differential Range Common-Mode Voltage Range Input Resistance Input Capacitance CONVERSION RATE Maximum Clock Frequency Data Latency DYNAMIC CHARACTERISTICS (fCLK = 105.26MHz, 4096-point FFT) Signal-To-Noise Ratio (Note 1) fIN = 7.5MHz SNR fIN = 20MHz fIN = 50MHz Signal-To-Noise And Distortion (Up to 5th Harmonic) (Note 1) fIN = 7.5MHz SINAD fIN = 20MHz fIN = 50MHz Spurious-Free Dynamic Range (Note 1) fIN = 7.5MHz SFDR fIN = 20MHz, TA = +25°C fIN = 50MHz 61 63 55.3 55.1 56.3 55.8 58.5 58.5 58 58.2 58.1 57.6 72 72 70 dBc dB dB fCLK 105 5.5 MHz Cycles VDIFF VCOM RIN CIN Switched capacitor load Differential or single-ended inputs ±1.0 VDD/2 ± 0.5 20 5 V V kΩ pF INL DNL fIN = 7.5MHz fIN = 7.5MHz, no missing codes guaranteed 10 ±0.75 ±0.5 < ±1 0 ±2.4 ±1.0 ±1.7 ±2 Bits LSB LSB % FS % FS SYMBOL CONDITIONS MIN TYP MAX UNITS 2 _______________________________________________________________________________________ 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference MAX1449 ELECTRICAL CHARACTERISTICS (continued) (VDD = +3.3V, OVDD = +2.0V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = +2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 105MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Third-Harmonic Distortion (Note 1) Intermodulation Distortion (First 5 Odd-Order IMDs) (Note 2) Third-Order Intermodulation Distortion (Note 2) Total Harmonic Distortion (First 5 Harmonics) (Note 1) Small-Signal Bandwidth Full-Power Bandwidth Aperture Delay Aperture Jitter Overdrive Recovery Time Differential Gain Differential Phase Output Noise INTERNAL REFERENCE Reference Output Voltage Reference Temperature Coefficient Load Regulation EXTERNAL REFERENCE Positive Reference Negative Reference Differential Reference Voltage REFIN Resistance DIGITAL INPUTS (CLK, PD, OE) CLK Input High Threshold VIH PD, OE CLK Input Low Threshold VIL PD, OE 0.8 x VDD 0.8 x VDD 0.2 x VDD 0.2 x VDD REFP REFN ∆VREF RREFIN VREFIN = +2.048V VREFIN = +2.048V VREFP -VREFN, VREFIN = +2.048V 0.98 2.162 1.138 1.024 >50 1.07 V V V MΩ REFOUT TCREF 2.048 ±1% 60 1.25 V ppm/°C mV/mA IN+ = IN- = COM FPBW tAD tAJ For 1.5 x full-scale input SYMBOL fIN = 7.5MHz HD3 fIN = 20MHz fIN = 50MHz IMD IM3 f1 = 38MHz at -6.5dB FS f2 = 42MHz at -6.5dB FS f1 = 38MHz at -6.5dB FS f2 = 42MHz at -6.5dB FS fIN = 7.5MHz, TA = +25°C THD fIN = 20MHz, TA = +25°C fIN = 50MHz Input at -20dB FS, differential inputs Input at -0.5dB FS, differential inputs CONDITIONS MIN TYP -72 -72 -70 -76 -76 -70 -70 -70 500 400 1 2 2 ±1 ±0.25 0.2 MHz MHz ns psRMS ns % degree LSBRMS -61.5 -61.5 dBc dBc dBc dBc MAX UNITS V V _______________________________________________________________________________________ 3 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference MAX1449 ELECTRICAL CHARACTERISTICS (continued) (VDD = +3.3V, OVDD = +2.0V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = +2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 105MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Input Hysteresis Input Leakage Input Capacitance DIGITAL OUTPUTS (D9–D0) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Output Supply Voltage Analog Supply Current SYMBOL VHYST IIH IIL CIN VOL VOH ILEAK COUT VDD OVDD IVDD Operating, fIN = 20MHz at -0.5dB FS Shutdown, clock idle, PD = OE = OVDD Operating, CL = 15pF , fIN = 20MHz at -0.5dB FS Shutdown, clock idle, PD = OE = OVDD Power Supply Rejection TIMING CHARACTERISTICS CLK Rise-to-Output Data Valid OE Fall-to-Output Enable OE Rise-to-Output Disable CLK Pulse Width High CLK Pulse Width Low Wake-Up Time PSRR Offset Gain Figure 6 (Note 3) Figure 5 Figure 5 Figure 6, clock period 9.52ns Figure 6, clock period 9.52ns (Note 4) ISINK = 200µA ISOURCE = 200µA OE = OVDD OE = OVDD 2.7 1.7 5 3.3 3.3 58 4 10 1 ±0.1 ±0.1 5 10 15 4.76 ±0.47 4.76 ±0.47 1.5 8 10 3.6 3.6 74 15 OVDD - 0.2 ±10 VIH = VDD = OVDD VIL = 0 5 0.2 CONDITIONS MIN TYP 0.1 ±5 ±5 pF V V µA pF V V mA µA mA µA mV/V %/V ns ns ns ns ns µs MAX UNITS V µA Output Supply Current IOVDD tDO tENABLE tDISABLE tCH tCL tWAKE Note 1: SNR, SINAD, THD, SFDR and HD3 are based on an analog input voltage of -0.5dB FS referenced to a +1.024V full-scale input voltage range. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is 6dB better if referenced to the two-tone envelope. Note 3: Digital outputs settle to VIH,VIL. Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down. 4 _______________________________________________________________________________________ 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference Typical Operating Characteristics (VDD = +3.3V, OVDD = +2.0V, internal reference, differential input at -0.5dB FS, fCLK = 106.2345MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) FFT PLOT (fIN = 7.5MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) MAX1449 toc01 MAX1449 FFT PLOT (fIN = 19.99MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) MAX1449 toc02 UNDERSAMPLING FFT PLOT (fIN = 50.12MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 3RD HARMONIC 2ND HARMONIC SNR = 57.9dB SINAD = 56.7dB THD = -71.3dBc SFDR = 71.1dBc MAX1449 toc03 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 10 20 30 40 50 2ND HARMONIC 3RD HARMONIC SNR = 58.6dB SINAD = 58.4dB THD = -72.7dBc SFDR = 73.6dBc 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 SNR = 58.5dB SINAD = 58.4dB THD = -73.7dBc SFDR = 75.9dBc 2ND HARMONIC 3RD HARMONIC 60 0 10 20 30 40 50 60 0 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) 10 20 30 40 50 ANALOG INPUT FREQUENCY (MHz) 60 FFT PLOT (fIN = 7.5MHz, 8192-POINT FFT, SINGLE-ENDED INPUT) MAX1449 toc04 FFT PLOT (fIN = 19.99MHz, 8192-POINT FFT, SINGLE-ENDED INPUT) -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 2ND HARMONIC 3RD HARMONIC SNR = 57.7dB SINAD = 57.2dB THD = -67dBc SFDR = 67.7dBc MAX1449 toc05 TWO-TONE INTERMODULATION (8192-POINT IMD, DIFFERENTIAL INPUT) -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 3RD ORDER IMD 2ND ORDER IMD f1 = 38MHz AT -6.5dB FS f2 = 42MHz AT -6.5dB FS f1 f2 MAX1449 toc06 0 -10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 10 20 30 40 50 3RD HARMONIC 2ND HARMONIC SNR = 57.7dB SINAD = 57.5dB THD = -71.8dBc SFDR = 74.4dBc 0 0 60 0 ANALOG INPUT FREQUENCY (MHz) 10 20 30 40 50 ANALOG INPUT FREQUENCY (MHz) 60 0 10 20 30 40 50 ANALOG INPUT FREQUENCY (MHz) 60 SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY MAX1449 toc07 SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY MAX1449 toc08 TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY MAX1449 toc09 80 DIFFERENTIAL 74 SFDR (dBc) 60 DIFFERENTIAL SINGLE-ENDED -50 58 -56 SINGLE-ENDED SINGLE-ENDED 62 THD (dBc) SNR (dB) 68 56 -62 54 -68 56 52 -74 DIFFERENTIAL 50 1 10 ANALOG INPUT FREQUENCY (MHz) 100 50 1 10 ANALOG INPUT FREQUENCY (MHz) 100 -80 1 10 ANALOG INPUT FREQUENCY (MHz) 100 _______________________________________________________________________________________ 5 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference MAX1449 Typical Operating Characteristics (continued) (VDD = +3.3V, OVDD = +2.0V, internal reference, differential input at -0.5dB FS, fCLK = 106.2345MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) SIGNAL-T0-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUENCY MAX1449 toc10 FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED MAX1449 toc11 SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED VIN = 100mVp-p MAX1449 toc12 60 DIFFERENTIAL 6 4 AMPLITUDE (dB) 2 0 -2 -4 6 4 AMPLITUDE (dB) 2 0 -2 -4 -6 -8 58 SINAD (dB) 56 SINGLE-ENDED 54 52 -6 50 1 10 ANALOG INPUT FREQUENCY (MHz) 100 -8 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz) 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz) SPURIOUS-FREE DYNAMIC RANGE vs. INPUT POWER (fIN = 19MHz) MAX1449 toc13 SIGNAL-TO-NOISE RATIO vs. INPUT POWER (fIN = 19MHz) MAX1449 toc14 TOTAL HARMONIC DISTORTION vs. INPUT POWER (fIN = 19MHz) MAX1449 toc15 80 75 70 SFDR (dBc) 65 60 55 50 -12 -9 -6 INPUT POWER (dB FS) -3 0 65 -50 -55 -60 THD (dBc) 60 SNR (dB) 55 -65 -70 50 45 -75 -80 -12 -9 -6 -3 0 -12 -9 -6 INPUT POWER (dB FS) -3 0 INPUT POWER (dB FS) 40 SIGNAL-TO-NOISE + DISTORTION vs. INPUT POWER (fIN = 19MHz) MAX1449 toc16 SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE MAX1449 toc17 SIGNAL-TO-NOISE vs. TEMPERATURE fIN = 26.1696MHz 66 MAX1449 toc18 65 84 fIN = 26.1696MHz 80 SFDR (dBc) 70 60 SINAD (dB) SNR (dB) 55 76 62 50 72 58 45 68 54 40 -12 -9 -6 -3 0 INPUT POWER (dB FS) 64 -40 -15 10 35 60 85 TEMPERATURE (°C) 50 -40 -15 10 35 60 85 TEMPERATURE (°C) 6 _______________________________________________________________________________________ 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference MAX1449 Typical Operating Characteristics (continued) (VDD = +3.3V, OVDD = +2.0V, internal reference, differential input at -0.5dB FS, fCLK = 106.2345MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) TOTAL HARMONIC DISTORTION vs. TEMPERATURE MAX1449 toc19 SIGNAL-TO-NOISE + DISTORTION vs. TEMPERATURE MAX1449 toc20 INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE (BEST STRAIGHT LINE) 0.4 0.3 0.2 INL (LSB) MAX1449 toc21 -60 fIN = 26.1696MHz -64 70 fIN = 26.1696MHz 66 SINAD (dB) 0.5 THD (dBc) -68 62 0.1 0 -0.1 -72 58 -76 54 -0.2 -0.3 -80 -40 -15 10 35 60 85 TEMPERATURE (°C) 50 -40 -15 10 35 60 85 TEMPERATURE (°C) -0.4 0 200 400 600 800 1000 1200 DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE MAX1449 toc22 GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE, VREFIN = +2.048V MAX1449 toc23 OFFSET ERROR vs. TEMPERATURE, EXTERNAL REFERENCE, VREFIN = +2.048V MAX1449 toc24 0.5 0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 0 200 400 600 800 1000 0.10 4 3 OFFSET ERROR (LSB) 2 1 0 -1 -2 0.08 GAIN ERROR (LSB) 0.06 0.04 0.02 1200 0 -40 -15 10 35 60 85 TEMPERATURE (°C) -40 -15 10 35 60 85 DIGITAL OUTPUT CODE TEMPERATURE (°C) ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE MAX1449 toc25 ANALOG SUPPLY CURRENT vs. TEMPERATURE MAX1449 toc26 DIGITAL SUPPLY CURRENT vs. TEMPERATURE MAX1449 toc27 63 61 59 IVDD (mA) 57 55 53 51 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 70 65 60 15 12 IOVDD (mA) -40 -15 10 35 60 85 IVDD (mA) 9 55 50 45 40 6 3 0 -40 -15 10 35 60 85 TEMPERATURE (°C) TEMPERATURE (°C) 3.60 _______________________________________________________________________________________ 7 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference MAX1449 Typical Operating Characteristics (continued) (VDD = +3.3V, OVDD = +2.0V, internal reference, differential input at -0.5dB FS, fCLK = 106.2345MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) DIGITAL SUPPLY CURRENT vs. TEMPERATURE MAX1449 toc28 ANALOG POWER-DOWN CURRENT vs. ANALOG SUPPLY VOLTAGE MAX1449 toc29 DIGITAL POWER-DOWN CURRENT vs. DIGITAL SUPPLY VOLTAGE MAX1449 toc30 12 3.00 12 10 IOVDD (mA) IVDD (µA) 2.80 9 IOVDD (µA) 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 2.60 8 6 2.40 6 2.20 3 4 -40 -15 10 35 60 85 TEMPERATURE (°C) 2.00 0 2.0 2.3 2.6 3.0 3.3 3.6 OVDD (V) SFDR, SNR, THD, SINAD vs. CLOCK FREQUENCY fIN = 50.123MHz SFDR, SNR, THD, SINAD (dB) 75 70 THD 65 SNR 60 2.025 55 50 100 104 108 112 116 120 CLOCK FREQUENCY (MHz) SINAD VREF (V) 2.050 SFDR MAX1449 toc31 INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE MAX1449 toc32 80 2.100 2.075 2.000 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX1449 toc33 OUTPUT NOISE HISTOGRAM (DC INPUT) 64676 MAX1449 toc34 2.10 70,000 60,000 50,000 COUNTS 2.08 VREF (V) 2.06 40,000 30,000 20,000 2.04 2.02 10,000 2.00 -40 -15 10 35 60 85 TEMPERATURE (°C) 0 0 607 252 0 N-2 N-1 N N+1 N+2 DIGITAL OUTPUT CODE 8 _______________________________________________________________________________________ 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference Pin Description PIN 1 2 3, 9, 10 4, 5, 8, 11, 14, 30 6 7 12 13 NAME REFN COM VDD GND IN+ INCLK PD FUNCTION Lower Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. Common-Mode Voltage Output. Bypass to GND with a > 0.1µF capacitor. Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. Analog Ground Positive Analog Input. For single-ended operation connect signal source to IN+. Negative Analog Input. For single-ended operation connect IN- to COM. Conversion Clock Input Power Down Input. High: Power-down mode Low: Normal operation Output Enable Input. High: Digital outputs disabled Low: Digital outputs enabled MAX1449 15 OE 16–20 D9–D5 Three-State Digital Outputs D9–D5. D9 is the MSB. Output Driver Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. Test Point. Do not connect. Output Driver Ground Three-State Digital Outputs D4–D0. D0 is the LSB. Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistordivider. Reference Input. VREFIN = 2 ✕ (VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. Upper Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. 21 22 23 24–28 OVDD T.P. OGND D4–D0 29 31 32 REFOUT REFIN REFP _______________________________________________________________________________________ 9 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference MAX1449 Detailed Description The MAX1449 uses a 10-stage, fully differential, pipelined architecture (Figure 1), that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage every half-clock cycle. Counting the delay through the output latch, the clock-cycle latency is 5.5. A 1.5-bit (2-comparator) flash ADC converts the held input voltage into a digital code. The following digitalto-analog converter (DAC) converts the digitized result back into an analog voltage, which is then subtracted from the original held input signal. The resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage where the process is repeated until the signal has been processed by all 10 stages. Each stage provides a 1bit resolution. Digital error-correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. and open simultaneously with S1, sampling the input waveform. Switches S4a and S4b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltage is held on capacitors C2a and C2b. The amplifier is used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. This value is then presented to the first stage quantizer and isolates the pipeline from the fast-changing input. The wide input bandwidth T/H amplifier allows the MAX1449 to track and sample/hold analog inputs of high frequencies beyond Nyquist. The analog inputs IN+ and IN- can be driven either differentially or single-ended. It is recommended to match the impedance of IN+ and IN- and set the common-mode voltage to mid-supply (VDD/2) for optimum performance. Analog Input and Reference Configuration The full-scale range of the MAX1449 is determined by the internally generated voltage difference between REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The ADC’s full-scale range is user-adjustable through the REFIN pin, which provides a high input impedance for this purpose. REFOUT, REFP, COM (VDD/2), and REFN are internally buffered low-impedance outputs. INTERNAL BIAS S2a COM S5a C1a S3a Input Track-and-Hold (T/H) Circuit Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuit in both track and hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a and S5b are closed. The fully differential circuit samples the input signal onto the two capacitors C2a and C2b through switches S4a and S4b. Switches S2a and S2b set the common mode for the amplifier input, MDAC VIN T/H Σ x2 VOUT S4a IN+ OUT C2a S4c S1 OUT S4b C2b C1b FLASH ADC 1.5 BITS DAC IN- VIN STAGE 1 STAGE 2 STAGE 10 S2b INTERNAL BIAS TRACK HOLD TRACK CLK S5b COM S3b DIGITAL CORRECTION LOGIC 10 D9–D0 VIN = INPUT VOLTAGE BETWEEN IN+ AND IN- (DIFFERENTIAL OR SINGLE-ENDED) INTERNAL HOLD NON-OVERLAPPING CLOCK SIGNALS Figure 1. Pipelined Architecture—Stage Blocks 10 Figure 2. Internal T/H Circuit ______________________________________________________________________________________ 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference The MAX1449 provides three modes of reference operation: • Internal reference mode • Buffered external reference mode • Unbuffered external reference mode In internal reference mode, the internal reference output REFOUT can be tied to the REFIN pin through a resistor (e.g., 10kΩ) or resistor-divider, if an application requires a reduced full-scale range. For stability purposes it is recommended to bypass REFIN with a >10nF capacitor to GND. In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a stable and accurate voltage at REFIN. In this mode, REFOUT may be left open or connected to REFIN through a >10kΩ resistor. In unbuffered external reference mode, REFIN is connected to GND thereby deactivating the on-chip buffers of REFP, COM, and REFN. With their buffers shut down, these pins become high impedance and can be driven by external reference sources. ered as an analog input and routed away from any analog input or other digital signal lines. The MAX1449 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50% must meet the specifications for high and low periods as stated in the E lectrical Characteristics. (See Figures 3 (3a, 3b) and 4 (4a, 4b) for the relationship between spurious-free dynamic range (SFDR), signal-to-noise ratio (SNR), total harmonic distortion (THD), or signal-to-noise plus distortion (SINAD) versus duty cycle.) MAX1449 Output Enable (OE), Power Down (PD), and Output Data (D0–D9) All data outputs, D0 (LSB) through D9 (MSB), are TTL/CMOS logic-compatible. There is a 5.5 clock-cycle latency between any particular sample and its valid output data. The output coding is straight offset binary (Table 1). With OE and PD high, the digital outputs enter a high-impedance state. If OE is held low with PD high, the outputs are latched at the last value prior to the power down. The capacitive load on the digital outputs D0 through D9 should be kept as low as possible (