MAX14548E

19-5248; Rev 0; 4/10 TION KIT EVALUA BLE ILA AVA 100Mbps, 16-Channel LLTs MAX14548E/MAX14548AE General Description The MAX14548E/MAX14548AE 16-channel, bidirectional level translators (LLTs) provide the level shifting necessary for 100Mbps data transfer in multivoltage systems. Externally applied voltages, VCC and VL, set the logic levels on either side of the device. Logic signals present on the VL side of the device appear as a high-voltage logic signal on the VCC side of the device and vice versa. The devices feature a programming frequency input (PF) that adjusts the one-shot accelerator on-time to guarantee a bit rate of 100Mbps with a load capacitance < 15pF and VL > 1.1V (MAX14548E) or VL > 1.4V (MAX14548AE) when driven low. The MAX14548E can drive capacitive loads up to 50/R 1.1pF with a guaranteed bit rate of 40Mbps when VL > 1.1/R 1.1V and PF is driven high. The MAX14548AE can drive capacitive loads up to 50pF with a guaranteed bit rate of 40Mbps when VL > 1.1V and PF is driven high. The device operate at full speed with external drivers that source as low as 4mA output current. Each I/O channel is pulled up to VCC or VL by an internal 35FA current source, allowing both devices to be driven by either push-pull or open-drain drivers. The devices feature multiple power-saving features including an enable input (EN) that places the device into a low-power shutdown mode when driven low and an automatic shutdown mode that disables the part when VCC is less than VL. The MAX14548AE output driver is designed to operate at full speed (100Mbps) with VL > 1.4V, which reduces the dynamic supply current vs. the MAX14548E. The state of I/O VCC_and I/O VL_are in high-impedance state during shutdown. The devices operate with VCC voltages from +1.7V to +3.6V and VL voltages from +1.1V to +3.6V, making them ideal for data transfer between low-voltage ASICs/ PLDs and higher voltage systems. The devices are available in a 40-bump WLP (2.16mm x 3.46mm) package with 0.4mm ball pitch, and operate over the extended -40NC to +85NC temperature range. S Bidirectional Level Translation S 100Mbps Guaranteed Data Rate S +1.7V to +3.6V Supply Voltage Range for VCC S +1.1V to +3.6V Supply Voltage Range for VL Features (VCC > VL) S -40NC to +85NC Extended Operating Temperature Range Applications CMOS Logic-Level Translation Low-Voltage ASIC Level Translation Smart Card Readers Portable Communication Devices Cell Phones GPS Telecommunications Equipment Typical Operating Circuit appears at end of data sheet. Ordering Information/Selector Guide PART MAX14548EEWL+ MAX14548AEEWL+ PINPACKAGE 40 WLP 40 WLP BIT RATE (PF = LOW) LOAD CAPACITANCE < 15pF (Mbps) 100 100 BIT RATE (PF = HIGH) LOAD CAPACITANCE < 50pF (Mbps) 40 40 LOW DYNAMIC SUPPLY CURRENT — Yes (VL > 1.1V) Note: All devices operate over the -40°C to +85°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. _______________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 100Mbps, 16-Channel LLTs MAX14548E/MAX14548AE ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND.) VCC, VL, EN, PF....................................................... -0.3V to +4V I/O VCC_ ................................................... -0.3V to (VCC + 0.3V) I/O VL_ ......................................................... -0.3V to (VL + 0.3V) Short-Circuit Duration I/O VL_, I/O VCC_ to GND .................................................... Continuous Continuous Power Dissipation (TA = +70NC) 40-Bump WLP (derate 17.2mW/NC above +70NC) .... 1379mW Junction-to-Ambient Thermal Resistance (BJA) (Note 1) ........................................................................ 58NC/W Operating Temperature Range .......................... -40NC to +85NC Storage Temperature Range............................ -65NC to +150NC Junction Temperature .....................................................+150NC Soldering Temperature (reflow) ......................................+260NC Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +1.7V to +3.6V, VL = +1.1V to +3.6V, VCC > VL, EN = VL, CVCC = 1FF, CVL = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3) PARAMETER POWER SUPPLIES VL Supply Range VCC Supply Range Supply Current from VCC Supply Current from VL VCC Shutdown Supply Current VL Shutdown Mode Supply Current VL VCC IQVCC IQVL ISHDN-VCC I/O VCC_ = VCC, I/O VL_ = VL I/O VCC_ = VCC, I/O VL_ = VL TA = +25NC, EN = GND, unconnected I/O pins TA = +25NC, EN = GND, unconnected I/O pins TA = +25NC, EN = VL, VCC = GND, unconnected I/O pins One I/O switching at 25MHz; all other I/O connected to VCC or VL; CLOAD = 0pF TA = +25NC, EN = GND TA = +25NC 0.3 VCC rising (VL = 3.6V) (Note 4) VCC falling (VL = 3.6V) (Note 4) I/O VL_ = GND, I/O VCC_ = GND I/O VCC_ = GND, I/O VL_ = GND (Note 5) 0.05 0.2 10 15 3 0.3 0.52 0.65 0.85 125 90 MAX14548E MAX14548AE 0.1 0.1 0.1 2.9 mA 2.6 0.1 6 1 FA FA V V V FA FA kI 1.1 1.7 3.6 3.6 40 20 1 1 FA 2 V V FA FA FA SYMBOL CONDITIONS MIN TYP MAX UNITS ISHDN-VL Dynamic Supply Current ID I/O VCC_, I/O VL_ Three-State Leakage Current EN, PF Input Leakage Current VL Shutdown Threshold VL - VCC Shutdown Threshold High VL - VCC Shutdown Threshold Low I/O VL_ Pullup Current I/O VCC_ Pullup Current I/O VL_ to I/O VCC_ DC Resistance 2 ILEAK ILEAK_EN_PF VTH_VL VTH_H VTH_L IVL_PU_ IVCC_PU_ RIOVL_IOVCC 100Mbps, 16-Channel LLTs ELECTRICAL CHARACTERISTICS (continued) (VCC = +1.7V to +3.6V, VL = +1.1V to +3.6V, VCC > VL, EN = VL, CVCC = 1FF, CVL = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3) PARAMETER ESD PROTECTION I/O VCC_, I/O VL_ All Other Pins LOGIC LEVELS I/O VL_ Input-Voltage High Threshold I/O VL_ Input-Voltage Low Threshold I/O VCC_ Input-Voltage High Threshold I/O VCC_ Input-Voltage Low Threshold EN, PF Input-Voltage High Threshold EN, PF Input-Voltage Low Threshold I/O VL_ Output-Voltage High I/O VL_ Output-Voltage Low, Drop to GND I/O VCC_ Output-Voltage High I/O VCC_ Output-Voltage Low, Drop to GND VIHL VILL VIHC VILC (Note 6) (Note 6) (Note 6) (Note 6) 1.1V < VL < 1.3V VIH VL = 1.8V VIL VOHL VOLL VOHC VOLC 1.1V < VL < 1.3V VL = 1.8V I/O VL_ source current = 10FA I/O VL_ sink current = 20FA, I/O VCC_ < 0.05V I/O VCC_ source current = 10FA I/O VCC_ sink current = 20FA, I/O VL_ < 0.05V On rising edge On falling edge On rising edge On falling edge 2.65 2.5 4 3.7 7 4.43 14.2 11.2 15.3 15.3 20.3 19.5 4/5 x VCC 1/3 x VCC 4/5 x VL 1/3 x VL VL 0.25 VL 0.4 0.4 0.4 VCC 0.4 0.2 VL 0.2 0.15 V V V V Human Body Model, CVCC = 1FF, CVL = 1FF Unpowered device Powered device Q12 kV Q5 Q2 kV SYMBOL CONDITIONS MIN TYP MAX UNITS MAX14548E/MAX14548AE V V V V V V RISE/FALL TIME ACCELERATOR STAGE PF = low Accelerator Pulse Duration PF = high VL Output Accelerator Source Impedance VCC Output Accelerator Source Impedance VL Output Accelerator Sink Impedance VCC Output Accelerator Sink Impedance VL = 1.62V VL = 3.2V VCC = 2.2V VCC = 3.6V VL = 1.62V VL = 3.2V VCC = 2.2V VCC = 3.6V ns ns I I I I 3 100Mbps, 16-Channel LLTs MAX14548E/MAX14548AE HIGH-SPEED TIMING CHARACTERISTICS—MAX14548E (VCC = +1.7V to +3.6V, VL = +1.1V to +3.6V, VCC > VL, EN = VL, PF = low, CVCC = 1FF, CVL = 1FF, CIOVL P 15pF, CIOVCC P 15pF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3) PARAMETER I/O VCC_ Rise Time I/O VCC_ Fall Time I/O VL_ Rise Time I/O VL_ Fall Time Propagation Delay (Driving I/O VL_) Propagation Delay (Driving I/O VCC_) Channel-to-Channel Skew Propagation Delay from I/O VL_ to I/O VCC_ After EN Propagation Delay from I/O VCC_ to I/O VL_ After EN Maximum Data Rate SYMBOL tRVCC tFVCC tRVL tFVL tPVL-VCC tPVCC-VL tSKEW tEN-VCC tEN-VL CONDITIONS Input rise time < 2ns, Figure 1 Input fall time < 2ns, Figure 1 Input rise time < 2ns, Figure 2 Input fall time < 2ns, Figure 2 Input rise time < 2ns, Figure 1 Input rise time < 2ns, Figure 2 Input rise time/fall time < 2ns RLOAD = 1MI, Figure 3 RLOAD = 1MI, Figure 3 Push-pull operation Open-drain operation 100 0.3 2.75 2.26 0.2 27 0.05 MIN TYP MAX 2 2 2 2 UNITS ns ns ns ns ns ns ns Fs Fs Mbps HIGH-SPEED TIMING CHARACTERISTICS—MAX14548AE (VCC = +1.7V to +3.6V, VL = +1.4V to +3.6V, VCC > VL, EN = VL, PF = low, CVCC = 1FF, CVL = 1FF, CIOVL P 15pF, CIOVCC P 15pF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3) PARAMETER I/O VCC_ Rise Time I/O VCC_ Fall Time I/O VL_ Rise Time I/O VL_ Fall Time Propagation Delay (Driving I/O VL_) Propagation Delay (Driving I/O VCC_) Channel-to-Channel Skew Propagation Delay from I/O VL_ to I/O VCC_ After EN Propagation Delay from I/O VCC_ to I/O VL_ After EN Maximum Data Rate SYMBOL tRVCC tFVCC tRVL tFVL tPVL-VCC tPVCC-VL tSKEW tEN-VCC tEN-VL CONDITIONS Input rise time < 2ns, Figure 1 Input fall time < 2ns, Figure 1 Input rise time < 2ns, Figure 2 Input rise time < 2ns, Figure 2 Input rise time < 2ns, Figure 1 Input rise time < 2ns, Figure 2 Input rise time/fall time < 2ns RLOAD = 1MI, Figure 3 RLOAD = 1MI, Figure 3 Push-pull operation Open-drain operation 100 0.3 2.75 2.26 0.2 27 0.05 MIN TYP MAX 2 2 2 2 UNITS ns ns ns ns ns ns ns Fs Fs Mbps 4 100Mbps, 16-Channel LLTs LOW-SPEED TIMING CHARACTERISTICS—MAX14548E (VCC = +1.7V to +3.6V, VL = +1.1V to +3.6V, VCC > VL, EN = VL, PF = high, CVCC = 1FF, CVL = 1FF, CIOVL P 50pF, CIOVCC P 50pF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3) PARAMETER I/O VCC_ Rise Time I/O VCC_ Fall Time I/O VL_ Rise Time I/O VL_ Fall Time Propagation Delay (Driving I/O VL_) Propagation Delay (Driving I/O VCC_) Channel-to-Channel Skew Propagation Delay from I/O VL_ to I/O VCC_ After EN Propagation Delay from I/O VCC_ to I/O VL_ After EN Maximum Data Rate SYMBOL tRVCC tFVCC tRVL tFVL tPVL-VCC tPVCC-VL tSKEW tEN-VCC tEN-VL CONDITIONS Input rise time < 6ns, Figure 1 Input fall time < 6ns, Figure 1 Input rise time < 6ns, Figure 2 Input rise time < 6ns, Figure 2 Input rise time < 6ns, Figure 1 Input rise time < 6ns, Figure 2 Input rise time/fall time < 6ns RLOAD = 1MI, Figure 3 RLOAD = 1MI, Figure 3 Push-pull operation Open-drain operation 40 0.3 4 3.37 0.2 27 0.06 0.5 MIN TYP MAX 6 6 6 6 UNITS ns ns ns ns ns ns ns Fs Fs Mbps MAX14548E/MAX14548AE LOW-SPEED TIMING CHARACTERISTICS—MAX14548AE (VCC = +1.7V to +3.6V, VL = +1.1V to +3.6V, VCC > VL, EN = VL, PF = high, CVCC = 1FF, CVL = 1FF, CIOVL P 50pF, CIOVCC P 50pF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +2.8V, VL = +1.8V and TA = +25NC.) (Notes 2, 3) PARAMETER I/O VCC_ Rise Time I/O VCC_ Fall Time I/O VL_ Rise Time I/O VL_ Fall Time Propagation Delay (Driving I/O VL_) Propagation Delay (Driving I/O VCC_) Channel-to-Channel Skew Propagation Delay from I/O VL_ to I/O VCC_ After EN Propagation Delay from I/O VCC_ to I/O VL_ After EN Maximum Data Rate SYMBOL tRVCC tFVCC tRVL tFVL tPVL-VCC tPVCC-VL tSKEW tEN-VCC tEN-VL CONDITIONS Input rise time < 6ns, Figure 1 Input fall time < 6ns, Figure 1 Input rise time < 6ns, Figure 2 Input rise time < 6ns, Figure 2 Input rise time < 6ns, Figure 1 Input rise time < 6ns, Figure 2 Input rise time/fall time < 6ns RLOAD = 1MI, Figure 3 RLOAD = 1MI, Figure 3 Push-pull operation Open-drain operation 40 0.3 4 3.37 0.2 27 0.06 MIN TYP MAX 6 6 6 6 UNITS ns ns ns ns ns ns ns Fs Fs Mbps Note 2: All units are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design and not production tested. Note 3: VL must be less than or equal to VCC during normal operation. However, VL can be greater than VCC during startup and shutdown conditions. Note 4: When VCC is below VL by more than the VL - VCC shutdown threshold, the device turns off its pullup generators and I/O VCC_ and I/O VL_ enter their respective shutdown states. Note 5: Guaranteed by design. Note 6: Input thresholds are referenced to the boost circuit. 5 100Mbps, 16-Channel LLTs MAX14548E/MAX14548AE VL VL EN VCC VCC tRVCC 90% I/O VL_ 50% 50% I/O VL_ I/O VCC_ CIOVCC tPLH NOTE: THE INPUT RISE/FALL TIMES ARE < 2ns FOR HIGH SPEED AND < 6ns FOR LOW SPEED. tPLH I/O VCC_ 10% 50% 10% 50% tFVCC 90% VL MAX14548E MAX14548AE VCC tPVL-VCC = tPLH OR tPHL Figure 1. Push-Pull Driving I/O VL_ Test Circuit and Timing VL VL EN VCC VCC tRVL I/O VCC_ tFVL VL MAX14548E MAX14548AE VCC 50% 90% 50% 50% 50% 90% I/O VL_ CIOVCC I/O VCC_ 10% 10% I/O VL_ tPLH tPLH tPVCC-VL = tPLH OR tPHL NOTE: THE INPUT RISE/FALL TIMES ARE < 2ns FOR HIGH SPEED AND < 6ns FOR LOW SPEED. Figure 2. Push-Pull Driving I/O VCC_ Test Circuit and Timing 6 100Mbps, 16-Channel LLTs MAX14548E/MAX14548AE EN MAX14548E VL MAX14548AE VCC I/O VCC_ I/O VL_ RLOAD VL CIOVCC I/O VL_ VL EN t’EN-VCC O VL O VCC/2 VCC O SOURCE I/O VCC_ VCC EN VL SOURCE I/O VL_ I/O VCC_ CIOVCC MAX14548E V MAX14548AE CC RLOAD EN t”EN-VCC VL O VL O I/O VCC_ VCC/2 VCC O I/O VL_ tEN-VCC IS WHICHEVER IS LARGER BETWEEN t'EN-VCC AND t"EN-VCC. EN VL SOURCE I/O VL_ RLOAD CIOVL I/O VCC_ VCC I/O VCC_ MAX14548E V CC MAX14548AE EN t’EN-VL VL O VCC O I/O VL_ VL /2 VL O EN VL SOURCE RLOAD I/O VCC_ I/O VL_ CIOVL MAX14548E VL MAX14548AE VCC EN t”EN-VL VL O VCC O I/O VL_ VL /2 VL O I/O VCC_ tEN-VL IS WHICHEVER IS LARGER BETWEEN t'EN-VL AND t"EN-VL. Figure 3. Enable Test and Timing 7 100Mbps, 16-Channel LLTs MAX14548E/MAX14548AE Typical Operating Characteristics (VCC = 1.8V, VL = 1.4V, CL = 15pF, RSOURCE = 150I, data rate = 100Mbps, push-pull driver, TA = +25NC, unless otherwise noted.) VL SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE (DRIVING ONE I/O VL_) MAX14548E toc01 VCC SUPPLY CURRENT vs. VL SUPPLY VOLTAGE (DRIVING ONE I/O VCC_) MAX14548E toc02 VCC SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE (DRIVING ONE I/O VL_) 6 VCC SUPPLY CURRENT (mA) 5 4 3 2 VCC SUPPLY CURRENT (mA) VL SUPPLY CURRENT (µA) 200 150 100 50 CLOAD = 15pF PF = LOW 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 MAX14548E MAX14548AE CLOAD = 15pF PF = HIGH DATA RATE = 40Mbps MAX14548AE MAX14548AE MAX14548E VCC = 3.6V CLOAD = 15pF PF = LOW DATA RATE = 40Mbps 1.1 1.6 2.1 2.6 3.1 3.6 MAX14548E 1 0 1.700 0 1.700 2.175 2.650 3.125 3.600 2.175 2.650 3.125 3.600 VCC SUPPLY VOLTAGE (V) VL SUPPLY VOLTAGE (V) VCC SUPPLY VOLTAGE (V) VCC SUPPLY CURRENT vs. VL SUPPLY VOLTAGE (DRIVING ONE I/O VCC_) MAX14548E toc04 VL SUPPLY CURRENT vs. CAPACITIVE LOAD (DRIVING ONE I/O VCC) 1600 VL SUPPLY CURRENT (µA) 1400 1200 1000 800 600 400 200 0 VCC SUPPLY CURRENT vs. CAPACITIVE LOAD (DRIVING ONE I/O VL_) 3000 VL SUPPLY CURRENT (µA) 2500 2000 1500 1000 500 6 VCC SUPPLY CURRENT (mA) 5 4 3 2 1 0 1.1 1.6 2.1 2.6 3.1 MAX14548E PF HIGH MAX14548AE PF HIGH MAX14548E PF LOW MAX14548AE PF LOW DATA RATE = 40Mbps 10 20 30 40 MAX14548E toc05 MAX14548AE PF HIGH MAX14548E PF HIGH MAX14548E MAX14548AE VCC = 3.6V CLOAD = 15pF PF = HIGH DATA RATE = 40Mbps 3.6 MAX14548E PF LOW MAX14548AE PF LOW 0 50 10 DATA RATE = 40Mbps 20 30 40 50 CAPACITIVE LOAD (pF) VL SUPPLY VOLTAGE (V) CAPACITIVE LOAD (pF) RISE TIME vs. CAPACITIVE LOAD ON I/O VCC (DRIVING ONE I/O VL) MAX14548E toc07 FALL TIME vs. CAPACITIVE LOAD ON I/O VCC (DRIVING ONE I/O VL) MAX14548E toc08 RISE TIME vs. CAPACITIVE LOAD ON I/O VL (DRIVING ONE I/O VCC) 3.0 2.5 RISE TIME (ns) 2.0 1.5 1.0 0.5 0 tFVCC MAX14548AE (PF HIGH) tFVCC MAX14548E (PF HIGH) 2.0 RISE TIME (ns) 1.5 1.0 0.5 0 10 2.0 FALL TIME (ns) 1.5 1.0 0.5 0 tFVCC MAX14548AE (PF HIGH) tRVCC MAX14548AE (PF LOW) tFVL MAX14548AE (PF HIGH) tRVL MAX14548AE (PF LOW) tRVCC MAX14548AE (PF LOW) DATA RATE = 40Mbps 20 30 tRVCC MAX14548E (PF LOW) tRVCC MAX14548E (PF LOW) DATA RATE = 40Mbps 10 20 30 tFVCC MAX14548E (PF HIGH) tFVL MAX14548E (PF HIGH) tRVL MAX14548E (PF LOW) DATA RATE = 40Mbps 10 20 30 40 50 40 50 40 50 CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF) 8 MAX14548E toc09 2.5 2.5 3.5 MAX14548E toc06 7 1800 3500 MAX14548E toc03 250 5.0 7 100Mbps, 16-Channel LLTs Typical Operating Characteristics (continued) (VCC = 1.8V, VL = 1.4V, CL = 15pF, RSOURCE = 150I, data rate = 100Mbps, push-pull driver, TA = +25NC, unless otherwise noted.) FALL TIME vs. CAPACITIVE LOAD ON I/O VL (DRIVING ONE I/O VCC) MAX14548E toc10 MAX14548E/MAX14548AE PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O VCC (DRIVING ONE I/O VL) 3.5 PROPAGATION DELAY (ns) 3.0 2.5 2.0 1.5 1.0 0.5 tFVL MAX14548AE (PF HIGH) tFVL MAX14548E (PF HIGH) 2.0 FALL TIME (ns) 1.5 1.0 0.5 0 10 tPVL-VCC MAX14548E (PF LOW) tPVL-VCC MAX14548AE (PF LOW) tPVL-VCC MAX14548E (PF HIGH) tRVL MAX14548AE (PF LOW) DATA RATE = 40Mbps 20 30 tRVL MAX14548E (PF LOW) tPVL-VCC MAX14548AE (PF HIGH) 0 40 50 10 DATA RATE = 40Mbps 20 30 40 50 CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF) PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O VL (DRIVING ONE I/O VCC) 4.0 PROPAGATION DELAY (ns) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 10 TYPICAL I/O VL_ DRIVING (DATA RATE = 100Mbps, CIOVCC = 10pF), PF = LOW, MAX14548E MAX14548E toc13 tPVCC-VL MAX14548E (PF HIGH) tPVCC-VL MAX14548E (PF LOW) tPVCC-VL MAX14548AE (PF LOW) DATA RATE = 40Mbps 20 30 40 MAX14548E toc12 4.5 MAX14548E toc11 2.5 4.0 tPVCC-VL MAX14548AE (PF HIGH) I/O VL 1V/div I/O VCC 1V/div 50 10ns/div CAPACITIVE LOAD (pF) TYPICAL I/O VL_ DRIVING (DATA RATE = 40Mbps, CIOVCC = 47pF), PF = HIGH, MAX14548E MAX14548E toc14 TYPICAL I/O VCC_ DRIVING (DATA RATE = 100Mbps, CIOVL = 10pF), PF = LOW, MAX14548E MAX14548E toc15 I/O VL 1V/div I/O VCC 1V/div I/O VCC 1V/div I/O VL 1V/div 20ns/div 10ns/div 9 100Mbps, 16-Channel LLTs MAX14548E/MAX14548AE Typical Operating Characteristics (continued) (VCC = 1.8V, VL = 1.4V, CL = 15pF, RSOURCE = 150I, data rate = 100Mbps, push-pull driver, TA = +25NC, unless otherwise noted.) TYPICAL I/O VCC_ DRIVING (DATA RATE = 40Mbps, CIOVL = 47pF), PF = HIGH, MAX14548E MAX14548E toc16 TYPICAL I/O VL_ DRIVING (DATA RATE = 100Mbps, CIOVCC = 10pF), PF = LOW, MAX14548AE MAX14548E toc17 I/O VCC 1V/div I/O VL 1V/div I/O VCC 1V/div I/O VL 1V/div 20ns/div 10ns/div TYPICAL I/O VL_ DRIVING (DATA RATE = 40Mbps, CIOVCC = 47pF), PF = HIGH, MAX14548AE MAX14548E toc18 TYPICAL I/O VCC_ DRIVING (DATA RATE = 100Mbps, CIOVL = 10pF), PF = LOW, MAX14548AE MAX14548E toc19 I/O VL 1V/div I/O VCC 1V/div I/O VCC 1V/div I/O VL 1V/div 20ns/div 10ns/div TYPICAL I/O VCC_ DRIVING (DATA RATE = 40Mbps, CIOVL = 47pF), PF = HIGH, MAX14548AE MAX14548E toc20 I/O VCC 1V/div I/O VL 1V/div 20ns/div 10 100Mbps, 16-Channel LLTs Pin Configuration TOP VIEW (BUMPS ON BOTTOM) MAX14548E/MAX14548AE MAX14548E MAX14548AE 2 3 4 5 6 7 8 1 + A I/O VL1 B I/O VL9 C GND D I/O VCC1 E I/O VCC9 I/O VCC10 I/O VCC11 I/O VCC12 I/O VCC13 I/O VCC14 I/O VCC15 I/O VCC16 I/O VCC2 I/O VCC3 I/O VCC4 I/O VCC5 I/O VCC6 I/O VCC7 I/O VCC8 VL VCC EN PF VCC VL GND I/O VL10 I/O VL11 I/O VL12 I/O VL13 I/O VL14 I/O VL15 I/O VL16 I/O VL2 I/O VL3 I/O VL4 I/O VL5 I/O VL6 I/O VL7 I/O VL8 WLP (2.16mm × 3.46mm) Pin Description PIN A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 C1, C8 NAME I/O VL1 I/O VL2 I/O VL3 I/O VL4 I/O VL5 I/O VL6 I/O VL7 I/O VL8 I/O VL9 I/O VL10 I/O VL11 I/O VL12 I/O VL13 I/O VL14 I/O VL15 I/O VL16 GND Input/Output 1. Referenced to VL. Input/Output 2. Referenced to VL. Input/Output 3. Referenced to VL. Input/Output 4. Referenced to VL. Input/Output 5. Referenced to VL. Input/Output 6. Referenced to VL. Input/Output 7. Referenced to VL. Input/Output 8. Referenced to VL. Input/Output 9. Referenced to VL. Input/Output 10. Referenced to VL. Input/Output 11. Referenced to VL. Input/Output 12. Referenced to VL. Input/Output 13. Referenced to VL. Input/Output 14. Referenced to VL. Input/Output 15. Referenced to VL. Input/Output 16. Referenced to VL. Ground 11 FUNCTION 100Mbps, 16-Channel LLTs MAX14548E/MAX14548AE Pin Description (continued) PIN C2, C7 NAME VL FUNCTION Logic Supply Voltage, +1.1V to +3.6V. Bypass VL to GND with a 1FF capacitor placed as close as possible to the device. Power-Supply Voltage, +1.7V to +3.6V. Bypass VCC to GND with a 0.1FF ceramic capacitor. For full ESD protection, connect an additional 1FF ceramic capacitor from VCC to GND as close as possible to the VCC input. Enable Input. Drive EN to GND for shutdown mode, or drive EN to VL or VCC for normal operation. Programmable Frequency Input. Drive PF low for high-frequency operation. Drive PF high for lower frequency operation. Input/Output 1. Referenced to VCC. Input/Output 2. Referenced to VCC. Input/Output 3. Referenced to VCC. Input/Output 4. Referenced to VCC. Input/Output 5. Referenced to VCC. Input/Output 6. Referenced to VCC. Input/Output 7. Referenced to VCC. Input/Output 8. Referenced to VCC. Input/Output 9. Referenced to VCC. Input/Output 10. Referenced to VCC. Input/Output 11. Referenced to VCC. Input/Output 12. Referenced to VCC. Input/Output 13. Referenced to VCC. Input/Output 14. Referenced to VCC. Input/Output 15. Referenced to VCC. Input/Output 16. Referenced to VCC. C3, C6 C4 C5 D1 D2 D3 D4 D5 D6 D7 D8 E1 E2 E3 E4 E5 E6 E7 E8 VCC EN PF I/O VCC1 I/O VCC2 I/O VCC3 I/O VCC4 I/O VCC5 I/O VCC6 I/O VCC7 I/O VCC8 I/O VCC9 I/O VCC10 I/O VCC11 I/O VCC12 I/O VCC13 I/O VCC14 I/O VCC15 I/O VCC16 12 100Mbps, 16-Channel LLTs Functional Diagram VL VCC MAX14548E MAX14548AE The devices feature a programmable frequency input (PF) that guarantees a bit rate of 100Mbps with a load capacitance < 15pF and VL > 1.1V (MAX14548E) or VL > 1.4V (MAX14548AE) when driven low. The MAX14548E can drive capacitive loads up to 50pF with a guaranteed bit rate of 40Mbps when VL R 1.1V and PF is driven high. The MAX14548AE can drive capacitive loads up to 50pF with a guaranteed bit rate of 40Mbps when VL R 1.1V and PF is driven high. For proper operation, ensure that 1.7V P VCC P 3.6V, 1.1V P VL P VCC. When power is supplied to VL while VCC is less than VL, the devices automatically enter a low-power mode and the I/Os are in high-impedance mode. The devices also enter shutdown mode when EN = 0. In both conditions where EN = 0 or VL > VCC, there is a known high-impedance state on I/O VL_and I/O VCC_. The maximum data rate depends heavily on the load capacitance (see the rise/fall time graphs in the Typical Operating Characteristics), output impedance of the driver, and the operating voltage range. The device architecture is based on an nMOS pass gate and output accelerator stages (Figure 4). The accelerators are active only when there is a rising/falling edge on a given I/O. A short pulse is then generated where the output accelerator stages become active and charge/ discharge the capacitances at the I/Os. Due to its architecture, both input stages become active during the one-shot pulse. This can lead to some current feeding into the external source that is driving the translator. However, this behavior helps speed up the transition on the driven side. The devices have internal current sources capable of sourcing 35FA to pull up the I/O lines. These internal pullup current sources allow the inputs to be driven with open-drain drivers and push-pull drivers. It is not recommended to use external pullup resistors on the I/O lines. The architecture of the devices permit either side to be driven with a minimum of 4mA drivers or larger. The device I/Os are designed to drive CMOS inputs. Do not load the I/O lines with a resistive load less than 25kI and do not place an RC circuit at the input of these devices to slow down the edges. If a slower rise/ fall time is required, refer to the MAX3000E/MAX3001E/ MAX3002–MAX3012 data sheet. MAX14548E/MAX14548AE I/O VL1 I/O VCC1 Level Translation I/O VL2 I/O VCC2 I/O VL15 I/O VCC15 I/O VL16 EN PF GND I/O VCC16 Input Driver Requirements Detailed Description The MAX14548E/MAX14548AE 16-channel, bidirectional level translators (LLTs) provide the level shifting necessary for 100Mbps data transfer in multivoltage systems. Externally applied voltages, VCC and VL, set the logic levels on either side of the device. Logic signals present on the VL side of the device appear as a high-voltage logic signal on the VCC side of the device and vice versa. The devices operate at full speed with external drivers that source as little as 4mA output current (min). Each I/O channel is pulled up to VCC or VL by an internal 35FA current source, allowing the devices to be driven by either push-pull or open-drain drivers. The devices feature an enable input (EN) that places the device into a low-power shutdown mode when driven low. They also feature an automatic shutdown mode that disables the part when VCC is less than VL. Output Load Requirements 13 100Mbps, 16-Channel LLTs MAX14548E/MAX14548AE VL ENABLE ENABLE ENABLE VCC 30µA I/O VL_ 30µA I/O VCC_ VL BOOST CIRCUIT VL BOOST CIRCUIT VCC VCC NOTE 1: THE MAX14548E/MAX14548AE ARE ENABLED WHEN VL < VCC - 0.2V AND EN = VL. Figure 4. Simplified Functional Diagram for One I/O Line The EN input places the devices into a low-power shutdown mode when driven low. The automatic shutdown mode disables the devices when VCC is unconnected or less than VL. When VCC is less than VL or EN = GND, the devices enter shutdown mode. The programmable frequency input (PF) adjusts the oneshot accelerator to guarantee a 100Mbps bit rate with a load capacitance 1.1V (MAX14548E) or VL > 1.4V (MAX14548AE) when driven low. The MAX14548E can drive capacitive loads up to 50pF with a guaranteed 40Mbps bit rate when VL > 1.1V and PF is driven high. The MAX14548AE can drive capacitive loads up to 50pF with a guaranteed 40Mbps bit rate when VL > 1.1V and PF is driven high. Shutdown Mode Applications Information Use standard high-speed layout practices when laying out a board with the MAX14548E/MAX14548AE. For example, to minimize line coupling, place all other signal lines not connected to the devices at least 1x the substrate height of the PCB away from the input and output lines of the devices. To reduce ripple and the chance of introducing data errors, bypass VL and VCC to ground with 0.1FF ceramic capacitors. Place all capacitors as close as possible to the power-supply inputs. For full ESD protection, bypass VCC with a 1FF ceramic capacitor located as close as possible to the VCC input. Layout Recommendations Data Rate and Capacitive Load (PF Input) Power-Supply Decoupling 14 100Mbps, 16-Channel LLTs MAX14548E/MAX14548AE RC 1MΩ CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE RD 1500Ω DISCHARGE RESISTANCE DEVICE UNDER TEST IP 100% 90% AMPS 36.8% 10% 0 0 tRL Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) Cs 100pF STORAGE CAPACITOR TIME tDL CURRENT WAVEFORM Figure 5a. Human Body ESD Test Model Figure 5b. Human Body Current Waveform The devices bidirectional level translators can operate as a unidirectional device by selecting one I/O as the input and the corresponding I/O as an output. These devices provide the smallest solution (WLP package) for level translation applications. As with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. The I/O VL_ and I/O VCC_ pins have extra protection against static electricity. ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. Human Body Model Figure 5a shows the Human Body Model, and Figure 5b shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a 1.5kI resistor. Unidirectional vs. Bidirectional Level Translator ESD Protection Due to the architecture of the devices, it is not recommended to use external pullup or pulldown resistors on the bus. In certain applications, the use of external pullup or pulldown resistors is desired to have a known bus state when there is no active driver on the bus. The devices include internal pullup current sources that set the bus state when the device is enabled. In shutdown mode, the state of I/O VCC_ and I/O VL_ is high impedance. The devices are designed to pass open-drain as well as CMOS push-pull signals. When used with open-drain signaling, the rise time is dominated by the interaction of the internal pullup current source and the parasitic load capacitance. The devices include internal rise time accelerators to speed up transitions, eliminating any need for external pullup resistors. For applications such as I2C or 1-WireM that require an external pullup resistor, refer to the MAX13046E and MAX13047E data sheets. Use with External Pullup/Pulldown Resistors Open-Drain Signaling 1-Wire is a registered trademark of Maxim Integrated Products, Inc. 15 100Mbps, 16-Channel LLTs MAX14548E/MAX14548AE Typical Operating Circuit +1.8V 1µF +1.8V SYSTEM CONTROLLER PF EN DATA 16 GND PF EN I/O VL_ GND I/O VCC_ DATA 16 GND VL VCC 1µF 0.1µF +2.8V +2.8V SYSTEM MAX14548A MAX14548AE Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 40 WLP PACKAGE CODE W402B3+1 DOCUMENT NO. 21-0437 16 100Mbps, 16-Channel LLTs Revision History REVISION NUMBER 0 REVISION DATE 4/10 Initial release DESCRIPTION PAGES CHANGED — MAX14548E/MAX14548AE Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 17 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.