MAX1454AUE

19-5945 Rev 0; 6/11 EVALUATION KIT AVAILABLE MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection General Description The MAX1454 is a highly integrated analog sensor signal conditioner targeted for automotive applications. The device provides amplification, calibration, and temperature compensation to enable an overall performance approaching the inherent repeatability of the sensor. The fully analog signal path introduces no quantization noise in the output signal while enabling digitally controlled trimming of the output. Offset and span are calibrated with integrated 16-bit DACs, allowing sensors to be truly interchangeable. The device architecture includes a programmable sensor excitation, a 32-step programmable-gain amplifier (PGA), a 2K x 8 bits internal flash memory, four 16-bit DACs, and an on-chip temperature sensor. In addition to offset and span compensation, the device provides a unique temperature-compensation method for offset TC and FSO TC to provide a remarkable degree of flexibility while minimizing manufacturing costs. The device is packaged in a 16-pin TSSOP and covers the automotive AEC-Q100 Grade 1 temperature range of -40NC to +125NC. Benefits and Features S Complete Signal Conditioning in a Single IC Package  Provides Amplification, Calibration, and Temperature Compensation  Accommodates Sensor Output Sensitivities from 1mV/V to 200mV/V  Overvoltage Protection to 45V  Reverse-Voltage Protection to 45V S High-Precision Compensation Reduces Downstream Circuit Complexity  Fully Analog Signal Path  16-Bit Offset and Span-Calibration Resolution  On-Chip Lookup Table Supports Multipoint Calibration Temperature Correction S Supports Both Current and Voltage-Bridge Excitation S Fast 85µs Step Response S Sensor Fault Detection S Simple PCB Layout S Single-Pin Digital Programming S No External Trim Components Required Applications Pressure Sensors Strain Gauges Pressure Calibrators and Controllers Resistive Element Sensors Humidity Sensors Ordering Information appears at end of data sheet. For related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX1454.related. ����������������������������������������������������������������� Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND.) VDD, VDDF ............................................................ -0.3V to +3.0V VDDX ....................................................................... -45V to +45V All Other Pins............................. -0.3V to Min (VDDX + 0.3V, 6V) Continuous Power Dissipation (TA = +70NC) 16-Pin TSSOP (derate 11.1mW/NC above +70NC) ... 888.9mW Operating Temperature Range ........................ -40NC to +125NC Junction Temperature .....................................................+150NC Storage Temperature Range............................ -65NC to +150NC Lead Temperature (soldering, 10s) .............................. +300NC Soldering Temperature (reflow) ......................................+260NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) TSSOP Junction-to-Ambient Thermal Resistance (qJA) .......... 90NC/W Junction-to-Case Thermal Resistance (qJC) ............... 27NC/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (VDDX = 5V, VGND = 0V, TA = +25NC, unless otherwise noted.) (Note 2) PARAMETER GENERAL CHARACTERISTICS External Supply Voltage External Supply Current Oscillator Frequency LDO Regulator Output Voltage Power-On-Reset Threshold External Supply Voltage-Ramp Rate ANALOG INPUT Input Impedance Input-Referred OffsetTemperature Coefficient Input-Referred AdjustableOffset Range RIN (Notes 5, 6) Offset TC = 0 at gain = 44 (Note 7) Percent of 4V span, no load, IRO[3:0] = 0000bin, source impedance = 5kI, VOUT = 0.5V to 4.5V; measured at VOUT = [0.5V, 2.5V, 4.5V] at a gain of 112 CMRR Specified for common-mode voltages between GND and VDDX (Note 8) 1 -150 1 Q1 +150 MI FV/NC mV VDDX IDDX fOSC VDD VPOR Not to be loaded by external circuitry, must be connected to a 0.1FF capacitor to GND Referred to VDDX pin (Note 4) 1 (Note 3) 0.85 2.375 3.0 5.0 2.5 1 2.5 2.4 5.5 3 1.15 2.625 V mA MHz V V V/ms SYMBOL CONDITIONS MIN TYP MAX UNITS Nonlinearity of Signal Path 0.01 % Common-Mode Rejection Ratio Input-Referred Adjustable FSO 90 200 dB mV/V ����������������������������������������������������������������� Maxim Integrated Products 2 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection ELECTRICAL CHARACTERISTICS (continued) (VDDX = 5V, VGND = 0V, TA = +25NC, unless otherwise noted.) (Note 2) PARAMETER ANALOG OUTPUT Selectable in 32 steps PGA[4:0] = 00000bin PGA[4:0] = 00101bin PGA[4:0] = 01010bin PGA[4:0] = 01100bin Differential Signal Gain PGA[4:0] = 01101bin PGA[4:0] = 01110bin PGA[4:0] = 01111bin PGA[4:0] = 10000bin PGA[4:0] = 10110bin PGA[4:0] = 11100bin PGA[4:0] = 11111bin Output-Voltage Swing Output-Voltage Low Output-Voltage High Output Current Drive Capability Output Source Current Limit Output Sink Current Limit Output Impedance at DC Output Offset Ratio Output Offset TC Ratio Step Response (63% Final Value) Maximum Capacitive Load Gain = 36 Noise at Output Pin DC to 1kHz, source impedance = 5kI Gain = 256 Gain = 512 Gain = 1024 Gain = 2048 DVOUT/ DOffset DAC DVOUT/ DOffset TC DAC VOUT = 2.5V 0.9 0.9 85 0.01 0.5 1.5 3 6 12 mVRMS -8 0.2 1.2 1.2 No load IOUT = 1mA sinking, TA = TMIN to TMAX IOUT = 1mA sourcing, TA = TMIN to TMAX Maintain DC output to 2mV error compared to no load case (Note 4) VDDX 0.55 Q1 8 5.5 12.5 40 58 72 86 101 130 374 1037 1823 VGND + 0.02 6 to 2048 6 14 44 64 80 96 112 144 416 1152 2048 6.5 15.5 48 70 88 106 123 158 458 1267 2253 VDDX 0.32 0.25 V V V mA mA mA I V/V V/V Fs FF V/V SYMBOL CONDITIONS MIN TYP MAX UNITS ����������������������������������������������������������������� Maxim Integrated Products 3 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection ELECTRICAL CHARACTERISTICS (continued) (VDDX = 5V, VGND = 0V, TA = +25NC, unless otherwise noted.) (Note 2) PARAMETER BRIDGE DRIVE Bridge Current IBDR CMRATIO[1:0] = 00 Current-Mirror Ratio AA CMRATIO[1:0] = 01 CMRATIO[1:0] = 10 CMRATIO[1:0] = 11 Maximum Bridge Load Capacitance FSO DAC Code Range Output Voltage Range VBDR Voltage excitation mode (Note 4) (Note 4) (Note 4) 0.1 4.8 9.6 14.4 24 1 0x4000 0.75 0xC000 VDDX 0.75 16 DVOUT/DCode DAC reference = VDDX = 5V DVOUT/DCode DAC reference = VBDR = 2.5V DVBDR/DCode DAC reference = VDDX = 5V DVBDR/DCode DAC reference = VBDR = 2.5V Including sign DVOUT/DCode Input referred, DAC reference = VDDX = 5V (Note 9) 76 38 76 38 5 3.7 6 12 18 30 2.5 7.2 14.4 21.6 36 nF Hex V A/A mA SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL-TO-ANALOG CONVERTERS (DACs) DAC Resolution Offset DAC Bit Weight Offset TC DAC Bit Weight FSO DAC Bit Weight FSO TC DAC Bit Weight COARSE-OFFSET DAC IRO DAC Resolution IRO DAC Bit Weight INTERNAL RESISTORS OUT/DIO Pullup Resistance Current Source Reference Resistor Current Source Reference Resistor Temperature Coefficient FLASH MEMORY Endurance Retention Page Erase Time Mass Erase Time (Notes 4, 10) TA = +85NC (Note 4) (Notes 4, 11) (Notes 4, 11) 10,000 10 32 32 Cycles Years ms ms RPULLUP RISRC TCRISRC 100 10 kI kI Bits mV/bit Bits FV/bit FV/bit FV/bit FV/bit 600 ppm/NC ����������������������������������������������������������������� Maxim Integrated Products 4 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection ELECTRICAL CHARACTERISTICS (continued) (VDDX = 5V, VGND = 0V, TA = +25NC, unless otherwise noted.) (Note 2) PARAMETER Operating Current Program/Erase Current TEMPERATURE-TO-DIGITAL CONVERTER Temperature ADC Resolution Offset Gain Nonlinearity Lowest Digital Output Highest Digital Output DIGITAL INPUT (OUT/DIO) Input Low Voltage Input High Voltage OVERVOLTAGE PROTECTION Overvoltage-Protection Threshold FAULT DETECTION IN+/IN- Low Comparator Threshold IN+/IN- High Comparator Threshold Detection-Threshold Accuracy Comparator Hysteresis Output Clip Level During Fault Conditions Note Note Note Note Note Note Note 2: 3: 4: 5: 6: 7: 8: IOUT = 1mA sinking 0.2 x VBDR 0.8 x VBDR Q25 20 150 250 V V mV mV mV 5.53 5.75 6.0 V VIL VIH 0 VDDX x 2/3 VDDX/3 VDDX V V 8 Q3 1.5 Q0.5 0x00 0xAF Bits LSB NC/Bit LSB hex hex SYMBOL (Note 4) (Note 4) CONDITIONS MIN TYP MAX 8 7 UNITS mA mA All units are production tested at TA = +25NC and +125NC. Specifications over temperature are guaranteed by design. Excludes sensor or load current. Analog mode with voltage excitation on BDR pin, FSODAC = 0x8000. Specification is guaranteed by design. All electronics temperature errors are compensated together with sensor errors. The sensor and the device must be at the same temperature during calibration and use. This is the maximum allowable sensor offset. This is the sensor’s sensitivity normalized to its drive voltage, assuming a desired full-span output of VDDX - 1V and a nominal bridge voltage of VDDX/2. Note 9: Bit weight is ratiometric to VDDX. Note 10: Programming of the flash memory at room temperature is recommended. Note 11: No commands can be executed until the erase operation has completed. During erase operations, all commands sent to the device are ignored. ����������������������������������������������������������������� Maxim Integrated Products 5 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection Typical Operating Characteristics (VDD = 5V, TA = +25NC, unless otherwise noted.) OUTPUT NOISE MAX1454 toc01 16-BIT DAC DIFFERENTIAL NONLINEARITY MAX1454 toc02 IRO DAC DIFFERENTIAL NONLINEARITY 0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 PGA GAIN = 44V/V MAX1454 toc03 20 15 10 OUT/DIO (mV) VIN+ = VIN- = GND, C = 10nF, NO LOAD 36V/V GAIN SETTTING 10 8 6 4 DNL (LSB) 2 0 -2 -4 -6 -8 -10 0.5 5 0 -5 -10 -15 -20 0 100 200 300 400 500 TIME (ms) 0 16,384 32,768 49,152 65,536 0 5 10 IRO DAC CODE 15 16-BIT DAC CODE SIGNAL-PATH NONLINEARITY GAIN ERROR RELATIVE TO 25°C (% ) SIGNAL-PATH GAIN DEVIATION vs. TEMPERATURE MAX1454 toc05 MAX1454 toc04 OUTPUT VOLTAGE vs. INPUT SIGNAL FREQUENCY OUTPUT VOLTAGES NORMALIZED TO DC NORMALIZED OUTPUT VOLTAGE (dB) 0 -3 -6 -9 -12 -15 20mVP-P SINE-WAVE INPUT SIGNAL, PGA GAIN = 52V/V, 112V/V, 208V/V 100 1k INPUT SIGNAL FREQUENCY (Hz) 10k MAX1454 toc06 0.10 0.08 0.06 ERROR (%SPAN) SPAN = 4V 0.50 0.40 0.30 0.20 0.10 0 -0.10 -0.20 -0.30 -0.40 -0.50 44V/V 1024V/V 256V/V 6V/V 3 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 0 15 2.5 44V/V 6V/V 256V/V 1024V/V 3.5 4.5 -50 -25 0 25 50 75 100 125 OUT/DIO VOLTAGE (V) TEMPERATURE (°C) STEP RESPONSE (VARIOUS GAIN SETTINGS) MAX1454 toc07 OUTPUT VOLTAGE vs. INPUT VOLTAGE (FAULT DETECTION ENABLED) 3.5 OUTPUT VOLTAGE (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 OUTPUT CLIP LEVEL VBDR = 2.5V, OUTPUT PROGRAMMED TO 2.5V MAX1454 toc08 4.0 6V/V 1kHz SQUARE WAVE 256V/V, 1024V/V 44V/V OUT/DIO 1V/div 100µs/div 0 0.5 1.0 1.5 2.0 2.5 VIN+ = VIN- (V) ����������������������������������������������������������������� Maxim Integrated Products 6 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection Pin Configuration TOP VIEW N.C. N.C. GND IN+ BDR INI.C. N.C. 1 2 3 4 5 6 7 8 + 16 15 N.C. VDDX VDD VDDF OUT/DIO I.C. I.C. GND MAX1454 14 13 12 11 10 9 TSSOP Pin Description PIN 1, 2, 8, 16 3, 9 4 5 6 7, 10, 11 12 13 14 15 NAME N.C. GND IN+ BDR INI.C. OUT/DIO VDDF VDD VDDX No Connection. Not internally connected. Ground Positive Bridge Input. IN+ can be swapped to IN- by Configuration Register 1. Bridge Drive Negative Bridge Input. IN- can be swapped to IN+ by Configuration Register 1. Internally Connected. Connect I.C. to GND. Analog Output and Digital I/O (Multiplexed) Flash Memory Supply Voltage. Connect VDDF to VDD. Regulated Supply Voltage. Requires a 0.1FF capacitor from VDD to GND. External Supply Voltage. Bypass to GND with a 0.1FF capacitor. FUNCTION ����������������������������������������������������������������� Maxim Integrated Products 7 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection Detailed Description The MAX1454 is a highly integrated analog sensor signal conditioner targeted for automotive applications. The device provides amplification, calibration, and temperature compensation to enable an overall performance approaching the inherent repeatability of the sensor. The fully analog signal path introduces no quantization noise in the output signal while enabling digitally controlled calibration of offset and span with integrated 16-bit DACs, allowing sensors to be truly interchangeable. The device architecture includes a programmable sensor excitation, a 32-step PGA, a 2K x 8 bits internal flash memory, four 16-bit DACs, and an on-chip temperature sensor. In addition to offset and span compensation, the device provides a unique temperature-compensation method for offset TC and FSO TC, which was developed to provide a remarkable degree of flexibility while minimizing manufacturing costs. The device uses four 16-bit DACs (offset, FSO, offset TC, and FSO TC) with coefficients ranging from 0x0000 to 0xFFFF. The offset DAC and FSO DAC are referenced to VDDX (76FV resolution when VDDX = 5V). The offset TC DAC and FSO TC DAC are referenced to the bridge voltage (38FV resolution when bridge voltage is 2.5V). The user can select from one to 110 temperature points to compensate their sensor. This allows the latitude to compensate a sensor with a simple 1st-order linear correction or to match an unusual temperature curve. Programming up to 110 independent 16-bit flash memory locations corrects performance in 1.5NC temperature increments, over a range of -40NC to +125NC. For sensors that exhibit a characteristic temperature performance, a select number of calibration points can be used with a number of preset values that define the temperature curve. For full temperature compensation, the sensor and the device must be at the same temperature. In cases where the sensor is at a different temperature than the device, the device can use the sensor excitation voltage to provide 1st-order temperature compensation. The single-pin, multiplexed, serial digital input/output (DIO) communication architecture, and the ability to timeshare its activity with the sensor’s output signal, enables output sensing and calibration programming on a single line. The device allows complete calibration and sensor verification to be performed at a single test station. Once calibration coefficients have been stored in the device, the customer can retest to verify performance as part of a regular QA audit, or to generate final test data on individual sensors. The device (Figure 1) provides an analog amplification path for the sensor signal. It also uses an analog architecture for 1st-order temperature correction. A digitally controlled analog path is then used for nonlinear temperature correction. Calibration and correction is achieved by varying the offset and gain of a PGA, and by varying the sensor bridge excitation current or voltage. The PGA utilizes a switched-capacitor CMOS VDDX OVERVOLTAGE, UNDERVOLTAGE, AND REVERSE-VOLTAGE PROTECTION VDDX IRO DAC VDDX LDO VDD MAX1454 IN+ IN- C FAULT DETECTION PGA OUT OUT/DIO 5V DIO BDR CURRENT SOURCE TEMP SENSOR 8-BIT ADC 16-BIT DAC - FSO (176) 16-BIT DAC - OFFSET (176) 16-BIT DAC - OFFSET TC VDDF DIGITAL INTERFACE AND FLASH MEMORY VDDX 16-BIT DAC - FSO TC VBDR GND Figure 1. Functional Diagram ����������������������������������������������������������������� Maxim Integrated Products 8 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection technology, with an input-referred offset-trimming range of more than Q150mV. The PGA provides gain values from 6V/V to 2048V/V in 32 steps. The device includes an internal 2K x 8-bit flash memory to store calibration coefficients and user data. The internal memory contains the following information as 16-bitwide words: U Configuration Register 1 (CONFIG1) U Configuration Register 2 (CONFIG2) U Offset calibration coefficient (ODAC) table U Offset Temperature Coefficient register (OTCDAC) U Full-span output calibration coefficient (FSODAC) table U FSO Temperature Coefficient register (FSOTCDAC) U Power-Up Configuration register (PWRUPCFG) U 256 bytes (2048 bits) uncommitted for customer programming of manufacturing data (e.g., serial number and date) Initial offset correction is accomplished at the input stage of the signal-gain amplifiers by a coarse offset setting. Final offset correction occurs through the use of a temperature-indexed lookup table with 176 16-bit entries. The on-chip temperature sensor provides a unique 16-bit offset-trim value from the table with an indexing resolution of approximately 1.5NC, from -40NC to +125NC. Every 4ms (programmable through the CONFIG2 register), the on-chip temperature sensor provides indexing into the offset lookup table in flash memory, with the resulting value transferred to the offset DAC register. The resulting voltage is fed into a summing junction at the PGA output, compensating the sensor offset with a resolution of Q76FV (Q0.0019% FSO). If the offset TC DAC is set to zero, then the maximum temperature error is typically one degree of temperature drift of the sensor, given the offset DAC has corrected the sensor at every 1.5NC. Two functional blocks control the FSO gain calibration. First, a coarse gain is set by digitally selecting the gain of the PGA. Second, FSO DAC (and FSO TC DAC in current excitation mode) sets the sensor bridge current or voltage with the digital input obtained from the flash memory. FSO correction occurs through the use of a temperature-indexed lookup table with 176 16-bit entries. The on-chip temperature sensor provides a unique FSO trim from the table with one 16-bit value at every 1.5NC, from -40NC to +125NC. In most applications, the device and the sensor are at the same temperature, and coefficients in the offset and FSO lookup table correct both linear and nonlinear temperature errors to an accuracy approaching the sensor’s repeatability error. In these applications, the offset TC DAC and FSO TC DACs should be set to nominal values. In applications where the sensor and the device are at different temperatures, the FSO and offset DAC lookup tables cannot be used. Writing 16-bit calibration coefficients into the offset TC and FSO TC registers compensates 1st-order temperature errors. The piezoresistive sensor is powered by a current source, resulting in a temperature-dependent bridge voltage due to the sensor’s temperature coefficient of resistance (TCR). The reference inputs of the offset TC DAC and FSO TC DAC are connected to the bridge voltage, causing their outputs to change as a function of temperature. When properly programmed, they provide 1st-order temperature compensation of the input signal. Only two test temperatures are required for linear temperature compensation. The device uses a 10kI internal feedback resistor (RISRC) for FSO temperature compensation. Since the required feedback resistor value is sensor dependent, the device offers the ability to adjust the current-mirror ratio (CMRATIO) of the bridge driver. By selecting one of four CMRATIO settings in the CONFIG1 register, the bridge driver’s feedback loop can be optimized for silicon piezoresistive sensors typically ranging from 2kI to 10kI. The signal conditioner uses an internal temperature sensor to generate an 8-bit temperature index. An ADC converts the integrated temperature-sensor output to an 8-bit value every 4ms (programmable through the CONFIG2 register). This digitized value is then transferred into the temperature index register. The typical transfer function for the temperature index is as follows: TEMPINDEX = 0.6561 x temperature (NC) + 53.6 where TEMPINDEX is truncated to an 8-bit integer value. Typical values for the temperature index register are given in Table 13. Linear and Nonlinear Temperature Compensation Offset Correction Internal Temperature Sensor/ADC FSO Correction ����������������������������������������������������������������� Maxim Integrated Products 9 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection This index determines which FSO and offset DAC settings get loaded from the flash memory. The temperature-indexing boundaries are outside of the specified Absolute Maximum Ratings to eliminate indexing wrap-around errors. The minimum indexing value is 0x00, corresponding to approximately -82NC. All temperatures below this value generate the index 0x00. The maximum indexing value is 0xAF, corresponding to approximately +185NC. All temperatures higher than +185NC generate the index 0xAF. U The internal temperature sensor stores the 8-bit TEMPINDEX value. U Registers CONFIG1, CONFIG2, ODAC, FSODAC, OTCDAC, and FSOTCDAC are loaded from flash memory. U After each time the DAC refresh timer reaches its set time period, the internal-temperature ADC updates the 8-bit TEMPINDEX value and the ODAC and FSODAC registers are refreshed from the temperature-indexed flash memory locations. Calibration Operation (Registers Updated by Serial Communications) U Power is applied to the device. U The power-on-reset functions have completed. U The digital listening mode detects serial communication. U The registers can then be loaded from the serial digital interface by use of serial commands. See the Serial-Interface Command Format section. U (Optionally) After calibration, the device can be set to run in fixed analog operation using a software command. Note that the configuration and DAC registers refresh from flash memory upon entering fixed analog mode. The internal flash memory is organized as a 2K by 8-bit memory. It is divided into four pages with 512 bytes per page. Each page can be individually erased. The memory structure is arranged as shown in Table 1. The lookup tables for ODAC and FSODAC are also shown, with the respective TEMPINDEX pointer. The ODAC table occupies a segment from address 0x000 to address 0x15F, and the FSODAC table occupies a segment from 0x200 to 0x35F. The flash memory is configured as an 8-bit wide array so each of the 16-bit registers is stored as two 8-bit quantities. The configuration registers and the FSOTCDAC and OTCDAC registers are loaded from the preassigned locations in the flash memory. The ODAC and FSODAC registers are loaded from memory lookup tables using an index pointer that is a function of temperature. Maxim programs all flash memory locations to 0xFF, except for the reserved locations, 0x400 and 0x401. Values stored at 0x400 and 0x401 should be kept at the factory-programmed defaults. Overvoltage protection shuts down the device when the supply voltage is typically above 5.75V. A power-on reset prevents erroneous operation with supply voltages below 2.4V. Reverse voltage protects the device from negative voltages due to transients, reverse battery, etc. These protections allow the device to withstand any supply voltage from -45V to +45V. When enabled, the fault-detection circuitry on the device detects faults on the sensor inputs (IN+ and IN-). If either one of the sensor inputs is below the input low threshold (20% of VBDR) or above the input high threshold (80% of VBDR), a fault signal is asserted internally. If the part is in analog mode, the internal fault signal causes the voltage on the OUT/DIO pin to clip to a fixed DC level (typically 150mV). Enable or disable fault detection through the CONFIG2 register, bit 6 (ENFDET). The device has six 16-bit ICRs (ODAC, FSODAC, OTCDAC, FSOTCDAC, CONFIG1, and CONFIG2) that are loaded from flash memory, or loaded from the serial digital interface when in the digital programming mode. Data can be loaded into the ICRs under two different modes of operations (fixed analog operation and calibration operation). Fixed Analog Operation U The device has been calibrated. U Power is applied to the device. U The power-on-reset functions have completed. U The digital listening mode times out and the device goes into the fixed analog mode. Overvoltage, Undervoltage, Reverse-Voltage Protection Sensor Fault Detection Internal Flash Memory Internal Calibration Registers (ICRs) ���������������������������������������������������������������� Maxim Integrated Products 10 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection Table 1. Flash Memory Address Map PAGE LOW-BYTE ADDRESS (hex) 000 002 : 15C 15E 160 162 164 0 166 168 16A 16C 16E : 17E 180 : 1FE 200 202 : 35C 35E 1 360 : 37E 380 : 3FE 400 2 402 : 5FE 600 3 : 7FE HIGH-BYTE ADDRESS (hex) 001 003 : 15D 15F 161 163 165 167 169 16B 16D 16F : 17F 181 : 1FF 201 203 : 35D 35F 361 : 37F 381 : 3FF 401 403 : 5FF 601 : 7FF — Reserved — Reserved* Reserved — 128 general-purpose user bytes — Reserved 00 01 : AE AF to FF FSODAC lookup table — 128 general-purpose user bytes — Reserved TEMPINDEX[7:0] (hex) 00 01 : AE AF to FF — — — — — — — CONFIG1 CONFIG2 Reserved OTCDAC Reserved FSOTCDAC PWRUPCFG ODAC lookup table CONTENTS *Do not change values stored at locations 0x400 and 0x401 from the factory defaults. ���������������������������������������������������������������� Maxim Integrated Products 11 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection The DIO serial interface is used for asynchronous serial data communications between the device and a host calibration test system. The device automatically detects the baud rate of the host computer when the host transmits the initialization sequence. Baud rates between 4800bps and 38,400bps can be detected and used regardless of the internal oscillator frequency setting. Data format is always 1 start bit, 8 data bits, 1 stop bit, and no parity. Communications are only allowed when the device is in digital mode. Sending the initialization sequence shown below enables the device to establish the baud rate that initializes the serial port. The initialization sequence is 1 byte transmission of 01hex, as follows: 1111111101000000011111111. The first start bit 0 initiates the baud-rate synchronization sequence. The 8 data bits 01hex (LSB first) follow this and then the stop bit, which is indicated above as a 1, terminates the baud-rate synchronization sequence. This initialization sequence on OUT/DIO should occur after a period of 2ms after stable power is applied to the device. This allows time for the power-on-reset function to complete. All communication commands into the device follow a defined format utilizing an interface register set (IRS). The IRS is an 8-bit command that contains both an interface register set data (IRSD) nibble (4 bits) and an interface register set address (IRSA) nibble (4 bits). All internal calibration registers and flash memory locations are accessed for read and write through this interface register set. The IRS byte command is structured as follows: IRS[7:0] = IRSD[3:0], IRSA[3:0] THREE-STATE NEED WEAK PULLUP* THREE-STATE NEED WEAK PULLUP* 1111 STOP-BIT 11111 Communications Protocol where: IRSA[3:0] is the 4-bit interface register set address and indicates which register receives the data nibble IRSD[3:0]; IRSA[0] is the first bit on the serial interface after the start bit; IRSD[3:0] is the 4-bit interface register set data; IRSD[0] is the 5th bit received on the serial interface after the start bit The IRSA address decoding is shown in Table 14. A special command register to internal logic (CRIL[3:0]) causes execution of special command sequences within the device. These command sequences are listed as CRIL command codes, as shown in Table 15. A 16-bit write to any of the internal calibration registers is performed as follows: 1) Write the 16 data bits to DHR[15:0] using 4 byte accesses into the interface register set. 2) Write the address of the target internal calibration register to ICRA[3:0]. 3) Write the load internal calibration register (LdICR) command to CRIL[3:0]. When a LdICR command is issued to the CRIL register, the calibration register loaded depends on the address in the internal calibration register address (ICRA). Table 16 specifies which calibration register is decoded. Initialization Sequence Special Command Sequences Write Examples Serial-Interface Command Format DRIVEN BY TESTER DRIVEN BY MAX1454 1 000 MSB OUT/DIO 1 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 1 START-BIT LSB MSB STOP-BIT 1111 0 0 0 0 0 START-BIT LSB *PROGRMMABLE DELAY DETERMINED BY READDLY SETTING. Figure 2. OUT/DIO Output Data Format ���������������������������������������������������������������� Maxim Integrated Products 12 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection The internal flash memory needs to be erased (bytes set to FFhex) prior to programming the desired contents. The internal flash memory can be entirely erased with the ERASE command, or partially erased with the PageErase command (see Table 15). It is necessary to wait 32ms after issuing the ERASE or PageErase command before sending the next command. After the memory has been erased (value of every byte = FFhex), the user can program its contents using the following procedure: 1) Write the 8 data bits to DHR[7:0] using 2 byte accesses into the interface register set. 2) Write the address of the target internal memory location to IEEA[10:0] using 3 byte accesses into the interface register set. 3) Write the flash memory write command (EEPW) to CRIL[3:0]. Caution: It is not recommended to change values of flash memory locations 0x400 and 0x401. Changing the values at these locations (through a memory write or page/total erasure) can cause the device to lose its factory trim settings, which can affect device performance. Erasing and Writing the Flash Memory The data returned on an RdIRS command depends on the address in IRSP. Table 17 defines what is returned for the various addresses. When an RdAlg command is written to CRIL[3:0] the analog signal designated by ALOC[4:0] is asserted on the OUT/DIO pin. The duration of the analog signal is determined by ATIM[3:0], after which the pin reverts to a digital I/O. The host computer or calibration system must three-state its connection to OUT/DIO after asserting the stop bit. Do not load the OUT/DIO line when reading nonbuffered internal signals. The analog output sequence is shown in Figure 3. The digital serial interface and analog output are internally multiplexed onto OUT/DIO. The duration of the analog signal is controlled by ATIM[3:0], as given in Table 18. The analog signal driven onto the OUT/DIO pin is determined by the value in the ALOC register. The signals are specified in Table 19. The device supports burst mode operation for reading/ writing blocks of data from/to flash memory addresses 0x000 to 0x3FF. Addresses 0x400 and 0x401 cannot be accessed with burst mode. First, program the starting address of the flash memory into IEEA[10:0]. Next, enable burst mode by writing a 1 to the burst mode enable bit (BURSTEN). In burst mode, an internal counter is used to increment the memory address with every read/write operation. With the 0-to-1 transition of BURSTEN, the memory address stored in IEEA[10:0] is latched into the internal counter as the starting address. Once the burst enable is high, the internal counter takes precedence over the memory address bits. All the memory read/ write operations happen on the address indicated by the internal counter. Burst Mode Operation When an RdIRS command is written to CRIL[3:0], OUT/ DIO is configured as a digital output and the contents of the register designated by IRSP[3:0] are sent out as a byte framed by a start bit. Once the tester finishes sending the RdIRS command, it must three-state its connection to OUT/DIO to allow the device to drive the OUT/DIO line. The device three-states OUT/DIO high for a programmable number of byte times (determined by READDLY[1:0]) and then sends out the data byte (with a start and stop bit). The sequence is shown in Figure 2. Multiplexed Analog and Serial Digital Output DRIVEN BY TESTER THREE-STATE NEED WEAK PULLUP 2ATIM +1 BYTE TIMES THREE-STATE NEED WEAK PULLUP 111111111 1 OUT/DIO 1 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 START-BIT LSB MSB STOP-BIT VALID OUT Figure 3. Analog Output Timing ���������������������������������������������������������������� Maxim Integrated Products 13 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection To write to a flash memory location in burst mode, the user simply writes DHR[3:0], followed by DHR[7:4]. Since the internal counter keeps track of the memory address, there is no need to send address information to the part. After DHR[7:4] is written, a write command to the flash memory is automatically generated, the data in DHR[7:0] is written to the memory, and the address counter is incremented. If the user wishes to skip certain memory locations, first exit burst mode (by writing a 0 to BURSTEN), then program a new starting address. The user can now reenable burst mode again. During burst read operations, the device waits for a read command before sending out data whose address is derived from the internal counter. To start burst read mode, first program the flash memory address into IEEA[10:0]. Next, write a 1 to BURSTEN to enable burst mode. The IRSP register must then be programmed to 0 (through an IRSA = 8 command). Then, send the flash memory read (RdEEP) CRIL command to initiate an internal read; the device sends the contents of the flash memory out of the DIO/OUT pin through the serial interface. Similar to the burst write operation, the burst read operation does not skip memory locations. To skip memory locations, first write a zero to BURSTEN to end burst mode. Next, change the memory address bits using the corresponding command bytes. Once the desired starting address is loaded, reenable burst mode to resume burst reading. Always disable burst mode (IRSD = 0000 when IRSA = 1101) after burst reading/writing all the locations. This is necessary to continue in digital programming mode after all the burst read/writes are complete. Note: Use burst mode to program a maximum of 1024 locations. Care must be taken to avoid additional writes to prevent unintentionally rewriting locations. The internal address counter wraps around to address 0x000 after reaching address 0x3FF. Register Map Table 2. Registers REGISTER CONFIG1 CONFIG2 ODAC OTCDAC FSODAC FSOTCDAC PWRUPCFG Configuration Register 1 Configuration Register 2 Offset DAC Offset Temperature Coefficient DAC Full-Span Output DAC Full-Span Output Temperature Coefficient DAC Power-Up Configuration DESCRIPTION Table 3. Configuration Register 1 (CONFIG1[15:0]) BIT 15:11 10 9 8:5 4:3 2 1 0 NAME PGA[4:0] PGA Sign IRO Sign IRO[3:0] CMRATIO[1:0] Reserved ODAC Sign OTCDAC Sign Programmable-gain amplifier setting Logic 1 inverts IN- and IN+ polarity Logic 1 for positive input-referred offset (IRO), logic 0 for negative input-referred offset (IRO) Input-referred coarse-offset adjustment Bridge driver current-mirror ratio Set to logic 0 Logic 1 for positive offset DAC output, logic 0 for negative offset DAC output Logic 1 for positive offset TC DAC output, logic 0 for negative offset TC DAC output DESCRIPTION ���������������������������������������������������������������� Maxim Integrated Products 14 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection Table 4. Configuration Register 2 (CONFIG2[15:0]) BIT 15:7 6 5:4 3 2:1 0 NAME Reserved ENFDET REFRATE[1:0] ENPULLUP READDLY[1:0] EXCIMODE Reserved. Set to logic 0. Enable fault-detection circuitry. Logic 1 enables fault detection. DAC register refresh rate during fixed analog mode Enable internal pullup resistor on OUT/DIO pin. Logic 1 enables pullup. Number of byte times the part waits before responding to read requests Logic 1 for voltage excitation mode, logic 0 for current excitation mode DESCRIPTION Table 5. Power-Up Configuration Register (PWRUPCFG[15:0]) BIT 15:7 6:3 2:0 NAME Reserved DIGMODETIME[3:0] CTRLREP[2:0] Reserved. Set to logic 0. Number of ms the part waits to receive a control word before switching to analog mode Number of repetitions of the control word required to switch the part into digital mode DESCRIPTION Table 6. PGA Setting (PGA[4:0]) PGA[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 PGA GAIN (V/V) 6 7 9 11 12 14 18 22 28 36 44 52 64 80 96 112 PGA[4:0] 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 PGA GAIN (V/V) 144 176 208 256 288 352 416 512 576 704 832 1024 1152 1408 1664 2048 ���������������������������������������������������������������� Maxim Integrated Products 15 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection Table 7. Input-Referred Offset Setting (IRO Sign, IRO[3:0]) INPUTREFERRED OFFSET CORRECTION AS % OF VDDX 1.11 1.04 0.96 0.89 0.81 0.74 0.67 0.59 0.52 0.44 0.37 0.30 0.22 0.15 0.07 0 INPUT-REFERRED OFFSET CORRECTION AT VDDX = 5V DC (mV) 55.5 51.8 48.1 44.4 40.7 37 33.3 29.6 25.9 22.2 18.5 14.8 11.1 7.4 3.7 0 INPUT-REFERRED OFFSET IRO[3:0] CORRECTION AS % OF VDDX 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 -0.07 -0.15 -0.22 -0.30 -0.37 -0.44 -0.52 -0.59 -0.67 -0.74 -0.81 -0.89 -0.96 -1.04 -1.11 INPUT-REFERRED OFFSET CORRECTION AT VDDX = 5V DC (mV) 0 -3.7 -7.4 -11.1 -14.8 -18.5 -22.2 -25.9 -29.6 -33.3 -37 -40.7 -44.4 -48.1 -51.8 -55.5 IRO SIGN IRO[3:0] IRO SIGN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 8. Bridge Driver Current-Mirror Ratio Setting (CMRATIO[1:0]) CMRATIO[1:0] 00 01 10 11 CURRENTMIRROR RATIO 6 12 18 30 BRIDGE RESISTANCE (kI) 10 5 3.33 2 Table 9. DAC Refresh Rate (REFRATE[1:0]) REFRATE[1:0] 00 01 10 11 UPDATE INTERVAL (ms) 4.096 16.384 65.536 131.072 Table 10. Wait Time for Read Requests (READDLY[1:0])* READDLY[1:0] 00 01 10 11 RESPONSE DELAY IN BYTE TIMES (8-BIT TIME) 1 byte time (i.e., (1 x 8)/baud rate) 2 byte times 4 byte times 8 byte times *The selected delay time is applied before and after the requested byte is read. ���������������������������������������������������������������� Maxim Integrated Products 16 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection Table 11. DIGMODETIME Setting* (DIGMODETIME[3:0] ) DIGMODETIME[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 to 1111 DESCRIPTION Part stays in digital mode for 1ms after power-up (for each repetition of the control word) 2ms wait 3ms wait 4ms wait 5ms wait 8ms wait 10ms wait 15ms wait 20ms wait 25ms wait 30ms wait** Table 12. CTRLREP Setting (CTRLREP[2:0]) CTRLREP[2:0] 000 001 010 011 100 101 110 111 DESCRIPTION 1 control word expected 1 control word expected 2 control words expected 3 control words expected 4 control words expected 5 control words expected 6 control words expected Part powers up in digital mode* *Parts ship with a CTRLREP setting of 111. Table 13. Temperature Index Typical Values TEMPERATURE (NC) -40 +25 +85 +125 27 70 109 136 TEMPINDEX[7:0] DECIMAL HEXADECIMAL 1B 46 6D 88 *Wait times specified are based on a typical oscillator frequency of 1MHz. Wait times are proportional to the oscillation frequency. Actual wait times depend on the factory-trimmed oscillator frequency. **Parts ship with a DIGMODETIME setting of 1111. Table 14. IRSA Decoding (IRSA[3:0]) IRSA[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1100 to 1111 DESCRIPTION Write IRSD[3:0] to DHR[3:0] (data hold register). Write IRSD[3:0] to DHR[7:4] (data hold register). Write IRSD[3:0] to DHR[11:8] (data hold register). Write IRSD[3:0] to DHR[15:12] (data hold register). Reserved. Reserved. Write IRSD[3:0] to ICRA[3:0] or IEEA[3:0] (internal calibration register address or internal flash memory address nibble 0). Write IRSD[3:0] to IEEA[7:4] (internal flash memory address nibble 1). Write IRSD[3:0] to IRSP[3:0] or IEEA[10:8] (interface register set pointer where IRSP[2:0] is IEEA[10:8]). Write IRSD[3:0] to CRIL[3:0] (command register to internal logic). Write IRSD[3:0] to ATIM[3:0] (analog timeout value on read). Write IRSD[3:0] to ALOC[3:0] (analog location). Write IRSD[0] to ALOC[4] (analog location). Write IRSD[0] to the burst mode enable bit (BURSTEN). See the Burst Mode Operation section for details regarding read/write operations in this mode. Logic 1 enables burst mode. Reserved. ���������������������������������������������������������������� Maxim Integrated Products 17 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection Table 15. CRIL Command Codes (CRIL[3:0]) CRIL[3:0] 0000 0001 0010 0011 0100 0101 NAME LdlCR EEPW ERASE RdICR RdEEP RdIRS DESCRIPTION Load internal calibration register at address given in ICRA with data from DHR[15:0]. Flash memory write of 8 data bits from DHR[7:0] to address location pointed by IEEA[10:0]. Erase all flash memory (all bytes equal FFhex). Read internal calibration register as pointed to by ICRA and load data into DHR[15:0]. Read internal flash memory location pointed by IEEA[10:0] and load data into DHR[7:0]. Read interface register set pointer IRSP[3:0] and output the multiplexed digital signal onto OUT/DIO (see Table 17). Output the multiplexed analog signal (i.e., test mux output) onto OUT/DIO. The duration (in byte times) that the signal is asserted onto the pin is specified by ATIM[3:0] (Table 18) and the analog location is specified by ALOC[4:0] (Table 19). Erases the page of the flash memory as pointed by IEEA[10:9]. There are 512 bytes per page. Switch to fixed analog mode. Reserved. Relearn the baud rate. 0110 0111 1000 1001 to 1110 1111 RdAlg PageErase SwToANA Reserved RELEARN Table 16. ICRA Decoding (ICRA[3:0]) IRCA[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 to 1111 NAME CONFIG1 CONFIG2 ODAC OTCDAC FSODAC FSOTCDAC PWRUPCFG Reserved Configuration Register 1 Configuration Register 2 Offset DAC Offset Temperature Coefficient DAC Full-Span Output DAC Full-Span Output Temperature Coefficient DAC Power-Up Configuration Reserved (do not write to these locations) DESCRIPTION Table 17. IRSP Decoding (IRSP[3:0]) IRSP[3:0] 0000 0001 0010 0011 0100 0101 DHR[7:0] DHR[15:8] 0bin, IEEA[10:8], ICRA[3:0] concatenated CRIL[3:0], IRSP[3:0] concatenated 0000bin, ATIM[3:0] concatenated IEEA[7:0] flash memory address byte RETURNED VALUE IRSP[3:0] 0110 0111 1000 1001 1010 to 1110 1111 RETURNED VALUE IEED[7:0] flash memory data byte TEMPINDEX[7:0] BitClock[7:0] 00bin, BURSTEN, ALOC[4:0] concatenated Reserved 11001010 (CAhex) (this can be used to test communication) ���������������������������������������������������������������� Maxim Integrated Products 18 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection Table 18. ATIM Definition (ATIM[3:0]) ATIM[3:0] 0000 0001 0010 0011 0100 0101 0110 DURATION OF ANALOG SIGNAL SPECIFIED IN BYTE TIMES (8-BIT TIME) 20 + 1 = 2 byte times (i.e., (2 x 8)/baud rate) 21+ 1 = 3 byte times 22 + 1 = 5 byte times 23+ 1 = 9 byte times 24 + 1 = 17 byte times 25 + 1 = 33 byte times ATIM[3:0] 0111 1000 1001 1010 1011 1100 1101 1110 or 1111 DURATION OF ANALOG SIGNAL SPECIFIED IN BYTE TIMES (8-BIT TIME) 27 + 1 = 129 byte times 28 + 1 = 257 byte times 29 + 1 = 513 byte times 210 + 1 = 1025 byte times 211 + 1 = 2049 byte times 212 + 1 = 4097 byte times 213 + 1 = 8193 byte times 214 + 1 = 16,385 byte times 26 + 1 = 65 byte times Table 19. ALOC Definition (ALOC[4:0]) ALOC[4:0] BUFFERED OUTPUTS 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 to 11101 11110 11111 OUT BDR1 VISRC VDD AGND VDUALDAC VODAC VOTCDAC VREF Reserved Reserved REFD3BUF Reserved Reserved IN+ INBDR2 VDDI GND Reserved CLIPLVL Hi-Z PGA output Bridge drive voltage Bridge drive current-setting voltage (see the Detailed Block Diagram) Internal regulated supply Internal analog ground; approximately 1/2 of VDD Full-scale output plus full-scale output TC DAC (see the Detailed Block Diagram) Offset DAC (see the Detailed Block Diagram) Offset TC DAC (see the Detailed Block Diagram) Bandgap voltage reference (nominally 1.25V) Reserved Reserved Ratiometric reference; approximately 1/3 of VDDX Reserved Reserved Sensor’s positive input Sensor’s negative input Bridge drive voltage Internal positive supply Internal ground Reserved Output clip level during fault conditions (buffered output) High-impedance state on OUT/DIO NAME DESCRIPTION NONBUFFERED OUTPUTS SPECIAL-PURPOSE OUTPUTS ���������������������������������������������������������������� Maxim Integrated Products 19 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection POWER-ON POWER-ON RESET LOADS VALUES FROM FLASH MEMORY. SERIAL COMMUNICATION READY AFTER 2ms NO YES CTRLREP = 0x7? NO SET DIGITAL MODE TIMEOUT COUNTER AND CONTROL WORD REPETITION COUNTER BASED ON PWRUPCFG REGISTER SETTING NO INITIALIZATION BYTE RECEIVED? YES SYNCHRONIZE BAUD RATE FROM INITIALIZATION BYTE NO INITIALIZATION BYTE RECEIVED? YES SYNCHRONIZE BAUD RATE FROM INITIALIZATION BYTE NO DECREMENT DIGITAL MODE TIMEOUT COUNTER NO TIMEOUT COUNTER = 0? YES RESET DIGITAL MODE TIMEOUT COUNTER BASED ON DIGMODETIME SETTING NO CONTROL WORD RECEIVED? (0xAD) YES DECREMENT CONTROL WORD REPETITION COUNTER NO DECREMENT DIGITAL MODE TIMEOUT COUNTER NO TIMEOUT COUNTER = 0? YES NO REPETITION COUNTER = 0? YES DEVICE ENTERS DIGITAL PROGRAMMING MODE COMMAND BYTE RECEIVED? YES NO NO EXECUTE COMMAND COMMAND BYTE = 0x89? YES DEVICE ENTERS FIXED ANALOG MODE Figure 4. Power-Up Flow Chart ���������������������������������������������������������������� Maxim Integrated Products 20 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection The device uses a power-up state machine to determine whether the device should switch to the fixed analog mode, or enable the digital programming mode (Figure 4). At power-up, the device loads the PWRUPCFG register to establish a wait time (Table 11), and the number of control words (Table 12) required to enter the digital programming mode. If the wait time expires, the device automatically switches to the fixed analog mode. However, if the interface receives the correct number of control words within the established wait times, the device enters the digital programming mode. A serial command enables the device to switch into the fixed analog mode after the part has been programmed. Note: Setting CTRLREP[2:0] to 111 in the PWRUPCFG flash memory location forces the part into the digital programming mode without the need for control words (an initialization byte is still required). By default, parts shipped from the factory are programmed to start in the digital programming mode. The device compensates for sensor offset, FSO, and temperature errors by loading the internal calibra tion registers with the compensation values. These compensation values can be loaded to registers directly through the serial digital interface during calibration, or loaded automatically from flash memory at power-on. During the calibration process, the device is configured, tested, and compensation values are calculated and stored in the internal flash memory. Once programmed, after each power-up, the device autoloads the registers from flash memory and is ready for use without further configuration. Compensation requires an examination of the sensor performance over the operating pressure and temperature range. A minimum of two test temperatures and two test pressures (zero and full scale) are required to correct the linear component of temperature error to achieve pressure calibration. For higher temperature accuracy, more test temperatures must be used. A typical compensation procedure can be summarized in the following sections. Initialize the Device Initialize the device registers with known values (e.g., compensation coefficients of a similar device) or determine values for IRO, PGA gain, FSO DAC, and offset Power-Up Control Sequence DAC based on sensor parameters (offset, sensitivity, bridge resistance, etc). Select a current-mirror ratio value corresponding to the sensor in use. Initialization is an important step to ensure that the device output remains in range over the full operating conditions. When the device is initialized successfully, the excitation voltage is within the normal range, and the output voltage is around the desired offset value (when zero pressure is applied). Characterize the Sensor at Test Temperatures 1) Set the temperature to the first test temperature point and allow the system to reach equilibrium. 2) By changing the FSO DAC through an iterative process, set the bridge voltage to a value that produces the desired output span. Change the offset DAC as necessary. 3) Once the desired output span is achieved, change the offset DAC to produce the final offset. 4) Record the values of TEMPINDEX, FSODAC, and ODAC. The device flash memory can be used to store the information. 5) Change the temperature to the next value and repeat this procedure to determine a unique value for the TEMPINDEX, FSODAC, and ODAC at every test temperature. Calculate Compensation Coefficients 1) FSO Lookup Table: Using a fitting function, fit the FSODAC and TEMPINDEX values obtained during the characterization step and generate an array of 176 elements (FSODAC vs. TEMPINDEX array, where 0 ≤ TEMPINDEX ≤ 175). 2) Offset Lookup Table: Using a fitting function, fit the ODAC and TEMPINDEX values obtained during the characterization step and generate an array of 176 elements (ODAC vs. TEMPINDEX array). Program Flash Memory and Final Test 1) Program the device by writing to the ODAC and FSODAC lookup tables, and the OTCDAC, FSOTCDAC, CONFIG1, CONFIG2, PWRUPCFG, and user data locations in flash memory. 2) While the sensor is still at the last test temperature point, perform a final test to verify the compensation accuracy. Sensor Compensation Overview ���������������������������������������������������������������� Maxim Integrated Products 21 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection Applications Information Ratiometric output configuration provides an output that is proportional to the power-supply voltage. This output can then be applied to a ratiometric ADC to produce a digital value independent of supply voltage. Ratiometricity is an important consideration for battery-operated instruments, automotive, and some industrial applications. The device provides a high-performance ratiometric output with a minimum number of external components (Figure 5). These external components include the following: U Supply bypass capacitor (VDDX) U 0.1FF output capacitor (VDD) U Optional output capacitor (OUT/DIO) Typical Ratiometric Operating Circuit Nonratiometric output configuration enables the sensor power to vary over a wide range. A high-performance voltage reference, such as the MAX15006B, is incorporated in the circuit to provide a stable supply and reference for device operation. A typical nonratiometric circuit is shown in Figure 6. Nonratiometric operation is valuable when a wide range of input voltage is to be expected and the system ADC or readout device does not enable ratiometric operation. +5V Typical Nonratiometric Operating Circuit (6V DC < VPWR < 40V DC) 15 5 6 VDDX BDR INVDD VDDF MAX1454 14 13 4 IN+ OUT/DIO GND 9 12 0.1µF 0.1µF 0.01µF OUT/DIO GND Figure 5. Basic Ratiometric Output Configuration 8 5 BDR 6 IN15 VDDX VDD VDDF 13 14 MAX15006B OUT GND 5 IN 1 2N4392 VPWR +6V TO +40V MAX1454 4 IN+ OUT/DIO 12 OUT/DIO 0.1µF 2.2µF 0.1µF 0.01µF GND GND 9 Figure 6. Basic Nonratiometric Output Configuration ���������������������������������������������������������������� Maxim Integrated Products 22 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection Detailed Block Diagram VDDX VDD FLASH MEMORY (LOOKUP PLUS CONFIGURATION DATA) FLASH ADDRESS 0x000 + 0x001 1/3 VDDX VDUALDAC : 0x15E + 0x15F 1/3 VDDX C OVERVOLTAGE, UNDERVOLTAGE, AND REVERSEVOLTAGE PROTECTION LDO USAGE OFFSET DAC LOOKUP TABLE (176 x 16 BITS) CONFIGURATION REGISTER 1 CONFIGURATION REGISTER 2 RESERVED OFFSET TC REGISTER RESERVED FSO TC REGISTER POWER-UP CONFIG REGISTER RESERVED VDDF 0x160 + 0x161 16 0x162 + 0x163 0x164 + 0x165 0x166 + 0x167 0x168 + 0x169 16 0x16A + 0x16B 0x16C + 0x16D 0x16E + 0x16F : 16 + SIGN 0x17E + 0x17F 0x180 + 0x181 : 0x1FE + 0x1FF 0x200 + 0x201 16 + SIGN : 0x35E + 0x35F 0x360 + 0x361 : 0x37E + 0x37F 0x380 + 0x381 : 0x3FE + 0x3FF 6x, 12x, 18x, OR 30x CURRENT MIRROR FSO DAC 1/3 VBDR -1/2 FSO TC DAC 1/3 VBDR VOTCDAC OFFSET TC DAC CURRENT MODE 50kI VISRC RISRC 10kI CURRENT MODE CURRENT MODE USER STORAGE (128 BYTES) 1/3 VDDX VOLTAGE MODE GND 1/3 C VODAC FSO DAC LOOKUP TABLE (176 x 16 BITS) OFFSET DAC RESERVED USER STORAGE (128 BYTES) BANDGAP TEMP SENSOR TEMP ADC 8 0x400 + 0x401 : 0x7FE + 0x7FF DIO RESERVED BDR IN- FAULT DETECTION 3 PHASE REVERSAL MUX DIGITAL INTERFACE OUT 5V DIO DRIVER OUT/DIO OUT/DIO MUX IN+ C C GND INPUT-REFERRED OFFSET (COARSE OFFSET) IRO SIGN, IRO[3:0] 1, 1111 1, 1110 1, 1101 1, 1100 1, 1011 1, 1010 1, 1001 1, 1000 1, 0111 1, 0110 1, 0101 1, 0100 1, 0011 1, 0010 1, 0001 1, 0000 OFFSET (mV) 55.5 51.8 48.1 44.4 40.7 37.0 33.3 29.6 25.9 22.2 18.5 14.8 11.1 7.4 3.7 0 IRO SIGN, IRO[3:0] 0, 0000 0, 0001 0, 0010 0, 0011 0, 0100 0, 0101 0, 0110 0, 0111 0, 1000 0, 1001 0, 1010 0, 1011 0, 1100 0, 1101 0, 1110 0, 1111 OFFSET (mV) 0 -3.7 -7.4 -11.1 -14.8 -18.5 -22.2 -25.9 -29.6 -33.3 -37.0 -40.7 -44.4 -48.1 -51.8 -55.5 PGA[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 PROGRAMMABLE GAIN STAGE PGA GAIN (V/V) 6 7 9 11 12 14 18 22 28 36 44 52 64 80 96 112 PGA[4:0] 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 PGA GAIN (V/V) 144 176 208 256 288 352 416 512 576 704 832 1024 1152 1408 1664 2048 ���������������������������������������������������������������� Maxim Integrated Products 23 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 16 TSSOP PACKAGE CODE U16M+1 OUTLINE NO. 21-0066 LAND PATTERN NO. 90-0117 Ordering Information PART MAX1454AUE/V+ TEMP RANGE -40NC to +125NC PIN-PACKAGE 16 TSSOP +Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. ���������������������������������������������������������������� Maxim Integrated Products 24 MAX1454 Precision Sensor Signal Conditioner with Overvoltage Protection Revision History REVISION NUMBER 0 REVISION DATE 6/11 Initial release DESCRIPTION PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 25 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.