MAX14569

19-5523; Rev 0; 9/10 Dual-Pair LLT with Charge Pump and High-ESD Protection General Description The MAX14569 is a dedicated dual-pair unidirectional logic-level translator that is ideal for industrial and metering applications. Voltages VCC and VL set the logic levels on either side of the device. Logic-high signals present on the VL side of the device appear as highvoltage logic signals on the VCC side of the device and vice versa. The device has two pairs of logic-level translators in back-to-back configuration: one logic-level translator from a low voltage to a high voltage and the other logiclevel translator from a high voltage to a low voltage. The device also features a high-efficiency charge pump to boost the battery input, VBAT, to VCC (5V). The device features an extreme power-saving mode that reduces supply current to a typical 0.01FA. The device also features thermal short-circuit protection for enhanced protection in applications that route signals externally. In addition, the device features enhanced high electrostatic discharge (ESD) Human Body Model (HBM) protection on OUTAVCC, INBVCC, OUTCVCC, and INDVCC ports up to Q25kV. The MAX14569 is available in a 16-pin QSOP package, and is specified over the -40NC to +85NC extended temperature range. Features S Ultra-Low Shutdown Supply Current, 0.01µA (typ) S Ultra-Low VL Supply Current, 1µA (max) S Operates Down to 1.6V on VL S Continuous Current Drive Capability > 10mA S Extended ESD Protection on VCC Input and MAX14569 Output Lines ±25kV Human Body Model ±15kV IEC 61000-4-2 Air-Gap Discharge ±12kV IEC 61000-4-2 Contact Discharge S 16-Pin QSOP Package S -40NC to +85NC Extended Operating Temperature Range Applications Automatic Meter Reader Remote Communications System Industrial Networking Ordering Information PART MAX14569EEE+T TEMP RANGE -40NC to +85NC PIN-PACKAGE 16 QSOP +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. Typical Operating Circuit 1.8V TO 3.3V 0.1 F 0.47 F 1F LITHIUM BATTERY VL VBAT CP1 CHARGE PUMP CP2 VCC 5V µPROCESSOR EN DATA DATA ENAB INAVL OUTBVL 2.2 F OUTAVCC INBVCC METER TRANSMITTER UNIT GND EN DATA DATA GND ENCD INCVL OUTDVL MAX14569 OUTCVCC INDVCC GND METER TRANSMITTER UNIT GND _______________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Dual-Pair LLT with Charge Pump and High-ESD Protection MAX14569 ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND.) VBAT, VL .................................................................. -0.3V to +6V VCC (no shutdown condition) ..................... (VBAT - 0.3V) to +6V VCC (shutdown condition) ....................................... -0.3V to +6V CP1 .......................................................... -0.3V to (VBAT + 0.3V) CP2 .......................................................................... -0.3V to +6V ENAB, ENCD ........................................................... -0.3V to +6V INAVL, INCVL .......................................................... -0.3V to +6V OUTBVL, OUTDVL ...................................... -0.3V to (VL + 0.3V) INBVCC, INDVCC .................................... -0.3V to (VCC + 0.3V) OUTAVCC, OUTCVCC ............................. -0.3V to (VCC + 0.3V) Short-Circuit Current OUTAVCC, OUTCVCC, OUTBVL, OUTDVL to GND ................ Continuous Short-Circuit Duration OUTAVCC, OUTCVCC, OUTBVL, OUTDVL to GND .................................... Continuous Continuous Power Dissipation (TA = +70NC) QSOP (derate 9.6mW/NC above +70NC) .................. 771.5mW Junction-to-Ambient Thermal Resistance (Note 1) BJA ........................................................................... 103.7NC/W Junction-to-Case Thermal Resistance (Note 1) BJC ............................................................................... 37NC/W Operating Temperature Range .......................... -40NC to +85NC Storage Temperature Range............................ -65NC to +150NC Junction Temperature .....................................................+150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VBAT = 2.3V to 5.5V, VL = 1.6V to 5.5V, CVBAT = 1FF, CVCC = 2.2FF, CVL = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VBAT = 3.6V, VL = 3.0V, and TA = +25NC.) (Notes 2, 3, 4) PARAMETER POWER SUPPLIES VBAT Supply Range VL Supply Range Supply Current from VL VBAT Shutdown Supply Current VL Shutdown Supply Current VBAT Change in Supply Current with ENAB and ENCD at VIL OUTAVCC Shutdown Mode Leakage Current OUTCVCC Shutdown Mode Leakage Current OUTBVL, OUTDVL Shutdown Mode Leakage Current INBVCC Shutdown Mode Leakage Current INDVCC Shutdown Mode Leakage Current VBAT VL IQVL ISHDN-VBAT ISHDN-VL INBVCC = INDVCC = VCC, INAVL = INCVL = VL VINAVL = VINCVL = 0V, VENAB = VENCD = 0V VENAB = VENCD = 0V VENAB = VENCD = VIL (Notes 2, 4, 5) VENAB = 0V, VENCD = VIH, VOUTAVCC = 5V VENAB = VIH, VENCD = 0V, VOUTCVCC = 5V VENAB = VENCD = 0V, VOUTBVL = VOUTDVL = 0V VENAB = 0V, VENCD = VIH, VINBVCC = 5V VENAB = VIH, VENCD = 0V, VINDVCC = 5V 0.01 0.01 0.01 0.01 2.3 1.6 5.5 5.5 1 0.5 0.5 V V FA FA FA SYMBOL CONDITIONS MIN TYP MAX UNITS DIVBAT 1 FA IOUTAVCC_LEAK IOUTCVCC_LEAK IOUTBVL_LEAK IOUTDVL_LEAK IINBVCC_LEAK IINDVCC_LEAK 1 1 FA FA 0.01 1 FA 0.01 0.01 1 1 FA FA 2 Dual-Pair LLT with Charge Pump and High-ESD Protection ELECTRICAL CHARACTERISTICS (continued) (VBAT = 2.3V to 5.5V, VL = 1.6V to 5.5V, CVBAT = 1FF, CVCC = 2.2FF, CVL = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VBAT = 3.6V, VL = 3.0V, and TA = +25NC.) (Notes 2, 3, 4) PARAMETER INAVL, INCVL Leakage Current ENAB, ENCD Input Leakage Current OUTAVCC, OUTCVCC Short-Circuit Output Current LOGIC LEVELS INAVL, INCVL InputVoltage High INAVL, INCVL InputVoltage Low INBVCC, INDVCC InputVoltage High INBVCC, INDVCC InputVoltage Low ENAB, ENCD InputVoltage High ENAB, ENCD InputVoltage Low ENAB, ENCD InputVoltage Hysteresis VIHL VILL VIHC VILC VIH VIL VHYS OUTBVL or OUTDVL source current = 100FA, INBVCC or INDVCC > VIHC OUTBVL or OUTDVL source current = 4mA, INBVCC or INDVCC > VIHC OUTBVL or OUTDVL sink current = 100FA, INBVCC or INDVCC < VILC OUTBVL or OUTDVL sink current = 4mA, INBVCC or INDVCC < VILC OUTAVCC or OUTCVCC source current = 100FA, INAVL or INCVL > VIHL, 2.7V P VBAT P 4.5V OUTAVCC or OUTCVCC source current = 20mA, INAVL or INCVL > VIHL, 2.7V P VBAT P 4.5V VL - 0.1 V VL - 0.4 120 1.2 0.4 0.7 x VCC 0.3 x VCC 0.7 x VL 0.3 x VL V V V V V V mV SYMBOL IINAVL_LEAK IINCVL_LEAK IENAB_LEAK IENCD_LEAK ISH CONDITIONS VINAVL = VINCVL = VL VENAB = VENCD = 5V VOUTAVCC = 0V or VOUTCVCC = 0V, VBAT R 2.7V 100 MIN TYP 0.01 0.01 250 MAX 1 1 UNITS FA FA mA MAX14569 OUTBVL, OUTDVL Output-Voltage High VOHL 0.1 V 0.4 OUTBVL, OUTDVL Output-Voltage Low VOLL 4.6 V 4.3 OUTAVCC, OUTCVCC Output-Voltage High VOHC 3 Dual-Pair LLT with Charge Pump and High-ESD Protection MAX14569 ELECTRICAL CHARACTERISTICS (continued) (VBAT = 2.3V to 5.5V, VL = 1.6V to 5.5V, CVBAT = 1FF, CVCC = 2.2FF, CVL = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VBAT = 3.6V, VL = 3.0V, and TA = +25NC.) (Notes 2, 3, 4) PARAMETER SYMBOL CONDITIONS OUTAVCC or OUTCVCC sink current = 100FA, INAVL or INCVL < VILL, 2.7V P VBAT P 4.5V OUTAVCC or OUTCVCC sink current = 20mA, INAVL or INCVL < VILL, 2.7V P VBAT P 4.5V MIN TYP MAX UNITS 0.1 V 0.4 OUTAVCC, OUTCVCC Output-Voltage Low VOLC TIMING CHARACTERISTICS (Note 6) OUTAVCC, OUTCVCC Rise Time OUTAVCC, OUTCVCC Fall Time OUTBVL, OUTDVL Rise Time OUTBVL, OUTDVL Fall Time Propagation Delay (Driving INAVL, INCVL) Low-to-High Propagation Delay (Driving INAVL, INCVL) High-to-Low Propagation Delay (Driving INBVCC, INDVCC) Low-to-High Propagation Delay (Driving INBVCC, INDVCC) High-to-Low Maximum Data Rate CHARGE PUMP VCC Output Voltage VCC Output Voltage Ripple VCC Line Regulation VCC Load Regulation Quiescent Current CP_ Leakage Current DVCC IQ ICP_LEAK VCC ICC = 10mA, 2.7V P VBAT P 4.5V ICC = 40mA, 3.0V P VBAT P 4.5V ICC = 40mA ICC = 10mA, 2.7V P VBAT P 4.5V 0 P ICC P 40mA, VBAT = 3.6V ICC = 0mA, VBAT = 3.6V VBAT = 3.6V, VCC = 0V VENAB = VENCD = 0V -1 -1 200 0.01 0.5 4.7 4.7 5.0 5.0 45 +1 5.3 5.3 V mVP-P % % FA FA tRVCC tFVCC tRVL tFVL Figure 1 Figure 1 Figure 2 Figure 2 25 25 25 25 ns ns ns ns tPVL-VCC-LH Figure 1 30 ns tPVL-VCC-HL Figure 1 30 ns tPVCC-VL-LH Figure 2 30 ns tPVCC-VL-HL Figure 2 12 30 ns Mbps 4 Dual-Pair LLT with Charge Pump and High-ESD Protection ELECTRICAL CHARACTERISTICS (continued) (VBAT = 2.3V to 5.5V, VL = 1.6V to 5.5V, CVBAT = 1FF, CVCC = 2.2FF, CVL = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VBAT = 3.6V, VL = 3.0V, and TA = +25NC.) (Notes 2, 3, 4) PARAMETER CP_ Switching Frequency Efficiency THERMAL PROTECTION Thermal Shutdown Thermal Hysteresis ESD PROTECTION Human Body Model OUTAVCC, INBVCC, OUTCVCC, INDVCC IEC 61000-4-2 Air Gap Discharge IEC 61000-4-2 Contact Discharge Human Body Model ±25 ±15 ±12 ±2 kV kV TSHDN THYST +150 +20 NC NC SYMBOL fCP E CONDITIONS No capacitor between CP1 and CP2, 2.7V P VBAT P 4.5V ICC = 10mA, VBAT = 2.7V, VCC = 5.0V MIN 0.5 TYP 1 90 MAX 1.5 UNITS MHz % MAX14569 All Other Pins Note 2: VL must be less than or equal to VCC during normal operation. However, VL can be greater than VCC during startup and shutdown conditions. Note 3: All units are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by design and not production tested. Note 4: Connect a 0.47µF capacitor between CP1 and CP2. Note 5: DIVBAT = [IVBAT(VENAB = VENCD = VIL) - IVBAT(VENAB = VENCD= 0V)]. Guaranteed by design and not production tested. Note 6: VCC = 5.0V, VL = 1.6V to VCC, VBAT = 2.7V to 3.6V, VENAB = VENCD > VIH, RS = 50I, RL = 1MI, CL = 15pF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VBAT = 3.6V, VL = 3.0V, and TA = +25NC. 5 Dual-Pair LLT with Charge Pump and High-ESD Protection MAX14569 tRVCC VL VBAT 90% 90% tFVCC MAX14569 50I INAVL/ INCVL VL VCC OUTAVCC/ OUTCVCC 50% CL RL OUTAVCC/ 10% OUTCVCC INAVL/ INCVL 50% 50% 10% 50% tPVL-VCC-LH tPVL-VCC-HL Figure 1. Push-Pull Driving INAVL/INCVL Test Circuit and Timing tRVL VL VBAT tFVL MAX14569 50I INBVCC/ INDVCC VCC VL OUTBVL/ OUTDVL CL RL INBVCC/ INDVCC 50% OUTBVL/ OUTDVL 90% 50% 90% 50% 50% 10% 10% tPVCC-VL-LH tPVCC-VL-HL Figure 2. Push-Pull Driving INBVCC/INDVCC Test Circuit and Timing 6 Dual-Pair LLT with Charge Pump and High-ESD Protection Typical Operating Characteristics (VBAT = 3.6V, VL = 3V, CVBAT = 1FF, CVCC = 2.2FF, CVL = 0.1FF, connect 0.47FF capacitor between CP1 and CP2, data rate = 1Mbps, TA = +25NC, unless otherwise noted.) VBAT SHUTDOWN SUPPLY CURRENT vs. VBAT VOLTAGE MAX14569 toc01 MAX14569 VBAT SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE MAX14569 toc02 VL SHUTDOWN SUPPLY CURRENT vs. VL VOLTAGE VL SHUTDOWN SUPPLY CURRENT (nA) 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 1.6 2.1 2.6 VL VOLTAGE (V) 3.1 3.6 VENAB = VENCD = 0V MAX14569 toc03 5.0 VBAT SHUTDOWN SUPPLY CURRENT (nA) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2.3 3.1 3.9 VBAT VOLTAGE (V) 4.7 VENAB = VENCD = 0V VINAVL = VINCVL = 0V 10 VBAT SHUTDOWN SUPPLY CURRENT (nA) 9 8 7 6 5 4 3 2 1 0 -40 -15 10 35 60 VBAT = 4.5V VBAT = 3.6V VBAT = 2.7V VENAB = VENCD = 0V VINAVL = VINCVL = 0V 0.50 5.5 85 TEMPERATURE (°C) VL SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE MAX14569 toc04 CP_ OPERATING FREQUENCY vs. VBAT MAX14569 toc05 VCC SHORT-CIRCUIT CURRENT vs. VBAT 900 800 700 ISH (mA) 600 500 400 300 200 100 0 OUTAVCC/OUTCVCC SHORT-TO-GROUND TA = -40°C TA = 25°C TA = 85°C MAX14569 toc06 0.8 VL SHUTDOWN SUPPLY CURRENT (nA) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -40 VENAB = VENCD = 0V 1000 CP_ OPERATING FREQUENCY (kHz) 990 980 970 960 950 940 930 920 910 900 2.3 3.2 VBAT (V) 4.1 TA = -40°C TA = 25°C TA = 85°C 1000 VL = 3.3V VL = 2.7V VL = 1.8V -15 10 35 60 85 5.0 2.3 3.2 VBAT (V) 4.1 5.0 TEMPERATURE (°C) CP_ LINE REGULATION (VCC vs. VBAT) MAX14569 toc07 CP_ LOAD REGULATION (VCC vs. ICC) MAX14569 toc08 OUTPUT RIPPLE vs. LOAD CURRENT VCC OUTPUT VOLTAGE RIPPLE (mVP-P) 180 160 140 120 100 80 60 40 20 0 0 5 10 15 20 ICC (mA) 25 30 35 40 ENAB = ENCD = HIGH VBAT = 3.6V MAX14569 toc09 5.10 5.08 5.06 5.04 VCC (V) 5.00 4.98 4.96 4.94 4.92 4.90 2.7 3.0 3.3 3.6 VBAT (V) 3.9 4.2 5.02 ENAB = ENCD = HIGH ICC = 10mA 5.2 5.1 5.0 VCC (V) 4.9 4.8 4.7 4.6 4.5 ENAB = ENCD = HIGH 200 4.5 0 5 10 15 20 ICC (mA) 25 30 35 40 7 Dual-Pair LLT with Charge Pump and High-ESD Protection MAX14569 Typical Operating Characteristics (continued) (VBAT = 3.6V, VL = 3V, CVBAT = 1FF, CVCC = 2.2FF, CVL = 0.1FF, connect 0.47FF capacitor between CP1 and CP2, data rate = 1Mbps, TA = +25NC, unless otherwise noted.) OUTBVL/OUTDVL FALL TIME vs. LOAD CAPACITANCE MAX14569 toc10 OUTBVL/OUTDVL RISE TIME vs. LOAD CAPACITANCE 9 OUTBVL/OUTDVL RISE TIME (ns) 8 7 6 5 4 3 2 1 0 MAX14569 toc11 10 9 OUTBVL/OUTDVL FALL TIME (ns) 8 7 6 5 4 3 2 1 0 0 20 40 60 80 10 100 0 20 40 60 80 100 LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) OUTBVL/OUTDVL PROPAGATION DELAY vs. LOAD CAPACITANCE OUTBVL/OUTDVL PROPAGATION DELAY (ns) MAX14569 toc12 OUTAVCC/OUTCVCC FALL TIME vs. LOAD CAPACITANCE OUTAVCC/OUTCVCC FALL TIME (ns) 90 80 70 60 50 40 30 20 10 0 MAX14569 toc13 10 9 8 7 6 5 4 3 2 1 0 0 20 40 60 80 100 tPVCC-VL-HL tPVCC-VL-LH 100 0 200 400 600 800 1000 LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) OUTAVCC/OUTCVCC RISE TIME vs. LOAD CAPACITANCE OUTAVCC/OUTCVCC PROPAGATION DELAY (ns) MAX14569 toc14 OUTAVCC/OUTCVCC PROPAGATION DELAY vs. LOAD CAPACITANCE 90 80 70 60 50 40 30 20 10 0 0 200 400 600 800 1000 LOAD CAPACITANCE (pF) tPVL-VCC-LH tPVL-VCC-HL MAX14569 toc15 100 OUTAVCC/OUTCVCC RISE TIME (ns) 90 80 70 60 50 40 30 20 10 0 0 200 400 600 800 100 1000 LOAD CAPACITANCE (pF) 8 Dual-Pair LLT with Charge Pump and High-ESD Protection Typical Operating Characteristics (continued) (VBAT = 3.6V, VL = 3V, CVBAT = 1FF, CVCC = 2.2FF, CVL = 0.1FF, connect 0.47FF capacitor between CP1 and CP2, data rate = 1Mbps, TA = +25NC, unless otherwise noted.) MAX14569 DRIVING INAVL/INCVL MAX14569 toc16 DRIVING INAVL/INCVL MAX14569 toc17 COUTAVCC/COUTCVCC = 15pF IN_VL 2V/div COUTAVCC/COUTCVCC = 150pF IN_VL 2V/div OUT_VCC 2V/div OUT_VCC 2V/div 400ns/div 400ns/div DRIVING INAVL/INCVL MAX14569 toc18 DRIVING INBVCC/INDVCC MAX14569 toc19 COUTAVCC/COUTCVCC = 1000pF IN_VL 2V/div IN_VCC 2V/div OUT_VCC 2V/div OUT_VL 2V/div COUTBVL/COUTDVL = 15pF 400ns/div 400ns/div 9 Dual-Pair LLT with Charge Pump and High-ESD Protection MAX14569 Pin Configuration TOP VIEW VL 1 ENAB 2 ENCD 3 INAVL 4 OUTBVL 5 INCVL 6 OUTDVL 7 GND 8 + 16 CP1 15 VBAT MAX14569 14 CP2 13 VCC 12 OUTAVCC 11 INBVCC 10 OUTCVCC 9 INDVCC QSOP Pin Description PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME VL ENAB ENCD INAVL OUTBVL INCVL OUTDVL GND INDVCC OUTCVCC INBVCC OUTAVCC VCC CP2 VBAT CP1 FUNCTION Logic Supply Voltage, +1.6V to +5.5V. Bypass VL to GND with a 0.1FF capacitor placed as close as possible to the device. Enable Input for A and B Ports. Drive ENAB low for shutdown mode, or drive ENAB high for normal operation. Enable Input for C and D Ports. Drive ENCD low for shutdown mode, or drive ENCD high for normal operation. Input A Port. Referenced to VL. Output B Port. Referenced to VL. Input C Port. Referenced to VL. Output D Port. Referenced to VL. Ground Input D Port. Referenced to VCC. Output C Port. Referenced to VCC. Input B Port. Referenced to VCC. Output A Port. Referenced to VCC. Charge-Pump Output. Bypass VCC to GND with a 2.2FF ceramic capacitor placed as close as possible to the VCC pin to have high ESD protection on OUTAVCC, INBVCC, OUTCVCC, and INDVCC pins. External Charge-Pump Capacitor Connection Battery Input, +2.3V to +5.5V. Bypass VBAT to GND with a 1FF capacitor placed as close as possible to the device. External Charge-Pump Capacitor Connection 10 Dual-Pair LLT with Charge Pump and High-ESD Protection Detailed Description The MAX14569 is a dedicated dual-pair unidirectional logic-level translator that is ideal for automatic remotemetering applications. Externally applied voltage VL and regulated output voltage VCC set the logic levels on either side of the device. The device boosts the VBAT supply input voltage to a charge-pump-regulated output, VCC. Logic-high signals present on the VL side of the device appear as a highvoltage logic signals on the VCC side of the device and vice versa. The device has two pairs of logic-level translators in back-to-back configuration: one logic-level translator from a low voltage to a high voltage and the other logiclevel translator from a high voltage to a low voltage. The device features an extreme power-saving mode that reduces supply current to a typical 0.01FA. The device also features thermal short-circuit protection on the VCC side for enhanced protection in applications that route signals externally. For proper operation, ensure that 2.3V P VBAT P 5.5V, 1.6V P VL P 5.5V. The device enters low-power shutdown mode when ENAB = ENCD = GND (see the Functional Table). In shutdown mode, the INAVL, INBVCC, INCVL, INDVCC, OUTAVCC and OUTCVCC are in high-impedance mode and the OUTBVL and OUTDVL are pulled down to GND. The maximum data rate depends heavily on the load capacitance (see the rise/fall times in the Typical Operating Characteristics), output impedance of the driver, and the operating voltage range. The device is designed to drive a wide variety of load types including a high capacitive load. To protect the VCC outputs (OUTAVCC, OUTCVCC) from a harsh external environment, the VCC outputs are ruggedized with a high ESD-capable output structure. When the high capacitive load is connected to the VCC output side, the current is limited by the charge-pump circuit along with the output driver impedance. The device is also protected by the thermal protection. Level Translation MAX14569 Output Load Requirements Functional Diagram INPUTS VL VBAT VCC Functional Table ENAB Low ENCD Low DRIVERS OUTPUT EVENTS Device is in shutdown OUTAVCC, OUTCVCC: high impedance OUTBVL, OUTDVL: pulldown to GND OUTAVCC: high impedance OUTBVL: pulldown to GND INCVL to OUTCVCC INDVCC to OUTDVL INAVL to OUTAVCC INBVCC to OUTBVL OUTCVCC: high impedance OUTDVL: pulldown to GND INAVL to OUTAVCC INBVCC to OUTBVL INCVL to OUTCVCC INDVCC to OUTDVL MAX14569 ENAB INAVL VL OUTBVL VL CHARGE PUMP VCC OUTAVCC VCC INBVCC Low High High ENCD INCVL VL OUTDVL VCC INDVCC VL VCC OUTCVCC Low High High GND 11 Dual-Pair LLT with Charge Pump and High-ESD Protection MAX14569 The device features two enable inputs (ENAB, ENCD) that place the device into a low-power shutdown mode when both are driven low. If either ENAB or ENCD is pulled high, the internal charge pump starts working and generates 5V on VCC. When both ENAB and ENCD are driven low, the MAX14569 enters shutdown mode and draws a minimum current from VL and VBAT. To minimize supply current in shutdown mode, connect INAVL and INCVL to ground. The internal charge pump provides 5V on VCC when VBAT is between 2.7V and 4.5V. When VBAT is between 2.3V and 2.7V, VCC is twice the voltage of VBAT. The output is regulated to 5V as long as the battery voltage supports it. The device features thermal shutdown function necessary to protect the device. When the junction temperature exceeds +150NC (typ), the charge pump turns off and OUTAVCC, OUTBVL, OUTCVCC, OUTDVL are low. This limits the device temperature from rising further. When the temperature drops 20NC (typ) below +150NC (typ), the device resumes normal operation. Shutdown Mode discharges encountered during handling and assembly. The OUTAVCC, INBVCC, OUTCVCC, INDVCC pins have extra protection against static electricity. Maxim’s engineers have developed state-of-the-art structures to protect these pins against ESD of Q25kV without damage. The ESD structures withstand high ESD in all states: normal operation, shutdown, and powered down. After an ESD event, the device keeps working without latchup or damage. ESD protection can be tested in various ways. The OUTAVCC, INBVCC, OUTCVCC, and INDVCC pins are characterized for protection to the following limits: U Q25kV using the Human Body Model U Q15kV using the Air-Gap Discharge Method specified in IEC 61000-4-2 U Q12kV using the Contact Discharge Method specified in IEC 61000-4-2 ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. Figure 3 shows the Human Body Model, and Figure 4 shows the current waveform it generates when discharged into a low-impedance state. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a 1.5kI resistor. Charge Pump Thermal Protection ESD Test Conditions Human Body Model Applications Information Use standard high-speed layout practices when laying out a board with the device. For example, to minimize line coupling, place all other signal lines not connected to the device at least 1x the substrate height of the PCB away from the input and output lines of the device. To reduce ripple and the chance of introducing data errors, bypass VL to ground with a 0.1FF ceramic capacitor, VBAT to ground with a 1FF ceramic capacitor, and VCC to ground with a 2.2FF ceramic capacitor. Place all capacitors as close as possible to the power-supply inputs. As with all Maxim devices, ESD protection structures are incorporated on all pins to protect against electrostatic Layout Recommendations Power-Supply Decoupling ±25kV ESD Protection The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment. It does not specifically refer to integrated circuits. The major difference between tests done using the Human Body Model and IEC 61000-4-2 is higher peak current in IEC 61000-4-2, because series resistance is lower in the IEC 61000-4-2 model. Hence, the ESD withstand voltage measured to IEC 61000-4-2 is generally lower than that measured using the Human Body Model. Figure 5 shows the IEC 61000-4-2 model, and Figure 6 shows the current waveform for the Q8kV, IEC 61000-4-2, level 4, ESD Contact Discharge Method. IEC 61000-4-2 12 Dual-Pair LLT with Charge Pump and High-ESD Protection MAX14569 RC 1MΩ CHARGE-CURRENT LIMIT RESISTOR HIGHVOLTAGE DC SOURCE RD 1500Ω DISCHARGE RESISTANCE DEVICE UNDER TEST HIGHVOLTAGE DC SOURCE RC 50MΩ to 100MΩ CHARGE CURRENT LIMIT RESISTOR RD 330Ω DISCHARGE RESISTANCE DEVICE UNDER TEST Cs 100pF STORAGE CAPACITOR Cs 150pF STORAGE CAPACITOR Figure 3. Human Body ESD Test Model Figure 5. IEC 61000-4-2 ESD Test Model I 100% 90% IP 100% 90% AMPERES 36.8% 10% 0 0 tRL Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) I PEAK TIME tDL CURRENT WAVEFORM 10% t r = 0.7ns to 1ns t 60ns 30ns Figure 4. Human Body Current Waveform Figure 6. IEC 61000-4-2 ESD Generator Current Waveform Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-“ in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 16 QSOP PACKAGE CODE E16+4 OUTLINE NO. 21-0055 LAND PATTERN NO. 90-0167 13 Dual-Pair LLT with Charge Pump and High-ESD Protection MAX14569 Revision History REVISION NUMBER 0 REVISION DATE 9/10 Initial release DESCRIPTION PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 © Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.