MAX1473

19-2748; Rev 3; 11/03 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range General Description The MAX1473 fully integrated low-power CMOS superheterodyne receiver is ideal for receiving amplitudeshift-keyed (ASK) data in the 300MHz to 450MHz frequency range. Its signal range is from -114dBm to 0dBm. With few external components and a low-current power-down mode, it is ideal for cost- and power-sensitive applications typical in the automotive and consumer markets. The chip consists of a low-noise amplifier (LNA), a fully differential image-rejection mixer, an onchip phase-locked-loop (PLL) with integrated voltagecontrolled oscillator (VCO), a 10.7MHz IF limiting amplifier stage with received-signal-strength indicator (RSSI), and analog baseband data-recovery circuitry. The MAX1473 also has a discrete one-step automatic gain control (AGC) that drops the LNA gain by 35dB when the RF input signal is greater than -57dBm. The MAX1473 is available in 28-pin TSSOP and 32-pin thin QFN packages. Both versions are specified for the extended (-40°C to +85°C) temperature range. Features o Optimized for 315MHz or 433MHz ISM Band o Operates from Single 3.3V or 5.0V Supplies o High Dynamic Range with On-Chip AGC o Selectable Image-Rejection Center Frequency o Selectable x64 or x32 fLO/fXTAL Ratio o Low 5.2mA Operating Supply Current o 18dB PRFIN_MIN Average carrier power level Peak power level LNA gain from low to high Time for valid signal detection after V P WRDN = VOH 300 0 -120 -114 8 150 250 450 µs MHz dBm dBm dB ms SYMBOL CONDITIONS MIN TYP MAX UNITS _______________________________________________________________________________________ 3 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range MAX1473 AC ELECTRICAL CHARACTERISTICS (continued) (Typical Application Circuit, VDD = 3.0V to 3.6V, all RF inputs are referenced to 50Ω, fRF = 315MHz, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = 3.3V and TA = +25°C.) (Note 1) PARAMETER LO Signal Feedthrough to Antenna Output Impedance Noise Figure LNA IN LOW-GAIN MODE Input Impedance (Note 4) 1dB Compression Point Input-Referred 3rd-Order Intercept LO Signal Feedthrough to Antenna Output Impedance Noise Figure Power Gain Voltage Gain Reduction MIXER Input Impedance Input-Referred 3rd-Order Intercept Output Impedance Noise Figure Image Rejection (not Including LNA Tank) Conversion Gain INTERMEDIATE FREQUENCY (IF) Input Impedance Operating Frequency 3dB Bandwidth RSSI Linearity RSSI Dynamic Range RSSI Level RSSI Gain AGC Threshold LNA gain from low to high LNA gain from high to low PRFIN < -120dBm PRFIN > 0dBm, AGC enabled ZIN_IF fIF Bandpass response 330 10.7 20 ±0.5 80 1.15 2.35 14.2 1.45 2.05 Ω MHz MHz dB dB V mV/dB V S11MIX IIP3MIX ZOUT_MIX NFMIX fRF = 433MHz, VIRSEL = VDD fRF = 375MHz, VIRSEL = VDD/2 fRF = 315MHz, VIRSEL = 0V 330Ω IF filter load Normalized to 50Ω 0.25 - j2.4 -18 330 16 42 44 44 13 dB dB dBm Ω dB AGC enabled (depends on tank Q) S22LNA NFLNA Normalized to 50Ω S11LNA P1dBLNA IIP3LNA Normalized to 50Ω fRF = 433MHz fRF = 375MHz fRF = 315MHz 1 - j4.7 1 - j3.9 1 - j3.4 -10 -7 -80 0.4 2 0 35 dB dB dB dBm dBm dBm S22LNA NFLNA Normalized to 50Ω SYMBOL CONDITIONS MIN TYP -80 0.12 - j4.4 2 dB MAX UNITS dBm 4 _______________________________________________________________________________________ 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range AC ELECTRICAL CHARACTERISTICS (continued) (Typical Application Circuit, VDD = 3.0V to 3.6V, all RF inputs are referenced to 50Ω, fRF = 315MHz, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = 3.3V and TA = +25°C.) (Note 1) PARAMETER DATA FILTER Maximum Bandwidth DATA SLICER Comparator Bandwidth Maximum Load Capacitance Output High Voltage Output Low Voltage CRYSTAL OSCILLATOR fRF = 433MHz Crystal Frequency (Note 5) fXTAL fRF = 315MHz Crystal Tolerance Input Impedance From each pin to ground VXTALSEL = 0V VXTALSEL = VDD VXTALSEL = 0V VXTALSEL = VDD 6.6128 13.2256 4.7547 9.5094 50 6.2 MHz MHz ppm pF BWCMP CLOAD 100 10 VDD5 0 kHz pF V V BWDF 100 kHz SYMBOL CONDITIONS MIN TYP MAX UNITS MAX1473 Note 1: 100% tested at TA = +25°C. Guaranteed by design and characterization over temperature. Note 2: IRSEL is internally set to 375MHz IR mode. It can be left open when the 375MHz image rejection setting is desired. A 1nF capacitor is recommended in noisy environments. Note 3: BER = 2 x 10-3, Manchester encoded, data rate = 4kbps, IF bandwidth = 280kHz. Note 4: Input impedance is measured at the LNAIN pin. Note that the impedance includes the 15nH inductive degeneration connected from the LNA source to ground. The equivalent input circuit is 50Ω in series with 2.2pF. Note 5: Crystal oscillator frequency for other RF carrier frequency within the 300MHz to 450MHz range is (fRF - 10.7MHz)/64 for XTALSEL = 0V, and (fRF - 10.7MHz)/32 for XTALSEL = VDD. _______________________________________________________________________________________ 5 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range MAX1473 Typical Operating Characteristics (Typical Application Circuit, VDD = 3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE +105°C MAX1473 toc01 SUPPLY CURRENT vs. RF FREQUENCY MAX1473 toc02 BIT-ERROR RATE vs. AVERAGE RF INPUT POWER MAX1473 toc03 5.6 5.5 SUPPLY CURRENT (mA) 5.4 5.3 5.2 5.1 5.0 4.9 3.0 3.1 3.2 3.3 3.4 3.5 -40°C +25°C 7.0 100 fRF = 433MHz 10 BIT-ERROR RATE (%) 6.5 SUPPLY CURRENT (mA) +105°C 6.0 +85°C 1 fRF = 315MHz 0.1 5.5 +25°C -40°C 4.5 +85°C 5.0 0.01 250 300 350 400 450 500 -121 -120 RF FREQUENCY (MHz) -119 -118 -117 -116 -115 -114 AVERAGE INPUT POWER (dBm) 3.6 SUPPLY VOLTAGE (V) SENSITIVITY vs. TEMPERATURE -106 -107 SENSITIVITY (dBm) -108 -109 -110 -111 -112 -113 -114 -40 -15 10 35 60 85 110 TEMPERATURE (°C) fRF = 315MHz PEAK RF INPUT POWER 1% BER IF BANDWIDTH = 280MHz fRF = 433MHz RSSI (V) MAX1473 toc04 RSSI vs. RF INPUT POWER IF BANDWIDTH = 280kHz 2.2 VAGCDIS = VDD 2.0 RSSI (V) 1.8 1.6 1.4 1.2 1.0 -140 -120 -100 -80 -60 -40 -20 0 RF INPUT POWER (dBm) VAGCDIS = 0V MAX1473 toc05 RSSI AND DELTA vs. IF INPUT POWER 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 -90 -70 -50 -30 -10 10 IF INPUT POWER (dBm) RSSI DELTA MAX1473 toc06 -105 2.4 3.5 2.5 1.5 0.5 -0.5 -1.5 -2.5 -3.5 DELTA (dB) SYSTEM GAIN vs. FREQUENCY MAX1473 toc07 IMAGE REJECTION vs. RF FREQUENCY MAX1473 toc08 IMAGE REJECTION vs. TEMPERATURE 45 IMAGE REJECTION (dB) 44 44 43 43 42 42 41 41 fRF = 433MHz fRF = 375MHz fRF = 315MHz MAX1473 toc09 30 20 SYSTEM GAIN (dB) 10 0 -10 -20 -30 0 5 10 15 20 25 FROM RFIN TO MIXOUT fRF = 315MHz 50dB IMAGE REJECTION LOWER SIDEBAND UPPER SIDEBAND 55 45 50 IMAGE REJECTION (dB) 45 40 fRF = 375MHz 35 fRF = 433MHz 30 fRF = 315MHz 30 280 330 380 430 480 -40 -15 10 35 60 85 IF FREQUENCY (MHz) RF FREQUENCY (MHz) TEMPERATURE (°C) 6 _______________________________________________________________________________________ 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range Typical Operating Characteristics (continued) (Typical Application Circuit, VDD = 3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.) MAX1473 NORMALIZED IF GAIN vs. IF FREQUENCY MAX1473 toc10 S11 MAGNITUDE-LOG PLOT OF RFIN 20 10 MAGNITUDE (dB) 0 -10 -20 -30 -40 315MHz -34dB MAX1473 toc11 S11 SMITH PLOT OF RFIN MAX1473 toc12 5 30 600MHz NORMALIZED IF GAIN (dB) 0 -5 -10 100MHz -15 -50 -60 -20 1 10 IF FREQUENCY (MHz) 100 -70 10 109 208 307 406 505 604 703 802 901 1000 RF FREQUENCY (MHz) REGULATOR VOLTAGE vs. REGULATOR CURRENT MAX1473 toc13 PHASE NOISE vs. OFFSET FREQUENCY MAX1473 toc14 PHASE NOISE vs. OFFSET FREQUENCY fRF = 433MHz MAX1473 toc15 3.1 3.0 REGULATOR VOLTAGE (V) -40°C 2.9 2.8 2.7 2.6 2.5 5 VDD = 5.0V 15 25 35 +25°C +85°C 0 -20 PHASE NOISE (dBc/Hz) -40 -60 -80 -100 -120 fRF = 315MHz 0 -20 PHASE NOISE (dBc/Hz) -40 -60 -80 -100 -120 +105°C 45 -140 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 OFFSET FREQUENCY (MHz) -140 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 OFFSET FREQUENCY (MHz) REGULATOR CURRENT (mA) _______________________________________________________________________________________ 7 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range MAX1473 Pin Description PIN TSSOP 1 2, 7 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 — QFN 29 4, 30 31 32 2 3 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 22 23 24 26 27 28 1, 13, 21, 25 NAME XTAL1 AVDD LNAIN LNASRC AGND LNAOUT MIXIN1 MIXIN2 AGND IRSEL MIXOUT DGND DVDD AGCDIS XTALSEL IFIN1 IFIN2 DFO DSN OPP DFFB DSP VDD5 PDOUT PWRDN XTAL2 N.C. FUNCTION 1st Crystal Input. (See Phase-Locked Loop section.) Positive Analog Supply Voltage for RF Sections. (See Typical Application Circuit.) Low-Noise Amplifier Input. (See Low-Noise Amplifier section.) Low-Noise Amplifier Source for External Inductive Degeneration. Connect inductor to ground to set LNA input impedance. (See Low-Noise Amplifier section.) Analog Ground Low-Noise Amplifier Output. Connect to mixer through an LC tank filter. (See Low-Noise Amplifier section.) 1st Differential Mixer Input. Connect through a 100pF capacitor to VDD side of the LC tank. 2nd Differential Mixer Input. Connect through a 100pF capacitor to LC tank filter from LNAOUT. Analog Ground Image Rejection Select Pin. Set VIRSEL = 0V to center image rejection at 315MHz. Leave IRSEL floating to center image rejection at 375MHz. Set VIRSEL = VDD to center image rejection at 433MHz. 330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter. Digital Ground Positive Digital Supply Voltage. Decouple to DGND with a 0.01µF capacitor. AGC Control Pin. Pull high to disable AGC. Crystal Divider Ratio Select Pin. Drive XTALSEL low to select divider ratio of 64, or drive XTALSEL high to select divider ratio of 32. 1st Differential Intermediate Frequency Limiter Amplifier Input. Decouple to AGND with a 1500pF capacitor. 2nd Differential Intermediate Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz bandpass filter. Data Filter Output Negative Data Slicer Input Noninverting Op-Amp Input for the Sallen-Key Data Filter Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter. Positive Data Slicer Input 5V Supply Voltage. VDD5 is shorted to AVDD for 3.3V operation. Peak Detector Output Power-Down Select Input. Drive this pin with a logic high to power on the IC. 2nd Crystal Input No Connection DATAOUT Digital Baseband Data Output 8 _______________________________________________________________________________________ 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range Detailed Description The MAX1473 CMOS superheterodyne receiver and a few external components provide the complete receive chain from the antenna to the digital output data. Depending on signal power and component selection, data rates as high as 100kbps can be achieved. The MAX1473 is designed to receive binary ASK data modulated in the 300MHz to 450MHz frequency range. ASK modulation uses a difference in amplitude of the carrier to represent logic 0 and logic 1 data. CTOTAL = C2 + CPARASITICS LPARASITICS and CPARASITICS include inductance and capacitance of the PC board traces, package pins, mixer input impedance, LNA output impedance, etc. These parasitics at high frequencies cannot be ignored, and can have a dramatic effect on the tank filter center frequency. Lab experimentation should be done to optimize the center frequency of the tank. MAX1473 Mixer A unique feature of the MAX1473 is the integrated image rejection of the mixer. This device eliminates the need for a costly front-end SAW filter for most applications. Advantages of not using a SAW filter are increased sensitivity, simplified antenna matching, less board space, and lower cost. The mixer cell is a pair of double balanced mixers that perform an IQ downconversion of the RF input to the 10.7MHz IF from a low-side injected LO (i.e., fLO = fRF fIF). The image-rejection circuit then combines these signals to achieve a minimum 45dB of image rejection over the full temperature range. Low-side injection is required due to the on-chip image rejection architecture. The IF output is driven by a source-follower biased to create a driving impedance of 330Ω; this provides a good match to the off-chip 330Ω ceramic IF filter. The voltage conversion gain is approximately 13dB when the mixer is driving a 330Ω load. The IRSEL pin is a logic input that selects one of the three possible image-rejection frequencies. When VIRSEL = 0V, the image rejection is tuned to 315MHz. VIRSEL = VDD/2 tunes the image rejection to 375MHz, and when VIRSEL = VDD, the image rejection is tuned to 433MHz. The IRSEL pin is internally set to VDD/2 (image rejection at 375MHz) when it is left floating, thereby eliminating the need for an external VDD/2 voltage. Low-Noise Amplifier The LNA is an NMOS cascode amplifier with off-chip inductive degeneration that achieves approximately 16dB of power gain with a 2.0dB noise figure and an IIP3 of -12dBm. The gain and noise figure are dependent on both the antenna matching network at the LNA input and the LC tank network between the LNA output and the mixer inputs. The off-chip inductive degeneration is achieved by connecting an inductor from LNASRC to AGND. This inductor sets the real part of the input impedance at LNAIN, allowing for a more flexible input impedance match, such as a typical PC board trace antenna. A nominal value for this inductor with a 50Ω input impedance is 15nH, but is affected by PC board trace. See Typical Operating Characteristics for the relationship between the inductance and the LNA input impedance. The AGC circuit monitors the RSSI output. When the RSSI output reaches 2.05V, which corresponds to an RF input level of approximately -57dBm, the AGC switches on the LNA gain reduction resistor. The resistor reduces the LNA gain by 35dB, thereby reducing the RSSI output by about 500mV. The LNA resumes high-gain mode when the RSSI level drops back below 1.45V (approximately -65dBm at RF input) for 150ms. The AGC has a hysteresis of ~8dB. With the AGC function, the MAX1473 can reliably produce an ASK output for RF input levels up to 0dBm with a modulation depth of 18dB. The LC tank filter connected to LNAOUT comprises L3 and C2 (see Typical Application Circuit). Select L3 and C2 to resonate at the desired RF input frequency. The resonant frequency is given by: f= 1 2π L TOTAL × C TOTAL Phase-Locked Loop The PLL block contains a phase detector, charge pump/integrated loop filter, VCO, asynchronous 64x clock divider, and crystal oscillator driver. Besides the crystal, this PLL does not require any external components. The VCO generates a low-side local oscillator (LO). The relationship between the RF, IF, and reference frequencies is given by: fREF = (fRF - fIF) / (32 ✕ M) where: M = 1 (VXTALSEL = VDD) or 2 (VXTALSEL = 0V) To allow the smallest possible IF bandwidth (for best sensitivity), the tolerance of the reference must be minimized. where: LTOTAL = L3 + LPARASITICS _______________________________________________________________________________________ 9 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range MAX1473 The IF section presents a differential 330Ω load to provide matching for the off-chip ceramic filter. The six internal AC-coupled limiting amplifiers produce an overall gain of approximately 65dB, with a bandpass filter-type response centered near the 10.7MHz IF frequency with a 3dB bandwidth of approximately 11.5MHz. The RSSI circuit demodulates the IF by producing a DC output proportional to the log of the IF signal level, with a slope of approximately 14.2mV/dB (see Typical Operating Characteristics). The AGC circuit monitors the RSSI output. When the RSSI output reaches 2.05V, which corresponds to an RF input level of approximately -57dBm, the AGC switches on the LNA gain reduction resistor. The resistor reduces the LNA gain by 35dB, thereby reducing the RSSI output by about 500mV. The LNA resumes high-gain mode when the RSSI level drops back below 1.45V (approximately -65dBm at RF input) for 150ms. The AGC has a hysteresis of ~8dB. With the AGC function, the MAX1473 can reliably produce an ASK output for RF input levels up to 0dBm with modulation depth of 18dB. Intermediate Frequency/RSSI Applications Information Crystal Oscillator The XTAL oscillator in the MAX1473 is designed to present a capacitance of approximately 3pF between the XTAL1 and XTAL2. If a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its stated operating frequency, introducing an error in the reference frequency. Crystals designed to operate with higher differential load capacitance always pull the reference frequency higher. For example, a 4.7547MHz crystal designed to operate with a 10pF load capacitance oscillates at 4.7563MHz with the MAX1473, causing the receiver to be tuned to 315.1MHz rather than 315.0MHz, an error of about 100kHz, or 320ppm. In actuality, the oscillator pulls every crystal. The crystal’s natural frequency is really below its specified frequency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. This pulling is already accounted for in the specification of the load capacitance. Table 1. Component Values for Typical Application Circuit COMPONENT L1 L2 L3 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 R1 X1 X2 VALUE FOR 433MHz RF 56nH 15nH 15nH 100pF 2.7pF 100pF 100pF 1500pF 220pF 470pF 0.47µF 220pF 0.01µF 0.01µF 15pF 15pF 5kΩ 6.6128MHz or 13.2256MHz 10.7MHz ceramic filter VALUE FOR 315MHz RF 110nH 15nH 27nH 100pF 4.7pF 100pF 100pF 1500pF 220pF 470pF 0.47µF 220pF 0.01µF 0.01µF 15pF 15pF 5kΩ 4.7547MHz or 9.5094MHz 10.7MHz ceramic filter DESCRIPTION Toko LL1608-FH Murata LQP11A Murata LQP11A 5% ± 0.1pF 5% 5% 10% 5% 5% 20% 10% 20% 20% Depends on XTAL Depends on XTAL 5% — Murata SFECV10.7 series 10 ______________________________________________________________________________________ 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range Additional pulling can be calculated if the electrical parameters of the crystal are known. The frequency pulling is given by:  C 1 1  × 106 fp = m  2  Ccase + Cload Ccase + Cspec    where: fp is the amount the crystal frequency pulled in ppm. Cm is the motional capacitance of the crystal. Ccase is the case capacitance. Cspec is the specified load capacitance. Cload is the actual load capacitance. When the crystal is loaded as specified, i.e., Cload = Cspec, the frequency pulling equals zero. MAX1473 MAX1473 RSSI RDF2 100kΩ RDF1 100kΩ 19 DFO C6 21 OPP C5 22 DFFB Data Filter The data filter is implemented as a 2nd-order lowpass Sallen-Key filter. The pole locations are set by the combination of two on-chip resistors and two external capacitors. Adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. The corner frequency should be set to approximately 1.5 times the fastest expected data rate from the transmitter. Keeping the corner frequency near the data rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity. The configuration shown in Figure 1 can create a Butterworth or Bessel response. The Butterworth filter offers a very flat amplitude response in the passband and a rolloff rate of 40dB/decade for the two-pole filter. The Bessel filter has a linear phase response, which works well for filtering digital data. To calculate the value of C5 and C6, use the following equations along with the coefficients in Table 2: C5 = C6 = Figure 1. Sallen-Key Lowpass Data Filter Choosing standard capacitor values changes C5 to 470pF and C6 to 220pF, as shown in the T ypical Application Circuit. Table 2. Coefficents to Calculate C5 and C6 FILTER TYPE Butterworth (Q = 0.707) Bessel (Q = 0.577) a 1.414 1.3617 b 1.000 0.618 Data Slicer The purpose of the data slicer is to take the analog output of the data filter and convert it to a digital signal. This is achieved by using a comparator and comparing the analog input to a threshold voltage. One input is supplied by the data filter output. Both comparator inputs are accessible off chip to allow for different methods of generating the slicing threshold, which is applied to the second comparator input. The suggested data slicer configuration uses a resistor (R1) connected between DSN and DSP with a capacitor (C4) from DSN to DGND (Figure 2). This configuration averages the analog output of the filter and sets the threshold to approximately 50% of that amplitude. With this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. The sizes of R1 and C4 affect how fast the threshold tracks to the analog amplitude. Be sure to keep the corner frequency of the RC circuit much lower than the lowest expected data rate. Note that a long string of zeros or 1’s can cause the threshold to drift. This configuration works best if a cod- a 100k π fc a 4 100k π fc ( )( )( ) ( )( )( ) b where fC is the desired 3dB corner frequency. For example, choose a Butterworth filter response with a corner frequency of 5kHz: C5 = ( 1.414 100kΩ 3.14 5kHz )( 1.000 )( )( ) ≈ 450pF ______________________________________________________________________________________ 11 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range MAX1473 MAX1473 DATA SLICER MAX1473 DATA SLICER 25 DATAOUT R1 25 DATAOUT 20 DSN R1 23 DSP 19 DFO 23 DSP R3 20 DSN R4 19 DFO C4 R2 *OPTIONAL C4 Figure 2. Generating Data Slicer Threshold ing scheme, such as Manchester coding, which has an equal number of zeros and 1’s, is used. To prevent continuous toggling of DATAOUT in the absence of an RF signal due to noise, hysteresis can be added to the data slicer as shown in Figure 3. Figure 3. Generating Data Slicer Hysteresis MAX1473 Peak Detector The peak detector output (PDOUT), in conjunction with an external RC filter, creates a DC output voltage equal to the peak value of the data signal. The resistor provides a path for the capacitor to discharge, allowing the peak detector to dynamically follow peak changes of the data filter output voltage. For faster receiver startup, the circuit shown in Figure 4 can be used. DATA SLICER 25 DATAOUT 20 DSN 23 DSP 25kΩ 19 DFO 26 PDOUT Layout Considerations A properly designed PC board is an essential part of any RF/microwave circuit. On high-frequency inputs and outputs, use controlled-impedance lines and keep them as short as possible to minimize losses and radiation. At high frequencies, trace lengths that are on the order of λ/10 or longer act as antennas. Keeping the traces short also reduces parasitic inductance. Generally, 1in of a PC board trace adds about 20nH of parasitic inductance. The parasitic inductance can have a dramatic effect on the effective inductance of a passive component. For example, a 0.5in trace connecting a 100nH inductor adds an extra 10nH of inductance or 10%. To reduce the parasitic inductance, use wider traces and a solid ground or power plane below the signal traces. Also, use low-inductance connections to ground on all GND pins, and place decoupling capacitors close to all VDD connections. 12 47nF Figure 4. Using PDOUT for Faster Startup Chip Information TRANSISTOR COUNT: 3035 PROCESS: CMOS ______________________________________________________________________________________ 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range Typical Application Circuit VDD3 X1 VDD5 MAX1473 C11 RF INPUT C13 1 2 XTAL1 AVDD LNAIN LNASRC AGND LNAOUT AVDD MIXIN1 MIXIN2 AGND IRSEL MIXOUT DGND DVDD X2 IF FILTER C10 IN GND OUT XTAL2 PWRDN PDOUT 28 27 26 25 24 23 22 21 20 19 18 17 16 15 C12 C1 L1 3 4 TO/FROM µP POWER DOWN DATA OUT MAX1473 DATAOUT VDD5 DSP DFFB OPP DSN DFO IFIN2 IFIN1 XTALSEL AGCDIS L2 5 6 R2 R3 VDD3 L3 C3 C2 8 9 C4 C9 11 12 13 14 10 7 C7 R1 C5 C6 C8 COMPONENT VALUES IN TABLE 1 ______________________________________________________________________________________ 13 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range MAX1473 Functional Diagram LNASRC 4 AGCDIS LNAOUT 15 6 MIXIN1 MIXIN2 8 9 IRSEL 11 MIXOUT 12 IFIN1 17 IFIN2 18 LNAIN 3 LNA AUTOMATIC GAIN CONTROL 0˚ Q IMAGE REJECTION 90˚ ∑ MAX1473 RSSI IF LIMITING AMPS AVDD VDD5 2,7 24 3.3V REG I DVDD 14 DIVIDE BY 64 PHASE DETECTOR ÷1 VCO RDF2 100kΩ DATA FILTER RDF1 100kΩ DGND 13 LOOP FILTER CRYSTAL DRIVER 1 28 POWER DOWN 27 PWRDN 25 DATAOUT DATA SLICER AGND 5,10 ÷2 16 XTALSEL 20 23 19 26 PDOUT 21 OPP 22 DFFB XTAL1 XTAL2 DSN DSP DFO 14 ______________________________________________________________________________________ 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) TSSOP4.40mm.EPS MAX1473 ______________________________________________________________________________________ 15 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range MAX1473 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 0.15 C A D2 C L D b D2/2 0.10 M C A B PIN # 1 I.D. D/2 0.15 C B k PIN # 1 I.D. 0.35x45 E/2 E2/2 E (NE-1) X e C L E2 k L DETAIL A e (ND-1) X e C L C L L L e 0.10 C A 0.08 C e C A1 A3 PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm APPROVAL DOCUMENT CONTROL NO. REV. 21-0140 C 1 2 16 ______________________________________________________________________________________ QFN THIN.EPS 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX1473 COMMON DIMENSIONS EXPOSED PAD VARIATIONS NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm APPROVAL DOCUMENT CONTROL NO. REV. 21-0140 C 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.