MAX147AEAP

19-0465; Rev 1; 6/97 KIT ATION EVALU BLE AVAILA +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs ____________________________Features o 8-Channel Single-Ended or 4-Channel Differential Inputs o Single-Supply Operation: +2.7V to +3.6V (MAX146) +2.7V to +5.25V (MAX147) o Internal 2.5V Reference (MAX146) o Low Power: 1.2mA (133ksps, 3V supply) 54µA (1ksps, 3V supply) 1µA (power-down mode) o SPI/QSPI/Microwire/TMS320-Compatible 4-Wire Serial Interface o Software-Configurable Unipolar or Bipolar Inputs o 20-Pin DIP/SSOP Packages _______________General Description The MAX146/MAX147 12-bit data-acquisition systems combine an 8-channel multiplexer, high-bandwidth track/hold, and serial interface with high conversion speed and low power consumption. The MAX146 operates from a single +2.7V to +3.6V supply; the MAX147 operates from a single +2.7V to +5.25V supply. Both devices’ analog inputs are software configurable for unipolar/bipolar and single-ended/differential operation. The 4-wire serial interface connects directly to SPI™/ QSPI™ and Microwire™ devices without external logic. A serial strobe output allows direct connection to TMS320family digital signal processors. The MAX146/MAX147 use either the internal clock or an external serial-interface clock to perform successive-approximation analog-todigital conversions. The MAX146 has an internal 2.5V reference, while the MAX147 requires an external reference. Both parts have a reference-buffer amplifier with a ±1.5% voltageadjustment range. These devices provide a hard-wired SHDN pin and a software-selectable power-down, and can be programmed to automatically shut down at the end of a conversion. Accessing the serial interface automatically powers up the MAX146/MAX147, and the quick turn-on time allows them to be shut down between all conversions. This technique can cut supply current to under 60µA at reduced sampling rates. The MAX146/MAX147 are available in 20-pin DIP and SSOP packages. For 4-channel versions of these devices, see the MAX1246/MAX1247 data sheet. MAX146/MAX147 ______________Ordering Information PART† MAX146ACPP MAX146BCPP MAX146ACAP MAX146BCAP MAX146BC/D TEMP. RANGE 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C PIN-PACKAGE 20 Plastic DIP 20 Plastic DIP 20 SSOP 20 SSOP Dice* INL (LSB) ±1/2 ±1 ±1/2 ±1 ±1 Ordering Information continued at end of data sheet. † Contact factory for availability of alternate surface-mount packages. *Dice are specified at TA = +25°C, DC parameters only. __________Typical Operating Circuit +3V CH0 VDD DGND 0.1µF VDD ________________________Applications Portable Data Logging Medical Instruments Pen Digitizers Data Acquisition Battery-Powered Instruments Process Control 0V TO +2.5V ANALOG INPUTS MAX146 AGND CPU CH7 COM CS SCLK DIN I/O SCK (SK) MOSI (SO) MISO (SI) VSS 4.7µF VREF Pin Configuration appears at end of data sheet. 0.047µF REFADJ DOUT SSTRB SHDN SPI and QSPI are registered trademarks of Motorola, Inc. Microwire is a registered trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs MAX146/MAX147 ABSOLUTE MAXIMUM RATINGS VDD to AGND, DGND................................................. -0.3V to 6V AGND to DGND ...................................................... -0.3V to 0.3V CH0–CH7, COM to AGND, DGND ............ -0.3V to (VDD + 0.3V) VREF, REFADJ to AGND ........................... -0.3V to (VDD + 0.3V) Digital Inputs to DGND .............................................. -0.3V to 6V Digital Outputs to DGND ........................... -0.3V to (VDD + 0.3V) Digital Output Sink Current .................................................25mA Continuous Power Dissipation (TA = +70°C) Plastic DIP (derate 11.11mW/°C above +70°C) ......... 889mW SSOP (derate 8.00mW/°C above +70°C) ................... 640mW CERDIP (derate 11.11mW/°C above +70°C) .............. 889mW Operating Temperature Ranges MAX146_C_P/MAX147_C_P .............................. 0°C to +70°C MAX146_E_P/MAX147_E_P............................ -40°C to +85°C MAX146_MJP/MAX147_MJP ........................ -55°C to +125°C Storage Temperature Range ............................ -60°C to +150°C Lead Temperature (soldering, 10sec) ............................ +300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +3.6V (MAX146); VDD = +2.7V to +5.25V (MAX147); COM = 0V; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX146—4.7µF capacitor at VREF pin; MAX147—external reference, VREF = 2.500 V applied to VREF pin; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error Gain Error (Note 3) Gain Temperature Coefficient Channel-to-Channel Offset Matching Signal-to-Noise + Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Small-Signal Bandwidth Full-Power Bandwidth CONVERSION RATE Internal clock, SHDN = FLOAT Conversion Time (Note 5) Track/Hold Acquisition Time Aperture Delay Aperture Jitter Internal Clock Frequency External Clock Frequency 2 SHDN = FLOAT SHDN = VDD 0.1 Data transfer only 0 tCONV tACQ 30 3.6V, MAX147 only CONDITIONS MIN 2.0 3.0 0.8 0.2 VIN = 0V or VDD (Note 9) VDD - 0.4 1.1 SHDN = 0V or VDD SHDN = FLOAT SHDN = FLOAT VDD / 2 ±100 VDD - 1.1 0.4 ±4.0 ±0.01 ±1 15 TYP MAX UNITS DIGITAL INPUTS (DIN, SCLK, CS, SHDN) DIN, SCLK, CS Input High Voltage DIN, SCLK, CS Input Low Voltage DIN, SCLK, CS Input Hysteresis DIN, SCLK, CS Input Leakage DIN, SCLK, CS Input Capacitance SHDN Input High Voltage SHDN Input Mid Voltage SHDN Input Low Voltage SHDN Input Current SHDN Voltage, Floating SHDN Maximum Allowed Leakage, Mid Input DIGITAL OUTPUTS (DOUT, SSTRB) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Positive Supply Voltage VDD MAX146 MAX147 Operating mode, full-scale input Positive Supply Current, MAX146 IDD VDD = 3.6V Fast power-down Full power-down Positive Supply Current, MAX147 Positive Supply Current, MAX147 Supply Rejection (Note 10) IDD IDD PSR Operating mode, full-scale input Full power-down VDD = 5.25V VDD = 3.6V VDD = 5.25V VDD = 3.6V 2.70 2.70 1.2 30 1.2 1.8 0.9 2.1 1.2 ±0.3 3.60 5.25 2.0 70 10 2.5 1.5 15 10 V mA µA mA µA µA mV VOL VOH IL COUT ISINK = 5mA ISINK = 16mA ISOURCE = 0.5mA CS = VDD CS = VDD (Note 9) VDD - 0.5 ±0.01 ±10 15 0.4 0.8 V V µA pF VIH VIL VHYST IIN CIN VSH VSM VSL IS VFLT V V V µA pF V V V µA V nA Full-scale input, external reference = 2.500V, VDD = 2.7V to VDD(MAX) 4 _______________________________________________________________________________________ +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs TIMING CHARACTERISTICS (VDD = +2.7V to +3.6V (MAX146); VDD = +2.7V to +5.25V (MAX147); TA = TMIN to TMAX; unless otherwise noted.) PARAMETER Acquisition Time DIN to SCLK Setup DIN to SCLK Hold SCLK Fall to Output Data Valid CS Fall to Output Enable CS Rise to Output Disable CS to SCLK Rise Setup CS to SCLK Rise Hold SCLK Pulse Width High SCLK Pulse Width Low SCLK Fall to SSTRB CS Fall to SSTRB Output Enable CS Rise to SSTRB Output Disable SSTRB Rise to SCLK Rise SYMBOL tACQ tDS tDH tDO tDV tTR tCSS tCSH tCH tCL tSSTRB tSDV tSTR tSCK Figure 1 External clock mode only, Figure 1 External clock mode only, Figure 2 Internal clock mode only (Note 9) 0 Figure 1 Figure 1 Figure 2 100 0 200 200 240 240 240 MAX14_ _C/E MAX14_ Figure 1 _M CONDITIONS MIN 1.5 100 0 20 20 200 240 240 240 TYP MAX UNITS µs ns ns ns ns ns ns ns ns ns ns ns ns ns MAX146/MAX147 Note 1: Tested at VDD = 2.7V; COM = 0V; unipolar single-ended input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 3: MAX146—internal reference, offset nulled; MAX147—external reference (VREF = +2.500V), offset nulled. Note 4: Ground “on” channel; sine wave applied to all “off” channels. Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Note 6: The common-mode range for the analog inputs is from AGND to VDD. Note 7: External load should not change during conversion for specified accuracy. Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVp-p. Note 9: Guaranteed by design. Not subject to production testing. Note 10: Measured as |VFS(2.7V) - VFS(VDD, MAX)|. __________________________________________Typical Operating Characteristics (VDD = 3.0V, VREF = 2.500V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. CODE 0.5 0.4 0.3 0.2 INL (LSB) INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 1024 2048 CODE 3072 4096 MAX146/47-01 INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 2.25 2.75 3.25 4.25 3.75 VDD (V) 4.75 5.25 MAX147 MAX146 INL (LSB) MAX146/47-02 INTEGRAL NONLINEARITY vs. TEMPERATURE 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 -60 -20 20 60 100 140 TEMPERATURE (°C) MAX147 MAX146 VDD = 2.7V MAX146/47-03 0.50 _______________________________________________________________________________________ 5 +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs MAX146/MAX147 ____________________________Typical Operating Characteristics (continued) (VDD = 3.0V, VREF = 2.500V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.) MAX146 INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE MAX146/47-05 MAX146/47-06 SUPPLY CURRENT vs. SUPPLY VOLTAGE SHUTDOWN SUPPLY CURRENT (µA) RL = ∞ CODE = 101010100000 MAX146/47-04 SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE 3.5 FULL POWER-DOWN 3.0 2.5 2.5010 VREF (V) 2.75 3.25 3.75 VDD (V) 4.25 4.75 5.25 2.0 1.5 1.0 0.5 0 2.25 2.5005 2.5000 2.4995 2.4990 2.25 2.5020 2.5015 2.00 1.75 SUPPLY CURRENT (mA) 1.50 1.25 1.00 0.75 CLOAD = 50pF MAX146 CLOAD = 20pF MAX147 0.50 2.25 2.75 3.25 3.75 4.25 4.75 5.25 2.75 3.25 3.75 VDD (V) 4.25 4.75 5.25 SUPPLY VOLTAGE (V) SUPPLY CURRENT vs. TEMPERATURE MAX146/47-07 SHUTDOWN CURRENT vs. TEMPERATURE MAX1247-08 MAX146 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX146/47-09 1.3 MAX146 2.0 2.501 2.500 2.499 VREF (V) VDD = 3.6V VDD = 2.7V 2.498 2.497 2.496 SHUTDOWN CURRENT (µA) 1.2 SUPPLY CURRENT (mA) 1.6 1.1 1.2 1.0 MAX147 0.9 RLOAD = ∞ CODE = 101010100000 -60 -20 20 60 100 140 0.8 0.4 2.495 0 -60 -20 20 60 100 140 TEMPERATURE (°C) 2.494 -60 -20 20 60 100 140 TEMPERATURE (°C) 0.8 TEMPERATURE (°C) FFT PLOT 20 0 -20 AMPLITUDE (dB) ENOB -40 -60 -80 11.2 -100 -120 0 10 20 30 40 50 FREQUENCY (kHz) 60 70 11.0 1 11.6 VDD = 2.7V fIN = 10kHz fSAMPLE = 133kHz MAX146/47-10 EFFECTIVE NUMBER OF BITS vs. FREQUENCY VDD = 2.7V 11.8 MAX146/47-11 12.0 11.4 10 FREQUENCY (kHz) 100 6 _______________________________________________________________________________________ +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs ____________________________Typical Operating Characteristics (continued) (VDD = 3.0V, VREF = 2.500V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.) MAX146/MAX147 OFFSET vs. SUPPLY VOLTAGE 0.50 0.45 0.40 GAIN ERROR (LSB) 0.35 OFFSET (LSB) 0.30 0.25 0.20 0.15 0.10 0.05 0 2.25 2.75 3.25 3.75 4.25 VDD (V) 4.75 5.25 MAX146/47-12 GAIN ERROR vs. SUPPLY VOLTAGE MAX146/47-13 CHANNEL-TO-CHANNEL GAIN MATCHING vs. SUPPLY VOLTAGE 0.50 0.45 0.40 GAIN MATCHING (LSB) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 MAX146/47-14 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 2.25 2.75 3.25 3.75 VDD (V) 4.25 4.75 5.25 0 2.25 2.75 3.25 3.75 VDD (V) 4.25 4.75 5.25 OFFSET vs. TEMPERATURE MAX146/47-15 GAIN ERROR vs. TEMPERATURE 0.50 0.45 0.40 GAIN ERROR (LSB) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 GAIN MATCHING (LSB) MAX146/47-16 CHANNEL-TO-CHANNEL GAIN MATCHING vs. TEMPERATURE 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 MAX146/47-17 0.50 0.45 0.40 0.35 OFFSET (LSB) 0.30 0.25 0.20 0.15 0.10 0.05 0 -55 -30 -5 20 45 70 95 120 145 -55 -30 -5 TEMPERATURE (˚C) 20 45 70 95 TEMPERATURE (˚C) 120 145 -55 -30 -5 20 45 70 95 TEMPERATURE (˚C) 120 145 CHANNEL-TO-CHANNEL OFFSET MATCHING vs. SUPPLY VOLTAGE 0.50 0.45 OFFSET MATCHING (LSB) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 2.25 2.75 3.25 3.75 VDD (V) 4.25 4.75 5.25 MAX146/47-18 CHANNEL-TO-CHANNEL OFFSET MATCHING vs. TEMPERATURE 0.50 0.45 OFFSET MATCHING (LSB) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 -55 -30 -5 20 45 70 95 TEMPERATURE (˚C) 120 145 MAX146/47-19 _______________________________________________________________________________________ 7 +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs MAX146/MAX147 ______________________________________________________________Pin Description PIN 1–8 9 NAME CH0–CH7 COM Sampling Analog Inputs Ground reference for analog inputs. COM sets zero-code voltage in single-ended mode. Must be stable to ±0.5LSB. Three-Level Shutdown Input. Pulling SHDN low shuts the MAX146/MAX147 down; otherwise, they are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in external compensation mode. Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In internal reference mode (MAX146 only), the reference buffer provides a 2.500V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to VDD. Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD. Analog Ground Digital Ground Serial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high. Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX146/MAX147 begin the A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is high (external clock mode). Serial Data Input. Data is clocked in at SCLK’s rising edge. Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is high impedance. Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets the conversion speed. (Duty cycle must be 40% to 60%.) Positive Supply Voltage FUNCTION 10 SHDN 11 VREF 12 13 14 15 REFADJ AGND DGND DOUT 16 SSTRB 17 18 19 20 DIN CS SCLK VDD VDD VDD 6k DOUT CLOAD 50pF DGND CLOAD 50pF DGND a) VOH to High-Z DOUT CLOAD 50pF DGND b) VOL to High-Z 6k DOUT CLOAD 50pF DGND a) High-Z to VOH and VOL to VOH DOUT 6k 6k b) High-Z to VOL and VOH to VOL Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disable Time 8 _______________________________________________________________________________________ +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs _______________Detailed Description The MAX146/MAX147 analog-to-digital converters (ADCs) use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. A flexible serial interface provides easy interface to microprocessors (µPs). Figure 3 is a block diagram of the MAX146/ MAX147. on the falling SCLK edge after the last bit of the input control word has been entered. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the negative input (IN-). In single-ended mode, IN- is simply COM. This unbalances node ZERO at the comparator’s input. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to 0V within the limits of 12-bit resolution. This action is equivalent to transferring a 16pF x [(VIN+) (V IN -)] charge from C HOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal. MAX146/MAX147 Pseudo-Differential Input The sampling architecture of the ADC’s analog comparator is illustrated in the equivalent input circuit (Figure 4). In single-ended mode, IN+ is internally switched to CH0–CH7, and IN- is switched to COM. In differential mode, IN+ and IN- are selected from the following pairs: CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure the channels with Tables 2 and 3. In differential mode, IN- and IN+ are internally switched to either of the analog inputs. This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side (IN-) must remain stable within ±0.5LSB (±0.1LSB for best results) with respect to AGND during a conversion. To accomplish this, connect a 0.1µF capacitor from IN- (the selected analog input) to AGND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. The acquisition interval spans three SCLK cycles and ends Track/Hold The T/H enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. It enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. If the converter is set up for single-ended inputs, IN- is connected to COM, and the converter samples the “+” input. If the converter is set up for differential inputs, IN- connects to the “-” input, and the difference of |IN+ - IN-| is sampled. At the end of the conversion, the positive input connects back to IN+, and CHOLD charges to the input signal. CS SCLK DIN SHDN CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 18 19 17 10 1 2 3 4 5 6 7 8 9 +1.21V REFERENCE (MAX146) 20k INPUT SHIFT REGISTER INT CLOCK CONTROL LOGIC OUTPUT SHIFT REGISTER ANALOG INPUT MUX T/H CLOCK IN 12-BIT SAR ADC OUT REF A ≈ 2.06* 15 16 DOUT SSTRB 12-BIT CAPACITIVE DAC VREF INPUT CHOLD MUX – + 16pF CSWITCH TRACK T/H SWITCH RIN 9k HOLD AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. COMPARATOR ZERO CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 20 14 13 VDD DGND AGND REFADJ 12 VREF 11 +2.500V *A ≈ 2.00 (MAX147) MAX146 MAX147 SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM. DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7. Figure 3. Block Diagram Figure 4. Equivalent Input Circuit 9 _______________________________________________________________________________________ +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. The acquisition time, tACQ, is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. It is calculated by the following equation: tACQ = 9 x (RS + RIN) x 16pF where RIN = 9kΩ, RS = the source impedance of the input signal, and tACQ is never less than 1.5µs. Note that source impedances below 1kΩ do not significantly affect the ADC’s AC performance. Higher source impedances can be used if a 0.01µF capacitor is connected to the individual analog inputs. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC’s signal bandwidth. MAX146/MAX147 Analog Input Protection Internal protection diodes, which clamp the analog input to VDD and AGND, allow the channel input pins to swing from AGND - 0.3V to V DD + 0.3V without damage. However, for accurate conversions near full scale, the inputs must not exceed VDD by more than 50mV or be lower than AGND by 50mV. If the analog input exceeds 50mV beyond the supplies, do not forward bias the protection diodes of off channels over 2mA. Quick Look To quickly evaluate the MAX146/MAX147’s analog performance, use the circuit of Figure 5. The MAX146/ MAX147 require a control byte to be written to DIN before each conversion. Tying DIN to +3V feeds in control bytes of $FF (HEX), which trigger single-ended unipolar conversions on CH7 in external clock mode without powering down between conversions. In external clock mode, the SSTRB output pulses high for one clock period before the most significant bit of the 12-bit conversion result is shifted out of DOUT. Varying the analog input to CH7 will alter the sequence of bits from DOUT. A total of 15 clock cycles is required per conversion. All transitions of the SSTRB and DOUT outputs occur on the falling edge of SCLK. Input Bandwidth The ADC’s input tracking circuitry has a 2.25MHz small-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. OSCILLOSCOPE 0V TO 2.500V ANALOG INPUT 0.01µF +3V +3V VOUT 1000pF 2.5V C1 0.1µF MAX146 MAX147 CH7 VDD DGND AGND COM CS 0.1µF +3V SCLK SSTRB DOUT* +3V 2MHz OSCILLATOR CH1 CH2 CH3 CH4 REFADJ SCLK DIN DOUT VREF SSTRB SHDN N.C. MAX872 COMP OPTIONAL FOR MAX146, REQUIRED FOR MAX147 * FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX) Figure 5. Quick-Look Circuit 10 ______________________________________________________________________________________ +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs MAX146/MAX147 Table 1. Control-Byte Format BIT 7 (MSB) START BIT 7(MSB) 6 5 4 3 BIT 6 SEL2 NAME START SEL2 SEL1 SEL0 UNI/BIP BIT 5 SEL1 DESCRIPTION The first logic “1” bit after CS goes low defines the beginning of the control byte. These three bits select which of the eight channels are used for the conversion (Tables 2 and 3). BIT 4 SEL0 BIT 3 UNI/BIP BIT 2 SGL/DIF BIT 1 PD1 BIT 0 (LSB) PD0 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range from -VREF/2 to +VREF/2. 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In singleended mode, input signal voltages are referred to COM. In differential mode, the voltage difference between two channels is measured (Tables 2 and 3). Selects clock and power-down modes. PD1 PD0 Mode 0 0 Full power-down 0 1 Fast power-down (MAX146 only) 1 0 Internal clock mode 1 1 External clock mode 2 SGL/DIF 1 0(LSB) PD1 PD0 Table 2. Channel Selection in Single-Ended Mode (SGL/DIF = 1) SEL2 0 1 0 1 0 1 0 1 SEL1 0 0 0 0 1 1 1 1 SEL0 0 0 1 1 0 0 1 1 CH0 + CH1 + + + + + + + CH2 CH3 CH4 CH5 CH6 CH7 COM – – – – – – – – Table 3. Channel Selection in Differential Mode (SGL/DIF = 0) SEL2 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 – + – + – + – + 11 CH0 + CH1 – + – + – + – CH2 CH3 CH4 CH5 CH6 CH7 ______________________________________________________________________________________ +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs MAX146/MAX147 How to Start a Conversion Start a conversion by clocking a control byte into DIN. With CS low, each rising edge on SCLK clocks a bit from DIN into the MAX146/MAX147’s internal shift register. After CS falls, the first arriving logic “1” bit defines the control byte’s MSB. Until this first “start” bit arrives, any number of logic “0” bits can be clocked into DIN with no effect. Table 1 shows the control-byte format. The MAX146/MAX147 are compatible with SPI™/ QSPI™ and Microwire™ devices. For SPI, select the correct clock polarity and sampling edge in the SPI control registers: set CPOL = 0 and CPHA = 0. Microwire, SPI, and QSPI all transmit a byte and receive a byte at the same time. Using the Typical Operating Circuit, the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the 12-bit conversion result). See Figure 20 for MAX146/MAX147 QSPI connections. 4) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB2. 5) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB3. 6) Pull CS high. Figure 6 shows the timing for this sequence. Bytes RB2 and RB3 contain the result of the conversion, padded with one leading zero and three trailing zeros. The total conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. To avoid excessive T/H droop, make sure the total conversion time does not exceed 120µs. Digital Output In unipolar input mode, the output is straight binary (Figure 17). For bipolar input mode, the output is two’s complement (Figure 18). Data is clocked out at the falling edge of SCLK in MSB-first format. Simple Software Interface Make sure the CPU’s serial interface runs in master mode so the CPU generates the serial clock. Choose a clock frequency from 100kHz to 2MHz. 1) Set up the control byte for external clock mode and call it TB1. TB1 should be of the format: 1XXXXX11 binary, where the Xs denote the particular channel and conversion mode selected. 2) Use a general-purpose I/O line on the CPU to pull CS low. 3) Transmit TB1 and, simultaneously, receive a byte and call it RB1. Ignore RB1. Clock Modes The MAX146/MAX147 may use either an external serial clock or the internal clock to perform the successive-approximation conversion. In both clock modes, the external clock shifts data in and out of the MAX146/MAX147. The T/H acquires the input signal as the last three bits of the control byte are clocked into DIN. Bits PD1 and PD0 of the control byte program the clock mode. Figures 7–10 show the timing characteristics common to both modes. CS tACQ SCLK 1 4 SEL2 SEL1 SEL0 UNI/ BIP START SGL/ PD1 DIF 8 12 16 20 24 DIN SSTRB PD0 RB1 DOUT ACQUISITION 1.5µs (fSCLK = 2MHz) B11 MSB B10 B9 RB2 B8 B7 B6 B5 B4 B3 B2 B1 RB3 B0 LSB FILLED WITH ZEROS A/D STATE IDLE CONVERSION IDLE Figure 6. 24-Clock External Clock Mode Conversion Timing (Microwire and SPI Compatible, QSPI Compatible with fSCLK ≤ 2MHz) 12 ______________________________________________________________________________________ +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs MAX146/MAX147 CS ••• tCSH SCLK tCSS tCL tCH tCSH ••• tDS tDH DIN tDV DOUT ••• tDO ••• tTR Figure 7. Detailed Serial-Interface Timing CS tSDV SSTRB ••• ••• tSTR ••• ••• tSSTRB tSSTRB SCLK •••• •••• PD0 CLOCKED IN Figure 8. External Clock Mode SSTRB Detailed Timing External Clock In external clock mode, the external clock not only shifts data in and out, but it also drives the analog-to-digital conversion steps. SSTRB pulses high for one clock period after the last bit of the control byte. Successive-approximation bit decisions are made and appear at DOUT on each of the next 12 SCLK falling edges (Figure 6). SSTRB and DOUT go into a high-impedance state when CS goes high; after the next CS falling edge, SSTRB outputs a logic low. Figure 8 shows the SSTRB timing in external clock mode. The conversion must complete in some minimum time, or droop on the sample-and-hold capacitors may degrade conversion results. Use internal clock mode if the serial clock frequency is less than 100kHz, or if serial clock interruptions could cause the conversion interval to exceed 120µs. Internal Clock In internal clock mode, the MAX146/MAX147 generate their own conversion clocks internally. This frees the µP from the burden of running the SAR conversion clock and allows the conversion results to be read back at the 13 ______________________________________________________________________________________ +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs MAX146/MAX147 processor’s convenience, at any clock rate from 0MHz to 2MHz. SSTRB goes low at the start of the conversion and then goes high when the conversion is complete. SSTRB is low for a maximum of 7.5µs (SHDN = FLOAT), during which time SCLK should remain low for best noise performance. An internal register stores data when the conversion is in progress. SCLK clocks the data out of this register at any time after the conversion is complete. After SSTRB goes high, the next falling clock edge produces the MSB of the conversion at DOUT, followed by the remaining bits in MSB-first format (Figure 9). CS does not need to be held low once a conversion is started. Pulling CS high prevents data from being clocked into the MAX146/MAX147 and three-states DOUT, but it does not adversely affect an internal clock mode conversion already in progress. When internal clock mode is selected, SSTRB does not go into a highimpedance state when CS goes high. Figure 10 shows the SSTRB timing in internal clock mode. In this mode, data can be shifted in and out of the MAX146/MAX147 at clock rates exceeding 2.0MHz if the minimum acquisition time (tACQ) is kept above 1.5µs. CS SCLK 1 2 3 4 5 6 7 8 9 10 11 12 18 19 20 21 22 23 24 DIN START SEL2 SEL1 SEL0 UNI/ BIP SGL/ PD1 DIF PD0 SSTRB tCONV DOUT ACQUISITION 1.5µs (fSCLK = 2MHz) CONVERSION 7.5µs MAX (SHDN = FLOAT) B11 MSB B10 B9 B2 B1 B0 LSB FILLED WITH ZEROS A/D STATE IDLE IDLE Figure 9. Internal Clock Mode Timing CS tCONV tCSH SSTRB tSSTRB SCLK tDO PD0 CLOCK IN DOUT NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION. tSCK tCSS Figure. 10. Internal Clock Mode SSTRB Detailed Timing 14 ______________________________________________________________________________________ +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs Data Framing The falling edge of CS does not start a conversion. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte. A conversion starts on SCLK’s falling edge, after the eighth bit of the control byte (the PD0 bit) is clocked into DIN. The start bit is defined as follows: The first high bit clocked into DIN with CS low any time the converter is idle; e.g., after VDD is applied. OR The first high bit clocked into DIN after bit 5 of a conversion in progress is clocked onto the DOUT pin. If CS is toggled before the current conversion is complete, the next high bit clocked into DIN is recognized as a start bit; the current conversion is terminated, and a new one is started. The fastest the MAX146/MAX147 can run with CS held low between conversions is 15 clocks per conversion. Figure 11a shows the serial-interface timing necessary to perform a conversion every 15 SCLK cycles in external clock mode. If CS is tied low and SCLK is continuous, guarantee a start bit by first clocking in 16 zeros. Most microcontrollers (µCs) require that conversions occur in multiples of 8 SCLK clocks; 16 clocks per conversion is typically the fastest that a µC can drive the MAX146/MAX147. Figure 11b shows the serialinterface timing necessary to perform a conversion every 16 SCLK cycles in external clock mode. MAX146/MAX147 __________ Applications Information Power-On Reset When power is first applied, and if SHDN is not pulled low, internal power-on reset circuitry activates the MAX146/MAX147 in internal clock mode, ready to convert with SSTRB = high. After the power supplies stabilize, the internal reset time is 10µs, and no conversions should be performed during this phase. SSTRB is high on power-up and, if CS is low, the first logical 1 on DIN is interpreted as a start bit. Until a conversion takes place, DOUT shifts out zeros. (Also see Table 4.) CS 1 SCLK DIN DOUT SSTRB S CONTROL BYTE 0 S CONTROL BYTE 1 S CONTROL BYTE 2 8 15 1 8 15 1 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 CONVERSION RESULT 0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 CONVERSION RESULT 1 Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing CS 1 SCLK DIN DOUT S CONTROL BYTE 0 S CONTROL BYTE 1 B11 B10 B9 B8 CONVERSION RESULT 1 8 16 1 8 16 ••• ••• ••• ••• B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 CONVERSION RESULT 0 Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing ______________________________________________________________________________________ 15 +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs MAX146/MAX147 Reference-Buffer Compensation In addition to its shutdown function, SHDN selects internal or external compensation. The compensation affects both power-up time and maximum conversion speed. The100kHz minimum clock rate is limited by droop on the sample-and-hold and is independent of the compensation used. Float S HDN to select external compensation. The Typical Operating Circuit uses a 4.7µF capacitor at VREF. A 4.7µF value ensures reference-buffer stability and allows converter operation at the 2MHz full clock speed. External compensation increases power-up time (see the Choosing Power-Down Mode section and Table 4). Pull S HDN high to select internal compensation. Internal compensation requires no external capacitor at VREF and allows for the shortest power-up times. The maximum clock rate is 2MHz in internal clock mode and 400kHz in external clock mode. except the bandgap reference. With fast power-down mode, the supply current is 30µA. Power-up time can be shortened to 5µs in internal compensation mode. Table 4 shows how the choice of reference-buffer compensation and power-down mode affects both power-up delay and maximum sample rate. In external compensation mode, power-up time is 20ms with a 4.7µF compensation capacitor when the capacitor is initially fully discharged. From fast power-down, start-up time can be eliminated by using low-leakage capacitors that do not discharge more than 1/2LSB while shut down. In powerdown, leakage currents at VREF cause droop on the reference bypass capacitor. Figures 12a and 12b show the various power-down sequences in both external and internal clock modes. Choosing Power-Down Mode You can save power by placing the converter in a lowcurrent shutdown state between conversions. Select full power-down mode or fast power-down mode via bits 1 and 0 of the DIN control byte with SHDN high or floating (Tables 1 and 5). In both software power-down modes, the serial interface remains operational, but the ADC does not convert. Pull SHDN low at any time to shut down the converter completely. SHDN overrides bits 1 and 0 of the control byte. Full power-down mode turns off all chip functions that draw quiescent current, reducing supply current to 2µA (typ). Fast power-down mode turns off all circuitry Software Power-Down Software power-down is activated using bits PD1 and PD0 of the control byte. As shown in Table 5, PD1 and PD0 also specify the clock mode. When software shutdown is asserted, the ADC operates in the last specified clock mode until the conversion is complete. Then the ADC powers down into a low quiescent-current state. In internal clock mode, the interface remains active and conversion results may be clocked out after the MAX146/MAX147 enter a software power-down. The first logical 1 on DIN is interpreted as a start bit and powers up the MAX146/MAX147. Following the start bit, the data input word or control byte also determines clock mode and power-down states. For example, if the DIN word contains PD1 = 1, then the chip remains powered up. If PD0 = PD1 = 0, a power-down resumes after one conversion. Table 4. Typical Power-Up Delay Times REFERENCE BUFFER Enabled Enabled Enabled Enabled Disabled Disabled REFERENCEBUFFER COMPENSATION MODE Internal Internal External External — — VREF CAPACITOR (µF) — — 4.7 4.7 — — POWER-DOWN MODE Fast Full Fast Full Fast Full POWER-UP DELAY (µs) 5 300 See Figure 14c See Figure 14c 2 2 MAXIMUM SAMPLING RATE (ksps) 26 26 133 133 133 133 16 ______________________________________________________________________________________ +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs MAX146/MAX147 CLOCK MODE SHDN SETS EXTERNAL CLOCK MODE DIN SXXXXX11 SXXXXX00 EXTERNAL EXTERNAL SETS SOFTWARE POWER-DOWN SETS EXTERNAL CLOCK MODE SXX XXX1 1 DOUT 12 DATA BITS 12 DATA BITS VALID DATA INVALID DATA HARDWARE POWERDOWN MODE POWERED UP SOFTWARE POWER-DOWN POWERED UP POWERED UP Figure 12a. Timing Diagram Power-Down Modes, External Clock CLOCK MODE INTERNAL SETS INTERNAL CLOCK MODE SXXXXX10 SXXXXX00 SETS POWER-DOWN S DIN DOUT DATA VALID DATA VALID SSTRB MODE CONVERSION POWERED UP CONVERSION POWER-DOWN POWERED UP Figure 12b. Timing Diagram Power-Down Modes, Internal Clock Hardware Power-Down Pulling SHDN low places the converter in hardware power-down (Table 6). Unlike software power-down mode, the conversion is not completed; it stops coincidentally with SHDN being brought low. SHDN also controls the clock frequency in internal clock mode. Letting SHDN float sets the internal clock frequency to 1.8MHz. When returning to normal operation with SHDN floating, there is a tRC delay of approximately 2MΩ x CL, where CL is the capacitive loading on the SHDN pin. Pulling SHDN high sets internal clock frequency to 225kHz. This feature eases the settling-time requirement for the reference voltage. With an external reference, the MAX146/MAX147 can be considered fully powered up within 2µs of actively pulling SHDN high. ______________________________________________________________________________________ 17 +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs MAX146/MAX147 Power-Down Sequencing The MAX146/MAX147 auto power-down modes can save considerable power when operating at less than maximum sample rates. Figures 13, 14a, and 14b show the average supply current as a function of the sampling rate. The following discussion illustrates the various power-down sequences. Figure 14a depicts the MAX146 power consumption for one or eight channel conversions utilizing full powerdown mode and internal-reference compensation. A 0.047µF bypass capacitor at REFADJ forms an RC filter with the internal 20kΩ reference resistor with a 0.9ms time constant. To achieve full 12-bit accuracy, 10 time constants or 9ms are required after power-up. Waiting this 9ms in FASTPD mode instead of in full power-up can reduce power consumption by a factor of 10 or more. This is achieved by using the sequence shown in Figure 15. Lowest Power at up to 500 Conversions/Channel/Second The following examples show two different power-down sequences. Other combinations of clock rates, compensation modes, and power-down modes may give lowest power consumption in other applications. AVERAGE SUPPLY CURRENT vs. CONVERSION RATE WITH EXTERNAL REFERENCE VREF = VDD = 3.0V RLOAD = ∞ CODE = 101010100000 MAX146/47-13 AVERAGE SUPPLY CURRENT vs. CONVERSION RATE (USING FULLPD) RLOAD = ∞ CODE = 101010100000 MAX146/47-Fig14a 10,000 AVERAGE SUPPLY CURRENT (µA) 100 AVERAGE SUPPLY CURRENT (µA) 1000 100 8 CHANNELS 10 1 CHANNEL 10 8 CHANNELS 1 CHANNEL 1 0.1 0.1 1 10 100 1k 10k 100k 1M CONVERSION RATE (Hz) 1 0.01 0.1 1 10 100 1k CONVERSION RATE (Hz) Figure 13. Average Supply Current vs. Conversion Rate with External Reference AVERAGE SUPPLY CURRENT vs. CONVERSION RATE (USING FASTPD) RLOAD = ∞ CODE = 101010100000 1000 8 CHANNELS 100 1 CHANNEL 10 MAX146/47-Fig14b Figure 14a. MAX146 Supply Current vs. Conversion Rate, FULLPD TYPICAL REFERENCE-BUFFER POWER-UP DELAY vs. TIME IN SHUTDOWN MAX146/47-Fig14c 10,000 AVERAGE SUPPLY CURRENT (µA) 2.0 POWER-UP DELAY (ms) 1.5 1.0 0.5 1 0.1 1 10 100 1k 10k 100k 1M CONVERSION RATE (Hz) 0 0.001 0.01 0.1 1 10 TIME IN SHUTDOWN (sec) Figure 14b. MAX146 Supply Current vs. Conversion Rate, FASTPD 18 Figure 14c. Typical Reference-Buffer Power-Up Delay vs. Time in Shutdown ______________________________________________________________________________________ +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs MAX146/MAX147 COMPLETE CONVERSION SEQUENCE 9ms WAIT DIN (ZEROS) 1 FULLPD 1.21V REFADJ 0V 2.50V VREF 0V tBUFFEN ≈ 200µs τ = RC = 20kΩ x CREFADJ 00 1 FASTPD 01 1 NOPD CH1 11 1 CH7 00 FULLPD (ZEROS) 1 FASTPD 01 Figure 15. MAX146 FULLPD/FASTPD Power-Up Sequence Lowest Power at Higher Throughputs Figure 14b shows the power consumption with external-reference compensation in fast power-down, with one and eight channels converted. The external 4.7µF compensation requires a 200µs wait after power-up with one dummy conversion. This graph shows fast multi-channel conversion with the lowest power consumption possible. Full power-down mode may provide increased power savings in applications where the MAX146/MAX147 are inactive for long periods of time, but where intermittent bursts of high-speed conversions are required. +3.3V 24k MAX146 510k 100k 12 0.047µF REFADJ Internal and External References The MAX146 can be used with an internal or external reference voltage, whereas an external reference is required for the MAX147. An external reference can be connected directly at VREF or at the REFADJ pin. An internal buffer is designed to provide 2.5V at VREF for both the MAX146 and the MAX147. The MAX146’s internally trimmed 1.21V reference is buffered with a 2.06 gain. The MAX147’s REFADJ pin is also buffered with a 2.00 gain to scale an external 1.25V reference at REFADJ to 2.5V at VREF. Figure 16. MAX146 Reference-Adjust Circuit Table 5. Software Power-Down and Clock Mode PD1 0 0 1 1 PD0 0 1 0 1 DEVICE MODE Full Power-Down Fast Power-Down Internal Clock External Clock Internal Reference (MAX146) The MAX146’s full-scale range with the internal reference is 2.5V with unipolar inputs and ±1.25V with bipolar inputs. The internal reference voltage is adjustable to ±1.5% with the circuit in Figure 16. External Reference With both the MAX146 and MAX147, an external reference can be placed at either the input (REFADJ) or the output (VREF) of the internal reference-buffer amplifier. The REFADJ input impedance is typically 20kΩ for the MAX146, and higher than 100kΩ for the MAX147. At Table 6. Hard-Wired Power-Down and Internal Clock Frequency SHDN STATE 1 Floating 0 DEVICE MODE Enabled Enabled Power-Down REFERENCE BUFFER COMPENSATION Internal External N/A INTERNAL CLOCK FREQUENCY 225kHz 1.8MHz N/A ______________________________________________________________________________________ 19 +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs MAX146/MAX147 VREF, the DC input resistance is a minimum of 18kΩ. During conversion, an external reference at VREF must deliver up to 350µA DC load current and have 10Ω or less output impedance. If the reference has a higher output impedance or is noisy, bypass it close to the VREF pin with a 4.7µF capacitor. Using the REFADJ input makes buffering the external reference unnecessary. To use the direct VREF input, disable the internal buffer by tying REFADJ to VDD. In power-down, the input bias current to REFADJ is typically 25µA (MAX146) with REFADJ tied to VDD. Pull REFADJ to AGND to minimize the input bias current in power-down. OUTPUT CODE FULL-SCALE TRANSITION 11 . . . 111 11 . . . 110 11 . . . 101 FS = VREF + COM ZS = COM VREF 1LSB = 4096 00 . . . 011 Transfer Function Table 7 shows the full-scale voltage ranges for unipolar and bipolar modes. The external reference must have a temperature coefficient of 4ppm/°C or less to achieve accuracy to within 1LSB over the 0°C to +70°C commercial temperature range. Figure 17 depicts the nominal, unipolar input/output (I/O) transfer function, and Figure 18 shows the bipolar input/output transfer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary, with 1LSB = 610µV (2.500V / 4096) for unipolar operation, and 1LSB = 610µV [(2.500V / 2 - -2.500V / 2) / 4096] for bipolar operation. 00 . . . 010 00 . . . 001 00 . . . 000 01 (COM) 2 3 INPUT VOLTAGE (LSB) FS - 3/2LSB FS Figure 17. Unipolar Transfer Function, Full Scale (FS) = VREF + COM, Zero Scale (ZS) = COM Layout, Grounding, and Bypassing For best performance, use printed circuit boards. Wire-wrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Figure 19 shows the recommended system ground connections. Establish a single-point analog ground (star ground point) at AGND, separate from the logic ground. Connect all other analog grounds and DGND to the star ground. No other digital system ground should be connected to this ground. For lowest-noise operation, the ground return to the star ground’s power supply should be low impedance and as short as possible. High-frequency noise in the VDD power supply may affect the high-speed comparator in the ADC. Bypass the supply to the star ground with 0.1µF and 1µF capacitors close to pin 20 of the MAX146/MAX147. Minimize capacitor lead lengths for best supply-noise rejection. If the power supply is very noisy, a 10Ω resistor can be connected as a lowpass filter (Figure 19). High-Speed Digital Interfacing with QSPI The MAX146/MAX147 can interface with QSPI using the circuit in Figure 20 (fSCLK = 2.0MHz, CPOL = 0, CPHA = 0). This QSPI circuit can be programmed to do a conversion on each of the eight channels. The result is stored in memory without taxing the CPU, since QSPI incorporates its own microsequencer. The MAX146/MAX147 are QSPI compatible up to the maximum external clock frequency of 2MHz. Table 7. Full Scale and Zero Scale UNIPOLAR MODE Full Scale VREF + COM Zero Scale COM Positive Full Scale VREF / 2 + COM BIPOLAR MODE Zero Scale COM Negative Full Scale -VREF / 2 + COM 20 ______________________________________________________________________________________ +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs MAX146/MAX147 OUTPUT CODE FS = VREF + COM 2 ZS = COM -FS = -VREF + COM 2 VREF 4096 +3V +3V GND 011 . . . 111 011 . . . 110 SUPPLIES 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 1LSB = R* = 10Ω VDD 100 . . . 001 100 . . . 000 - FS *COM ≤ VREF / 2 COM* INPUT VOLTAGE (LSB) +FS - 1LSB *OPTIONAL AGND COM DGND +3V DGND MAX146 MAX147 DIGITAL CIRCUITRY Figure 18. Bipolar Transfer Function, Full Scale (FS) = VREF / 2 + COM, Zero Scale (ZS) = COM Figure 19. Power-Supply Grounding Connection TMS320LC3x Interface Figure 21 shows an application circuit to interface the MAX146/MAX147 to the TMS320 in external clock mode. The timing diagram for this interface circuit is shown in Figure 22. Use the following steps to initiate a conversion in the MAX146/MAX147 and to read the results: 1) The TMS320 should be configured with CLKX (transmit clock) as an active-high output clock and CLKR (TMS320 receive clock) as an active-high input clock. CLKX and CLKR on the TMS320 are tied together with the MAX146/MAX147’s SCLK input. 2) The MAX146/MAX147’s CS pin is driven low by the TMS320’s XF_ I/O port to enable data to be clocked into the MAX146/MAX147’s DIN. 3) An 8-bit word (1XXXXX11) should be written to the MAX146/MAX147 to initiate a conversion and place the device into external clock mode. Refer to Table 1 to select the proper XXXXX bit values for your specific application. 4) The MAX146/MAX147’s SSTRB output is monitored via the TMS320’s FSR input. A falling edge on the SSTRB output indicates that the conversion is in progress and data is ready to be received from the MAX146/MAX147. 5) The TMS320 reads in one data bit on each of the next 16 rising edges of SCLK. These data bits represent the 12-bit conversion result followed by four trailing bits, which should be ignored. 6) Pull CS high to disable the MAX146/MAX147 until the next conversion is initiated. ______________________________________________________________________________________ 21 +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs MAX146/MAX147 +3V +3V 0.1µF 1 2 3 ANALOG INPUTS 4 5 6 7 8 9 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM VDD 20 1µF (POWER SUPPLIES) SCK PCS0 MOSI SCLK 19 CS 18 MAX146 MAX147 DIN 17 SSTRB 16 DOUT 15 DGND 14 AGND 13 MC683XX MISO REFADJ 12 VREF 11 0.1µF +2.5V (GND) 10 SHDN Figure 20. MAX146/MAX147 QSPI Connections, External Reference XF CLKX CS SCLK TMS320LC3x CLKR DX DR FSR MAX146 MAX147 DIN DOUT SSTRB Figure 21. MAX146/MAX147-to-TMS320 Serial Interface 22 ______________________________________________________________________________________ +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs MAX146/MAX147 CS SCLK DIN START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0 HIGH IMPEDANCE HIGH IMPEDANCE SSTRB DOUT MSB B10 B1 LSB Figure 22. TMS320 Serial-Interface Timing Diagram _Ordering Information (continued) PART† MAX146AEPP MAX146BEPP MAX146AEAP MAX146BEAP MAX146AMJP MAX146BMJP MAX147ACPP MAX147BCPP MAX147ACAP MAX147BCAP MAX147BC/D MAX147AEPP MAX147BEPP MAX147AEAP MAX147BEAP MAX147AMJP MAX147BMJP † __________________Pin Configuration TOP VIEW CH0 1 CH1 2 CH2 3 CH3 4 CH4 5 CH5 6 CH6 7 CH7 8 COM 9 SHDN 10 20 VDD 19 SCLK 18 CS TEMP. RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C -55°C to +125°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C -55°C to +125°C PIN-PACKAGE 20 Plastic DIP 20 Plastic DIP 20 SSOP 20 SSOP 20 CERDIP** 20 CERDIP** 20 Plastic DIP 20 Plastic DIP 20 SSOP 20 SSOP Dice* 20 Plastic DIP 20 Plastic DIP 20 SSOP 20 SSOP 20 CERDIP** 20 CERDIP** INL (LSB) ±1/2 ±1 ±1/2 ±1 ±1/2 ±1 ±1/2 ±1 ±1/2 ±1 ±1 ±1/2 ±1 ±1/2 ±1 ±1/2 ±1 MAX146 MAX147 17 DIN 16 SSTRB 15 DOUT 14 DGND 13 AGND 12 REFADJ 11 VREF DIP/SSOP Contact factory for availability of alternate surface-mount packages. * Dice are specified at TA = +25°C, DC parameters only. ** Contact factory for availability of CERDIP package, and for processing to MIL-STD-883B. ___________________Chip Information TRANSISTOR COUNT: 2554 ______________________________________________________________________________________ 23 +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs MAX146/MAX147 ________________________________________________________Package Information SSOP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.