MAX14886CTL

19-5707; Rev 0; 12/10 TION KIT EVALUA BLE ILA AVA Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter General Description Features S Single +3.3V Supply S Meets HDMI v.1.4 Eye Mask Up to 2.25Gbps S Meets VESA DisplayPort Interoperability Guideline MAX14886 The MAX14886 high-speed, low-skew, active redriver multiplexer is ideal for switching between outputs of dual-graphics systems and signal conditioning to meet HDMIK v.1.4 compliance up to 2.25Gbps at an external HDMI connector. It is used for switching between integrated (e.g., Intel or AMD) and discrete graphics (e.g., NVIDIA or ATI GPU). The device is VESA DisplayPortK Interoperability Guideline v.1.1a-compliant (requires external DDC logic) and integrates seamlessly with an external HDMI connector on the motherboard. The device accommodates differential inputs as low as 200mV and drives transition minimized differential signaling (TMDS®) outputs to 1000mV (typ). A precision resistor on the output level adjust pin (ADJ) allows differentiated output back-termination resistors of 400I (typ) to better meet HDMI mask jitter compliance, while maintaining full TMDS swing requirements. The device supports AC-(DisplayPort) or DC-(HDMI) coupling directly to the graphics IC and must be DC-coupled to the HDMI connector. In addition, the device features current backflow protection at the HDMI connector and a low-power, active-high or active-low shutdown mode. The device operates with a single +3.3V supply, is specified over the 0NC to +70NC commercial temperature range, and is available in a 5mm x 5mm, 40-pin TQFN package. v.1.1a (Requires External DDC Logic) S Low-Power Shutdown Mode Active High or Active Low S Output Level Adjust (ADJ) for Output Back- Termination Without Amplitude Loss S Seamless Integration into Dual-Graphics Systems with External HDMI Connector DC-Coupled HDMI Outputs Mate Directly to HDMI Connector AC- or DC-Coupled TMDS-Formatted Inputs Ordering Information PART MAX14886CTL+ TEMP RANGE 0NC to +70NC PIN-PACKAGE 40 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Typical Operating Circuit 3.3V VAVCC = 3.3V Applications Dual Graphics Notebook Computers DisplayPort A 100nF 50Ω VCC D0AP D0AN D0CP HDMI SINK D0CN CKAP CKAN 100nF CKCP CKCN MAX14886 DisplayPort B D0BN EN1 EN2 ADJ CKBP CKBN GND 3.3kΩ HDMI is a trademark of HDMI Licensing, LLC. DisplayPort is a trademark of Video Electronics Standards Association (VESA). TMDS is a registered trademark of Silicon Image, Inc. _______________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MCU D0BP SEL HDMI CONNECTOR Dual Mode DisplayPort to HDMI External Switches or Adapters Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter MAX14886 ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND.) VCC ....................................................................... -0.3V to +4.0V EN1, EN2, SEL, ADJ ................................ -0.3V to (VCC + 0.3V) D_CP, D_CN, CKCP, CKCN Short-Circuit Output Current ............................................................. Q30mA All Other Pins Short-Circuit Current .................................. Q5mA Continuous Power Dissipation (TA = +70NC) TQFN (derate 35.7mW/NC above +70NC) .................. 2857mW Operating Temperature Range ............................. 0NC to +70NC Storage Temperature Range............................ -65NC to +150NC Maximum Junction Temperature.....................................+150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC PACKAGE THERMAL CHARACTERISTICS (Note 1) TQFN Junction-to-Ambient Thermal Resistance (qJA) .......... 45°C/W Junction-to-Case Thermal Resistance (qJC) ................. 2°C/W Note 1: Package thermal resistances were obtained using method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.3V, TA = 0NC to +70NC, RADJ = 3.3kI, CCL = 100nF, typical values are at TA = +25NC.) (Note 2) PARAMETER DC PERFORMANCE Supply Voltage Supply Current Total Supply Current Shutdown Supply Current Single-Ended Input Termination Resistance Single-Ended Output Voltage High Single-Ended Output Voltage Low VCC ICC IGND ISHUT RIN VOH VOL EN1 = high, EN2 = low 50I termination to AVCC, VAVCC = +3.3V (Note 3) EN1 = low or EN2 = high DC DC, VAVCC = +3.3V (Notes 3, 4) DC, VAVCC = +3.3V (Notes 3, 4) 40 VAVCC - 0.01 VAVCC - 0.6 3 3.6 52.5 105 100 60 VAVCC + 0.01 VAVCC - 0.45 V mA mA FA I V V SYMBOL CONDITIONS MIN TYP MAX UNITS 2 Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.3V, TA = 0NC to +70NC, RADJ = 3.3kI, CCL = 100nF, typical values are at TA = +25NC.) (Note 2) PARAMETER AC PERFORMANCE Differential Input Return Loss Input Frequency Range Differential Input Range Differential Output Voltage Output Rise/Fall Time Deterministic Jitter Random Jitter Lane-to-Lane Skew Propagation Delay CONTROL LOGIC (EN1, EN2, SEL) Input Logic-Low Voltage Input Logic-High Voltage Input Logic Hysteresis Input Pulldown/Pullup Resistor Shutdown Recovery Time TMDS Mux Switching Time ESD PROTECTION All Pins Human Body Model ±8 kV Note 2: All units are production tested at TA = +70NC. Specifications over temperature are guaranteed by design. Note 3: AVCC is an external supply. Note 4: Guaranteed by design; not production tested. SDD11 fIN VIDIFF VODIFF tR/F tDJ tRJ tSK tPD VIL VIH VHYST RIPULL tSHUT tMUX 1.4 50 400 20 50 50I single termination 20% to 80%, 2.25Gbps K28.5 pattern, up to 2.25Gbps (Note 4) D10.2 pattern, 2.25Gbps (Note 4) 50 250 0.6 150MHz P f P 1.25GHz Clock Data 25 225 200 900 -8 225 1125 1600 1250 80 0.04 1.1 dB MHz mV mV ps UI psRMS ps ps V V mV kI Fs ns SYMBOL CONDITIONS MIN TYP MAX UNITS MAX14886 3 Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter MAX14886 Typical Operating Characteristics (VCC = +3.3V, TA = +25NC, RADJ = 3.3kI, unless otherwise noted.) EYE DIAGRAM, VIN = 1600mVP-P, 250Mbps, NO BACK TERMINATION, 25MHz CLOCK, 640 x 480, 8-BIT COLOR, 60Hz MAX14886 toc01 EYE DIAGRAM, VIN = 200mVP-P, 250Mbps, NO BACK TERMINATION, 25MHz CLOCK, 640 x 480, 8-BIT COLOR, 60Hz MAX14886 toc02 EYE DIAGRAM, VIN = 1600mVP-P, 1.5Gbps, NO BACK TERMINATION, 150MHz CLOCK 800 600 400 VOLTAGE (mV) 200 0 -200 -400 -600 -800 MAX14886 toc03 800 600 400 VOLTAGE (mV) 200 0 -200 -400 -600 -800 -5 -4 -3 -2 -1 0 (ns) 1 2 3 4 800 600 400 VOLTAGE (mV) 200 0 -200 -400 -600 -800 -5 -4 -3 -2 -1 0 (ns) 1 2 3 4 -600 -400 -200 0 (ps) 200 400 600 EYE DIAGRAM, VIN = 200mVP-P, 1.5Gbps, NO BACK TERMINATION, 1080p, 8-BIT COLOR, 60Hz MAX14886 toc04 EYE DIAGRAM, VIN = 1600mVP-P, 2.25Gbps, NO BACK TERMINATION MAX14886 toc05 EYE DIAGRAM, VIN = 200mVP-P, 2.25Gbps, NO BACK TERMINATION, 225MHz CLOCK, 1080p, 12-BIT COLOR, 60Hz 800 600 400 VOLTAGE (mV) 200 0 -200 -400 -600 -800 MAX14886 toc06 800 600 400 VOLTAGE (mV) 200 0 -200 -400 -600 -800 -600 -400 -200 0 (ps) 200 400 800 600 400 VOLTAGE (mV) 200 0 -200 -400 -600 -800 600 -400 -300 -200 -100 0 (ps) 100 200 300 400 -400 -300 -200 -100 0 (ps) 100 200 300 400 EYE DIAGRAM, VIN = 200mVP-P, 2.25Gbps, 400Ω BACK TERMINATION, RSET = 3kΩ, FIGURE 1 800 600 400 VOLTAGE (mV) 200 0 -200 -400 -600 -800 -400 -300 -200 -100 0 (ps) 100 200 300 400 MAX14886 toc07 DIFFERENTIAL INPUT RETURN LOSS vs. FREQUENCY 0 -5 MAGNITUDE (dB) -10 -15 -20 -25 -30 -35 -40 -45 0 1 2 3 FREQUENCY (GHz) MAX14886 toc08 5 4 Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter Pin Configuration D1AN D1BN D2AN D2BN D1AP D1BP D2AP D2BP GND MAX14886 TOP VIEW VCC 31 GND 32 ADJ 33 SEL 34 GND 35 VCC 36 EN2 37 EN1 38 GND 39 VCC 40 30 29 28 27 26 25 24 23 22 GND 21 20 D2CP 19 D2CN 18 D1CP 17 D1CN 16 VCC 15 D0CP 14 D0CN 13 CKCP 12 CKCN 11 GND 10 GND MAX14886 + *EP 1 D0AP 2 D0AN 3 D0BP 4 D0BN 5 GND 6 CKAP 7 CKAN 8 CKBP 9 CKBN TQFN (5mm × 5mm × 0.75mm) *CONNECT EP TO GND. Pin Description PIN 1 2 3 4 5, 10, 11, 21, 26, 32, 35, 39 6 7 8 9 12 13 14 15 16, 31, 36, 40 17 NAME D0AP D0AN D0BP D0BN GND CKAP CKAN CKBP CKBN CKCN CKCP D0CN D0CP FUNCTION Noninverting Input D0 for Channel A Inverting Input D0 for Channel A Noninverting Input D0 for Channel B Inverting Input D0 for Channel B Ground Noninverting Input Clock for Channel A Inverting Input Clock for Channel A Noninverting Input Clock for Channel B Inverting Input Clock for Channel B Inverting Output Clock Noninverting Output Clock Inverting Output D0 Noninverting Output D0 Power-Supply Voltage. Bypass VCC to GND with low-ESR 10nF and 4.7FF ceramic capacitors in parallel as close as possible to the device. Recommended on each VCC pin. Inverting Output D1 37 EN2 PIN 18 19 20 22 23 24 25 27 28 29 30 33 34 NAME D1CP D2CN D2CP D2BP D2BN D2AP D2AN D1BP D1BN D1AP D1AN ADJ SEL FUNCTION Noninverting Output D1 Inverting Output D2 Noninverting Output D2 Noninverting Input D2 for Channel B Inverting Input D2 for Channel B Noninverting Input D2 for Channel A Inverting Input D2 for Channel A Noninverting Input D1 for Channel B Inverting Input D1 for Channel B Noninverting Input D1 for Channel A Inverting Input D1 for Channel A Output Level Adjust Mux Select Input. SEL is internally pulled down by a 400kI (typ) resistor. Active-Low Enable Input. EN2 is internally pulled up by a 400kI (typ) resistor. Active-High Enable Input. EN1 is internally pulled down by a 400kI (typ) resistor. Exposed Pad. Connect EP to GND. 5 VCC 38 — EN1 EP D1CN Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter MAX14886 Functional Diagram/Truth Tables VCC VCC EN1 0/Unconnected X MAX14886 EN2 X 1/Unconnected 0 FUNCTION Shutdown Shutdown Active 1 X = Don’t care. SEL 0/Unconnected 50Ω D2AP D2AN VCC 50Ω D_A_, CKA_ On Off D_B_, CKB_ Off On 50Ω D2BP D2BN VCC 50Ω 1 X = Don’t care. 50Ω D1AP D1AN VCC 50Ω D2CP D2CN 50Ω D1BP D1BN VCC 50Ω D1CP D1CN MULTIPLEXER/ LIMITING AMPLIFIER D0CP VCC D0CN 50Ω D0AP D0AN 50Ω 50Ω D0BP D0BN VCC 50Ω CKCP CKCN 50Ω CKAP CKAN VCC 50Ω 50Ω CKBP CKBN 50Ω CONTROL GND EN1 EN2 SEL ADJ 6 Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter Detailed Description The MAX14886 is a high-speed, low-skew, active redriver multiplexer designed to switch and amplify TMDS-formatted signals. Input buffers have 50I HDMIcompliant terminations to VCC (see the Functional Diagram/Truth Tables), allowing either DC-coupling to an HDMI source or AC-coupling to a DisplayPort source. Signals from the input buffers are multiplexed and redriven by the limiting amplifier and an open-collector output buffer. The HDMI monitor sink is DC-coupled to the outputs and provides DC bias. Both TMDS clock and data are multiplexed and redriven to full HDMI v.1.4 levels with low skew and jitter to guarantee mask compliance at an external HDMI connector. The device is VESA DisplayPort Interoperability Guideline v.1.1a-compliant and integrates seamlessly with an external HDMI connector on the motherboard. The low-frequency signals (DDC, CEC, and HPD) can be handled by external low-cost logic. The device accommodates differential inputs as low as 200mV and drives differential TMDS outputs to 1000mV (typ). A precision resistor on the output level adjust pin (ADJ) allows differential output back-termination resistors of 400I (typ) to better meet HDMI mask jitter compliance, while maintaining full TMDS swing requirements. This device also features both active-high and activelow enable inputs. One of the enable inputs can be connected to either VCC or GND, while the other can be used to control the device (see the Functional Diagram/ Truth Tables and Enable Inputs (EN1, EN2) section). This eliminates any issues with logic sense and the need for an inverter. The device accepts two sets of four differential DisplayPort-level TMDS-formatted inputs, each with magnitudes as low as 200mV. The selected channel is translated to full HDMI TMDS levels that are HDMI v.1.4 port mask-compliant up to 2.25Gbps. The device features both an active-high enable input (EN1) and an active-low enable input (EN2) that can be controlled by LVCMOS or LVTTL. EN1 has an internal 400kI (typ) pulldown resistor, and EN2 has an internal 400kI (typ) pullup resistor. When EN1 is driven low or left unconnected, or EN2 is driven high or left unconnected, the device enters low-power shutdown mode. For normal operation drive both EN1 high and EN2 low. See the Functional Diagram/Truth Tables. Only one input is necessary to control the device. If active-high enable is desired, connect EN2 to GND and use EN1 to control the device. Similarly, for active-low enable, connect EN1 to VCC and use EN2 to control the device. Note: The monitor sink termination must be present and powered before enabling the device (see the Control Sequence section and Figure 2). The device provides two sets of 4 channels for all the differential signals required by HDMI connections. The SEL input controls which channel is translated to the output channel (see the Functional Diagram/Truth Tables). An internal 400kI pulldown resistor guarantees that channel A is translated to the output if the SEL pin is not externally driven. The level-shifter’s output current and output signal swing are set with an external ±1% precision 3.3kI (typ) resistor. If a double output termination (400I typ) is desired for signal integrity reasons, the ADJ resistor value can be decreased to maintain a desired output swing (Figure 1). MAX14886 Digital Control Input (SEL) Output Level Adjust (ADJ) Applications Information The device’s high-speed, low-skew, active redriver multiplexer is ideal for switching between outputs of dual-graphics systems and signal conditioning to meet HDMI v.1.4 compliance at an external HDMI connector (Figure 1). It is well suited for switching between integrated (e.g., Intel or AMD) and discrete graphics (e.g., NVIDIA or ATI GPU). The device is VESA DisplayPort Interoperability Guideline v.1.1a-compliant (requires external DDC logic) and integrates seamlessly with an external HDMI connector on the motherboard. Outputs are terminated in normal use by the HDMI monitor. For 50I test equipment purposes, terminate each output with a high-frequency bias-T that has an inductor in series with a 50I resistor to VCC. The monitor sink termination must be present and powered before enabling the device. A simple circuit can be added to protect the device by forcing hot-plug detection (HPD) to be present before the part is enabled (Figure 2). HDMI Driver Level Translation Output Termination Enable Inputs (EN1, EN2) Control Sequence 7 Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter MAX14886 3.3V VAVCC = 3.3V 50Ω VCC D0AP D0CP 400Ω HDMI SINK SOURCE A D0AN D0CN CKAP CKCP 400Ω CKAN MAX14886 CKCN SOURCE B D0BN EN1 EN2 ADJ CKBP CKBN GND 3kΩ FOR DisplayPort SOURCE, ADD AC-COUPLING CAPACITORS. Figure 1. HDMI Driver Application with Output Back Termination MCU D0BP SEL HDMI CONNECTOR MAX14886 EN1 Adequate power-supply bypassing is necessary to maximize performance and noise immunity. Bypass each VCC pin to GND with high-frequency, low-ESR, X7R/X5R 10nF and 4.7FF surface-mount ceramic capacitors as close as possible to the device. Input and output trace characteristics affect the performance of the device. Connect each of the inputs and outputs to a 50I characteristic impedance trace in to minimize reflections. Avoid discontinuities in differential impedance and maximize common-mode noise immunity by maintaining the distance between differential traces and avoiding sharp corners. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50I characteristic impedance through connectors and across cables. Minimize skew by matching the electrical length of the traces. Power-Supply Bypassing CONTROL CPU EN GPIO HPD 10kΩ 10kΩ N Printed Circuit Board (PCB) Traces HPD +3.3V Figure 2. Control Sequence Protection Circuit 8 Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter The exposed-pad, 40-pin TQFN package incorporates features that provide a very low thermal resistance path for heat removal from the IC. The exposed pad on the device must be soldered to the circuit board ground plane for proper electrical and thermal performance. For more information on exposed-pad packages, refer to Application Note 862: HFAN-08.1: Thermal Considerations of QFN and Other Exposed-Paddle Packages. Exposed-Pad Package Chip Information PROCESS: BiCMOS MAX14886 Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 40 TQFN-EP PACKAGE CODE T4055+2 OUTLINE NO. 21-0140 LAND PATTERN NO. 90-0002 9 Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter MAX14886 Revision History REVISION NUMBER 0 REVISION DATE 12/10 Initial release DESCRIPTION PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 © Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.