MAX1497

19-3054; Rev 1a; 2/04 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface General Description The MAX1497/MAX1499 low-power, 3.5- and 4.5-digit, analog-to-digital converters (ADCs) with integrated lightemitting diode (LED) drivers operate from a single 2.7V to 5.25V power supply. They include an internal reference, a high-accuracy on-chip oscillator, and a multiplexed LED display driver. An internal charge pump generates the negative supply needed to power the integrated input buffers for single-supply operation. The ADC is configurable for either a ±2V or ±200mV input range and it outputs its conversion results to an LED and/or to a microcontroller (µC). Microcontroller communication is possible through an SPI™-/QSPI™/MICROWIRE™-compatible serial interface. The MAX1497 is a 3.5-digit (±1999 count) device and the MAX1499 is a 4.5-digit (±19,999 count) device. The MAX1497/MAX1499 do not require external precision integrating capacitors, autozero capacitors, crystal oscillators, charge pumps, or other circuitry required with dual-slope ADCs (commonly used in panel meter circuits). These devices also feature on-chip buffers for the differential signal and reference inputs, allowing direct interface with high-impedance signal sources. In addition, they use continuous internal offset-calibration and offer >100dB rejection of 50Hz and 60Hz line noise. Other features include data hold and peak detection, overrange and underrange detection, and a user-programmable low-battery monitor. The MAX1499 is available in a 32-pin, 7mm ✕ 7mm TQFP package and the MAX1497 is available in 28-pin SSOP and 28-pin PDIP packages. All devices in this family operate over the -40°C to +85°C extended temperature range. Features ♦ High Resolution MAX1499: 4.5 Digits (±19,999 Count) MAX1497: 3.5 Digits (±1999 Count) ♦ Sigma-Delta ADC Architecture No Integrating Capacitors Required No Autozeroing Capacitors Required >100dB of Simultaneous 50Hz and 60Hz Rejection ♦ Operate from a Single 2.7V or 5.25V Supply ♦ Selectable Input Range of ±200mV or ±2V ♦ Selectable Voltage Reference: Internal 2.048V or External ♦ Internal High-Accuracy Oscillator Needs No External Components ♦ Automatic Offset Calibration ♦ Low Power (Exclude LED Driver Current) Maximum 664µA Operating Current Maximum 268µA Shutdown Current ♦ Small 32-Pin, 7mm x 7mm TQFP Package (4.5 Digits), 28-Pin SSOP Package (3.5 Digits) ♦ Also Available in a PDIP Package (3.5 Digits) ♦ Multiplexed LED Drivers Resistor-Programmable Segment Current ♦ SPI-/QSPI-/MICROWIRE-Compatible Serial Interface ♦ Extended Temperature Range (-40°C to +85°C) MAX1497/MAX1499 Applications Digital Panel Meters Hand-Held Meters Digital Voltmeters Digital Multimeters PART MAX1497EAI* MAX1497EPI MAX1499ECJ Ordering Information TEMP RANGE PINRESOLUTION PACKAGE (DIGITS) 3.5 3.5 4.5 -40°C to +85°C 28 SSOP -40°C to +85°C 28 PDIP -40°C to +85°C 32 TQFP *Future product—contact factory for availability. Pin Configurations appear at end of data sheet. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 ABSOLUTE MAXIMUM RATINGS AVDD to GND (MAX1499).........................................-0.3V to +6V DVDD to GND (MAX1499) ........................................-0.3V to +6V AIN+, AIN- to GND (MAX1499) ...........VNEG to (AVDD to +0.3V) REF+, REF- to GND (MAX1499) ......... VNEG to (AVDD to +0.3V) LOWBATT to GND (MAX1499) ................-0.3V to (AVDD + 0.3V) CLK, EOC, CS, DIN, SCLK, DOUT to GND (MAX1499) .......................-0.3V to (DVDD + 0.3V) VNEG to GND (MAX1499) .......................-2.6V to (AVDD + 0.3V) LED_EN to GND (MAX1499)....................-0.3V to (DVDD + 0.3V) ISET to GND (MAX1499)..........................-0.3V to (AVDD + 0.3V) VDD to GND (MAX1497) ...........................................-0.3V to +6V AIN+, AIN- to GND (MAX1497)..............VNEG to (VDD to +0.3V) REF+, REF- to GND (MAX1497) ........... VNEG to (VDD to +0.3V) CLK, EOC, CS, DIN, SCLK, DOUT to GND (MAX1497)..........................-0.3V to (VDD + 0.3V) VNEG to GND (MAX1497)..........................-2.6V to (VDD + 0.3V) ISET to GND (MAX1497) ............................-0.3V to (VDD + 0.3V) VLED to GLED ..........................................................-0.3V to +6V GLED to GND ........................................................-0.3V to +0.3V SEG_ to GLED..........................................-0.3V to (VLED + 0.3V) DIG_ to GLED ..........................................-0.3V to (VLED + 0.3V) DIG_ Sink Current .............................................................300mA DIG_ Source Current...........................................................50mA SEG_ Sink Current ..............................................................50mA SEG_ Source Current..........................................................50mA Maximum Current Input into Any Other Pin ........................50mA Continuous Power Dissipation (TA = +70°C) 32-Pin TQFP (derate 20.7mW/°C above +70°C).....1652.9mW 28-Pin SSOP (derate 9.5mW/°C above +70°C) ...........762mW 28-Pin PDIP (derate 14.3mW/°C above +70°C)......1142.9mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = DVDD = VDD = +2.7V to +5.25V, GND = 0, GLED = 0, VLED = +2.7V to +5.25V, VREF+ - VREF- = 2.048V (external reference) CREF+ = CREF- = 0.1µF, CVNEG = 0.1µF. Internal clock mode, unless otherwise noted. All specifications are at TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER DC ACCURACY Noise-Free Resolution Integral Nonlinearity (Note 1) Range Change Ratio Rollover Error Output Noise Offset Error (Zero Input Reading) Gain Error Offset Drift (Zero Reading Drift) Gain Drift INPUT CONVERSION RATE External-Clock Frequency External-Clock Duty Cycle Conversion Rate Internal clock External clock, fCLK = 4.9152MHz 40 5 5 4.9152 60 MHz % Hz Offset VIN = 0 (Note 2) (Note 3) VIN = 0 (Note 4) -0 -0.5 0.1 ±1 INL MAX1499 MAX1497 2.000V range 200mV range (VAIN+ - VAIN- = 0.100V) on 200mV range (VAIN+ - VAIN- = 0.100V) on 2.0V range VAIN+ - VAIN- = full scale VAIN- - VAIN+ = full scale -19,999 -1999 ±1 ±1 10:1 ±1 10 0 +0.5 +19,999 +1999 Count Count Ratio Count µVP-P Reading %FSR µV/°C ppm/°C SYMBOL CONDITIONS MIN TYP MAX UNITS 2 _______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = VDD = +2.7V to +5.25V, GND = 0, GLED = 0, VLED = +2.7V to +5.25V, VREF+ - VREF- = 2.048V (external reference) CREF+ = CREF- = 0.1µF, CVNEG = 0.1µF. Internal clock mode, unless otherwise noted. All specifications are at TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL RANGE bit = 0 RANGE bit = 1 CONDITIONS MIN -2.0 -0.2 -2.2 Internal clock mode, 50Hz and 60Hz ±2% Normal-Mode 50Hz and 60Hz Rejection (Simultaneously) Common-Mode 50Hz and 60Hz Rejection (Simultaneously) Common-Mode Rejection Input Leakage Current Input Capacitance Average Dynamic Input Current LOWBATT TripThreshold LOWBATT Leakage Current Hysteresis INTERNAL REFERENCE (REF- = GND, INTREF bit = 1) (bypass REF+ to GND with a 4.7µF capacitor) REF Output Voltage REF Output Short-Circuit Current REF Output Temperature Coefficient Load Regulation Line Regulation Noise Voltage 0.1Hz to 10Hz 10Hz to 10kHz Differential (VREF+ - VREF-) -2.2 Internal clock mode, 50Hz and 60Hz ±2% Normal-Mode 50Hz and 60Hz Rejection (Simultaneously) Common-Mode 50Hz and 60Hz Rejection (Simultaneously) Common-Mode Rejection Input Leakage Current CMR CMR External clock mode, 50Hz and 60Hz ±2%, fCLK = 4.9152MHz For 50Hz and 60Hz ±2%, RSOURCE < 10kΩ At DC 100 120 150 100 10 dB TCVREF AVDD = VDD = 5V ISOURCE = 0 to 300µA, ISINK = 0 to 30µA VREF AVDD = VDD = 5V 2.007 2.048 1 40 6 50 25 400 2.048 +2.2 V 2.089 V mA ppm/°C mV/µA µV/V µVP-P (Note 6) -20 2.048 10 20 LOW-BATTERY VOLTAGE MONITOR (LOWBATT) (MAX1499 only) V pA mV CMR CMR External clock mode, 50Hz and 60Hz ±2%, fCLK = 4.9152MHz For 50Hz and 60Hz ±2%, RSOURCE < 10kΩ At DC 100 120 150 100 10 10 +20 dB TYP MAX +2.0 +0.2 +2.2 V UNITS ANALOG INPUTS (AIN+, AIN-) (bypass to GND with 0.1µF or greater capacitors) AIN Input Voltage Range (Note 5) AIN Absolute Input Voltage Range to GND MAX1497/MAX1499 dB dB nA pF nA EXTERNAL REFERENCE (INTREF bit = 0) (bypass REF+ and REF- to GND with 0.1µF or greater capacitors) REF Input Voltage Absolute REF+, REF- Input Voltage to GND dB dB nA _______________________________________________________________________________________ 3 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = VDD = +2.7V to +5.25V, GND = 0, GLED = 0, VLED = +2.7V to +5.25V, VREF+ - VREF- = 2.048V (external reference) CREF+ = CREF- = 0.1µF, CVNEG = 0.1µF. Internal clock mode, unless otherwise noted. All specifications are at TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER Input Capacitance Average Dynamic Input Current CHARGE PUMP Output Voltage Input Current VNEG IIN CVNEG = 0.1µF VIN = 0 or DVDD = VDD MAX1499 Input Low Voltage VINL MAX1497 MAX1499 Input High Voltage VINH MAX1497 Input Hysteresis DIGITAL OUTPUTS (DOUT, EOC) Output Low Voltage VOL ISINK = 1mA ISOURCE = 200µA, MAX1499 Output High Voltage VOH ISOURCE = 200µA, MAX1497 Tri-State Leakage Current Tri-State Output Capacitance POWER SUPPLY (Note 10) VDD Voltage AVDD Voltage DVDD Voltage Power-Supply Rejection VDD Power-Supply Rejection AVDD Power-Supply Rejection DVDD VDD Current (Notes 8, 9) VDD AVDD DVDD PSRR PSRRA PSRRD IVDD MAX1497 MAX1499 MAX1499 (Note 7) (Note 7) (Note 7) VDD = 5.25V VDD = 3.3V Standby mode AVDD = 5.25V AVDD Current (Notes 8, 9) IAVDD AVDD = 3.3V Standby mode 2.70 2.70 2.70 80 80 100 664 618 268 744 663 325 640 600 305 µA µA 5.25 5.25 5.25 V V V dB dB dB IL COUT DOUT only DOUT only 0.8 x DVDD 0.8 x VDD -1 15 +1 µA pF 0.4 V VHYS DVDD = VDD = 3.0V 0.7 x DVDD 0.7 x VDD 200 mV -2.60 -10 -2.42 -2.30 +10 0.3 x DVDD 0.3 x VDD V µA DIGITAL INPUTS (SCLK, DIN, CS, CLK) (Note 6) -20 SYMBOL CONDITIONS MIN TYP 10 +20 MAX UNITS pF nA V V V 4 _______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = VDD = +2.7V to +5.25V, GND = 0, GLED = 0, VLED = +2.7V to +5.25V, VREF+ - VREF- = 2.048V (external reference) CREF+ = CREF- = 0.1µF, CVNEG = 0.1µF. Internal clock mode, unless otherwise noted. All specifications are at TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER DVDD Current (Notes 8, 9) LED Drivers Bias Current LED DRIVERS (Table 6) LED Supply Voltage LED Shutdown Supply Current LED Supply Current Display Scan Rate Segment Current Slew Rate DIG_ Voltage Low Segment Drive Source Current Matching Segment Drive Source Current Interdigit Blanking Time VLED ISHDN ILED fOSC ∆ISEG/∆t VDIG ∆ISEG ISEG VLED - VSEG = 0.6V, RISET = 25kΩ 16 IDIG_ = 176mA LED driver shutdown mode Seven segments and decimal point on, RISET = 25kΩ MAX1499 MAX1497 176 512 640 25 0.178 ±3 20 4 0.300 ±10 25.5 2.70 5.25 10 V µA mA Hz mA/µs V % mA µs SYMBOL DVDD = 5V IDVDD DVDD = 3.3V Standby mode From AVDD or VDD 120 CONDITIONS MIN TYP MAX 320 180 20 µA µA UNITS MAX1497/MAX1499 _______________________________________________________________________________________ 5 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 TIMING CHARACTERISTICS (Notes 11, 12, Figure 8) (AVDD = DVDD = VDD = +2.7V to +5.25V, GND = 0, GLED = 0, VLED = +2.7V to +5.25V, VREF+ - VREF- = 2.048V (external reference) CREF+ = CREF- = 0.1µF, CVNEG = 0.1µF. Internal clock mode, unless otherwise noted. All specifications are at TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SCLK Operating Frequency SCLK Pulse-Width High SCLK Pulse-Width Low DIN to SCLK Setup DIN to SCLK Hold CS Fall to SCLK Rise Setup SCLK Rise to CS Rise Hold SCLK Fall to DOUT Valid CS Rise to DOUT Disable CS Fall to DOUT Enable SYMBOL fSCLK tCH tCL tDS tDH tCSS tCSH tDO tTR tDV CLOAD = 50pF, Figures 13, 14 CLOAD = 50pF, Figures 13, 14 CLOAD = 50pF, Figures 13, 14 CONDITIONS MIN 0 100 100 50 0 50 0 120 120 120 TYP MAX 4.2 UNITS MHz ns ns ns ns ns ns ns ns ns Note 1: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after nulling the gain error and offset error. Note 2: Offset calibrated. See OFFSET_CAL1 and OFFSET_CAL2 (MAX1499 only) in the On-Chip Registers section. Note 3: Offset nulled. Note 4: Offset drift error is eliminated by recalibration at the new temperature. Note 5: The input voltage range for the analog inputs is given with respect to the voltage on the negative input of the differential pair. Note 6: VAIN+ or VAIN- = -2.2V to +2.2V. VREF+ or VREF- = -2.2V to +2.2V. All input structures are identical. Production tested on AIN+ and REF+ only. Note 7: Measured at DC by changing the power-supply voltage from 2.7V to 5.25V and measuring the effect on the conversion error with external reference. PSRR at 50Hz and 60Hz exceeds 120dB with filter notches at 50Hz and 60Hz (Figure 2). Note 8: CLK and SCLK are disabled. Note 9: LED drivers are disabled. Note 10: Power-supply currents are measured with all digital inputs at either GND, DVDD, or VDD and with the device in internal-clock mode. Note 11: All input signals are specified with tRISE = tFALL = 5ns (10% to 90% of DVDD) and are timed from a voltage level of 50% of DVDD, unless otherwise noted. Note 12: See the serial-interface timing diagrams. 6 _______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 Typical Operating Characteristics (AVDD = DVDD = VDD = +2.7V to +5.25V, VLED = +2.7V to +5.25V, GND = 0, GLED = 0, external reference mode, REF+ = 2.048V, REF- = GND, CREF+ = CREF- = 0.1µF, RANGE bit = 1, internal clock mode, CVNEG = 0.1µF. TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX1499) MAX1497/99 toc01 SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX1497) MAX1497/99 toc02 SUPPLY CURRENT vs. TEMPERATURE (MAX1499) MAX1497/99 toc03 700 600 SUPPLY CURRENT (µA) 500 400 300 200 100 0 2.75 3.25 3.75 4.25 4.75 DIGITAL SUPPLY ANALOG SUPPLY 700 650 SUPPLY CURRENT (µA) 600 550 500 450 400 700 600 SUPPLY CURRENT (µA) ANALOG SUPPLY 500 400 300 200 100 0 DIGITAL SUPPLY 5.25 2.70 3.21 3.72 4.23 4.74 5.25 0 10 20 30 40 50 60 70 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) TEMPERATURE (°C) SUPPLY CURRENT vs. TEMPERATURE (MAX1497) MAX1497/99 toc04 SHUTDOWN CURRENT vs. TEMPERATURE (MAX1499) MAX1497/99 toc05 SHUTDOWN CURRENT vs. TEMPERATURE (MAX1497) MAX1497/99 toc06 700 690 680 SUPPLY CURRENT (µA) 670 660 650 640 630 620 610 600 -40 -15 10 35 60 300 250 SHUTDOWN CURRENT (µA) 200 150 100 50 DIGITAL SUPPLY 0 ANALOG SUPPLY 350 300 SHUTDOWN CURRENT (µA) 250 200 150 100 50 0 85 0 10 20 30 40 50 60 70 -40 -15 10 35 60 85 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) SHUTDOWN CURRENT vs. SUPPLY VOLTAGE (MAX1499) MAX1497/99 toc07 SHUTDOWN CURRENT vs. SUPPLY VOLTAGE (MAX1497) MAX1497/99 toc08 MAX1499 OFFSET ERROR vs. SUPPLY VOLTAGE MAX1497/99 toc09 300 250 SHUTDOWN CURRENT (µA) 200 150 100 50 DIGITAL SUPPLY 0 2.75 3.25 3.75 4.25 4.75 ANALOG SUPPLY 350 300 SHUTDOWN CURRENT (µA) 250 200 150 100 50 0 0.19 0.14 OFFSET ERROR (LSB) 0.09 0.04 -0.01 -0.06 -0.11 -0.16 5.25 2.70 3.21 3.72 4.23 4.74 5.25 2.75 3.25 3.75 4.25 4.75 5.25 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 7 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 Typical Operating Characteristics (continued) (AVDD = DVDD = VDD = +2.7V to +5.25V, VLED = +2.7V to +5.25V, GND = 0, GLED = 0, external reference mode, REF+ = 2.048V, REF- = GND, CREF+ = CREF- = 0.1µF, RANGE bit = 1, internal clock mode, CVNEG = 0.1µF. TA = +25°C, unless otherwise noted.) MAX1499 OFFSET ERROR vs. TEMPERATURE MAX1497/99 toc10 MAX1499 GAIN ERROR vs. SUPPLY VOLTAGE MAX1497/99 toc11 MAX1499 GAIN ERROR vs. TEMPERATURE -0.01 GAIN ERROR (% FULL SCALE) -0.02 -0.03 -0.04 -0.05 -0.06 -0.07 -0.08 -0.09 -0.10 MAX1497/99 toc12 0.6 0.5 OFFSET ERROR (LSB) 0.4 0.3 0.2 0.1 0 -0.1 -0.2 0 10 20 30 40 50 60 0.08 0.06 GAIN ERROR (% FULL SCALE) 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 0 70 2.75 3.25 3.75 4.25 4.75 5.25 0 10 20 30 40 50 60 70 TEMPERATURE (°C) SUPPLY VOLTAGE (V) TEMPERATURE (°C) MAX1499 (±200mV INPUT RANGE) INL vs. OUTPUT CODE MAX1497/99 toc13 MAX1499 (±2V INPUT RANGE) INL vs. OUTPUT CODE MAX1497/99 toc14 NOISE DISTRIBUTION MAX1497/99 toc15 1.0 1.0 25 0.5 INL (COUNTS) 0.5 INL (COUNTS) PERCENTAGE OF UNITS (%) 20 15 0 0 10 -0.5 -0.5 5 -1.0 -20,000 -10,000 0 OUTPUT CODE 10,000 20,000 -1.0 -20,000 0 -10,000 0 OUTPUT CODE 10,000 20,000 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 NOISE (LSB) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX1497/99 toc16 INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE MAX1497/99 toc17 DATA OUTPUT RATE vs. TEMPERATURE 5.08 DATA OUTPUT RATE (Hz) 5.06 5.04 5.02 5.00 4.98 4.96 4.94 4.92 MAX1497/99 toc18 2.054 2.053 REFERENCE VOLTAGE (V) 2.052 2.051 2.050 2.049 2.048 2.047 2.046 2.045 2.044 0 10 20 30 40 50 60 2.050 2.049 REFERENCE VOLTAGE (V) 2.048 2.047 2.046 2.045 2.044 5.10 4.90 2.75 3.25 3.75 4.25 4.75 5.25 -40 -15 10 35 60 85 SUPPLY VOLTAGE (V) TEMPERATURE (°C) 70 TEMPERATURE (°C) 8 _______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 Typical Operating Characteristics (continued) (AVDD = DVDD = VDD = +2.7V to +5.25V, VLED = +2.7V to +5.25V, GND = 0, GLED = 0, external reference mode, REF+ = 2.048V, REF- = GND, CREF+ = CREF- = 0.1µF, RANGE bit = 1, internal clock mode, CVNEG = 0.1µF. TA = +25°C, unless otherwise noted.) DATA OUTPUT RATE vs. SUPPLY VOLTAGE MAX1497/99 toc19 OFFSET ERROR vs. COMMON-MODE VOLTAGE MAX1497/99 toc20 VNEG STARTUP SCOPE SHOT MAX1497/99 toc21 5.020 5.015 DATA OUTPUT RATE (Hz) 5.010 5.005 5.000 4.995 4.990 4.985 4.980 2.70 3.21 3.72 4.23 4.74 0.20 0.15 OFFSET ERROR (LSB) 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 VDD 2V/div 1V/div VNEG 5.25 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 20ms/div SUPPLY VOLTAGE (V) COMMON-MODE VOLTAGE (V) CHARGE-PUMP OUTPUT VOLTAGE vs. ANALOG SUPPLY VOLTAGE MAX1497/99 toc22 SEGMENT CURRENT vs. SUPPLY VOLTAGE RISET = 25kΩ MAX1497/99 toc23 -2.40 30 25 SEGMENT CURRENT (µA) 20 15 10 5 0 -2.42 VNEG VOLTAGE (V) -2.44 -2.46 -2.48 -2.50 2.75 3.25 3.75 4.25 4.75 5.25 SUPPLY VOLTAGE (V) 2.70 3.21 3.72 4.23 4.74 5.25 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 9 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 Pin Description PIN MAX1497 1 2 MAX1499 31 32 NAME VNEG REFFUNCTION -2.5V Charge-Pump Voltage-Output. Connect a 0.1µF capacitor to GND. Negative Reference Voltage Input. For internal reference operation, connect REF- to GND. For external reference operation, bypass REF- to GND with a 0.1µF capacitor and set VREF- from -2.2V to +2.2V, provided VREF+ > VREF-. Positive Reference Voltage Input. For internal reference operation, connect a 4.7µF capacitor from REF+ to GND. For external reference operation, bypass REF+ to GND with a 0.1µF capacitor and set VREF+ from -2.2V to +2.2V, provided VREF+ > VREF-. Positive Analog Input. Positive side of fully differential analog input. Bypass AIN+ to GND with a 0.1µF or greater capacitor. Negative Analog Input. Negative side of fully differential analog input. Bypass AIN- to GND with a 0.1µF or greater capacitor. Segment Current Controller. Connect to ground through a resistor to set the segment current. See Table 6 for segment current selection. Ground Analog and Digital Circuit Supply Voltage. Connect VDD to a +2.7V to +5.25V power supply. Bypass VDD to GND with a 0.1µF and a 4.7µF capacitor. External Clock Input. When the EXTCLK register bit is set to one, CLK is the master clock input (frequency = 4.9152MHz) for the modulator and the filter. When the EXTCLK register bit is reset to zero, the internal clock is used. Connect CLK to GND or DVDD (MAX1499) or VDD (MAX1497) when the internal oscillator is used. Active-Low End-of-Conversion Logic Output. A logic low at EOC indicates that a new ADC result is available in the ADC result register. Active-Low Chip Select Input. Forcing CS low activates the serial interface. Serial Data Input. Data present at DIN is shifted into the internal registers in response to a rising edge at SCLK when CS is low. Serial Clock Input. Apply an external clock to SCLK to facilitate communication through the serial bus. SCLK may idle high or low. Serial Data Output. DOUT presets serial data in response to register queries. Data shifts out on the falling edge of SCLK. DOUT goes high impedance when CS is high. Digit 0 Driver Digit 1 Driver Ground for LED-Display Segment Driver Digit 2 Driver Digit 3 Driver Segment A Driver Segment B Driver Segment C Driver Segment D Driver Segment E Driver 3 1 REF+ 4 5 6 7 8 2 3 4 5 — AIN+ AINISET GND VDD 9 8 CLK 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 EOC CS DIN SCLK DOUT DIG0 DIG1 GLED DIG2 DIG3 SEGA SEGB SEGC SEGD SEGE 10 ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface Pin Description (continued) PIN MAX1497 25 26 27 28 — — — — MAX1499 25 26 27 28 6 7 19 29 NAME VLED SEGF SEGG SEGDP AVDD DVDD DIG4 LED_EN FUNCTION LED-Display Segment-Driver Supply. Connect to a +2.7V to +5.25V supply. Bypass with a 0.1µF capacitor to GLED. Segment F Driver Segment G Driver Segment DP Driver Analog Positive Supply Voltage. Connect AVDD to a +2.7V to +5.25V power supply. Bypass AVDD to GND with a 0.1µF capacitor. Digital Positive Supply Voltage. Connect DVDD to a +2.7V to +5.25V power supply. Bypass DVDD to GND with a 0.1µF capacitor. Digit 4 Driver Active-High LED Enable. The MAX1499 LED display driver turns off when LED_EN is driven to logic low. The MAX1499 LED display driver turns on when LED_EN is driven to logic high. Low-Battery Voltage Monitor. When the LOWBATT input voltage is lower than 2.048V, the LOWBATT bit in the status register is set to one. MAX1497/MAX1499 — 30 LOWBATT Detailed Description The MAX1497/MAX1499 low-power, highly integrated ADCs with LED drivers convert a ±2V differential input voltage (one count is equal to 100µV for the MAX1499 and 1mV for the MAX1497) with a sigma-delta ADC and output the result to an LED or µC. An additional ±200mV input range (one count is equal to 10µV for the MAX1499 and 100µV for the MAX1497) is available to measure small signals with increased resolution. The devices operate from a single 2.7V to 5.25V power supply and offer 3.5-digit (MAX1497) or 4.5-digit (MAX1499) conversion results. An internal 2.048V reference, internal charge pump, and a high-accuracy onchip oscillator eliminate external components. The MAX1497/MAX1499 interface with a µC using an SPI-/QSPI-/MICROWIRE-compatible serial interface. Data can either be sent directly to the display or to the µC first for processing before being displayed. The devices also feature on-chip buffers for the differential input signal and external reference inputs, allowing direct interface with high-impedance signal sources. In addition, they use continuous internal offsetcalibration and offer >100dB of 50Hz and 60Hz line noise rejection. Other features include data hold and peak detection, overrange and underrange detection. The MAX1499 also provides a low-battery monitor. Analog Input Protection Internal protection diodes limit the analog input range from VNEG to (AVDD + 0.3V) for the MAX1499, and from VNEG to (VDD to 0.3V) for the MAX1497. If the analog input exceeds this range, limit the input current to 10mA. Internal Analog Input/Reference Buffers The MAX1497/MAX1499 analog input/reference buffers allow the use of high-impedance signal sources. The input buffers’ common-mode input range allows the analog inputs and the reference to range from -2.2V to +2.2V. Modulator The MAX1497/MAX1499 perform analog-to-digital conversions using a single-bit, 3rd-order, sigma-delta modulator. The sigma-delta modulator converts the input signal into a digital pulse train whose average duty cycle represents the digitized signal information. The modulator quantizes the input signal at a much higher sample rate than the bandwidth of the input. The MAX1497/MAX1499 modulator provides 3rd-order frequency shaping of the quantization noise resulting from the single-bit quantizer. The modulator is fully differential for maximum signal-to-noise ratio and minimum susceptibility to power-supply noise. A single-bit data stream is then presented to the digital filter to remove the frequency-shaped quantization noise. ______________________________________________________________________________________ 11 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 AVDD DVDD SCLK DIN DOUT CS ISET VLED MAX1499 +2.5V SERIAL I/O AND CONTROL EOC SEG1 AIN+ ADC AININPUT BUFFERS REF+ BINARY-TOBCD CONVERTERS LED DRIVER SEGF SEGDP DIG0 DIG4 LED_EN GLED REF- OSCILLATOR CLOCK -2.5V 2.048V BANDGAP REFERENCE +2.5V CHARGE PUMP 2.048V -2.5V CLK TO CONTROL A = 1.22 GND VNEG LOWBATT Figure 1. MAX1499 Functional Diagram Digital Filtering The MAX1497/MAX1499 contain an on-chip digital lowpass filter that processes the data stream from the modulator using a SINC4 response:  sin(x)  4   x The SINC4 filter has a settling time of four output data periods (4 x 200ms). The MAX1497/MAX1499 have 25% overrange capability built into the modulator and digital filter. The digital filter is optimized for the fCLK equal to 4.9152MHz. Other clock frequencies can be used; however, 50Hz/60Hz noise rejection decreases. The frequency response of the SINC4 filter is calculated as follows:  1 (1 - Z -N )  4  H(z) =   N (1 - Z -1)    4  f   sin Nπ   fm    1 H(f) =   N    sin πf     fm     12 where N is the oversampling ratio, and fm = N x output data rate = 5Hz. Filter Characteristics Figure 2 shows the filter frequency response. The SINC4 characteristic -3dB cutoff frequency is 0.228 times the first notch frequency (5Hz). The oversampling ratio (OSR) for the MAX1497 is 128 and the OSR for the MAX1499 is 1024. The output data rate for the digital filter corresponds to the positioning of the first notch of the filter’s frequency response. The notches of the SINC4 filter are repeated at multiples of the first notch frequency. The SINC4 filter provides an attenuation of better than 100dB at these notches. For example, 50Hz is equal to 10 times the first notch frequency and 60Hz is equal to 12 times the first notch frequency. For large step changes at the input, allow a settling time of 800ms before valid data is read. Clock Modes Configure the MAX1497/MAX1499 to use either the internal oscillator or an externally applied clock to drive the modulator and filter. Set the EXTCLK bit in the control register to zero to put the device in internal-clock mode. Set the EXTCLK bit to one to put the device in ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 0 A A B F D C E DP D DIGIT 3 F G B C F E DP D DIGIT 2 A G B C F E DP D DIGIT 1 A G B C F E DP D DIGIT 0 A G B C DP -40 GAIN (dB) -80 G DIGIT 4 -120 Figure 3. Segment Connection for the MAX1499 (4.5 Digits) -160 -200 0 10 20 30 40 50 60 F A B D G DIGIT 3 C F E DP D DIGIT 2 A G B C F E DP D DIGIT 1 A G B C F E DP D DIGIT 0 A G B C DP FREQUENCY (Hz) Figure 2. Frequency Response of the SINC4 Filter (Notch at 60Hz) external-clock mode. When using the internal oscillator, connect CLK to GND or DVDD for the MAX1499, or connect CLK to V DD f or the MAX1497. The MAX1497/ MAX1499 ideally operate with a 4.9152MHz clock to achieve maximum rejection of 50Hz/60Hz commonmode, power-supply, and normal-mode noise. Internal-Clock Mode The MAX1497/MAX1499 contain an internal oscillator. The power-up condition for the MAX1497/MAX1499 is internal clock operation with the EXTCLK bit in the control register equal to zero. Using the internal oscillator saves board space by removing the need for an external clock source. External-Clock Mode For external clock operation, set the EXTCLK bit in the control register to one and drive CLK with a 4.9152MHz clock source for best 50Hz/60Hz rejection ratio. Other external clock frequencies allow for custom conversion rates. A 2.4576MHz clock signal reduces the conversion rate and the LED update rate by a factor of two while keeping good 50Hz/60Hz noise rejection. The MAX1497/MAX1499 operate with an external clock source of up to 5.05MHz. Figure 4. Segment Connection for the MAX1497 (3.5 Digits) Table 1. LED Priority Table SEG_SEL SPI/ADC HOLD 1 0 0 0 0 X 1 0 0 0 X X 1 0 0 PEAK X X X 1 0 DISPLAY VALUES FORM LED segment registers LED display register (user written) LED display register Peak register ADC result register X = Don’t care. LED Driver The MAX1499 has a 4.5-digit common-cathode display driver and the MAX1497 has a 3.5-digit common-cathode display driver. Figures 3 and 4 show the connection schemes for a standard seven-segment LED display. The LED update rate is 2.5Hz. The MAX1497/ MAX1499 automatically display the results of the ADC, if desired (Table 1). The MAX1497/MAX1499 also allow independent control of the LED driver through the serial interface, allowing for data processing of the ADC result before showing the result on the LED. Additionally, each LED segment can be individually controlled (see the LED segment-display register sections). Charge Pump The MAX1497/MAX1499 contain an internal charge pump to provide the negative supply voltage for the internal analog input/reference buffers. The bipolar input range of the analog input/reference buffers allows this device to accept negative inputs with high source impedances. Connect a 0.1µF capacitor from VNEG to GND. ______________________________________________________________________________________ 13 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 Table 2. Decimal-Point Control Table—MAX1499 DPON 0 0 0 0 1 1 1 1 DPSET1 0 0 1 1 0 0 1 1 DPSET2 0 1 0 1 0 1 0 1 DISPLAY OUTPUT 18888 18888 18888 18888 1888.8 188.88 18.888 1.8888 ZERO INPUT READING 0 0 0 0 0.0 0.00 0.000 0.0000 Table 3. Decimal-Point Control Table—MAX1497 DPON X X X X DPSET1 0 0 1 1 DPSET2 0 1 0 1 DISPLAY OUTPUT 188.8 18.88 1888 1.888 ZERO INPUT READING 0.0 0.00 0 0.000 X = Don’t care. Table 4. LED During Overrange and Underrange Conditions CONDITION Overrange Underrange MAX1497 1--MAX1499 1---- -1--- -1---- SEGDP SEGG SEGF SEGE SEGD SEGC SEGB SEGA A B C D E F G DP A B C D E F G DP Figure 5 shows a typical common-cathode configuration for two digits. In common-cathode configuration, the cathodes of all LEDs in a digit are connected together. Each segment driver of the MAX1497/ MAX1499 connects to its corresponding LEDs anodes. For example, segment driver SEGA connects to all LED segments designated as A. Similar configurations are followed for other segment drivers. The MAX1497/MAX1499 use a multiplexing scheme to drive one digit at a time. The scan rate is fast enough to make the digits appear to be lit. Figures 6 and 7 show data timing diagrams for the MAX1497/MAX1499 where T is the display scan period typically around 1/512Hz or 1.9531ms for the MAX1499 and 1/640Hz or 1.5625ms for the MAX1497. TON in Figures 6 and 7 denotes the amount of time each digit is on and is calculated as follows: T 1.95312ms = = 390.60µs (MAX1499) 5 5 T 1.5625ms = = 390.60µs (MAX1497) 4 4 TON = DIGIT 1 A F E D G B C DP F E DIGIT 2 A G B C DP D TON = Figure 5. Two-Digit Common-Cathode Configuration 14 The MAX1497/MAX1499 allow for full decimal-point control and feature leading-zero suppression. Use the DPON, DPSET1, and DPSET2 bits in the control register to set the value of the decimal point (Tables 2 and 3). The MAX1497/MAX1499 overrange and underrange display is shown in Table 4. ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 TON DIGIT 4 (MSD) DIGIT 3 DIGIT 2 DIGIT 1 DIGIT 0 (LSD) T DATA 4 MSD 3 2 1 0 LSD 4 3 2 1 0 4 Figure 6. LED Voltage Waveform—MAX1499 TON DIGIT 3 (MSD) DIGIT 2 DIGIT 1 DIGIT 0 (LSD) T DATA 3 MSD 2 1 0 LSD 3 2 1 0 3 2 1 Figure 7. LED Voltage Waveform—MAX1497 Leading-Zero Suppression The MAX1497/MAX1499 include a leading-zero suppression circuitry to turn off unnecessary zeros. For example, when DPSET1 and DPSET2 = [0,0], 0.0 is displayed instead of 000.0. This feature saves a substantial amount of power from being wasted. The MAX1497/MAX1499 accept either an external reference or an internal reference. The INTREF bit selects the reference mode (see the C ontrol Register (Read/Write) section). For internal reference operation, set the INTREF bit to one, connect REF- to GND, and bypass REF+ to GND with a 4.7µF capacitor. The internal reference provides a nominal 2.048V source between REF+ and GND. The internal reference temperature coefficient is typically 40ppm/°C. The default power-on state sets the MAX1497/ MAX1499 to use the external reference with the INTREF bit cleared to zero. The external reference inputs, REF+ and REF-, are fully differential. For a valid external reference input, VREF+ must be greater than VREF-. Bypass REF+ and REF- with a 0.1µF or greater capacitor to GND in external reference mode. Figure 16 shows the MAX1497/MAX1499 operating with an external single-ended reference. In this mode, REFis connected to GND and REF+ is driven with an external 2.048V reference. Bypass REF+ to GND with a 0.47µF capacitor. Interdigit Blanking The MAX1497/MAX1499 also include an interdigit blanking circuitry. Without this feature, it is possible to see a faint digit next to a digit that is completely on. The interdigit blanking circuitry prevents bleeding over into the next digit for a short period of time. The typical interdigit blanking time is 4µs. Reference The MAX1497/MAX1499 reference sets the full-scale range of the ADC transfer function. With a nominal 2.048V reference, the ADC full-scale range is ±2V with the RANGE bit equal to zero. With the RANGE bit set to one, the full-scale range is ±200mV. A decreased reference voltage decreases full-scale range (see the Transfer Functions section). ______________________________________________________________________________________ 15 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 Figure 15 shows the MAX1497/MAX1499 operating with an external differential reference. In this mode, REF- is connected to the top of the strain gauge and REF+ is connected to the midpoint of the resistor-divider of the supply. A logic high on CS tri-states DOUT and causes the MAX1497/MAX1499 to ignore any signals on SCLK and DIN. To clock data in or out of the internal shift register, drive CS low. SCLK synchronizes the data transfer. The rising edge of SCLK clocks DIN into the shift register, and the falling edge of SCLK clocks DOUT out of the shift register. DIN and DOUT are transferred MSB first (data is left justified). Figures 8–12 show the detailed serial interface timing diagrams for the 8- and 16-bit read/write operations. All communication with the MAX1497/MAX1499 begins with a command byte on DIN, where the first logic one on DIN is recognized as the START bit (MSB) for the command byte. The following seven clock cycles load the command into a shift register. These 7 bits specify which of the registers are accessed next, and whether a read or write operation takes place. Transitions on the serial clock after the command byte transfer, cause a write or read from the device until the correct number of Applications Information Serial Interface The SPI/QSPI/MICROWIRE serial interface consists of a chip select (CS), a serial clock (SCLK), a data in (DIN), a data out (DOUT), and an asynchronous EOC output. EOC provides an asynchronous end-of-conversion signal with a period of 200ms (fCLK = 4.9152MHz). The MAX1497 updates the data register when EOC goes high. Data is valid in the ADC result registers when EOC returns low. The serial interface provides access to 12 on-chip registers, allowing control to all the power modes and functional blocks. Table 5 lists the address and read/write accessibility of all the registers. CS tCSS tCL tCSH SCLK tCSH tCH tDS tDH DIN tDV DOUT tDO tTR Figure 8. Detailed Timing Diagram CS SCLK DIN 1 0 RS4 RS3 RS2 RS1 RS0 CONTROL BYTE x D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE DOUT Figure 9. Serial-Interface, 16-Bit, Write Timing Diagram 16 ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 CS SCLK DIN 1 0 RS4 RS3 RS2 RS1 RS0 CONTROL BYTE x D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE DOUT Figure 10. Serial-Interface, 8-Bit, Write Timing Diagram CS SCLK DIN 1 1 RS4 RS3 RS2 RS1 RS0 CONTROL BYTE x DATA BYTE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DOUT Figure 11. Serial-Interface, 16-Bit, Read Timing Diagram CS SCLK DIN 1 1 RS4 RS3 RS2 RS1 RS0 CONTROL BYTE x DATA BYTE D7 D6 D5 D4 D3 D2 D1 D0 DOUT Figure 12. Serial-Interface, 8-Bit, Read Timing Diagram ______________________________________________________________________________________ 17 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 Table 5. Register Address Table REGISTER N0. 1 2 3 4 5 6 7 8 9 10 11 12 — ADDRESS RS [4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 10100 All other addresses Status register Control register Overrange register Underrange register LED segment-display register 1 LED segment-display register 2 LED segment-display register 3 ADC custom offset register ADC result register 1 (16 MSBs) LED data register Peak register ADC result register 2 (4 LSBs) Reserved NAME WIDTH 8 16 16 16 16 16 8 16 16 16 16 8 — ACCESS Read only R/W R/W R/W R/W R/W R/W R/W Read only R/W Read only Read only — DVDD 6kΩ DOUT 6kΩ GND A) VOH TO HIGH-Z CLOAD 50pF DOUT DOUT DVDD 6kΩ CLOAD 50pF DOUT CLOAD 50pF GND B) HIGH-Z TO VOL AND VOH TO VOL CLOAD 50pF GND B) VOL TO HIGH-Z 6kΩ GND B) HIGH-Z TO VOH AND VOL TO VOH Figure 13. Load Circuits for Disable Time Figure 14. Load Circuits for Enable Time bits have been transferred (8 or 16). Once this has occurred, the MAX1497/MAX1499 wait for the next command byte. CS must not go high between data transfers. If CS is toggled before the end of a write or read operation, the device mode may be unknown. Clock in 32 zeros to clear the device state and reset the interface so it is ready to receive a new command byte. On-Chip Registers The MAX1497/MAX1499 contain 12 on-chip registers. These registers configure the various functions of the device and allow independent reading of the ADC results and writing to the LED display. Table 5 lists the address and size of each register. The first of these registers is the status register. The 8bit status register contains the status flags for the ADC. The second register is the 16-bit control register. This register sets the LED display controls, range modes, power-down modes, offset calibration, and the reset register function (CLR). The third register is the 16-bit overrange register, which sets the overrange limit of the analog input. The fourth register is the 16-bit underrange register, which sets the underrange limit of the analog input. Registers 5 through 7 contain the display data for the individual segments of the LED. The eighth register contains the custom offset value. The ninth register contains the 16 MSBs of the ADC conversion result. The 10th register contains the LED data. The 11th register contains the peak analog input value. The last register contains the lower four LSBs of the 20-bit ADC conversion result. 18 ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 Control and Status Registers Command Byte (Write Only) MSB Bit 7 START(1) Bit 6 R/W Bit 5 RS4 Bit 4 RS3 Bit 3 RS2 Bit 2 RS1 Bit 1 RS0 X LSB Bit 0 START: Start bit. The first 1 clocked into the MAX1497/ MAX1499 is the first bit of the command byte. (R/W): Read/Write. Set this bit to 1 to read from the specified register. Set this bit to zero to write to the selected register. Note that certain registers are read Status Register (Read Only) MSB SIGN OVER UNDER LOW_BATT only. Write commands to a read-only register are ignored. (RS4–RS0): Register address bits. RS4 to RS0 specify which register is accessed. X: Don’t care. LSB DRDY 0 0 0 Default values: 00h This register contains the status of the conversion results. SIGN: Latched negative-polarity indicator. Latches high when the result is negative. Clears by reading the status register, unless the condition remains true. OVER: Overrange bit. Latches high if an overrange condition occurs (the ADC result is larger than the value in the overrange register). Clears by reading the status register, unless the condition remains true. UNDER: Underrange bit. Latches high if an underrange condition occurs (the ADC result is less than the Control Register (Read/Write) MSB Bit 15 SPI/ADC Bit 7 HOLD Bit 14 EXTCLK Bit 6 PEAK Bit 13 INTREF Bit 5 RANGE Bit 12 DPON Bit 4 CLR value in the underrange register). Clears by reading the status register, unless the condition remains true. LOW_BATT: Low-battery bit. Latches high if the voltage at the LOWBATT is lower than 2.048V (typ). Clears by reading the status register, unless the condition remains true. For the MAX1497, LOWBATT is not used and the LOWBATT bit always returns to zero. DRDY: Data ready bit. Latches high to indicate a completed conversion result with valid data. Read the ADC result register to clear this bit. Bit 11 DPSET2 Bit 3 SEG_SEL Bit 10 DPSET1 Bit 2 OFFSET_CAL1 Bit 9 PD_DIG Bit 1 OFFSET_ CAL2 Bit 8 PD_ANA LSB Bit 0 ENABLE Default values: 0001h This register is the primary control register for the MAX1497/MAX1499. It is a 16-bit read/write register. It is used to indicate the desired clock and reference source. It sets the LED display controls, range modes, power-down modes, offset calibration, and the reset register function (CLR). ENABLE: (default = 1) LED driver enable bit. When set to 1, the MAX1497/MAX1499 enables the LED display drivers. A 0 in this location disables the LED display drivers. OFFSET_CAL2: (default = 0) Enhanced offset-calibration start bit (MAX1499, RANGE = 1). To achieve the lowest possible offset in the ±200mV input range, perform an enhanced offset calibration by setting this bit to 19 ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 1. The calibration takes about nine cycles (1800ms). After the calibration completes, set this bit to zero to resume ADC conversions. OFFSET_CAL1: (default = 0) Automatic offset calibration enable bit. When set to 1, the MAX1497/ MAX1499 disable automatic offset calibration. When this bit is set to zero, automatic offset calibration is enabled. SEG_SEL: (default = 0) SEG_SEL segment selection bit. When set to 1, the LED segment drivers use the LED segment registers to display individual segments that can form letters or numbers or other information on the display. The LED data register is not displayed. Send the data first to the LED segment-display registers and then set this bit high. CLR: (default = 0) Clear all registers bit. When set to 1, all registers reset to their power-on reset states after CS makes a low-to-high transition. RANGE: (default = 0) Input range select bit. When set to zero, the input voltage range is ±2V. When set to 1, the input voltage range is ±200mV. PEAK: (default = 0) Peak bit. When set to 1 (and the HOLD bit is set to zero), the LED shows the result stored in the peak register (see Table 6). HOLD: (default = 0) Hold bit. When set to 1, the LED register does not update from the ADC conversion results and holds the last result on the LED. The MAX1497/MAX1499 continue to perform conversions during HOLD (Table 1). PD_ANA: (default = 0) Power-down analog select bit. When set to 1, the analog circuits (analog modulator and ADC input buffers) go into the power-down mode. When set to zero, the device is in full power-up mode. Overrange Register (Read/Write) MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 PD_DIG: (default = 0) Power-down digital select bit. When set to 1, the digital circuits (digital filter and LED drivers) go into power-down mode. This also resets the values of the internal SRAM in the digital filter to zeros. When set to zero, the device returns to full power-up mode. When powering down PD_DIG, power down the LED segment drivers by clearing the ENABLE bit to zero. DPSET[2:1]: (default = 00) Decimal-point selection bits (Table 2 and 3). DPON: (default = 0) Decimal-point enable bit (Tables 2 and 3). INTREF: (default = 0) Reference select bit. For internal reference operation, set INTREF to 1. For external reference operation, set INTREF to zero. EXTCLK: (default = 0) External clock select bit. The EXTCLK bit controls selection of the internal clock or an external clock source. A 1 in this location selects the signal at the CLK input as the clock source. A zero in this location selects and powers up the internal clock oscillator. SPI/ADC: (default = 0) Display select bit. The SPI/ADC bit controls selection of the data fed into LED data register. A 1 in this location selects SPI/QSPI/ MICROWIRE data (user writes this data to the LED data register). A zero in this location selects the ADC result register data, unless hold or peak functions are active (Table 1). Note: When changing any one of the following control bits: O FFSET_CAL1 , RANGE, PD_ANA, PD_DIG, INTREF, and EXTCLK, wait 800ms before reading the ADC results. Default values: 7CF0h (for 3.5-digit, +1999) 4E1Fh (for 4.5-digit, +19,999) The overrange register is a 16-bit read/write register (D15 is the MSB). When the conversion result exceeds the value in the overrange register, the OVER bit in the status register latches to 1. The LED shows a 1 followed by four dashes for the MAX1499 or a 1 followed by three dashes for the MAX1497 (Table 4). The data is represented in two’s complement format. 20 ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface Underrange Register (Read/Write) MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 MAX1497/MAX1499 Default values: 8300h (for 3.5-digit, -2000) B1E0h (for 4.5-digit, -20,000) The underrange data register is 16-bit read/write register (D15 is the MSB). When the conversion result falls below the value in the underrange register, the UNDR bit in the status register sets to 1. The LED shows a -1 followed by four dashes for the MAX1499 or a -1 followed by three dashes for the MAX1497 (Table 4). The data is represented in two’s complement format. Default values: 0000h LED Segment-Display Register 1 (Read/Write) MSB Bit 15 A1 Bit 7 C0 Bit 14 G1 Bit 6 A0 Bit 13 D1 Bit 5 G0 Bit 1 F1 Bit 4 D0 Bit 11 E1 Bit 3 F0 Bit 10 DP2 Bit 2 E0 Bit 9 X Bit 1 DP1 Bit 8 B0 LSB Bit 0 0 LED segment-display register 1 is a 16-bit read/write register. When the LED bit (in the control register) is set to 1, the MAX1497/MAX1499 provide direct access to individual LED segments. The bits in the LED segmentdisplay register determine if a segment is on or off. Write a zero to turn on a segment and a 1 to turn off a segment. DP1: Segment DP driver bit of digit 1. The default value turns on the LED segment. E0: Segment E driver bit of digit 0. The default value turns on the LED segment. F0: Segment F driver bit of digit 0. The default value turns on the LED segment. D0: Segment D driver bit of digit 0. The default value turns on the LED segment. G0: Segment G driver bit of digit 0. The default value turns on the LED segment. A0: Segment A driver bit of digit 0. The default value turns on the LED segment. C0: Segment C driver bit of digit 0. The default value turns on the LED segment. B0: Segment B driver bit of digit 0. The default value turns on the LED segment. X: Don’t care. DP2: Segment DP driver bit of digit 2. The default value turns on the LED segment. E1: Segment E driver bit of digit 1. The default value turns on the LED segment. F1: Segment F driver bit of digit 1. The default value turns on the LED segment. D1: Segment D driver bit of digit 1. The default value turns on the LED segment. G1: Segment G driver bit of digit 1. The default value turns on the LED segment. A1: Segment A driver bit of digit 1. The default value turns on the LED segment. ______________________________________________________________________________________ 21 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 LED Segment-Display Register 2 (Read/Write) MSB Bit 15 F3 Bit 7 D2 Bit 14 E3 Bit 6 F2 Bit 13 DP4 Bit 5 E2 Bit 1 MINUS Bit 4 DP3 Bit 11 B2 Bit 3 X Bit 10 C2 Bit 2 B1 Bit 9 A2 Bit 1 C1 Bit 8 G2 LSB Bit 0 0 Default values: 0000h LED segment-display register 2 is a 16-bit read/write register. When the SEG_SEL bit (in the control register) is set to 1, the MAX1497/MAX1499 provide direct access to individual LED segments. The bits in the LED segment-display register determine if a segment is on or off. Write a zero to turn on a segment and a 1 to turn off a segment. C1: Segment C driver bit of digit 1. The default value turns on the LED segment. B1: Segment B driver bit of digit 1. The default value turns on the LED segment. MINUS: Segment minus driver bit. The default value turns on the LED minus segment. Setting this bit to 1 enables the plus sign on the LED display. DP3: Segment DP driver bit of digit 3. The default value turns on the LED segment. E2: Segment E driver bit of digit 2. The default value turns on the LED segment. F2: Segment F driver bit of digit 2. The default value turns on the LED segment. D2: Segment D driver bit of digit 2. The default value turns on the LED segment. G2: Segment G driver bit of digit 2. The default value turns on the LED segment. A2: Segment A driver bit of digit 2. The default value turns on the LED segment. C2: Segment C driver bit of digit 2. The default value turns on the LED segment. B2: Segment B driver bit of digit 2. The default value turns on the LED segment. DP4: Segment DP driver bit of digit 4. The default value turns on the LED segment (MAX1499 only). E3: Segment E driver bit of digit 3. The default value turns on the LED segment (MAX1499 only). F3: Segment F driver bit of digit 3. The default value turns on the LED segment (MAX1499 only). LED Segment-Display Register 3 (Read/Write) MSB X X BC_ B3 C3 A3 G3 D3 LSB Default values: 00h LED segment-display register 3 is an 8-bit read/write register. When the SEG_SEL bit (in the control register) is set to 1, the MAX1497/MAX1499 provide direct access to individual LED segments. The bits in the LED segment-display register determine if a segment is on or off. Write a zero to turn on a segment and a 1 to turn off a segment. D3: Segment D driver bit of digit 3. The default value turns on the LED segment (MAX1499 only). G3: Segment G driver bit of digit 3. The default value turns on the LED segment (MAX1499 only). A3: Segment A driver bit of digit 3. The default value turns on the LED segment (MAX1499 only). C3: Segment C driver bit of digit 3. The default value turns on the LED segment (MAX1499 only). B3: Segment B driver bit of digit 3. The default value turns on the LED segment (MAX1499 only). BC_: Segment B and C driver bit of digit 3 (3.5 digits) or Digit 4 (4.5 digits). The default value turns on the LED segment. X: Don’t care. 22 ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface ADC Custom Offset-Calibration Register (Read/Write) MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 MAX1497/MAX1499 Default values: 0000h In addition to automatic offset calibration, the MAX1497/MAX1499 offer a user-defined custom offset 16-bit read/write register. The final result of the ADC conversion is the input after autocalibration minus the value in the custom offset. The custom offset value is stored in this register. D15 is the MSB. The data is represented in two’s complement format. ADC Result Register 1 (Read Only) MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 LSB (MAX1497) D4 D3 D2 LSB (MAX1499) D1 D0 Default values: 0000h ADC result register 1 is a 16-bit read-only register. This register stores the 16 MSBs of the ADC result. The data is represented in two’s complement format. For the MAX1499, the data is 16-bit and D15 is the MSB. For the MAX1497, the data is 12-bit, D15 is the MSB, and D4 is the LSB. ADC Result Register 2 (Read Only) MSB D3 D2 D1 LSB D0 0 0 0 0 Default values: 00h ADC result register 2 is an 8-bit read-only register. This register stores the 4 LSBs of the ADC result. Use this result with the result in ADC result-register 1 to form a 20-bit two’s complement conversion result. LED Data Register (Read/Write) MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 LSB (MAX1497) D4 D3 D2 LSB (MAX1499) D1 D0 Default values: 0000h The LED data register is a 16-bit read/write register. This register updates from ADC result register 1 or from the serial interface by selecting the SPI/ADC bit in the control register. The data is represented in two’s complement format. For the MAX1499, the data is 16-bit and D15 is the MSB. For the MAX1497, the data is 12-bit, D15 is the MSB, and D4 is the LSB, followed by 4 trailing sub-bits. ______________________________________________________________________________________ 23 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 PEAK Register (Read Only) MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 LSB (MAX1497) D4 D3 D2 LSB (MAX1499) D1 D0 Default values: B1E0h The peak data register is a 16-bit read only register. Set the PEAK bit to 1 to enable the PEAK function. This register stores the peak value of the ADC conversion result. First, the current ADC result is saved to the PEAK register, then the new ADC conversion result is compared to this value. If the new value is larger than the value in the peak register, the MAX1497/MAX1499 save the new value to the peak register. If the new value is less than the value in the peak register, the value in the peak register remains unchanged. Set the PEAK bit to zero to clear the value in the PEAK register. The data is represented in two’s complement format. For the MAX1499, the data is 16-bit and D15 is the MSB. For the MAX1497, the data is 12-bit, D15 is the MSB, and D4 is the LSB followed by 4 trailing sub-bits. 24 ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 ANALOG SUPPLY FERRITE BEAD 0.1µF 4.7µF AVDD REF+ 0.1µF RREF REF0.1µF ACTIVE GAUGE R AIN+ 0.1µF DUMMY GAUGE R GND 0.47µF 0.1µF AINSCLK DIN DOUT CS EOC GND +5V 0.1µF DVDD THERMOCOUPLE JUNCTION AIN+ TEMP SENSOR 0.1µF 4.7µF MAX1497 MAX1499 SPI µC MAX1497 MAX1499 AIN- +2.048V MAX6062 REF+ REF- Figure 15. Strain-Gauge Application with the MAX1497/MAX1499 Figure 16. Thermocouple Application with the MAX1497/MAX1499 Power-On Reset At power-on, the serial interface, logic LED drivers, digital filter, and modulator circuits reset. The registers return to their default values. Allow time for the reference to settle before starting calibration. powers down the analog modulator and ADC input buffers. Writing a zero to the ENABLE bit in the control word, powers down the LED drivers. Peak The MAX1497/MAX1499 feature peak detection circuitry. When activated (PEAK bit = 1), the devices display only the highest voltage measured to the LED. Offset Calibration The MAX1497/MAX1499 offer on-chip offset calibration. The device offset calibrates during every conversion when the OFFSET_CAL1 bit is zero in the control register. Enhanced offset calibration is only needed in the MAX1499 when the RANGE bit = 1. It is performed on demand by setting the OFFSET_CAL2 bit to 1. Hold The MAX1497/MAX1499 feature data-hold circuitry. When activated (HOLD bit = 1), the device displays the current reading on the LED. Enhanced Offset Calibration Enhanced offset calibration is a more accurate calibration method that is needed in the case of the ±200mV range and 4.5-digit resolution. The MAX1499 performs the enhanced calibration on demand by setting the OFFSET_CAL2 bit to 1. Low Battery The MAX1499 features a low-battery detection input. When the voltage at LOWBATT drops below 2.048V (typ), the LOWBATT bit of the status register goes high. Strain-Gauge Measurement Connect the differential inputs of the MAX1497/MAX1499 to the bridge network of the strain gauge. In Figure 15, the analog supply voltage powers the bridge network and the MAX1497/MAX1499 along with the reference voltage. The MAX1497/MAX1499 handle an analog input voltage range of ±200mV and ±2V full scale. The analog/reference inputs of the parts allow the analog input range to have an absolute value of anywhere between -2.2V and +2.2V. Power-Down Modes The MAX1497/MAX1499 feature independent powerdown control of the analog and digital LED drivers circuitry. Writing a 1 to the PD_DIG and PD_ANA bits in the control word, powers down the analog and digital circuitry, reducing the supply current to 268µA (typ). PD_DIG powers down the digital filter, while PD_ANA ______________________________________________________________________________________ 25 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 LED 1---19,999 ADC RESULT LED 1---19,999 ADC RESULT >4E1Fh 4E1Fh 4E1Fh 4E1Fh 2 1 0 -0 -1 -2 0002h 0001h 0000h FFFFh FFFEh FFFDh B1E0h 1.5V. Computing Power Dissipation The following can be used to compute power dissipation: PD = (VLED x IVLED ) + (VLED - VDIODE) (DUTY x ISEG x N) + VSUPPLY x ISUPPLY VLED = LED driver supply voltage IVLED = VLED bias current VDIODE = LED forward voltage DUTY = segment ON time during each digit ON time ISEG = segment current set by RISET N = number of segments driven (worst case is eight) VSUPPLY = supply voltage of the part ISUPPLY = supply current from VDD for the MAX1497 or AVDD + DVDD for the MAX1499 28 ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface Definitions INL Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line is either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. INL for the MAX1497/ MAX1499 is measured using the endpoint method. Gain Error Gain error is the amount of deviation between the measured full-scale transition point and the ideal full-scale transition point. MAX1497/MAX1499 Common-Mode Rejection Common-mode rejection (CMR) is the ability of a device to reject a signal that is common to both input terminals. The common-mode signal can be either an AC or a DC signal or a combination of the two. CMR is often expressed in decibels. DNL Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of ±1 LSB. A DNL error specification of less than ±1 LSB guarantees no missing codes and a monotonic transfer function. Normal-Mode 50Hz and 60Hz Rejection (Simultaneously) Normal-mode rejection is a measure of how much output changes when a 50Hz and a 60Hz signal is injected into only one of the differential inputs. The MAX1497/ MAX1499 sigma-delta converter uses its internal digital filter to provide normal-mode rejection to both 50Hz and 60Hz power-line frequencies simultaneously. Rollover Error Rollover error is defined as the absolute-value difference between a near positive full-scale reading and near negative full-scale reading. Rollover error is tested by applying a full-scale positive voltage, swapping AIN+ and AIN-, and adding the results. Power-Supply Rejection Ratio Power-supply rejection ratio (PSRR) is the ratio of the input supply change (in volts) to the change in the converter output (in volts). It is typically measured in decibels. Zero Input Reading Ideally, with AIN+ connected to AIN-, the MAX1497/ MAX1499 digital ADC result is 0000h. Zero input reading is the measured deviation from the ideal 0x0000 and the actual measured point. Pin Configurations LED_EN SEGDP TOP VIEW VNEG 1 REF- 2 REF+ 3 AIN+ 4 AIN- 5 ISET 6 GND 7 VDD 8 CLK 9 EOC 10 CS 11 DIN 12 SCLK 13 DOUT 14 28 SEGDP 27 SEGG LOWBATT TOP VIEW VNEG REF- SEGG 32 REF+ 1 2 3 4 5 6 7 8 9 EOC 31 30 29 28 27 26 VLED 25 24 SEGE 23 SEGD 22 SEGC 21 SEGB 20 SEGA 19 DIG4 18 DIG3 17 DIG2 16 GLED 26 SEGF AIN+ 25 VLED 24 SEGE AINISET GND AVDD DVDD CLK MAX1497 23 SEGD 22 SEGC 21 SEGB 20 SEGA 19 DIG3 MAX1499 CS DIN SCLK DOUT DIG0 17 GLED 16 DIG1 15 DIG0 TQFP SSOP/PDIP Chip Information TRANSISTOR COUNT: 80,000 PROCESS: BiCMOS ______________________________________________________________________________________ DIG1 18 DIG2 10 11 12 13 14 15 SEGF 29 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 Typical Operating Circuits VIN AIN+ AIN- SEGA–SEGDP SEGMENT CONNECTIONS DIG0–DIG3 DIGIT CONNECTIONS CLK SCLK VDD 10µF 0.1µF VLED 2.7V TO 5.25V 25kΩ ISET VNEG 0.1µF MAX1497 CS DIN DOUT EOC µC GND REF- REF+ 4.7µF GLED VIN AIN+ AINLOWBATT VLED DVDD SEGA–SEGDP SEGMENT CONNECTIONS DIG0–DIG4 DIGIT CONNECTIONS CLK SCLK MAX1499 CS DIN DOUT EOC µC 10µF 0.1µF AVDD LISO 0.1µF ISET VNEG 0.1µF 25kΩ GND REFREF+ 4.7µF GLED 2.7V TO 5.25V 10µF 30 ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 32L/48L,TQFP.EPS MAX1497/MAX1499 ______________________________________________________________________________________ 31 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) SSOP.EPS 2 1 INCHES DIM A A1 B C E H D E e H L MIN 0.068 0.002 0.010 MAX 0.078 0.008 0.015 MILLIMETERS MIN 1.73 0.05 0.25 MAX 1.99 0.21 0.38 D D D D D INCHES MIN 0.239 0.239 0.278 0.317 0.397 MAX 0.249 0.249 0.289 0.328 0.407 MILLIMETERS MIN 6.07 6.07 7.07 8.07 10.07 MAX 6.33 6.33 7.33 8.33 10.33 N 14L 16L 20L 24L 28L 0.20 0.09 0.004 0.008 SEE VARIATIONS 0.205 0.301 0.025 0∞ 0.212 0.311 0.037 8∞ 5.20 7.65 0.63 0∞ 5.38 7.90 0.95 8∞ 0.0256 BSC 0.65 BSC N A C e D B A1 L NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006"). 3. CONTROLLING DIMENSION: MILLIMETERS. 4. MEETS JEDEC MO150. 5. LEADS TO BE COPLANAR WITHIN 0.10 MM. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, SSOP, 5.3 MM APPROVAL DOCUMENT CONTROL NO. REV. 21-0056 C 1 1 32 ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) PDIPW.EPS MAX1497/MAX1499 N D1 INCHES DIM A A1 A2 A3 B B1 C D1 E E1 e eA eB L MAX MIN 0.200 0.015 0.125 0.175 0.080 0.055 0.020 0.016 0.065 0.045 0.012 0.008 0.009 0.005 0.625 0.600 0.525 0.575 0.100 BSC 0.600 BSC 0.700 0.120 0.150 MILLIMETERS MAX MIN 5.08 0.39 3.18 4.45 2.03 1.40 0.51 0.41 1.65 1.14 0.21 0.30 0.13 0.22 15.24 15.87 13.34 14.61 2.54 BSC 15.24 BSC 3.05 17.78 3.81 1 TOP VIEW E D A A1 A3 E1 A2 0∞-15∞ VARIATIONS: INCHES C eA eB L e B1 B MILLIMETERS MIN 31.24 36.32 51.44 MAX 32.26 37.34 52.71 N MS011 24 AA 28 40 AB AC DIM D D D MIN 1.230 1.430 2.025 MAX 1.270 1.470 2.075 FRONT VIEW SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, .600" PDIP APPROVAL DOCUMENT CONTROL NO. REV. 21-0044 B 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.