MAX15026

19-4108; Rev 1; 5/09 KIT ATION EVALU ILABLE AVA Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller General Description The MAX15026 synchronous step-down controller operates from a 4.5V to 28V input voltage range and generates an adjustable output voltage from 85% of the input voltage down to 0.6V while supporting loads up to 25A. The device allows monotonic startup into a prebiased bus without discharging the output and features adaptive internal digital soft-start. The MAX15026 offers the ability to adjust the switching frequency from 200kHz to 2MHz with an external resistor. The MAX15026’s adaptive synchronous rectification eliminates the need for an external freewheeling Schottky diode. The device also utilizes the external low-side MOSFET’s on-resistance as a current-sense element, eliminating the need for a current-sense resistor. This protects the DC-DC components from damage during output overloaded conditions or output shortcircuit faults without requiring a current-sense resistor. Hiccup-mode current limit reduces power dissipation during short-circuit conditions. The MAX15026 includes a power-good output and an enable input with precise turn-on/turn-off threshold, which can be used for input supply monitoring and for power sequencing. Additional protection features include sink-mode current limit and thermal shutdown. Sink-mode current limit prevents reverse inductor current from reaching dangerous levels when the device is sinking current from the output. The MAX15026 is available in a space-saving and thermally enhanced 3mm x 3mm, 14-pin TDFN-EP package. The MAX15026 operates over the extended -40°C to +85°C and automotive -40°C to +125°C temperature ranges. o o o o Features 4.5V to 28V or 5V ±10% Input Supply Range 0.6V to (0.85 x VIN) Adjustable Output Adjustable 200kHz to 2MHz Switching Frequency Ability to Start into a Prebiased Load MAX15026 o Lossless, Cycle-by-Cycle Valley Mode Current Limit with Adjustable, Temperature-Compensated Threshold o o o o o o o o o Sink-Mode Current-Limit Protection Adaptive Internal Digital Soft-Start ±1% Accurate Voltage Reference Internal Boost Diode Adaptive Synchronous Rectification Eliminates External Freewheeling Schottky Diode Hiccup-Mode Short-Circuit Protection Thermal Shutdown Power-Good Output and Enable Input for Power Sequencing ±5% Accurate Enable Input Threshold Ordering Information PART MAX15026BETD+ MAX15026BATD+ TEMP RANGE -40°C to +85°C -40°C to +125°C PIN-PACKAGE 14 TDFN-EP* 14 TDFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Pin Configuration TOP VIEW Applications Set-Top Boxes LCD TV Secondary Supplies Switches/Routers Power Modules DSP Power Supplies Points-of-Load Regulators IN VCC PGOOD EN LIM COMP FB 1 2 3 4 5 6 7 *EP + 14 13 12 DH LX BST DL DRV GND RT MAX15026 11 10 9 8 TDFN (3mm x 3mm) *EP = EXPOSED PAD. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller MAX15026 ABSOLUTE MAXIMUM RATINGS IN to GND ...............................................................-0.3V to +30V BST to GND ............................................................-0.3V to +36V LX to GND .................................................................-1V to +30V EN to GND................................................................-0.3V to +6V PGOOD to GND .....................................................-0.3V to +30V BST to LX..................................................................-0.3V to +6V DH to LX ...............................................….-0.3V to (VBST + 0.3V) DRV to GND .............................................................-0.3V to +6V DL to GND ................................................-0.3V to (VDRV + 0.3V) VCC to GND...............-0.3V to the lower of +6V and (VIN + 0.3V) All Other Pins to GND.................................-0.3V to (VCC + 0.3V) VCC Short Circuit to GND ...........................................Continuous DRV Input Current.............................................................600mA PGOOD Sink Current ............................................................5mA Continuous Power Dissipation (TA = +70°C) (Note 1) 14-Pin TDFN-EP, Multilayer Board (derate 24.4mW/°C above +70°C) ..............................1951mW Operating Temperature Range MAX15026BETD+.............................................-40°C to +85°C MAX15026BATD+...........................................-40°C to +125°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Note 1: Dissipation wattage values are based on still air with no heatsink. Actual maximum power dissipation is a function of heat extraction technique and may be substantially higher. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = 12V, RRT = 27kΩ, RLIM = 30kΩ, CVCC = 4.7µF, CIN = 1µF, TA = -40°C to +85°C (MAX15026BETD+), TA = TJ = -40°C to +125°C (MAX15026BATD+), unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER GENERAL Input Voltage Range Quiescent Supply Current Shutdown Supply Current Enable to Output Delay VCC High to Output Delay VCC REGULATOR Output Voltage VCC Regulator Dropout VCC Short-Circuit Output Current VCC Undervoltage Lockout VCC Undervoltage Lockout Hysteresis ERROR AMPLIFIER (FB, COMP) FB Input Voltage Set-Point FB Input Bias Current FB to COMP Transconductance Amplifier Open-Loop Gain Amplifier Unity-Gain Bandwidth VCOMP-RAMP Minimum Voltage COMP Source/Sink Current ICOMP VCOMP = 1.4V 50 Capacitor from COMP to GND = 50pF VFB IFB gM VFB = 0.6V ICOMP = ±20µA 585 -250 600 1200 80 4 160 80 110 591 597 +250 1800 mV nA µS dB MHz mV µA VCC_UVLO VCC 6V < VIN < 28V, ILOAD = 25mA VIN = 12V, 1mA < ILOAD < 70mA VIN = 4.5V, ILOAD = 70mA VIN = 5V VCC rising 100 3.8 200 4.0 400 5.0 5.25 5.5 0.28 300 4.2 V V mA V mV EN = VCC IIN_SBY VIN 4.5 VIN = VCC = VDRV VFB = 0.9V, no switching EN = GND 4.5 1.75 290 480 375 28 5.5 2.75 500 V mA µA µs µs SYMBOL CONDITIONS MIN TYP MAX UNITS 2 _______________________________________________________________________________________ Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller ELECTRICAL CHARACTERISTICS (continued) (VIN = 12V, RRT = 27kΩ, RLIM = 30kΩ, CVCC = 4.7µF, CIN = 1µF, TA = -40°C to +85°C (MAX15026BETD+), TA = TJ = -40°C to +125°C (MAX15026BATD+), unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER ENABLE (EN) EN Input High EN Input Low EN Input Leakage Current OSCILLATOR Switching Frequency 1MHz Switching Frequency 2MHz Switching Frequency Switching Frequency Adjustment Range (Note 3) RT Voltage PWM Ramp Peak-to-Peak Amplitude PWM Ramp Valley Minimum Controllable On-Time Maximum Duty Cycle Minimum Low-Side On-Time OUTPUT DRIVERS/DRIVER SUPPLY (DRV) DRV Undervoltage Lockout DRV Undervoltage Lockout Hysteresis DH On-Resistance DL On-Resistance DH Peak Current DL Peak Current DH/DL Break-Before-Make Time SOFT-START Soft-Start Duration Reference Voltage Steps CURRENT LIMIT/HICCUP Current-Limit Threshold Adjustment Range Cycle-by-cycle valley current-limit threshold adjustment range valley limit = VLIM/10 30 300 mV 2048 64 Switching Cycles Steps Low, sinking 100mA, VBST = 5V High, sourcing 100mA, VBST = 5V Low, sinking 100mA, VBST = 5.2V High, sourcing 100mA, VBST = 5.2V CLOAD = 10nF CLOAD = 10nF Sinking Sourcing Sinking Sourcing VDRV_UVLO VDRV rising 4.0 4.2 400 1 1.5 1 1.5 4 3 4 3 10 3 4.5 3 4.5 4.4 V mV Ω Ω A A ns fSW = 600kHz RRT = 15.7kΩ 85 75 VRT VRAMP VVALLEY fSW RRT = 27kΩ RRT = 15.7kΩ RRT = 7.2kΩ 540 0.9 1.8 200 1.19 1.205 1.8 0.8 65 88 110 150 100 600 1 2.0 660 1.1 2.4 2000 1.22 kHz MHz MHz kHz V V V ns % ns VEN_H VEN_L ILEAK_EN VEN rising VEN falling VEN = 5.5V 1.14 0.997 -1 1.20 1.05 1.26 1.103 +1 V V µA SYMBOL CONDITIONS MIN TYP MAX UNITS MAX15026 Time from high side at 1V to low side at 1V _______________________________________________________________________________________ 3 Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller MAX15026 ELECTRICAL CHARACTERISTICS (continued) (VIN = 12V, RRT = 27kΩ, RLIM = 30kΩ, CVCC = 4.7µF, CIN = 1µF, TA = -40°C to +85°C (MAX15026BETD+), TA = TJ = -40°C to +125°C (MAX15026BATD+), unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER LIM Reference Current LIM Reference Current Tempco Number of Consecutive CurrentLimit Events to Hiccup Soft-Start Timeout Soft-Start Restart Timeout Hiccup Timeout Peak Low-Side Sink Current Limit BOOST Boost Switch Resistance POWER-GOOD OUTPUT PGOOD Threshold Rising PGOOD Threshold Falling PGOOD Output Leakage PGOOD Output Low Voltage THERMAL SHUTDOWN Thermal-Shutdown Threshold Thermal-Shutdown Hysteresis Temperature rising Temperature falling +150 20 °C °C ILEAK_PGD VPGOOD_L VIN = VPGOOD = 28V, VEN = 5V, VFB = 1V IPGOOD = 2mA, EN = GND 90 88 -1 94.5 92 97.5 94.5 +1 0.4 %VFB %VFB µA V VIN = VCC = 5V, IBST = 10mA 3 8 Ω Out of soft-start Sink limit = 1.5V, RLIM = 30kΩ (Note 4) SYMBOL ILIM CONDITIONS VLIM = 0.3V to 3V (Note 4) VLIM = 0.3V to 3V MIN 45 TYP 50 2300 7 4096 8192 4096 75 MAX 55 UNITS µA ppm/°C Events Switching Cycles Switching Cycles Switching Cycles mV Note 2: All devices are 100% tested at room temperature and guaranteed by design over the specified temperature range. 17.3 × 109 Note 3: Select RRT as: RRT = where fSW is in Hertz. fSW + (1x10−7 )x(fSW 2 ) Note 4: TA = +25°C. 4 _______________________________________________________________________________________ Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller Typical Operating Characteristics (VIN = 12V, TA = +25°C, unless otherwise noted.) (See the circuit of Figure 5.) EFFICIENCY vs. LOAD CURRENT (VIN = 12V, VCC = VDRV = 5V) MAX15026 toc01 MAX15026 toc02 MAX15026 EFFICIENCY vs. LOAD CURRENT 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 2 4 6 8 10 12 LOAD CURRENT (A) VOUT = 3.3V VOUT = 1.2V VOUT = 5V VOUT = 1.8V 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 VOUT vs. LOAD CURRENT -0.1 % OUTPUT FROM NOMINAL -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 MAX15026 toc03 0 VOUT = 5V VOUT = 3.3V VOUT = 1.8V VOUT = 1.2V 2 4 6 8 10 12 0 2 4 6 8 10 12 LOAD CURRENT (A) LOAD CURRENT (A) VCC vs. LOAD CURRENT MAX15026 toc04 VCC LINE REGULATION 5mA 5.2 5.1 5.0 VCC (V) 4.9 4.8 4.7 4.6 5.240 5.238 5.236 0 5 10 15 VIN (V) 20 25 30 -40 50mA 5.244 VCC (V) 5.242 MAX15026 toc05 VCC vs. TEMPERATURE MAX15026 toc06 5.265 5.260 5.255 5.250 VCC (V) 5.245 5.240 5.235 5.230 5.225 0 20 60 40 LOAD CURRENT (mA) 80 5.3 5.248 5.246 4.5 4.4 4.3 100 -15 10 35 60 85 TEMPERATURE (°C) SWITCHING FREQUENCY vs. RESISTANCE MAX15026 toc07 SWITCHING FREQUENCY vs. TEMPERATURE MAX15026 toc08 SUPPLY CURRENT vs. SWITCHING FREQUENCY 80 SUPPLY CURRENT (mA) 70 60 50 40 30 20 10 MAX15026 toc09 2500 SWITCHING FREQUENCY (kHz) 2500 SWITCHING FREQUENCY (kHz) 90 2000 2000 RRT = 7.2kΩ RRT = 15.7kΩ RRT = 27kΩ RRT = 85kΩ 1500 1500 1000 1000 500 500 0 0 20 40 60 80 100 RESISTANCE (kΩ) 0 -40 -15 10 35 60 85 TEMPERATURE (°C) 0 100 1000 SWITCHING FREQUENCY (kHz) 10,000 _______________________________________________________________________________________ 5 Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller MAX15026 Typical Operating Characteristics (continued) (VIN = 12V, TA = +25°C, unless otherwise noted.) (See the circuit of Figure 5.) LIM REFERENCE CURRENT vs. TEMPERATURE MAX15026 toc10 SINK AND SOURCE CURRENT-LIMIT THRESHOLDS vs. RESISTANCE (RILIM) MAX15026 toc11 LOAD TRANSIENT ON OUT MAX15026 toc12 70 LIM REFERENCE CURRENT (μA) 60 50 40 30 20 10 0 -40 -15 10 35 60 0.2 CURRENT-LIMIT THRESHOLDS (V) 0.1 0 -0.1 -0.2 SINK CURRENT-LIMIT VOUT 200mV/div AC-COUPLED SOURCE CURRENT-LIMIT 10A IOUT -0.3 -0.4 1A 85 0 10 20 30 40 50 60 70 TEMPERATURE (°C) RESISTANCE (kΩ) 400μs/div STARTUP AND DISABLE FROM EN (RLOAD = 1.5Ω) STARTUP RISE TIME MAX15026 toc14 POWER-DOWN FALL TIME MAX15026 toc15 MAX15026 toc13 VIN 5V/div VOUT 1V/div VIN 5V/div PGOOD 5V/div VIN 5V/div VOUT 1V/div VOUT 1V/div 4ms/div 1ms/div 4ms/div STARTUP WITH PREBIASED OUTPUT (1.5V) MAX15026 toc16 STARTUP WITH PREBIASED OUTPUT (1.5V) MAX15026 toc17 OUTPUT SHORT-CIRCUIT BEHAVIOR MONITOR OUTPUT VOLTAGE AND CURRENT MAX15026 toc18 VIN 5V/div VIN 5V/div VOUT 2V OUTPUT PREBIAS 500mV/div 0 0.5V OUTPUT PREBIAS VOUT 1V/div VOUT 1V/div 20A/div IOUT 0 1ms/div 2ms/div 4ms/div 6 _______________________________________________________________________________________ Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller MAX15026 Pin Description PIN 1 NAME IN FUNCTION Regulator Input. Bypass IN to GND with a 1µF minimum ceramic capacitor. Connect IN to VCC when operating in the 5V ±10% range. 5.25V Linear Regulator Output. Bypass VCC to GND with a minimum of 4.7µF low-ESR ceramic capacitor to ensure stability up to the regulated rated current when VCC supplies the drive current at DRV. Bypass VCC to GND when VCC supplies the device core quiescent current with a 2.2µF minimum ceramic capacitor. Open-Drain Power-Good Output. Connect PGOOD with an external resistor to any supply voltage. Active-High Enable Input. Pull EN to GND to disable the output. Connect EN to VCC for always-on operation. EN can be used for power sequencing and as a UVLO adjustment input. Current-Limit Adjustment. Connect a resistor from LIM to GND to adjust current-limit threshold from 30mV (RLIM = 6kΩ) to 300mV (RLIM = 60kΩ). See the Setting the Valley Current Limit section. Compensation Input. Connect compensation network from COMP to FB or from COMP to GND. See the Compensation section. Feedback Input. Connect FB to a resistive divider between output and GND to adjust the output voltage between 0.6V and (0.85 x Input Voltage). See the Setting the Output Voltage section. Oscillator Timing Resistor Input. Connect a resistor from RT to GND to set the oscillator frequency from 200kHz to 2MHz. See the Setting the Switching Frequency section. Ground Drive Supply Voltage. DRV is internally connected to the anode terminal of the internal boost diode. Bypass DRV to GND with a 2.2µF minimum ceramic capacitor (see the Typical Application Circuits). Low-Side Gate-Driver Output. DL swings from DRV to GND. DL is low during UVLO. Boost Flying Capacitor. Connect a ceramic capacitor with a minimum value of 100nF between BST and LX. External Inductor Connection. Connect LX to the switching side of the inductor. LX serves as the lower supply rail for the high-side gate driver and as a sensing input of the drain to source voltage drop of the synchronous MOSFET. High-Side Gate-Driver Output. DH swings from LX to BST. DH is low during UVLO. Exposed Paddle. Internally connected to GND. Connect EP to a large copper plane at GND potential to improve thermal dissipation. Do not use EP as the only GND ground connection. 2 VCC 3 4 5 6 7 8 9 10 11 12 PGOOD EN LIM COMP FB RT GND DRV DL BST 13 14 — LX DH EP _______________________________________________________________________________________ 7 Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller MAX15026 Functional Diagram MAX15026 VREF OSCILLATOR RT ENABLE COMPARATOR EN VREF BGAP_OK EN_INT OSC_ENABLE CK VREF HICCUP CK ENABLE FB1 DAC_VREF SOFT-START/ SOFT-STOP LOGIC AND HICCUP LOGIC HICCUP TIMEOUT DH_DL_ENABLE PWM COMPARATOR VREF CK DC-DC AND OSCILLATOR ENABLE LOGIC CK VCC BGAP_OK VCC UVLO VL_OK DH_DL_ENABLE HICCUP TIMEOUT DRV UVLO VDRV_OK PWM CONTROL HICCUP LOGIC RAMP GENERATOR RAMP BST BOOST DRIVER GATEP HIGHSIDE DRIVER gM COMP VBGAP BANDGAP OK GENERATOR BGAP_OK PWM VIN_OK VBGAP INTERNAL VOLTAGE REGULATOR DH LX DRV BGAP_OK VDRV LOWSIDE DRIVER LIM/20 DL VIN_OK LIM THERMAL SHUTDOWN AND ILIM CURRENT GEN GND SHUTDOWN SINK CURRENT-LIMIT COMPARATOR VIN_OK VIN_OK IBIAS MAIN BIAS CURRENT GENERATOR FB ENABLE PGOOD IN IN UVLO VALLEY CURRENT-LIMIT COMPARATOR VREF LIM/10 PGOOD COMPARATOR GND VREF = 0.6V VBGAP = 1.24V BANDGAP REFERENCE 8 _______________________________________________________________________________________ Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller MAX15026 Detailed Description The MAX15026 synchronous step-down controller operates from a 4.5V to 28V input voltage range and generates an adjustable output voltage from 85% of the input voltage down to 0.6V while supporting loads up to 25A. As long as the device supply voltage is within 5.0V to 5.5V, the input power bus (VIN) can be as low as 3.3V. The MAX15026 offers adjustable switching frequency from 200kHz to 2MHz with an external resistor. The adjustable switching frequency provides design flexibility in selecting passive components. The MAX15026 adopts an adaptive synchronous rectification to eliminate an external freewheeling Schottky diode and improve efficiency. The device utilizes the on-resistance of the external low-side MOSFET as a currentsense element. The current-limit threshold voltage is resistor-adjustable from 30mV to 300mV and is temperature-compensated, so that the effects of the MOSFET RDS(ON) variation over temperature are reduced. This current-sensing scheme protects the external components from damage during output overloaded conditions or output short-circuit faults without requiring a current-sense resistor. Hiccup-mode current limit reduces power dissipation during short-circuit conditions. The MAX15026 includes a power-good output and an enable input with precise turn-on/-off threshold to be used for monitoring and for power sequencing. The MAX15026 features internal digital soft-start that allows prebias startup without discharging the output. The digital soft-start function employs sink current limiting to prevent the regulator from sinking excessive current when the prebias voltage exceeds the programmed steady-state regulation level. The digital soft-start feature prevents the synchronous rectifier MOSFET and the body diode of the high-side MOSFET from experiencing dangerous levels of current while the regulator is sinking current from the output. The MAX15026 shuts down at a junction temperature of +150°C to prevent damage to the device. or the maximum duty cycle is reached. During the ontime of the high-side MOSFET, the inductor current ramps up. During the second-half of the switching cycle, the high-side MOSFET turns off and the low-side n-channel MOSFET turns on. The inductor releases the stored energy as the inductor current ramps down, providing current to the output. Under overload conditions, when the inductor current exceeds the selected valley currentlimit threshold (see the Current-Limit Circuit (LIM) section), the high-side MOSFET does not turn on at the subsequent clock rising edge and the low-side MOSFET remains on to let the inductor current ramp down. Internal 5.25V Linear Regulator An internal linear regulator (VCC) provides a 5.25V nominal supply to power the internal functions and to drive the low-side MOSFET. Connect IN and VCC together when using an external 5V ±10% power supply. The maximum regulator input voltage (VIN) is 28V. Bypass IN to GND with a 1µF ceramic capacitor. Bypass the output of the linear regulator (VCC) with a 4.7µF ceramic capacitor to GND. The VCC dropout voltage is typically 125mV. When VIN is higher than 5.5V, VCC is typically 5.25V. The MAX15026 also employs an undervoltage lockout circuit that disables the internal linear regulator when VCC falls below 3.6V (typ). The 400mV UVLO hysteresis prevents chattering on power-up/power-down. The internal V CC linear regulator can source up to 70mA to supply the IC, power the low-side gate driver, recharge the external boost capacitor, and supply small external loads. The current available for external loads depends on the current consumed by the MOSFET gate drivers. For example, when switching at 600kHz, a MOSFET with 18nC total gate charge (at VGS = 5V) requires (18nC x 600kHz) = 11mA. The internal control functions consume 5mA maximum. The current available for external loads is: (70 – (2 x 11) – 5)mA ≅ 43mA DC-DC PWM Controller The MAX15026 step-down controller uses a PWM voltage-mode control scheme (see the Functional Diagram). Control-loop compensation is external for providing maximum flexibility in choosing the operating frequency and output LC filter components. An internal transconductance error amplifier produces an integrated error voltage at COMP that helps to provide higher DC accuracy. The voltage at COMP sets the duty cycle using a PWM comparator and a ramp generator. On the rising edge of an internal clock, the high-side n-channel MOSFET turns on and remains on until either the appropriate duty cycle MOSFET Gate Drivers (DH, DL) DH and DL are optimized for driving large-size n-channel power MOSFETs. Under normal operating conditions and after startup, the DL low-side drive waveform is always the complement of the DH high-side drive waveform, with controlled dead-time to prevent crossconduction or shoot-through. An adaptive dead-time circuit monitors the DH and DL outputs and prevents the opposite-side MOSFET from turning on until the other MOSFET is fully off. Thus, the circuit allows the high-side driver to turn on only when the DL gate driver has turned off, preventing the low-side (DL) from turning on until the DH gate driver has turned off. 9 _______________________________________________________________________________________ Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller The adaptive driver dead-time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency. There must be a low-resistance, low-inductance path from DL and DH to the MOSFET gates for the adaptive dead-time circuits to function properly. The stray impedance in the gate discharge path can cause the sense circuitry to interpret the MOSFET gate as off while the V GS of the MOSFET is still high. To minimize stray impedance, use very short, wide traces. Synchronous rectification reduces conduction losses in the rectifier by replacing the normal low-side Schottky catch diode with a low-resistance MOSFET switch. The MAX15026 features a robust internal pulldown transistor with a typical 1Ω RDS(ON) to drive DL low. This low on-resistance prevents DL from being pulled up during the fast rise time of the LX node, due to capacitive coupling from the drain to the gate of the low-side synchronous rectifier MOSFET. stop sequence is completed, the MOSFET drivers are both turned off. See Figure 1. Connect EN to VCC for always-on operation. Owing to the accurate turn-on/-off thresholds, EN can be used as UVLO adjustment input, and for power sequencing together with the PGOOD output. When the valley current limit is reached during soft-start the MAX15026 regulates to the output impedance times the limited inductor current and turns off after 4096 clock cycles. When starting up into a large capacitive load (for example) the inrush current will not exceed the current-limit value. If the soft-start is not completed before 4096 clock cycles, the device will turn off. The device remains off for 8192 clock cycles before trying to soft-start again. This implementation allows the softstart time to be automatically adapted to the time necessary to keep the inductor current below the limit while charging the output capacitor. MAX15026 High-Side Gate-Drive Supply (BST) and Internal Boost Switch An internal switch between BST and DH turns on to boost the gate voltage above VIN providing the necessary gate-to-source voltage to turn on the high-side MOSFET. The boost capacitor connected between BST and LX holds up the voltage across the floating gate driver during the high-side MOSFET on-time. The charge lost by the boost capacitor for delivering the gate charge is replenished when the high-side MOSFET turns off and LX node goes to ground. When LX is low, an internal high-voltage switch connected between VDRV and BST recharges the boost capacitor. See the Boost Capacitor section in the Applications Information to choose the right size of the boost capacitor. Power-Good Output (PGOOD) The MAX15026 includes a power-good comparator to monitor the output voltage and detect the power-good threshold, fixed at 94.5% of the nominal FB voltage. The open-drain PGOOD output requires an external pullup resistor. PGOOD sinks up to 2mA of current while low. PGOOD goes high (high-impedance) when the regulator output increases above 94.5% of the designed nominal regulated voltage. PGOOD goes low when the regulator output voltage drops to below 92% of the nominal regulated voltage. PGOOD asserts low during hiccup timeout period. Startup into a Prebiased Output When the MAX15026 starts into a prebiased output, DH and DL are off so that the converter does not sink current from the output. DH and DL do not start switching until the PWM comparator commands the first PWM pulse. The first PWM pulse occurs when the ramping reference voltage increases above the FB voltage. When the output voltage is biased above the output set-point, the controller tries to pull the output down to the set-point once the internal soft-start is complete. This pulldown is limited by the sink current limit, which is slowly increased to its normal value to minimize output undershoot. Enable Input (EN), Soft-Start, and Soft-Stop Drive EN high to turn on the MAX15026. A soft-start sequence starts to increase step-wise the reference voltage of the error amplifier. The duration of the softstart ramp is 2048 switching cycles and the resolution is 1/64th of the steady-state regulation voltage allowing a smooth increase of the output voltage. A logic-low on EN initiates a soft-stop sequence by stepping down the reference voltage of the error amplifier. After the soft- 10 ______________________________________________________________________________________ Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller MAX15026 UVLO VCC A B C D E F G H I EN VOUT 2048 CLK CYCLES DAC_VREF 2048 CLK CYCLES DH DL SYMBOL UVLO VCC EN VOUT DAC_VREF DH DL A DEFINITION Undervoltage threshold value is provided in the Electrical Characteristics table. Internal 5.25V linear regulator output. Active-high enable input. Regulator output voltage. Regulator internal soft-start and soft-stop signal. Regulator high-side gate-driver output. Regulator low-side gate-driver output. VCC rising while below the UVLO threshold. EN is low. SYMBOL B C D E F G H I DEFINITION VCC is higher than the UVLO threshold. EN is low. EN is pulled high. DH and DL start switching. Normal operation. VCC drops below UVLO. VCC goes above the UVLO threshold. DH and DL start switching. Normal operation. EN is pulled low. VOUT enters soft-stop. EN is pulled high. DH and DL start switching. Normal operation. VCC drops below UVLO. Figure 1. Power-On/-Off Sequencing Current-Limit Circuit (LIM) The current-limit circuit employs a valley and sink current-sensing algorithm that uses the on-resistance of the low-side MOSFET as a current-sensing element, to eliminate costly sense resistors. The current-limit circuit is also temperature compensated to track the on-resistance variation of the MOSFET over temperature. The current limit is adjustable with an external resistor at LIM, and accommodates MOSFETs with a wide range of on-resistance characteristics (see the Setting the Valley Current Limit section). The adjustment range is from 30mV to 300mV for the valley current limit, corresponding to resistor values of 6kΩ to 60kΩ. The valley current-limit threshold across the low-side MOSFET is precisely 1/10th of the voltage at LIM, while the sink current-limit threshold is 1/20th of the voltage at LIM. Valley current limit acts when the inductor current flows towards the load, and LX is more negative than GND during the low-side MOSFET on-time. If the magnitude of current-sense signal exceeds the valley current-limit threshold at the end of the low-side MOSFET on-time, the MAX15026 does not initiate a new PWM cycle and lets the inductor current decay in the next cycle. The controller also rolls back the internal reference voltage so that the controller finds a regulation point determined by the current-limit value and the resistance of the short. In this manner, the controller acts as a constant current source. This method greatly reduces inductor ripple current during the short event, which reduces inductor sizing restrictions, and reduces the possibility for audible noise. After a timeout, the device goes into hiccup mode. Once the short is removed, the internal reference voltage soft-starts back up to the normal reference voltage and regulation continues. 11 ______________________________________________________________________________________ Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller Sink current limit is implemented by monitoring the voltage drop across the low-side MOSFET when LX is more positive than GND. When the voltage drop across the low-side MOSFET exceeds 1/20th of the voltage at LIM at any time during the low-side MOSFET on-time, the low-side MOSFET turns off, and the inductor current flows from the output through the body diode of the highside MOSFET. When the sink current limit activates, the DH/DL switching sequence is no longer complementary. Carefully observe the PCB layout guidelines to ensure that noise and DC errors do not corrupt the currentsense signals at LX and GND. Mount the MAX15026 close to the low-side MOSFET with short, direct traces making a Kelvin-sense connection so that trace resistance does not add to the intended sense resistance of the low-side MOSFET. MAX15026 unwanted triggering of the thermal-overload protection in normal operation. Applications Information Effective Input Voltage Range The MAX15026 operates from input supplies up to 28V and regulates down to 0.6V. The minimum voltage conversion ratio (VOUT/VIN) is limited by the minimum controllable on-time. For proper fixed-frequency PWM operation, the voltage conversion ratio must obey the following condition, VOUT > t ON(MIN) × fSW VIN where tON(MIN) is 125ns and fSW is the switching frequency in Hertz. Pulse-skipping occurs to decrease the effective duty cycle when the desired voltage conversion does not meet the above condition. Decrease the switching frequency or lower VIN to avoid pulse skipping. The maximum voltage conversion ratio is limited by the maximum duty cycle (Dmax): VOUT × VDROP2 + (1 − Dmax ) × VDROP1 D < Dmax − max VIN VIN Hiccup-Mode Overcurrent Protection Hiccup-mode overcurrent protection reduces power dissipation during prolonged short-circuit or deep overload conditions. An internal three-bit counter counts up on each switching cycle when the valley current-limit threshold is reached. The counter counts down on each switching cycle when the threshold is not reached, and stops at zero (000). The counter reaches 111 (= 7 events) when the valley mode current-limit condition persists. The MAX15026 stops both DL and DH drivers and waits for 4096 switching cycles (hiccup timeout delay) before attempting a new soft-start sequence. The hiccup-mode protection remains active during the softstart time. Undervoltage Lockout The MAX15026 provides an internal undervoltage lockout (UVLO) circuit to monitor the voltage on VCC. The UVLO circuit prevents the MAX15026 from operating when VCC is lower than VUVLO. The UVLO threshold is 4V, with 400mV hysteresis to prevent chattering on the rising/falling edge of the supply voltage. DL and DH stay low to inhibit switching when the device is in undervoltage lockout. where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PCB resistance. VDROP2 is the sum of the resistance in the charging path, including high-side switch, inductor, and PCB resistance. In practice, provide adequate margin to the above conditions for good load-transient response. Setting the Output Voltage Set the MAX15026 output voltage by connecting a resistive divider from the output to FB to GND (Figure 2). Select R2 from between 1kΩ and 50kΩ. Calculate R1 with the following equation: ⎡⎛ V ⎞⎤ R1 = R2 ⎢⎜ OUT ⎟ − 1⎥ ⎢⎝ VFB ⎠ ⎥ ⎣ ⎦ where VFB = 0.592V (see the Electrical Characteristics table) and VOUT can range from 0.592V to (0.85 x VIN). Resistor R1 also plays a role in the design of the Type III compensation network. Review the values of R1 and R2 when using a Type III compensation network (see the Type III Compensation Network (See Figure 4) section). Thermal-Overload Protection Thermal-overload protection limits total power dissipation in the MAX15026. When the junction temperature of the device exceeds +150°C, an on-chip thermal sensor shuts down the device, forcing DL and DH low, allowing the device to cool. The thermal sensor turns the device on again after the junction temperature cools by 20°C. The regulator shuts down and soft-start resets during thermal shutdown. Power dissipation in the LDO regulator and excessive driving losses at DH/DL trigger thermal-overload protection. Carefully evaluate the total power dissipation (see the P ower Dissipation s ection) to avoid 12 ______________________________________________________________________________________ Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller OUT frequency, input voltage, output voltage, and selected LIR determine the inductor value as follows, (V − V ) V L = OUT IN OUT VINfSWIOUTLIR where VIN, VOUT, and IOUT are typical values (so that efficiency is optimum for typical conditions). The switching frequency is set by R RT (see the S etting the Switching Frequency section). The exact inductor value is not critical and can be adjusted to make trade-offs among size, cost, and efficiency. Lower inductor values minimize size and cost, but also improve transient response and reduce efficiency due to higher peak currents. On the other hand, higher inductance increases efficiency by reducing the RMS current. Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. The saturation current rating (ISAT) must be high enough to ensure that saturation can occur only above the maximum current-limit value (ICL(MAX)), given the tolerance of the onresistance of the low-side MOSFET and of the LIM reference current (ILIM). Combining these conditions, select an inductor with a saturation current (ISAT) of: ISAT ≥ 1.35 x ICL(TYP) where ICL(TYP) is the typical current-limit set-point. The factor 1.35 includes RDS(ON) variation of 25% and 10% for the LIM reference current error. A variety of inductors from different manufacturers are available to meet this requirement (for example, Coilcraft MSS1278-142ML and other inductors from the same series). MAX15026 R1 FB R2 MAX15026 Figure 2. Adjustable Output Voltage Setting the Switching Frequency An external resistor connecting RT to GND sets the switching frequency (fSW). The relationship between fSW and RRT is: RRT = 17.3 × 109 fSW + (1x10−7 )x(fSW 2 ) where fSW is in kHz and RRT is in kΩ. For example, a 600kHz switching frequency is set with RRT = 27.2kΩ. Higher frequencies allow designs with lower inductor values and less output capacitance. Peak currents and I2R losses are lower at higher switching frequencies, but core losses, gate-charge currents, and switching losses increase. Setting the Valley Current Limit The minimum current-limit threshold must be high enough to support the maximum expected load current with the worst-case low-side MOSFET on-resistance value as the RDS(ON) of the low-side MOSFET is used as the current-sense element. The inductor’s valley current occurs at ILOAD(MAX) minus one half of the ripple current. The minimum value of the current-limit threshold voltage (VITH) must be higher than the voltage on the low-side MOSFET during the ripple-current valley: ⎛ LIR ⎞ VITH > RDS(ON,MAX) × ILOAD(MAX) × ⎜1 − ⎟ ⎝ 2⎠ where R DS(ON) i s the on-resistance of the low-side MOSFET in ohms. Use the maximum value for RDS(ON) from the data sheet of the low-side MOSFET. Inductor Selection Three key inductor parameters must be specified for operation with the MAX15026: inductance value (L), inductor saturation current (ISAT), and DC resistance (RDC). To determine the inductance value, select the ratio of inductor peak-to-peak AC current to DC average current (LIR) first. For LIR values which are too high, the RMS currents are high, and therefore I2R losses are high. Use high-valued inductors to achieve low LIR values. Typically, inductance is proportional to resistance for a given package type, which again makes I2R losses high for very low LIR values. A good compromise between size and loss is a 30% peak-to-peak ripple current to average-current ratio (LIR = 0.3). The switching ______________________________________________________________________________________ 13 Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller MAX15026 Connect an external resistor (RLIM) from LIM to GND to adjust the current-limit threshold. The relationship between the current-limit threshold (VITH) and RLIM is: RLIM = 10 × VITH 50μA where IP-P is the peak-to-peak inductor current ripple (see the Inductor Selection section). Use these equations for initial capacitor selection. Decide on the final values by testing a prototype or an evaluation circuit. Check the output capacitor against load-transient response requirements. The allowable deviation of the output voltage during fast load transients determines the capacitor output capacitance, ESR, and equivalent series inductance (ESL). The output capacitor supplies the load current during a load step until the controller responds with a higher duty cycle. The response time (tRESPONSE) depends on the closed-loop bandwidth of the converter (see the C ompensation section). The resistive drop across the ESR of the output capacitor, the voltage drop across the ESL (ΔVESL) of the capacitor, and the capacitor discharge, cause a voltage droop during the load step. Use a combination of low-ESR tantalum/aluminum electrolytic and ceramic capacitors for improved transient load and voltage ripple performance. Nonleaded capacitors and capacitors in parallel help reduce the ESL. Keep the maximum output voltage deviation below the tolerable limits of the load. Use the following equations to calculate the required ESR, ESL, and capacitance value during a load step: ΔVESR ESR = ISTEP ×t I COUT = STEP RESPONSE ΔVQ ESL = ΔVESL × t STEP ISTEP 1 tRESPONSE ≅ 3 × fO where RLIM is in kΩ and VITH is in mV. An RLIM resistance range of 6kΩ to 60kΩ corresponds to a current-limit threshold of 30mV to 300mV. Use 1% tolerance resistors when adjusting the current limit to minimize error in the current-limit threshold. Input Capacitor The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the switching circuitry. The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents as defined by the following equation, IRMS = ILOAD(MAX) VOUT (VIN − VOUT ) VIN IRMS attains a maximum value when the input voltage equals twice the output voltage (V IN = 2V OUT ), so I RMS(MAX) = I LOAD(MAX) /2. For most applications, non-tantalum capacitors (ceramic, aluminum, polymer, or OS-CON) are preferred at the inputs due to the robustness of non-tantalum capacitors to accommodate high inrush currents of systems being powered from very low-impedance sources. Additionally, two (or more) smaller-value low-ESR capacitors can be connected in parallel for lower cost. Output Capacitor The key selection parameters for the output capacitor are capacitance value, ESR, and voltage rating. These parameters affect the overall stability, output ripple voltage, and transient response. The output ripple has two components: variations in the charge stored in the output capacitor, and the voltage drop across the capacitor’s ESR caused by the current flowing into and out of the capacitor: ΔVRIPPLE ≅ ΔVESR + ΔVQ The output voltage ripple as a consequence of the ESR and the output capacitance is: ΔVESR = IP −P × ESR IP −P ΔVQ = 8 × COUT × fSW ⎞ ⎛V −V ⎞ ⎛V IP −P = ⎜ IN OUT ⎟ × ⎜ OUT ⎟ fSW × L ⎠ ⎝ VIN ⎠ ⎝ 14 where ISTEP is the load step, tSTEP is the rise time of the load step, tRESPONSE is the response time of the controller and fO is the closed-loop crossover frequency. Compensation The MAX15026 provides an internal transconductance amplifier with the inverting input and the output available for external frequency compensation. The flexibility of external compensation offers a wide selection of output filtering components, especially the output capacitor. Use high-ESR aluminum electrolytic capacitors for cost-sensitive applications. Use low-ESR tantalum or ceramic capacitors at the output for size sensitive applications. The high switching frequency of the MAX15026 allows the use of ceramic capacitors at the output. Choose all passive power components to meet the output ripple, component size, and component cost ______________________________________________________________________________________ Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller requirements. Choose the small-signal components for the error amplifier to achieve the desired closed-loop bandwidth and phase margin. To choose the appropriate compensation network type, the power-supply poles and zeros, the zero crossover frequency, and the type of the output capacitor must be determined. In a buck converter, the LC filter in the output stage introduces a pair of complex poles at the following frequency: fPO = 1 2π × L OUT × COUT Type II Compensation Network (Figure 3) If fZO is lower than fO and close to fPO, the phase lead of the capacitor ESR zero almost cancels the phase loss of one of the complex poles of the LC filter around the crossover frequency. Use a Type II compensation network with a midband zero and a high-frequency pole to stabilize the loop. In Figure 3, RF and CF introduce a midband zero (fZ1). RF and CCF in the Type II compensation network provide a high-frequency pole (fP1), which mitigates the effects of the output high-frequency ripple. Follow the instructions below to calculate the component values for the Type II compensation network in Figure 3: 1) Calculate the gain of the modulator (GAIN MOD), comprised of the regulator’s pulse-width modulator, LC filter, feedback divider, and associated circuitry at the crossover frequency: GAINMOD = VIN VRAMP × ESR V × FB (2π × fO × LOUT ) VOUT MAX15026 The output capacitor introduces a zero at: fZO = 1 2π × ESR × COUT where ESR is the equivalent series resistance of the output capacitor. The loop-gain crossover frequency (fO), where the loop gain equals 1 (0dB) should be set below 1/10th of the switching frequency: f fO ≤ SW 10 Choosing a lower crossover frequency reduces the effects of noise pick-up into the feedback loop, such as jittery duty cycle. To maintain a stable system, two stability criteria must be met: 1) The phase shift at the crossover frequency fO, must be less than 180°. In other words, the phase margin of the loop must be greater than zero. 2) The gain at the frequency where the phase shift is -180° (gain margin) must be less than 1. Maintain a phase margin of around 60° to achieve a robust loop stability and well-behaved transient response. When using an electrolytic or large-ESR tantalum output capacitor the capacitor ESR zero fZO typically occurs between the LC poles and the crossover frequency fO (fPO < fZO < fO). Choose Type II (PI—proportional-integral) compensation network. When using a ceramic or low-ESR tantalum output capacitor, the capacitor ESR zero typically occurs above the desired crossover frequency fO, that is fPO < fO < fZO. Choose Type III (PID—proportional, integral, and derivative) compensation network. where VIN is the input voltage of the regulator, VRAMP is the amplitude of the ramp in the pulse-width modulator, VFB is the FB input voltage set-point (0.592V typically, see the Electrical Characteristics table), and VOUT is the desired output voltage. The gain of the error amplifier (GainEA) in midband frequencies is: GAINEA = gM x RF where gM is the transconductance of the error amplifier. The total loop gain, which is the product of the modulator gain and the error amplifier gain at fO, is 1. GAINMOD × GAINEA = 1 So: VIN ESR V × × FB × gM × RF = 1 VRAMP (2π × fO × L OUT ) VOUT Solving for RF: V × ( 2π × fO × LOUT ) × VOUT RF = RAMP VFB × VIN × gM × ESR 2) Set a midband zero (fZ1) at 0.75 x fPO (to cancel one of the LC poles): fZ1 = 1 = 0.75 × fPO 2π × RF × CF 15 ______________________________________________________________________________________ Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller MAX15026 Solving for CF: CF = 1 2π × RF × fPO × 0.75 Depending on the location of the ESR zero (fZO), use fP2 to cancel fZO, or to provide additional attenuation of the high-frequency output ripple: 1 fP3 = C × CCF 2π × RF × F CF + CCF fP3 attenuates the high-frequency output ripple. Place the zeros and poles so the phase margin peaks around fO. Ensure that RF>>2/gM and the parallel resistance of R1, R 2 , and R I is greater than 1/g M . Otherwise, a 180° phase shift is introduced to the response making the loop unstable. Use the following compensation procedure: 1) With RF ≥ 10kΩ, place the first zero (fZ1) at 0.8 x fPO. fZ1 = So: CF = 1 2π × RF × 0.8 × fPO 1 = 0.8 × fPO 2π × RF × CF 3) Place a high-frequency pole at fP1 = 0.5 x fSW (to attenuate the ripple at the switching frequency, fSW) and calculate CCF using the following equation: CCF = 1 π × RF × fSW − 1 CF Type III Compensation Network (See Figure 4) When using a low-ESR tantalum or ceramic type, the ESR-induced zero frequency is usually above the targeted zero crossover frequency (fO). Use Type III compensation. Type III compensation provides three poles and two zeros at the following frequencies: 1 2π × RF × CF 1 fZ2 = 2π × CI × (R1 + RI) fZ1 = Two midband zeros (fZ1 and fZ2) cancel the pair of complex poles introduced by the LC filter: fP1 = 0 fP1 introduces a pole at zero frequency (integrator) for nulling DC output voltage errors: fP2 = 1 2π × RI × CI 2) The gain of the modulator (GAINMOD), comprises the pulse-width modulator, LC filter, feedback divider, and associated circuitry at the crossover frequency is: GAINMOD = VIN 1 × VRAMP (2π × fO )2 × L OUT × COUT VOUT VOUT R1 RF gM VREF RF CF CCF gM VREF COMP COMP RI CI R1 CF CCF R2 R2 Figure 3. Type II Compensation Network 16 Figure 4. Type III Compensation Network ______________________________________________________________________________________ Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller The gain of the error amplifier (GAINEA) in midband frequencies is: GAINEA = 2π x fO x C1 x RF The total loop gain as the product of the modulator gain and the error amplifier gain at fO is 1. GAINMOD × GAINEA = 1 So: VIN VRAMP Solving for CI: CI = VRAMP × (2π × fO × L OUT × COUT ) VIN × RF × 1 (2π × fO )2 × COUT × L OUT 5) Place the third pole (fP3) at 1/2 the switching frequency and calculate CCF: CCF = MAX15026 (2π × 0.5 × fSW × RF × CF ) − 1 R2 = VFB VOUT − VFB × R1 CF 6) Calculate R2 as: MOSFET Selection The MAX15026 step-down controller drives two external logic-level n-channel MOSFETs. The key selection parameters to choose these MOSFETs include: • On-Resistance (RDS(ON) ) • Maximum Drain-to-Source Voltage (VDS(MAX)) • Minimum Threshold Voltage (VTH(MIN)) • Total Gate Charge (QG) • Reverse Transfer Capacitance (CRSS) • Power Dissipation The two n-channel MOSFETs must be a logic-level type with guaranteed on-resistance specifications at VGS = 4.5V. For maximum efficiency, choose a high-side MOSFET that has conduction losses equal to the switching losses at the typical input voltage. Ensure that the conduction losses at minimum input voltage do not exceed the MOSFET package thermal limits, or violate the overall thermal budget. Also, ensure that the conduction losses plus switching losses at the maximum input voltage do not exceed package ratings or violate the overall thermal budget. Ensure that the DL gate driver can drive the low-side MOSFET. In particular, check that the dv/dt caused by the high-side MOSFET turning on does not pull up the low-side MOSFET gate through the drain-to-gate capacitance of the low-side MOSFET, which is the most frequent cause of cross-conduction problems. Check power dissipation when using the internal linear regulator to power the gate drivers. Select MOSFETs with low gate charge so that VCC can power both drivers without overheating the device. PDRIVE = VCC x QG_TOTAL x fSW where QG_TOTAL is the sum of the gate charges of the two external MOSFETs. 3) Use the second pole (fP2) to cancel fZO when fPO < fO < fZO < fSW/2. The frequency response of the loop gain does not flatten out soon after the 0dB crossover, and maintains a -20dB/decade slope up to 1/2 of the switching frequency. This is likely to occur if the output capacitor is a low-ESR tantalum. Set fP2 = fZO. When using a ceramic capacitor, the capacitor ESR zero f ZO is likely to be located even above 1/2 the switching frequency, fPO < fO < fSW/2 < fZO. In this case, place the frequency of the second pole (fP2) high enough to not significantly erode the phase margin at the crossover frequency. For example, set fP2 at 5 x fO so that the contribution to phase loss at the crossover frequency fO is only about 11°: fP2 = 5 x fPO Once fP2 is known, calculate RI: RI = 1 2π × fP2 × CI 4) Place the second zero (fZ2) at 0.2 x fO or at fPO, whichever is lower, and calculate R1 using the following equation: R1 = 1 2π × fZ2 × CI − RI ______________________________________________________________________________________ 17 Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller MAX15026 Boost Capacitor The MAX15026 uses a bootstrap circuit to generate the necessary gate-to-source voltage to turn on the highside MOSFET. The selected n-channel high-side MOSFET determines the appropriate boost capacitance value (CBST in the Typical Application Circuits) according to the following equation: CBST = QG ΔVBST estimation of the junction temperature requires a direct measurement of the case temperature (TC) when actual operating conditions significantly deviate from those described in the JEDEC standards. The junction temperature is then: TJ = TC + (PT x θJC) Use 8.7°C/W as θJC thermal impedance for the 14-pin TDFN package. The case-to-ambient thermal impedance (θCA) is dependent on how well the heat is transferred from the PCB to the ambient. Solder the exposed pad of the TDFN package to a large copper area to spread heat through the board surface, minimizing the case-to-ambient thermal impedance. Use large copper areas to keep the PCB temperature low. where Q G is the total gate charge of the high-side MOSFET and ΔVBST is the voltage variation allowed on the high-side MOSFET driver after turn-on. Choose ΔVBST so the available gate-drive voltage is not significantly degraded (e.g. ΔVBST = 100mV to 300mV) when determining CBST. Use a low-ESR ceramic capacitor as the boost flying capacitor with a minimum value of 100nF. PCB Layout Guidelines Place all power components on the top side of the board, and run the power stage currents using traces or copper fills on the top side only. Make a star connection on the top side of traces to GND to minimize voltage drops in signal paths. Keep the power traces and load connections short, especially at the ground terminals. This practice is essential for high efficiency and jitter-free operation. Use thick copper PCBs (2oz or above) to enhance efficiency. Place the MAX15026 adjacent to the synchronous rectifier MOSFET, preferably on the back side, to keep LX, GND, DH, and DL traces short and wide. Use multiple small vias to route these signals from the top to the bottom side. Use an internal quiet copper plane to shield the analog components on the bottom side from the power components on the top side. Make the MAX15026 ground connections as follows: create a small analog ground plane near the device. Connect this plane to GND and use this plane for the ground connection for the VIN bypass capacitor, compensation components, feedback dividers, VCC capacitor, RT resistor, and LIM resistor. Use Kelvin sense connections for LX and GND to the synchronous rectifier MOSFET for current limiting to guarantee the current-limit accuracy. Route high-speed switching nodes (BST, LX, DH, and DL) away from the sensitive analog areas (RT, COMP, LIM, and FB). Group all GND-referred and feedback components close to the device. Keep the FB and compensation network as small as possible to prevent noise pickup. Power Dissipation The maximum power dissipation of the device depends on the thermal resistance from the die to the ambient environment and the ambient temperature. The thermal resistance depends on the device package, PCB copper area, other thermal mass, and airflow. The power dissipated into the package (PT) depends on the supply configuration (see the Typical Application Circuits). Use the following equation to calculate power dissipation: PT = (VIN - VCC) x ILDO + VDRV x IDRV + VCC x IIN where ILDO is the current supplied by the internal regulator, IDRV is the supply current consumed by the drivers at DRV, and I IN is the supply current of the MAX15026 without the contribution of the IDRV, as given in the Typical Operating Characteristics. For example, in the application circuit of Figure 5, ILDO = IDRV + IIN and VDRV = VCC so that PT = VIN x (IDRV + IIN). Use the following equation to estimate the temperature rise of the die: TJ = TA + (PT x θJA) where θJA is the junction-to-ambient thermal impedance of the package, PT is power dissipated in the device, and TA is the ambient temperature. The θJA is 24.4°C/W for 14-pin TDFN package on multilayer boards, with the conditions specified by the respective JEDEC standards (JESD51-5, JESD51-7). An accurate 18 ______________________________________________________________________________________ Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller MAX15026 Typical Application Circuits Single 4.5V to 28V Supply Operation Figure 5 shows an application circuit for a single 4.5V to 28V power-supply operation. 4.5V TO 28V VIN PANASONIC EEEFCIE331P C1 330μF IN VCC DH ON-SEMICONDUCTOR Q1 NTMFS4835NTIG ( ) VOUT C5 22μF MAX15026 LX C3 0.47μF BST DL R1* DRV C6 2.2μF Q2 L1 1.4μH C4 470μF COILCRAFT MSS1278-142ML PGOOD PGOOD LIM SANYO 4C54701 ENABLE EN ( ON-SEMICONDUCTOR ) NTMFS4835NTIG COMP C7 68pF R3 4.02kΩ C9 0.022μF R1 11.8kΩ R5 10kΩ C10 4.7μF R7 4.02kΩ C8 68pF FB GND RT R4 27kΩ R6 15.4kΩ *R1 IS A SMALL-VALUE RESISTOR TO DECOUPLE SWITCHING TRANSIENTS CAUSED BY THE MOSFET DRIVER (2.2Ω). C11 1500pF Figure 5. VIN = 4.5V to 28V ______________________________________________________________________________________ 19 Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller MAX15026 Typical Application Circuits (continued) Single 4.5V to 5.5V Supply Operation Figure 6 shows an application circuit for a single 4.5V to 5.5V power-supply operation. 4.5V TO 5.5V VIN IN VCC DH Q1 MAX15026 LX CBST L1 VOUT CF1 PGOOD PGOOD LIM BST DL DRV C1 Q2 ENABLE EN COMP FB R3 C2 GND RT RT C3 RLIM C4 R2 R1 Figure 6. VCC = VIN = VDRV = 4.5V to 5.5V 20 ______________________________________________________________________________________ Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller MAX15026 Typical Application Circuits (continued) Auxiliary 5V Supply Operation Figure 7 shows an application circuit for a +12V supply to drive the external MOSFETs and an auxiliary +5V supply to power the device. VIN +12V IN VCC DH Q1 MAX15026 LX CBST L1 VOUT CF1 PGOOD PGOOD LIM BST DL DRV C1 Q2 ENABLE EN COMP FB R3 C2 C3 R2 RLIM C4 R1 GND RT RT VAUX 4.5V TO 5.5V Figure 7. Operation with Auxiliary 5V Supply ______________________________________________________________________________________ 21 Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller MAX15026 Chip Information PROCESS: BiCMOS PACKAGE TYPE 14 TDFN-EP Package Information For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE CODE T1433+2 DOCUMENT NO. 21-0137 22 ______________________________________________________________________________________ Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller Revision History REVISION NUMBER 0 1 REVISION DATE 5/08 5/09 Initial release Revised General Description, Ordering Information, Absolute Maximum Ratings, Electrical Characteristics, Power-Good Output (PGOOD) section, and Typical Application Circuits. DESCRIPTION PAGES CHANGED — 1–4, 10, 15, 19 MAX15026 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.