19-5918; Rev 0; 6/11
High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator with VID Control
General Description
The MAX15109 high-efficiency, current-mode, synchronous step-down switching regulator with integrated power switches deliver up to 8A of output current. This regulator operates from 2.7V to 5.5V and provides four output voltages using two VID control inputs. This IC utilizes a current-mode control architecture with a high gain transconductance error amplifier. The current-mode control architecture facilitates easy compensation design and ensures cycle-by-cycle current limit with fast response to line and load transients. This regulator offers skip-mode functionality to reduce current consumption and achieve a higher efficiency at light loads. The low RDS(ON) integrated switches ensure high efficiency at heavy loads while minimizing critical inductance, making the layout design a much simpler task with respect to discrete solutions. The high switching frequency (1MHz), along with the PWM current-mode architecture allows for a compact, all-ceramic capacitor design. The IC features a capacitor-programmable slew-rate control to reduce input current at the startup and when the output changes state under VID control. Internal control circuitry ensures safe-startup into a prebiased output. Power sequencing is controlled with the enable input and power-good output. The IC is available in a 20-bump (4 x 5 array), 2.5mm x 2mm, WLP package and is fully specified over the -40NC to +85NC temperature range.
Features
S Continuous 8A Output Current S Efficiency Over 90% S ±1% Accuracy Over Load, Line, and Temperature S Operates from a 2.7V to 5.5V Supply S VID Control Inputs for Selecting Output Voltage S Programmable Slew-Rate Control S Safe Startup into Prebiased Output S 1MHz Switching Frequency S Stable with Low-ESR Ceramic Output Capacitors S Enable Input and Power-Good Output for PowerSupply Sequencing S Cycle-by-Cycle Overcurrent Protection Faults S Fully Protected Against Overcurrent and Overtemperature S Input Undervoltage Lockout S 20-Bump (4 x 5 Array), 2.5mm x 2mm, WLP Package
MAX15109
Ordering Information
PART MAX15109EWP+ TEMP RANGE -40NC to +85NC PIN-PACKAGE 20 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Applications
Distributed Power Systems DDR Memory Notebook Power
2.7V TO 5.5V VID0 VID1
Typical Operating Circuit
OUTPUT
VID0 VID1 IN
LX FB PGND
MAX15109
INX COMP PGOOD
SS
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator with VID Control MAX15109
ABSOLUTE MAXIMUM RATINGS
IN, PGOOD to PGND .............................................. -0.3V to +6V LX to PGND ................................................ -0.3V to (VIN + 0.3V) LX to PGND ..................................... -1V to (VIN + 0.3V) for 50ns EN, COMP, FB, SS, VID0, VID1 to PGND......................................... -0.3V to (VIN + 0.3V) LX Current (Note 1) ............................................... -12A to +12A Output Short-Circuit Duration .................................... Continuous Continuous Power Dissipation (TA = +70NC) WLP (derate 21.3mW/NC above TA = +70NC) .......... 745.5mW Operating Temperature Range .......................... -40NC to +85NC Operating Junction Temperature (Note 2) ......................+105NC Storage Temperature Range............................ -65NC to +150NC Soldering Temperature (reflow) (Note 3) ........................+260NC
Note 1: LX has internal clamp diodes to PGND and IN. Do not exceed the power dissipation limits of the device when forward biasing these diodes. Note 2: Limit the junction temperature to +105NC for continuous operation at full current. Note 3: The WLP package is constructed using a unique set of package techniques that impose a limit on the thermal profile the device can be exposed to during board-level solder attach and rework. This limit permits only the use of the solder profiles recommended in the industry-standard specification JEDEC 020A, paragraph 7.6, Table 3 for IR/VPR and convection reflow. Preheating is required. Hand or wave soldering is not allowed.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 5V, CSS = 4.7nF, TA = TJ = -40NC to +85NC. Typical values are at TA = +25NC, unless otherwise noted.) (Note 4) PARAMETER IN Voltage Range IN Shutdown Supply Current IN Supply Current VIN Undervoltage Lockout Threshold VIN Undervoltage Lockout Hysteresis ERROR AMPLIFIER Transconductance Voltage Gain Output Voltage Accuracy FB Input Bias Current COMP to Current-Sense Transconductance COMP Clamp Low Compensation RAMP Valley POWER SWITCHES High-Side Switch Current-Limit Threshold Low-Side Switch Sink Current-Limit Threshold Low-Side Switch Source Current-Limit Threshold IHSCL 14 14 14 A A A gMV AVEA VFB IFB GMOD VFB = 0.68V Over line, load, and temperature -1 -100 25 0.93 1 1.4 90 +1 +100 mS dB % nA A/V V V IIN SYMBOL VIN VEN = 0V VEN = 5V, VFB = 1V, not switching LX starts switching, VIN rising LX stops switching, VIN falling CONDITIONS MIN 2.7 0.3 3.4 2.6 200 TYP MAX 5.5 3 6 2.7 UNITS V FA mA V mV
2
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High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator with VID Control
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 5V, CSS = 4.7nF, TA = TJ = -40NC to +85NC. Typical values are at TA = +25NC, unless otherwise noted.) (Note 4) PARAMETER LX Leakage Current RMS LX Output Current OSCILLATOR Switching Frequency Maximum Duty Cycle Minimum Controllable On-Time ENABLE EN Input High Threshold Voltage EN Input Low Threshold Voltage EN Input Leakage Current VID CONTROL INPUTS VID_ High Threshold Voltage VID_ Low Threshold Voltage VID1 Input Leakage Current VID0 Input Leakage Current SOFT-START, PREBIAS Soft-Start Current SS Discharge Resistance SS Prebias Mode Stop Voltage HICCUP Number of Consecutive Current-Limit Events to Hiccup Timeout POWER-GOOD OUTPUT VID0 0 0 1 1 VID1 0 1 0 1 824 705 654 580 559 853 729 677 602 578 22 884 755 701 624 600 100 1 +160 Temperature falling 25 8 1024 Events Clock Cycles ISS RSS VSS = 0.45V, sourcing ISS = 10mA, sinking SS rising 10 8.5 0.58 FA I V VVID_ rising VVID_ falling VVID1 = 5V VVID0 = 5V 0.67 0.33 30 1 V V FA FA VEN rising VEN falling VEN = 5V 1.3 0.4 1 V V FA fSW DMAX 850 1000 94 100 1150 kHz % ns SYMBOL VEN = 0V 8 CONDITIONS MIN TYP MAX 10 UNITS FA A
MAX15109
PGOOD Threshold
PGT
FB rising
mV
FB falling PGOOD VOL PGOOD Leakage THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis IPGOOD = 5mA, VFB = 0.5V VPGOOD = 5V, VFB = 0.68V
mV mV FA NC NC
Note 4: Specifications are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by design and characterization.
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3
High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator with VID Control MAX15109
Typical Operating Characteristics
(Circuit of Typical Application Circuit, TA = +25NC, unless otherwise noted.)
EFFICIENCY vs. OUTPUT CURRENT (VIN = 5V)
MAX15109 toc01
EFFICIENCY vs. OUTPUT CURRENT (VIN = 3.3V)
MAX15109 toc02
OUTPUT VOLTAGE vs. SUPPLY VOLTAGE (VOUT = 0.9V)
MAX15109 toc03a
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 1 2 3 4 5
VOUT = 0.9V
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0
VOUT = 0.9V
0.915 0.910 OUTPUT VOLTAGE (V) 0.905 0.900 0.895 0.890 0.885
VOUT = 0.675V
VOUT = 0.725V VOUT = 0.8V
VOUT = 0.675V
VOUT = 0.725V VOUT = 0.8V
4A LOAD
8A LOAD
6
7
8
0
1
2
3
4
5
6
7
8
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE vs. SUPPLY VOLTAGE (VOUT = 0.675V)
MAX15109 toc03b
OUTPUT VOLTAGE vs. OUTPUT CURRENT (VOUT = 0.9V)
MAX15109 toc04a
0.690 0.685 OUTPUT VOLTAGE (V) 0.680 0.675 0.670 0.665 0.660 2.7 3.1 3.5 3.9 4.3 4.7 5.1
0.915 0.910 OUTPUT VOLTAGE (V) 0.905 0.900 0.895 0.890 0.885
4A LOAD
VIN = 5V
8A LOAD
VIN = 3.3V
5.5
0
1
2
3
4
5
6
7
8
SUPPLY VOLTAGE (V)
OUTPUT CURRENT (A)
OUTPUT VOLTAGE vs. OUTPUT CURRENT (VOUT = 0.675V)
MAX15109 toc04b
OUTPUT VOLTAGE ERROR vs. SUPPLY VOLTAGE
MAX15109 toc05
0.690 0.685 OUTPUT VOLTAGE (V) 0.680 0.675 0.670 0.665 0.660 0 1 2 3 4 5 6 7
0 -0.10 -0.20 -0.30 -0.40 -0.50
OUTPUT VOLTAGE ERROR (%)
VIN = 5V
VOUT = 0.675V
VIN = 3.3V
VOUT = 0.9V
8 -0.60 2.7 3.1 3.5 3.9 4.3
ILOAD = 8A
4.7 5.1 5.5
OUTPUT CURRENT (A)
SUPPLY VOLTAGE (V)
4
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High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator with VID Control
Typical Operating Characteristics (continued)
(Circuit of Typical Application Circuit, TA = +25NC, unless otherwise noted.)
LOAD-TRANSIENT RESPONSE (VIN = 5V, VOUT = 0.9V) SWITCHING WAVEFORMS (IOUT = 8A, VIN = 5V)
MAX15109
MAX15109 toc06
MAX15109 toc07
VOUT 10mV/div AC-COUPLED
VOUT 10mV/div AC-COUPLED
ILX 5A/div 4A IOUT 2A 40µs/div 400ns/div VLX 5V/div
SWITCHING WAVEFORM IN SKIP MODE (IOUT = 10mA, VIN = 5V)
MAX15109 toc08
SHUTDOWN WAVEFORM (ILOAD = 8A)
MAX15109 toc09
VOUT 10mV/div AC-COUPLED ILX 2A/div VLX 5V/div
VEN 2V/div VLX 5V/div ILX 5A/div VOUT 500mV/div VPGOOD 2V/div 10µs/div
40µs/div
SOFT-START WAVEFORMS (NO LOAD, SKIP MODE)
MAX15109 toc10a
SOFT-START WAVEFORMS (ILOAD = 8A)
VEN 2V/div VLX 5V/div
MAX15109 toc10b
VEN 2V/div VLX 5V/div
VOUT 500mV/div VPGOOD 5V/div 200µs/div 200µs/div
VOUT 500mV/div VPGOOD 5V/div
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5
High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator with VID Control MAX15109
Typical Operating Characteristics
(Circuit of Typical Application Circuit, TA = +25NC, unless otherwise noted.)
0.675V VID TRANSITIONS (VIN = 3.3V, IOUT = 8A) 0.725V VID TRANSITIONS (VIN = 3.3V, IOUT = 8A)
MAX15109 toc11a
MAX15109 toc11b
0.9V VOUT 50mV/div 0.8V 0.725V 0.675V 0.725V
0.9V VOUT 50mV/div 0.8V
0.675V
40µs/div
40µs/div
0.8V VID TRANSITIONS (VIN = 3.3V, IOUT = 8A)
MAX15109 toc11c
0.9V VID TRANSITIONS (VIN = 3.3V, IOUT = 8A)
MAX15109 toc11d
0.9V
0.9V VOUT 50mV/div
0.8V
VOUT 50mV/div 0.725V 0.675V
0.8V 0.725V 0.675V
40µs/div
40µs/div
INPUT SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
MAX15109 toc12
INPUT CURRENT vs. INPUT VOLTAGE
NO LOAD
4.0
INPUT CURRENT (mA)
MAX15109 toc13
2.0 INPUT SHUTDOWN CURRENT (µA) 1.6 1.2 0.8 0.4 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1
5.0
3.0 2.0 1.0 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 INPUT VOLTAGE (V)
5.5
SUPPLY VOLTAGE (V)
6
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High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator with VID Control
Typical Operating Characteristics (continued)
(Circuit of Typical Application Circuit, TA = +25NC, unless otherwise noted.)
RMS INPUT CURRENT vs. SUPPLY VOLTAGE
IIN 2A/div VOUT 500mV/div 0.7 RMS INPUT CURRENT (A) 0.6 0.5 0.4 0.3 0.2 0.1 0 400µs/div 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 SUPPLY VOLTAGE (V) SHORT-CIRCUIT ON OUTPUT
MAX15109 toc15
MAX15109
SHORT-CIRCUIT HICCUP MODE
MAX15109 toc14
0.8
IOUT 10A/div
FB VOLTAGE vs. TEMPERATURE (VOUT = 0.9V)
NO LOAD
MAX15109 toc16
SOFT-START WAVEFORMS (EXTERNAL REFIN)
MAX15109 toc17
0.915 0.910 FB VOLTAGE (V) 0.905 0.900 0.895 0.890 0.885 -40 -15 10 35 VIN = 3.3V VIN = 5V
VSS 500mV/div VOUT 500mV/div
VPGOOD 2V/div
60
65
100µs/div
TEMPERATURE (°C)
ENABLE INTO PREBIASED 0.5V OUTPUT (8A LOAD)
MAX15109 toc18
ENABLE INTO PREBIASED 0.5V OUTPUT (NO LOAD)
MAX15109 toc19
VEN 2V/div VOUT 500mV/div ILX 5A/div
VEN 2V/div VOUT 500mV/div ILX 2A/div
VPGOOD 2V/div
VPGOOD 2V/div 200µs/div
200µs/div
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7
High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator with VID Control MAX15109
Pin Configuration
BOTTOM VIEW
5 4
MAX15109 3 2 1
VID0
PGOOD
LX
LX
PGND
A
FB
I.C.
IN
LX
PGND
B
SS
VID1
IN
LX
PGND
C
COMP
EN
IN
INX
PGND
D
WLP
Pin Description
BUMP A1, B1, C1, D1 A2, A3, B2, C2 A4 A5 B3, C3, D3 B4 B5 C4 C5 NAME PGND LX PGOOD VID0 IN I.C. FB VID1 SS FUNCTION Power Ground. Low-side switch source terminal. Connect PGND and the return terminals of input and output capacitors to the power ground plane. Inductor Connection. Connect LX to the switching side of the inductor. LX is high impedance when the device is in shutdown mode. Open-Drain Power-Good Output. PGOOD goes low when VFB is below the PGOOD threshold. VID0 Logic Input. Use VID0 and VID1 to select output voltage. Input Power Supply. Input supply range is 2.7V to 5.5V. Bypass IN with a minimum 10FF ceramic capacitor to PGND. See the Typical Application Circuit. Internally Connected. Leave unconnected. Feedback Input. Connect FB to the sense the output voltage. VID1 Logic Input. Use VID0 and VID1 to select output voltage. Soft-Start and VID Transition Timing Control. Connect a capacitor from SS to PGND to set the startup time and the output voltage transition timing. See the Output Voltage Transition Timing section for details. Internally Unconnected. INX is not internally connected to IN. However, do externally connect INX to IN to increase the area of the power plane for optimal heat dissipation. Enable Input. EN is a digital input that turns the regulator on and off. Drive EN high to turn on the regulator. Connect to IN for always-on operation. Error Amplifier Output. Connect compensation network from COMP to signal ground (SGND). See the Compensation Design Guidelines section.
D2 D4 D5
INX EN COMP
8
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High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator with VID Control
Functional Diagram
MAX15109
EN
MAX15109
IN INX BIAS GENERATOR EN LOGIC, IN UVLO THERMAL SHDN SHDN
HIGH-SIDE CURRENT LIMIT VOLTAGE REFERENCE VREF CURRENT-SENSE AMPLIFIER LX LX
VID0 VID1
IN VID CONTROL STRONG PREBIAS FORCED_START 0.58V IN
SS CK SS BUFFER
CONTROL LOGIC
LX
IN 10µA PGND ERROR AMPLIFIER FB GROUND SENSE BUFFER RAMP OSCILLATOR RAMP GEN CK C LOW-SIDE SOURCE-SINK CURRENT LIMIT AND ZERO-CROSSING COMPARATOR SINK SOURCE ZX
COMP
POWER-GOOD COMPARATOR VPGT, VPGH
PGOOD
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9
High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator with VID Control MAX15109
Detailed Description
The MAX15109 high-efficiency, current-mode switching regulator delivers up to 8A of output current. The regulator operates from 2.7V to 5.5V and provides a VID selectable output. The IC current-mode control architecture uses a high gain transconductance error amplifier that facilitates an easy compensation design and ensures cycle-by-cycle current limit with fast response to line and load transients. The regulator features a 1MHz fixed switching frequency, allowing for all-ceramic capacitor designs with fast transient responses. The high operating frequency minimizes the size of external components. The IC is available in a 2.5mm x 2mm (4 x 5 array), 0.5mm pitch WLP package. The regulator offers skip-mode functionality to reduce current consumption and achieve a high efficiency at light output loads. The low RDS(ON) integrated switches ensure high efficiency at heavy loads while minimizing critical inductance, making the layout design a much simpler task than that of discrete solutions. The IC’s simple layout and footprint assure first-pass success in new designs. The IC has output voltages of 0.9V, 0.8V, 0.725V, and 0.625V by configuring the VID inputs. The regulator offers capacitor-programmable soft-start to reduce input inrush current. The device safely starts up into a prebiased output. The IC includes an enable input and opendrain PGOOD output for sequencing with other devices. The controller logic block determines the duty cycle of the high-side MOSFET under different line, load, and temperature conditions. Under normal operation, where the current-limit and temperature protection are not triggered, the controller logic block takes the output from the PWM comparator to generate the driver signals for both high-side and low-side MOSFETs. The control logic block controls the break-before-make logic and all the necessary timing. The high-side MOSFET turns on at the beginning of the oscillator cycle and turns off when the COMP voltage crosses the internal current-mode ramp waveform. The internal ramp is the sum of the compensation ramp and the current-mode ramp. The high-side MOSFET also turns off if the maximum duty cycle exceeds 95%, or when the current limit is reached. The low-side MOSFET turns on for the remainder of the switching cycle. The IC can soft-start into a prebiased output without discharging the output capacitor. In safe prebiased startup, both low-side and high-side MOSFETs remain off to avoid discharging the prebiased output. PWM operation starts when the voltage on SS crosses the voltage on FB.
Starting into a Prebiased Output
The IC can start into a prebiased voltage higher than the nominal set point without abruptly discharging the output. Forced PWM operation starts when the SS voltage reaches 0.58V, forcing the converter to start. When the low-side sink current-limit threshold of 14A is reached, the low-side switch turns off before the end of the clock period. The low-side sink current limit is 14A. The highside switch turns on until one of the following conditions is satisfied: • High-side source current hits the reduced high-side current limit (14A). The high-side switch turns off for the remaining time of clock period. • The clock period ends. Reduced high-side current limit is activated in order to recirculate the current into the high-side power switch rather than into the internal high-side body diode, which can cause damage to the devices. The high-side current limit is set to 14A. Low-side sink current limit protects the low-side switch from excessive reverse current during prebiased operation. The IC features independent device enable control and power-good signal that allow for flexible power sequencing. Drive the enable input (EN) high to enable the regulator, or connect EN to IN for always-on operation. Power-good (PGOOD) is an open-drain output that goes high when VFB is above the PGOOD threshold, and goes low if VFB is below the PGOOD threshold.
Controller Function—PWM Logic
Enable Input
10
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High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator with VID Control
The IC utilizes a soft-start feature to slowly ramp up the regulated output voltage to reduce input inrush current during startup. Connect a capacitor from SS to PGND to set the startup time. See the Output Voltage Transition Timing section for capacitor selection details. A high-gain error amplifier provides accuracy for the voltage feedback loop regulation. Connect a compensation network between COMP and SGND. See the Compensation Design Guidelines section. The error amplifier transconductance is 1.4mS. COMP clamp low is set to 0.8V, just below the PWM ramp compensation valley, helping COMP to rapidly return to the correct set point during load and line transients.
Programmable Soft-Start (SS)
Error Amplifier
turn-on without reaching the current limit. If the currentlimit condition persists, the counter fills up reaching eight events. The control logic then discharges SS, stops both high-side and low-side MOSFETs and waits for a hiccup period (1024 clock cycles) before attempting a new softstart sequence. The hiccup-mode also operates during soft-start. The IC contains an internal thermal sensor that limits the total power dissipation to protect it in the event of an extended thermal fault condition. When the die temperature exceeds +160NC, the thermal sensor shuts down the device, turning off the DC-DC converter to allow the die to cool. After the die temperature falls by 25NC, the device restarts, following the soft-start sequence. The IC operates in skip mode. When in skip mode, LX output becomes high impedance when the inductor current falls below 0.7A. The inductor current does not become negative. During a clock cycle, if the inductor current falls below the 0.7A threshold (during off-time), the low side turns off. At the next clock cycle, if the output voltage is above the set point the PWM logic keeps both high-side and low-side MOSFETs off. If instead the output voltage is below the set point, the PWM logic drives the high-side on for a minimum fixed on-time (330ns). In this way, the system skips cycles, reducing the frequency of operations, and switches only as needed to service load at the cost of an increase in output-voltage ripple. See the Skip Mode Frequency and Output Ripple section for details. In skip mode, power dissipation is reduced and efficiency improved at light loads because the internal power MOSFETs do not switch at every clock cycle.
MAX15109
Thermal Shutdown Protection
The PWM comparator compares COMP voltage to the current-derived ramp waveform (LX current to COMP voltage transconductance value is 25A/V). To avoid instability due to subharmonic oscillations when the duty cycle is around 50% or higher, a compensation ramp is added to the current-derived ramp waveform. The compensation ramp slope (0.3V x 1MHz = 0.3V/Fs) is equivalent to half of the inductor current down-slope in the worst case (load 2A, current ripple 30% and maximum duty-cycle operation of 95%). The compensation ramp valley is set to 1V. When the converter output is connected to ground or the device is overloaded, each high-side MOSFET currentlimit event (14A) turns off the high-side MOSFET and turns on the low-side MOSFET. A 3-bit counter increments on each current-limit event. The counter is reset after three consecutive events of high-side MOSFET
PWM Comparator
Skip Mode Operation
Overcurrent Protection and Hiccup
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11
High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator with VID Control MAX15109
Applications Information
Setting the Output Voltage The output voltage is selected by using the VID0 and VID1 control inputs. Table 1 summarizes the output voltages. where fSW is the internally fixed 1MHz switching frequency, and DIL is the estimated inductor ripple current (typically set to 0.3 x ILOAD). In addition, the peak inductor current, IL_PK, must always be below the high-side current-limit value, IHSCL, and the inductor saturation current rating, IL_SAT. Ensure that the following relationship is satisfied: IL_PK = ILOAD + 1 × ∆IL < MIN(IHSCL ,IL_SAT ) 2
Table 1. Output Voltages
VID0 0 0 1 1 VID1 0 1 0 1 VOLTAGE (V) 0.9 0.8 0.725 0.675
A large inductor value results in reduced inductor ripple current, leading to a reduced output ripple voltage. A high-value inductor is of a larger physical size with a higher series resistance (DCR) and a lower saturation current rating. Choose inductor values to produce a ripple current equal to 30% of the load current. Choose the inductor with the following formula: L= V VOUT × 1- OUT fSW × ∆IL VIN
Inductor Selection
For a step-down converter, the input capacitor CIN helps to keep the DC input voltage steady, in spite of discontinuous input AC current. Use low-ESR capacitors to minimize the voltage ripple due to ESR. Size CIN using the following formula: CIN = ILOAD V × OUT fSW × ∆VIN_RIPPLE VIN
Input Capacitor Selection
FEEDBACK DIVIDER VOUT
ERROR AMPLIFIER
POWER MODULATOR
OUTPUT FILTER AND LOAD
COMPENSATION RAMP
VIN
FB COMP
C
gMC
QHS L CONTROL LOGIC PWM COMPARATOR QLS DCR IL
VOUT
ESR COUT
RLOAD
gMV
ROUT
RC
*CCC
CC VCOMP ROUT = AVEA/gMV SS *CCC IS OPTIONAL. GMOD VOUT IL NOTE: THE GMOD STAGE SHOWN ABOVE MODELS THE AVERAGE CURRENT OF THE INDUCTOR INJECTED INTO THE OUTPUT LOAD. THIS REPRESENTS A SIMPLIFICATION FOR THE POWER MODULATOR STAGE DRAWN ABOVE.
Figure 1. Peak Current-Mode Regulator Transfer Model 12 _____________________________________________________________________________________
High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator with VID Control
Make sure that the selected capacitance can accommodate the input ripple current given by: IRMS= IO × VOUT × (VIN - VOUT ) VIN In skip mode, the switching frequency (fSKIP) and output ripple voltage (VOUT-RIPPLE) shown in Figure 3 are calculated as follows: tON is a fixed time by design (330ns, typ); the peak inductor current reached is: V − VOUT I SKIP −LIMIT = IN × t ON 2AV tOFF1 is the time needed for the inductor current to reach the zero-crossing (~0A): t OFF1 = L × I SKIP-LIMIT VOUT
Skip Mode Frequency and Output Ripple
MAX15109
If necessary, use multiple capacitors in parallel to meet the RMS current rating requirement. Use low-ESR ceramic capacitors to minimize the voltage ripple due to ESR. Use the following formula to estimate the total output voltage peak-to-peak ripple:
∆VOUT = VOUT VOUT 1 × 1 × R ESR_COUT + fSW × L VIN 8 × fSW × C OUT
Output Capacitor Selection
Select the output capacitors to produce an output ripple voltage that is less than 2% of the set output voltage. The IC features programmable output voltage transition timing control. The regulator tracks the voltage on the SS pin that is set with a current-limited (10µA) VID DAC. A small capacitor at SS can therefore be used to set the transition timing for startup and VID transitions. I x ∆t C SS = SS ∆VOUT where ISS is the soft-start current of 10FA, δVOUT is the output-voltage transition, and δt is the transition time. When using large COUT capacitance values, the highside current limit can trigger during the soft-start period. To ensure the correct soft-start time, tSS, choose CSS large enough to satisfy: C SS >> C OUT = VOUT × I SS (IHSCL_MIN - I OUT ) × VFB
Output Voltage Transition Timing
During tON and tOFF1, the output capacitor stores a charge equal to:
1 1 2 L × (I SKIP-LIMIT - ILOAD ) × + VIN - VOUT VOUT ∆Q OUT = 2
During tOFF2 (= n x tCK, number of clock cycles skipped), the output capacitor loses this charge:
t OFF2 = ∆Q OUT → ILOAD
1 1 2 L × (I SKIP-LIMIT - ILOAD ) × + VIN - VOUT VOUT t OFF2 = 2 × ILOAD
Finally, frequency in skip mode is: fSKIP = 1 t ON + t OFF1 + t OFF2
IHSCL_MIN is the minimum high-side switch current-limit value.
Output ripple in skip mode is:
RSS VREF_EXT CSS SS
(ISKIP-LIMIT - ILOAD ) × t ON + R ESR,COUT × (I SKIP-LIMIT - ILOAD ) C OUT
MAX15109
VOUT-RIPPLE = VCOUT-RIPPLE + VESR-RIPPLE =
VOUT-RIPPLE = L × ISKIP-LIMIT + R ESR,COUT × (I SKIP-LIMIT - ILOAD ) C OUT × (VIN - VOUT )
Figure 2. Setting Soft-Start Time
Size COUT based on the above formula to limit output ripple in skip mode.
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High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator with VID Control MAX15109
The IC uses a fixed-frequency, peak-current-mode control scheme to provide easy compensation and fast transient response. The inductor peak current is monitored on a cycle-by-cycle basis and compared to the COMP voltage (output of the voltage error amplifier). The regulator’s duty cycle is modulated based on the inductor’s peak current value. This cycle-by-cycle control of the inductor current emulates a controlled current source. As a result, the inductor’s pole frequency is shifted beyond the gain bandwidth of the regulator. System stability is provided with the addition of a simple series capacitor-resistor from COMP to PGND. This pole-zero combination serves to tailor the desired response of the closed-loop system. The basic regulator loop consists of a power modulator (comprising the regulator’s pulsewidth modulator, compensation ramp, control circuitry, MOSFETs, and inductor), the capacitive output filter and load, an output feedback, and a voltage-loop error amplifier with its associated compensation circuitry. See Figure 1. The average current through the inductor is expressed as: IL = G MOD × VCOMP where IL is the average inductor current and GMOD is the power modulator’s transconductance. For a buck converter: VOUT = R LOAD × IL where RLOAD is the equivalent load resistor value. Combining the above two relationships, the power modulator’s transfer function in terms of VOUT with respect to VCOMP is: R ×I VFB = LOAD L = R LOAD × GMOD VCOMP IL G MOD Having defined the power modulator’s transfer function gain, the total system loop gain can be written as follows (see Figure 1): α= s(C C + C CC )(R C + R OUT ) + 1 × s(C C || C CC )(R C || R OUT ) + 1 R OUT × (sC CR C + 1)
Compensation Design Guidelines
β = G MOD × R LOAD ×
(sC OUTESR + 1) sC OUT (ESR + R LOAD ) + 1
Gain =
R2 A × VEA × α × β R1 + R 2 R OUT
where ROUT is the quotient of the error amplifier’s DC gain, AVEA, divided by the error amplifier’s transconductance, gMV; ROUT is much larger than RC. R2 V = FB R1 + R 2 VOUT Also, CC is much larger than CCC, therefore: C C + C CC ≈ C C and C C || C CC ≈ C CC Rewriting: Gain =
(sC CR C + 1) VFB A VEA × × VOUT A VEA sC C + 1 × (sC CCR C + 1) gMV
sC OUT (ESR + R LOAD ) + 1
G MOD R LOAD ×
(sC OUTESR + 1)
The dominant poles and zeros of the transfer loop gain are shown below: fP1 = gMV AVEA_dB/20 × C 2π × 10
C
fP2 =
1 2π × C OUT (ESR + R LOAD ) fP3 = fZ1 = fZ2 = 1 2π × C CCR C 1 2π × C CR C
1 2π × C OUTESR
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High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator with VID Control
The order of pole-zero occurrence is: fP1 < fP2 < fZ1 < fZ2 ≤ fP3 Under heavy load, fP2, approaches fZ1. A graphical representation of the asymptotic system closed-loop response, including dominant pole and zero locations is shown in Figure 3. If COUT is large, or exhibits a lossy equivalent series resistance (large ESR), the circuit’s second zero might come into play around the crossover frequency (fCO = ω/2G). In this case, a third pole can be induced by a second (optional) small compensation capacitor (CCC), connected from COMP to PGND. The loop response’s fourth asymptote (in bold, Figure 4) is the one of interest in establishing the desired crossover frequency (and determining the compensation component values). A lower crossover frequency provides for stable closed-loop operation at the expense of a slower load and line transient response. Increasing the crossover frequency improves the transient response at the (potential) cost of system instability. A standard rule of thumb sets the crossover frequency P 1/10th of the switching frequency. First, select the passive and active power components that meet the application’s requirements. Then, choose the small-signal compensation components to achieve the desired closed-loop frequency response and phase margin as outlined in the Closing the Loop: Designing the Compensation Circuitry section. Select RC using the transfer-loop’s fourth asymptote gain (assuming fCO > fP1, fP2, and fZ1 and setting the overall loop gain to unity) as follows: 1= VFB × gMV × R C × G MOD × R LOAD × VOUT 1 2π × fCO × C OUT × (ESR + R LOAD ) therefore: 2π × fCO × C OUT × (ESR + R LOAD ) V R C = OUT × VFB gMV × G MOD × R LOAD For RLOAD much greater than ESR, the equation can be further simplified as follows: V 2π × fCO × C OUT R C = OUT × VFB gMV × G MOD where VFB is equal to 0.6V. Determine CC by selecting the desired first system zero, fZ1, based on the desired phase margin. Typically, setting fZ1 below 1/5th of fCO provides sufficient phase margin. f 1 fZ1 = ≤ CO 2π × C CR C 5 Therefore: CC ≥ 5 2π × fCO × R C
MAX15109
Select the desired crossover frequency. Choose fCO approximately 1/10th of the switching frequency fSW, or fCO ≈ 100kHz.
Closing the Loop: Designing the Compensation Circuitry
IL ISKIP-LIMIT ILOAD tON VOUT VOUT-RIPPLE tOFF1 tOFF2 = n x tCK
Figure 3. Skip-Mode Waveforms ______________________________________________________________________________________ 15
High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator with VID Control MAX15109
If the ESR output zero is located at less than one-half the switching frequency, use the (optional) secondary compensation capacitor, CCC, to cancel it, as follows: 1 1 = fP3 = fZ2 = 2π × C CCR C 2π × C OUTESR therefore: C CC = C OUT × ESR RC therefore: C CC = 2 2π × fSW × R C
Overall CCC detracts from the overall system phase margin. Place this third pole well beyond the desired crossover frequency to minimize the interaction with the system loop response at crossover. Ignore CCC in these calculations if CCC is smaller than 10pF. The IC is available in a 20-bump WLP package and can dissipate up to 745.5mW at TA = +70NC. When the die temperature exceeds +160NC, the thermal-shutdown protection is activated. See the Thermal Shutdown Protection section.
Power Dissipation
If the ESR zero exceeds 1/2 the switching frequency, use the following equation: fP3 = f 1 = SW 2π × C CCR C 2
GAIN
1ST ASYMPTOTE VFB x VOUT -1 x 10AVEA[dB]/20 x GMOD x RLOAD 2ND ASYMPTOTE VFB x VOUT -1 x gMV x (CC)-1 x GMOD x RLOAD
3RD ASYMPTOTE VFB x VOUT -1 x gMV x (CC)-1 x GMOD x RLOAD x (COUT(ESR + RLOAD))-1 4TH ASYMPTOTE VFB x VOUT -1 x gMV x RC x GMOD x RLOAD x (COUT(ESR + RLOAD))-1 3RD POLE (CCCRC)-1 2ND ZERO (COUTESR)-1 UNITY 1ST POLE gMV x (10AVEA[dB]/20 CC)-1 1ST ZERO (CCRC)-1 2ND POLE (COUT(ESR + RLOAD))-1 CO RAD/S
5TH ASYMPTOTE VFB x VOUT -1 x gMV x RC x GMOD x (ESR || RLOAD) 6TH ASYMPTOTE VFB x VOUT -1 x gMV x (CCC)-1 x GMOD x (ESR || RLOAD)
Figure 4. Asymptotic Loop Response of Peak Current-Mode Regulator 16 _____________________________________________________________________________________
High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator with VID Control
Careful PCB layout is critical to achieve clean and stable operation. It is highly recommended to duplicate the MAX15109 evaluation kit layout for optimum performance. If deviation is necessary, follow these guidelines for good PCB layout: 1) Connect input and output capacitors to the power ground plane. 2) Place bypass capacitors as close to IN and the softstart capacitor as close to SS as possible. 3) Keep the high-current paths as short and wide as possible. Keep the path of switching current short and minimize the loop area formed by LX, the output capacitors, and the input capacitors.
Layout Procedure
4) Connect IN, LX, and PGND separately to a large copper area to help cool the IC to further improve efficiency. 5) Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close as possible to the IC. 6) Route high-speed switching nodes (such as LX) away from sensitive analog areas (such as FB, COMP, SGND, and SS).
MAX15109
Typical Application Circuit
VID0 2.7V TO 5.5V CIN2 22µF CIN2 22µF VID1 EN IN RPULL 100kI INX PGOOD REXT_REF 1kI CSS 33nF SS
LX
OUTPUT LOUT 0.56µH COUT2 47µF COUT1 0.1µF
FB
MAX15109
PGND
COMP REA 2.43kI CEA2 100pF CEA 6800pF
______________________________________________________________________________________
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High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator with VID Control MAX15109
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 20 WLP PACKAGE CODE W202D2Z+1 OUTLINE NO. 21-0505 LAND PATTERN NO. Refer to Application Note 1891
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High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulators with VID Control
Revision History
REVISION NUMBER 0 REVISION DATE 6/11 Initial release DESCRIPTION PAGES CHANGED —
MAX15109
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2011 Maxim Integrated Products
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