19-5967; Rev 0; 6/11
EVALUATION KIT AVAILABLE
MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
General Description
The MAX15118 high-efficiency, current-mode step-down regulator with integrated power switches operates from 2.7V to 5.5V and delivers up to 18A of output current in a small 2mm x 3.5mm package. The MAX15118 offers excellent efficiency with skip mode capability at lightload conditions, yet provides unmatched efficiency under heavy load conditions. The combination of small size and high efficiency makes this device suitable for both portable and nonportable applications. The MAX15118 utilizes a current-mode control architecture with a high-gain transconductance error amplifier, which allows a simple compensation scheme and enables a cycle-by-cycle current limit with fast response to line and load transients. A factory-trimmed switching frequency of 1MHz (PWM operation) allows for a compact, all-ceramic capacitor design. Integrated switches with low on-resistance ensure high efficiency at heavy loads while minimizing critical inductances. The MAX15118’s simple layout and footprint assure first-pass success in new designs. Other features of the MAX15118 include a capacitorprogrammable soft-start to reduce inrush current, safe startup into a prebiased output, an enable input, and a power-good output for power sequencing. The regulator is available in a 28-bump (4 x 7), 2.10mm x 3.56mm WLP package, and is fully specified over the -40NC to +85NC extended temperature range.
Features
S Continuous18AOutputCurrentOverTemperature S ±1%FeedbackAccuracyOverLoad,Line,and Temperature S Operatesfrom2.7Vto5.5VSupply S InputUndervoltageLockout S AdjustableOutputRangefrom0.6VUpto0.94xVIN S ProgrammableSoft-Start S Factory-Trimmed1MHzSwitchingFrequency S StablewithLow-ESRCeramicOutputCapacitors S Safe-StartupintoaPrebiasedOutput S ExternalReferenceInput S SelectableSkipModeOptionforImproved EfficiencyatLightLoads S EnableInput/PGOODOutputAllowsSequencing S RemoteGroundSenseforImprovedAccuracy S ThermalandOvercurrentProtection S Tiny2.10mmx3.56mm,28-BumpWLPPackage
Applications
Notebooks Servers Distributed Power Systems
Ordering Information appears at end of data sheet.
DDR Memory Base Stations
Typical Operating Circuits
ON OFF EN SKIP AIN VIN = 2.7V TO 5.5V IN CIN PGOOD PGOOD SS/REFIN CSS PWM MODE OPERATION GND CCC COMP RC CC R2 RPULL FB LX BST CBST LOUT COUT GSNS R1 VOUT
MAX15118
Typical Operating Circuits continued at end of data sheet.
For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/MAX15118.related
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Forpricing,delivery,andorderinginformation,pleasecontactMaximDirectat1-888-629-4642, orvisitMaxim’swebsiteatwww.maxim-ic.com.
MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
ABSOLUTEMAXIMUMRATINGS
IN, PGOOD to GND ................................................ -0.3V to +6V EN, COMP, FB, SS/REFIN, GSNS, SKIP, LX to GND .............................................. -0.3V to (VIN + 0.3V) LX to GND (for 50ns)........................................ -1V to (VIN + 1V) LX to GND (for 10ns)........................................ -2V to (VIN + 2V) BST to LX................................................................. -0.3V to +6V BST to GND ........................................................... -0.3V to +12V BST to IN ................................................................. -0.3V to +6V LX Continuous Current (Note 1) ......................................... Q20A Output Short-Circuit Duration ................................... Continuous Continuous Power Dissipation WLP (derate 81.53mW/NC above +70NC)...................... 3.26W Operating Temperature Range .......................... -40NC to +85NC Junction Temperature (Note 2) .......................................+110NC Storage Temperature Range............................ -65NC to +150NC Bump Reflow Temperature (Note 3) ...............................+260NC
Note1: LX has internal clamp diodes to GND and IN. Applications that forward bias these diodes must take care not to exceed the IC’s package power dissipation limits. Note2: Limit the junction temperature to +110NC for continuous operation at maximum output current. Note3: The WLP package is constructed using a unique set of package techniques that impose a limit on the thermal profile. The device can be exposed to during board-level solder attach and rework. This limit permits only the use of the solder profiles recommended in the industry-standard specification JEDEC 020A, paragraph 7.6, Table 3 for IR/VPR and convection reflow. Preheating is required. Hand or wave soldering is not allowed.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DCELECTRICALCHARACTERISTICS
(VIN = 5V, see the Typical Operating Circuits, TA = -40NC to +85NC. Typical values are at TA = +25NC, unless otherwise noted.) (Note 4) PARAMETER IN Voltage Range IN Supply Current IN Shutdown Current IN Undervoltage Lockout Threshold IN Undervoltage Lockout Threshold Hysteresis ERRORAMPLIFIER Transconductance Voltage Gain FB Setpoint Voltage FB Input Bias Current COMP to Current-Sense Transconductance COMP Clamp Low Voltage Slope Compensation Ramp Amplitude VSLOPE gM AVEA VFB IFB gMC VFB = 0.65V, VSS/REFIN = 0.6V Over line, load, and temperature 0.594 -500 150 0.97 130 1.2 90 0.600 0.606 +500 mS dB V nA A/V V mV SYMBOL VIN IIN ISHDN VUVLO VEN = VIN, VFB = 0.65V, no switching VEN = 0V VIN rising, LX starts switching VIN falling, LX stops switching CONDITIONS MIN 2.7 4.8 0.01 2.6 200 TYP MAX 5.5 7 3 2.68 UNITS V mA FA V mV
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MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
DCELECTRICALCHARACTERISTICS(continued)
(VIN = 5V, see the Typical Operating Circuits, TA = -40NC to +85NC. Typical values are at TA = +25NC, unless otherwise noted.) (Note 4) PARAMETER GROUNDSENSE GSNS Output Current POWERSWITCHES High-side switch Current-Limit Threshold LX Leakage Current BST Leakage Current BST On-Resistance LX RMS Output Current OSCILLATOR Switching Frequency Maximum Duty Cycle Minimum Controllable On-Time ENABLEFUNCTIONALITY EN Input High Threshold EN Input Low Threshold EN Input Leakage Current SKIPFUNCTIONALITY(Note5) SKIP Input High Threshold SKIP Input Low Threshold SKIP Pulldown Resistor Minimum LX On-Current in Skip Mode Zero-Crossing LX Threshold SOFT-STARTANDPREBIASFUNCTIONALITY Soft-Start Current SS/REFIN Discharge Resistance SS/REFIN Prebias Mode Stop Voltage SS/REFIN External Reference Input Range HICCUPMODE Number of Consecutive CurrentLimit Events to Hiccup Mode Hiccup Mode Timeout NHIC 8 1024 Events Clock Cycles ISS RSS VSS/REFIN = 0.45V, sourcing ISS/REFIN = 10mA, sinking VSS/REFIN rising 6.8 10 7 0.58 VIN 2.5 12.5 FA I V V VSKIP rising VSKIP falling 0.4 210 3.6 0.5 1.4 V V kI A A VIH VIL VEN rising VEN falling 0.4 -1 +1 1.4 V V FA fSW DMAX tON PWM mode Skip mode 850 1000 94 85 70 1150 kHz % ns RON_BST Low-side switch, sinking Low-side switch, sourcing VEN = 0V VEN = 0V IBST = 50mA 18 0.63 30 30 30 3 3 FA FA I A A VSS/REFIN = 0.6V, VGSNS = 0V 56 FA SYMBOL CONDITIONS MIN TYP MAX UNITS
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MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
DCELECTRICALCHARACTERISTICS(continued)
(VIN = 5V, see the Typical Operating Circuits, TA = -40NC to +85NC. Typical values are at TA = +25NC, unless otherwise noted.) (Note 4) PARAMETER POWER-GOODOUTPUT PGOOD Threshold PGOOD Threshold Hysteresis PGOOD Output Voltage Low PGOOD Leakage Current THERMALSHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis TSHDN Die temperature rising +150 20 NC NC VPG_OL IPG_LK VFB falling, PGOOD deasserts VFB rising IPGOOD = 5mA, VEN = 0V VPGOOD = 5.5V, VFB = 0.65V 0.514 0.530 25 18 50 1 0.542 V mV mV FA SYMBOL CONDITIONS MIN TYP MAX UNITS
Note4: All devices are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by design. Note5: Connect SKIP to EN for skip mode functionality. Connect SKIP to GND for PWM mode functionality.
Typical Operating Characteristics
(VIN = 5V, VOUT = 1.5V, CSS = 0.1µF, see the Typical Operating Circuits, TA = +25°C, unless otherwise noted.)
EFFICIENCY vs. OUTPUT CURRENT (VIN = 5V, PWM MODE)
MAX15118 toc01
EFFICIENCY vs. OUTPUT CURRENT (VIN = 3.3V, PWM MODE)
MAX15118 toc02
EFFICIENCY vs. OUTPUT CURRENT (VIN = 5V, SKIP MODE)
95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V VOUT = 0.8V VOUT = 3.3V
MAX15118 toc03
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 0 2 4 6 8
VOUT = 3.3V
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 VOUT = 0.8V
VOUT = 2.5V
100
VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V VOUT = 0.8V
VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V
10
12
14
16
18
0
2
4
6
8
10
12
14
16
18
0
2
4
6
8
10
12
14
16
18
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
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MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
Typical Operating Characteristics (continued)
(VIN = 5V, VOUT = 1.5V, CSS = 0.1µF, see the Typical Operating Circuits, TA = +25°C, unless otherwise noted.)
EFFICIENCY vs. OUTPUT CURRENT (VIN = 3.3V, SKIP MODE)
95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 0 2 4 6 8 10 12 14 16 18 OUTPUT CURRENT (A) 900 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 INPUT VOLTAGE (V) VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V VOUT = 0.8V VOUT = 2.5V
MAX15118 toc04
SWITCHING FREQUENCY vs. INPUT VOLTAGE
TA = +85°C
MAX15118 toc05
100
1100
SWITCHING FREQUENCY (kHz)
1050
TA = +25°C
1000 TA = -40°C
950
OUTPUT VOLTAGE vs. SUPPLY VOLTAGE (PWM MODE, VOUT = 1.5V)
MAX15118 toc06a
OUTPUT VOLTAGE vs. SUPPLY VOLTAGE (SKIP MODE, VOUT = 1.5V)
MAX15118 toc06b
1.520 1.515 OUTPUT VOLTAGE (V) 1.510 1.505 1.500 1.495 1.490 1.485 1.480 2.7 3.1 3.5 3.9 4.3 4.7 SUPPLY VOLTAGE (V) 5.1
ILOAD = 18A ILOAD = 10A
1.53 1.52 OUTPUT VOLTAGE (V) 1.51 1.50 1.49 1.48 1.47 2.7 3.1 3.5 3.9 4.3 4.7 5.1 ILOAD = 10A ILOAD = 2A NO LOAD
5.5
5.5
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE ERROR vs. SUPPLY VOLTAGE
MAX15118 toc07
OUTPUT VOLTAGE vs. OUTPUT CURRENT (PWM MODE, VOUT = 1.5V)
MAX15118 toc08a
0.50 0.40 OUTPUT VOLTAGE ERROR (%) 0.30 0.20 0.10 0 -0.10 -0.20 -0.30 -0.40 -0.50 2.90 3.55 4.20 VOUT = 1.5V VOUT = 1.8V ILOAD = 18A 4.85 VOUT = 1.2V NORMALIZED AT VIN = 3.5V
1.53 1.52 OUTPUT VOLTAGE (V) VIN = 5V 1.51 1.50 1.49 1.48 1.47 VIN = 3.3V
5.50
0
2
4
6
8
10
12
14
16
18
SUPPLY VOLTAGE (V)
OUTPUT CURRENT (A)
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MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
Typical Operating Characteristics (continued)
(VIN = 5V, VOUT = 1.5V, CSS = 0.1µF, see the Typical Operating Circuits, TA = +25°C, unless otherwise noted.)
OUTPUT VOLTAGE vs. OUTPUT CURRENT (SKIP MODE, VOUT = 1.5V)
MAX15118 toc08b
LOAD-TRANSIENT RESPONSE (VIN = 5V, VOUT = 1.5V, IOUT = 0.1A TO 9A)
MAX15118 toc09
1.53 1.52 OUTPUT VOLTAGE (V) VIN = 5V 1.51 1.50 1.49 1.48 1.47 0 2 4 6 8 10 12 14 16 VIN = 3.3V
PWM MODE
VOUT 50mV/div AC-COUPLED 9A IOUT 5A/div 0.1A
18
100µs/div
OUTPUT CURRENT (A)
LOAD-TRANSIENT RESPONSE (VIN = 3.3V, VOUT = 1.5V, ILOAD = 0.1A TO 9A)
MAX15118 toc10
LOAD-TRANSIENT RESPONSE (VIN = 5V, VOUT = 1.5V, ILOAD = 0.1A TO 9A)
MAX15118 toc11
PWM MODE
SKIP MODE
VOUT 50mV/div AC-COUPLED 9A IOUT 5A/div 0.1A
VOUT 50mV/div AC-COUPLED 9A IOUT 5A/div 0.1A
100µs/div
100µs/div
LOAD-TRANSIENT RESPONSE (VIN = 3.3V, VOUT = 1.5V, ILOAD = 0.1A TO 9A)
MAX15118 toc12
LOAD-TRANSIENT RESPONSE (VIN = 5V, VOUT = 1.5V, ILOAD = 1.8A TO 16A)
MAX15118 toc13
SKIP MODE
PWM MODE VOUT 50mV/div AC-COUPLED 16A 9A IOUT 5A/div 0.1A IOUT 5A/div 1.8A
VOUT 50mV/div AC-COUPLED
100µs/div
100µs/div
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MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
Typical Operating Characteristics (continued)
(VIN = 5V, VOUT = 1.5V, CSS = 0.1µF, see the Typical Operating Circuits, TA = +25°C, unless otherwise noted.)
LOAD-TRANSIENT RESPONSE (VIN = 3.3V, VOUT = 1.5V, ILOAD = 1.8A TO 16A)
MAX15118 toc14
SWITCHING WAVEFORMS (VIN = 5V, VOUT = 1.5V, ILOAD = 1.8A)
MAX15118 toc15
PWM MODE VOUT 50mV/div AC-COUPLED 16A IOUT 5A/div 1.8A
VOUT 20mV/div AC-COUPLED ILX 10A/div
VLX 2V/div
100µs/div
400ns/div
SWITCHING WAVEFORMS (VIN = 3.3V, VOUT = 1.5V, ILOAD = 18A)
MAX15118 toc16
SWITCHING WAVEFORMS IN SKIP MODE (VIN = 3.3V, VOUT = 1.5V, ILOAD = 10mA)
MAX15118 toc17
VOUT 20mV/div AC-COUPLED ILX 10A/div
VOUT 20mV/div AC-COUPLED ILX 5A/div
VLX 2V/div
VLX 2V/div
400ns/div
2µs/div
SHUTDOWN WAVEFORMS (VIN = 3.3V, VOUT = 1.5V, ILOAD = 9A)
MAX15118 toc18
SOFT-START WAVEFORMS (PWM MODE, ILOAD = 10A)
VENABLE 2V/div
MAX15118 toc19
VENABLE 2V/div VOUT 1V/div ILX 5A/div VPGOOD 2V/div
1ms/div
VOUT 500mV/div ILX 5A/div VPGOOD 2V/div
100µs/div
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MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
Typical Operating Characteristics (continued)
(VIN = 5V, VOUT = 1.5V, CSS = 0.1µF, see the Typical Operating Circuits, TA = +25°C, unless otherwise noted.)
SOFT-START WAVEFORMS (SKIP MODE, ILOAD = 2A) QUIESCENT CURRENT (SHUTDOWN)
VENABLE 2V/div VOUT 1V/div ILX 5A/div VPGOOD 2V/div
1ms/div RMS INPUT CURRENT (µA) VEN = 0V
MAX15118 toc21
MAX15118 toc20
1.5 1.2 0.9 0.6 0.3 0 2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY VOLTAGE (V)
HICCUP MODE (SHORT ON OUTPUT)
MAX15118 toc22
RMS INPUT CURRENT vs. SUPPLY VOLTAGE
IOUT 10A/div
RMS INPUT CURRENT (A) SHORT CIRCUIT ON OUTPUT
MAX15118 toc23
1.5 1.2 0.9 0.6 0.3 0 2.7
VOUT 500mV/div IIN 2A/div VIN 200mV/div AC-COUPLED
1ms/div
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY VOLTAGE (V)
FB VOLTAGE vs. TEMPERATURE (VOUT = 1.5V)
NO LOAD VIN = 5V, SKIP MODE FB VOLTAGE (V) 0.605 0.600 0.595 0.590 0.585 -40 -15 10 35 60 85 VIN = 3.3V, PWM MODE VIN = 5V, PWM MODE VIN = 3.3V, SKIP MODE
MAX15118 toc24
SOFT-START WAVEFORMS WITH SS/REFIN (NO LOAD, PWM MODE)
MAX15118 toc25
0.615 0.610
VSS/REFIN 500mV/div VOUT 1V/div
ILX 5A/div VPGOOD 2V/div
1ms/div
TEMPERATURE (°C)
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MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
Typical Operating Characteristics (continued)
(VIN = 5V, VOUT = 1.5V, CSS = 0.1µF, see the Typical Operating Circuits, TA = +25°C, unless otherwise noted.)
SOFT-START WAVEFORMS WITH SS/REFIN (NO LOAD, SKIP MODE)
MAX15118 toc26
STARTING INTO A 1V PREBIASED OUTPUT (ILOAD = 10A)
VSS/REFIN 500mV/div VOUT 1V/div ILX 5A/div VPGOOD 2V/div
1V
MAX15118 toc27
VENABLE 2V/div VOUT 500mV/div ILX 5A/div
VPGOOD 5V/div
1ms/div
1ms/div
STARTING INTO A 1V PREBIASED OUTPUT (NO LOAD, PWM MODE)
MAX15118 toc28
STARTING INTO A 1V PREBIASED OUTPUT (NO LOAD, SKIP MODE)
MAX15118 toc29
VENABLE 2V/div
1V
VENABLE 2V/div
1V
VOUT 500mV/div
VOUT 500mV/div ILX 5A/div
ILX 5A/div
VPGOOD 5V/div
1ms/div 1ms/div
VPGOOD 5V/div
INPUT CURRENT vs. INPUT VOLTAGE
NO LOAD, SKIP MODE
MAX15118 toc30
5 4 INPUT CURRENT (mA) 3 2 1 0 2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
INPUT VOLTAGE (V)
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MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
Pin Configuration
TOP VIEW (BUMP ON THE BOTTOM)
MAX15118 +
BST A1 GND B1 GND C1 GND D1 LX A2 LX B2 LX C2 GND D2 LX A3 GND B3 GND C3 GND D3 LX A4 LX B4 LX C4 AIN D4 IN A5 IN B5 IN C5 IN D5 PGOOD A6 N.C. B6 SKIP C6 EN D6 GSNS A7 FB B7 SS/REFIN C7 COMP D7
WLP
Pin Description
PIN A1 A2, A3, A4, B2, B4, C2, C4 A5, B5, C5, D5 A6 A7 B1, B3, C1, C3, D1, D2, D3 B6 B7 C6 NAME BST LX IN PGOOD GSNS GND N.C. FB SKIP FUNCTION Boost Input for the High-Side Switch Driver. Connect a capacitor from BST to LX. Inductor Connection. Connect LX to the switching side of the inductor. LX is high impedance when the MAX15118 is in shutdown mode. Input Power Supply. Bypass IN to GND with at least two 22FF low-ESR ceramic capacitors with sufficient ripple current ratings. Power-Good Open-Drain Output. PGOOD asserts high when VFB is above 0.555V (typ) and deasserts when VFB falls below 0.530V (typ). Remote Ground-Sense Input. Connect GSNS to the ground terminal of the load and to the bottom of the feedback resistors. Ground Connection. GND is the source terminal of the internal low-side switch. Connect all GND bumps to a component-side PCB copper ground plane at a single point near the input bypass capacitor return terminal. No Connection. Do not connect. Feedback Input. Connect FB to the center tap of an external resistor-divider from the output to the output capacitor return terminal to set the output voltage from 0.6V to 0.94 x VIN. Skip Mode Selector Input. Connect SKIP to EN for skip mode operation. Connect SKIP to GND or leave unconnected for continuous mode operation. Do not change the state of SKIP when EN is high. Soft-Start and External Voltage Reference Input. Connect a capacitor from SS/REFIN to GND to set the soft-start delay. See the Setting the Soft-Start Time section for more information. To use SS/REFIN as an external voltage reference, apply a voltage ranging from 0V to (VIN - 2.5V) to SS/REFIN to externally control the soft-start time and feedback voltage. Filtered Input Voltage Enable Input. Drive EN high to enable the MAX15118. Connect EN to IN for always-on operation. Error Amplifier Output. Connect the compensation network from COMP to GND. See the Compensation Design Guidelines section for more information.
C7 D4 D6 D7
SS/REFIN AIN EN COMP
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MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
Functional Diagram
SKIP EN AIN IN
BIAS GENERATOR
EN LOGIC, IN UVLO, THERMAL SHDN
SKIP MODE LOGIC
SKPM
CURRENT-SENSE AMPLIFIER
LX VOLTAGE REFERENCE 0.58V 0.6V LX SS/REFIN 10µA SS/REFIN BUFFER AV = 1 GSNS FB COMP PGOOD gM ERROR AMPLIFIER PREBIAS ABOVE FORCED PWM START PWM COMPARATOR IN BST
MAX15118
HIGH-SIDE CURRENT LIMIT
CONTROL LOGIC
LX
C
CK IN 555mV, RISING 530mV, FALLING GND COMPENSATION RAMP OSCILLATOR RAMP GENERATOR CK
LOW-SIDE SOURCE-SINK CURRENT-LIMIT AND ZEROCROSSING COMPARATOR
SOURCE SINK ZX
SKPM
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MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
Detailed Description
The MAX15118 high-efficiency, current-mode switching regulator delivers up to 18A of output current. The regulator provides output voltages from 0.6V up to 0.94 x VIN from 2.7V to 5.5V input supplies, making the device ideal for on-board point-of-load applications. The MAX15118 delivers current-mode control architecture using a high-gain transconductance error amplifier. The current-mode control architecture facilitates easy compensation design and ensures cycle-by-cycle current limit with fast response to line and load transients. The regulator features a 1MHz fixed switching frequency, allowing for all-ceramic capacitor designs and fast transient responses. The high operating frequency minimizes the size of external components. The regulator offers a selectable skip-mode functionality to reduce current consumption and achieve a higher efficiency at light output loads. Integrated switches ensure high efficiency at heavy loads while minimizing critical inductances. The MAX15118 features PWM current-mode control, allowing for an all-ceramic capacitor solution. The regulator offers capacitor-programmable soft-start to reduce input inrush current. The device safely starts up into a prebiased output. The MAX15118 includes an enable input and open-drain PGOOD output for sequencing with other devices. The controller logic block is the central processor that determines the duty cycle of the high-side MOSFET under different line, load, and temperature conditions. Under normal operation, where the current-limit and temperature protection are not triggered, the controller logic block takes the output from the PWM comparator and generates the driver signals for both high-side and low-side MOSFETs. The control logic block controls the break-before-make logic and all the necessary timing. The high-side MOSFET turns on at the beginning of the oscillator cycle and turns off when the COMP voltage crosses the internal current-mode ramp waveform. The internal ramp is the sum of the compensation ramp and the current-mode ramp derived from the inductor current (current-sense block). The high-side MOSFET also turns off if either the maximum duty cycle (94%, typ) or the current limit is reached. The low-side MOSFET turns on for the remainder of the oscillation cycle. The MAX15118 can soft-start into a prebiased output without discharging the output capacitor. In safe prebiased startup, both low-side and high-side MOSFETs remain off to avoid discharging the prebiased output. PWM operation starts when the voltage on SS/REFIN crosses the voltage on FB. The MAX15118 can start into a prebiased voltage higher than the nominal set point without abruptly discharging the output. Forced PWM operation starts when the SS/REFIN voltage reaches 0.58V (typ), forcing the converter to start. The low-side current limit is increased over 350µs to the maximum from the first LX pulse. When the low-side sink current-limit threshold of 30A is reached, the low-side switch turns off before the end of the clock period and the high-side switch turns on until one of the following conditions is satisfied: U High-side source current hits the reduced high-side current limit (30A, typ); in this case, the high-side switch is turned off for the remaining time of the clock period. U The clock period ends. Reduced high-side current limit is activated to recirculate the current into the high-side power switch rather than into the internal high-side body diode Low-side sink current limit is provided to protect the low-side switch from excessive reverse current during prebiased operation.
Starting into a Prebiased Output
Controller Function—PWM Logic
The MAX15118 features independent enable control and a power-good signal that allows for flexible power sequencing. Drive the enable input (EN) high to enable the regulator, or connect EN to IN for always-on operation.
Enable Input and Power-Good (PGOOD) Output
Power-good (PGOOD) is an open-drain output that asserts when VFB is above 555mV (typ) and deasserts low if VFB is below 530mV (typ). The MAX15118 utilizes a soft-start feature to slowly ramp up the regulated output voltage to reduce input inrush current during startup. Connect a capacitor from SS/REFIN to GND to set the startup time (see the Setting the Soft-Start Time section for capacitor selection details).
Programmable Soft-Start (SS/REFIN)
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MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
A high-gain transconductance error amplifier provides accuracy for the voltage-feedback loop regulation. Connect the necessary compensation network between COMP and GND (see the Compensation Design Guidelines section). The error-amplifier transconductance is 1.2mS (typ). COMP clamp low is set to 0.97V (typ), just below the slope ramp compensation valley, helping COMP to rapidly return to the correct set point during load and line transients. The MAX15118 features a ground-sense amplifier to prevent output voltage droop under heavy load conditions. Connect GSNS to the negative terminal of the load output capacitor to properly Kelvin-sense the output ground. Route the GSNS trace away from the switching nodes. The PWM comparator compares the COMP voltage to the current-derived ramp waveform (COMP voltage to LX current transconductance value is 150A/V, typ). To avoid instability due to subharmonic oscillations when the duty cycle is around 50% or higher, a slope compensation ramp is added to the current-derived ramp waveform. The compensation ramp slope is designed to ensure stable operation at any duty cycle up to 94%. When the converter output is shorted or the device is overloaded, each high-side MOSFET current-limit event turns off the high-side MOSFET and turns on the low-side MOSFET. On each current-limit event (either high-side or low-side) a 3-bit counter is incremented. The counter is reset after three consecutive switching cycles that do not reach the current limit. If the current-limit condition persists, the counter fills up reaching eight events. The control logic then keeps the low-side MOSFET turned on until the inductor current is fully discharged to avoid high currents circulating through the low-side body diode.
Error Amplifier
The control logic turns off both high-side and low-side MOSFETs and waits for the hiccup period (1024 clock cycles, typ) before attempting a new soft-start sequence. The hiccup mode is also enabled during soft-start time. The MAX15118 contains an internal thermal sensor that limits the total power dissipation to protect the device in the event of an extended thermal fault condition. When the die temperature exceeds +150NC (typ), the thermal sensor shuts down the device, turning off the DC-DC converter to allow the die to cool. After the die temperature falls by 20NC (typ), the device restarts.
Thermal Shutdown Protection
Ground-Sense Amplifier
PWM Comparator
Overcurrent Protection and Hiccup Mode
The MAX15118 features selectable skip mode operation when SKIP is connected to EN. When in skip mode, the LX output becomes high impedance when the inductor current falls below 0.5A (typ). The inductor current does not become negative. If during a clock cycle the inductor current falls below the 0.5A threshold (during off-time), the low-side turns off. At the next clock cycle, if the output voltage is above set point, the PWM logic keeps both high-side and low-side MOSFETs off. If instead the output voltage is below the set point, the PWM logic drives the high-side on until a reduced current limit threshold (3.6A, typ) is reached. In this way the system can skip cycles, reducing the frequency of operation, and switches only as needed to service load at the cost of an increase in output voltage ripple (see the Skip Mode Frequency and Output Ripple section). In skip mode, power dissipation is reduced and efficiency is improved at light loads because power MOSFETs do not switch at every clock cycle. The MAX15118 automatically enters continuous mode regardless of the state of SKIP when the load current increases beyond the skip mode current limit. Do not change the state of SKIP when EN is high.
Skip Mode Operation
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MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
Applications Information
The MAX15118 output voltage is adjustable from 0.6V up to 94% of VIN by connecting FB to the center tap of a resistor-divider between the output and GND (see the Typical Operating Circuits). Choose R1 and R2 values so that the DC errors due to the FB input bias current (Q500nA) do not affect the output voltage accuracy. With lower value resistors, the DC error is reduced, but the amount of power consumed in the resistor-divider increases. R2 values between 1kI and 20kI are acceptable (see Table 1 for typical values). Once R2 is chosen, calculate R1 using: R1=R2 × (VOUT /VFB ) - 1 where the feedback threshold voltage VFB = 0.6V (typ). When regulating for an output of 0.6V in skip mode, short FB to OUT and keep R2 connected from FB to GND. A high-valued inductor results in reduced inductor-ripple current, leading to a reduced output-ripple voltage. However, a high-valued inductor results in either a larger physical size or a high series resistance (DCR) and a lower saturation current rating. Typically, choose an inductor value to produce a current ripple, DIL, equal to 30% of load current. Choose the inductor with the following formula: L= V VOUT × 1- OUT fSW × LIR × ILOAD VIN
IL_PK = ILOAD + where: ∆IL(P-P) = 1 ∆IL(P-P) < min (24A, IL_SAT ) 2 VOUT VIN
Setting the Output Voltage
(VIN − VOUT ) x
L x fSW
For a step-down converter, the input capacitor, CIN, helps to keep the DC input voltage steady, in spite of discontinuous input AC current. Use low-ESR capacitors to minimize the voltage ripple due to ESR. Size CIN using the following formula:
Input Capacitor Selection
CIN =
ILOAD V × OUT fSW × ∆VIN_RIPPLE VIN
Inductor Selection
where DVIN_RIPPLE is the maximum-allowed input-ripple voltage across the input capacitors and is recommended to be less than 2% of the minimum input voltage, fSW is the switching frequency (1MHz), and ILOAD is the output load. The impedance of the input capacitor at the switching frequency should be less than that of the input source so high-frequency switching currents do not pass through the input source, but are instead shunted through the input capacitor. Ensure that the input capacitor can accommodate the input-ripple current requirement imposed by the switching currents. The RMS input-ripple current is given by:
-1 2 V OUT × (VIN - VOUT ) ×I IRMS = LOAD VIN
where fSW is the fixed 1MHz switching frequency, and LIR is the desired inductor current ratio (typically 0.3). In addition, the peak inductor current, IL_PK, must always be below the high-side current-limit and the inductor saturation current rating, IL_SAT. Ensure that the following relationship is satisfied:
where IRMS is the input RMS ripple current. Use multiple capacitors in parallel to meet the RMS current rating requirement.
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MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
The key selection parameters for the output capacitor are capacitance, ESR, ESL, and voltage-rating requirements. These affect the overall stability, output-ripple voltage, and transient response of the DC-DC converter. The output ripple occurs due to variations in the charge stored in the output capacitor, the voltage drop due to the capacitor’s ESR, and the voltage drop due to the capacitor’s ESL. Estimate the output-voltage ripple due to the output capacitance, ESR, and ESL as follows: VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) + VRIPPLE(ESL) where the output ripple due to output capacitance, ESR, and ESL is: VRIPPLE(C) = ∆IP −P 8 × C OUT × fSW
Output Capacitor Selection
Load-transient response also depends on the selected output capacitance. During a load transient, the output instantly changes by ESR x ∆ILOAD. Before the controller can respond, the output deviates further, depending on the inductor and output capacitor values. After a short time, the controller responds by regulating the output voltage back to the predetermined value. Use higher COUT values for applications that require light-load operation or transition between heavy load and light load, triggering skip mode, causing output undershooting or overshooting. When applying the load, limit the output undershooting by sizing COUT according to the following formula: ∆ILOAD C OUT = 3fCO × ∆VOUT where ∆ILOAD is the total load change, fCO is the unitygain bandwidth (or zero-crossing frequency), and ∆VOUT is the desired output undershooting. When removing the load and entering skip mode, the device cannot control output overshooting, since it has no sink current capability; see the Skip Mode Frequency and Output Ripple section to properly size COUT under this circumstance. A worst-case analysis in sizing the minimum output capacitance takes the total energy stored in the inductor into account, as well as the allowable sag/soar (undershoot/overshoot) voltage as follows:
C OUT (MIN) = L × I 2 OUT(MAX) − I 2 OUT(MIN)
VRIPPLE(ESR) = ∆IP −P × ESR and VRIPPLE(ESL) can be approximated as an inductive divider from LX to GND: VRIPPLE (ESL) = VLX × ESL ESL = VIN × L L
where VLX swings from VIN to GND. The peak-to-peak inductor current (DIP-P) is:
(VIN − VOUT ) ×
∆IP −P = L × fSW
VOUT VIN
(
When using ceramic capacitors, which generally have low-ESR, DVRIPPLE(C) dominates. When using electrolytic capacitors, DVRIPPLE(ESR) dominates. Use ceramic capacitors for low ESR and low ESL at the switching frequency of the converter. The ripple voltage due to ESL is negligible when using ceramic capacitors. As a general rule, a smaller inductor ripple-current results in less output-ripple voltage. Since inductor-ripple current depends on the inductor value and input voltage, the output-ripple voltage decreases with larger inductance and increases with higher input voltages. However, the inductor-ripple current also impacts transient-response performance, especially at low VIN to VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step.
(VFIN + VSOAR )
2
− V INIT
2
) , voltage soar (overshoot)
C OUT(MIN) =
L × I 2 OUT(MAX) − I 2 OUT(MIN) V INIT − (VFIN − VSAG )
2 2
(
) , voltage sag (undershoot)
where IOUT(MAX) and IOUT(MIN) are the initial and final values of the load current during the worst-case load dump, VINIT is the initial voltage prior to the transient, VFIN is the steady-state voltage after the transient, VSOAR is the allowed voltage soar (overshoot) above VFIN, and VSAG is the allowable voltage sag below VFIN. The terms (VFIN + VSOAR) and (VFIN - VSAG) represent the maximum/minimum transient output voltage reached during the transient, respectively. Use these equations for initial output-capacitor selection. Determine final values by testing a prototype or an evaluation circuit under the worst-case conditions.
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MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
Enable skip mode in battery-powered systems for high efficiency at light loads. In skip mode the switching frequency (fSKIP), as illustrated in Figure 1, is calculated as follows: fSKIP = where: t ON = L × I SKIP_LIMIT VIN − VOUT L × I SKIP_LIMIT VOUT 1 t ON + t OFF1 + t OFF2
Skip Mode Frequency and Output Ripple
and:
t OFF2 = ∆Q OUT ILOAD
1 1 I SKIP_LIMIT + − ILOAD L × I SKIP_LIMIT × × 2 VIN - VOUT VOUT t OFF2 = ILOAD
Output ripple in skip mode is: L × I SKIP_LIMIT VOUT_RIPPLE = + R ESR_COUT C OUT × (VIN - VOUT ) × (I SKIP_LIMIT - ILOAD )
t OFF1 =
IL ISKIP-LIMIT
ILOAD tON tOFF1 tOFF2 = n × tCK
VOUT
VOUT_RIPPLE
Figure 1. Skip Mode Waveform
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MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
The MAX15118 uses a fixed-frequency, peak currentmode control scheme to provide easy compensation and fast transient response. The inductor peak current is monitored on a cycle-by-cycle basis and compared to the COMP voltage (output of the voltage error amplifier). The regulator’s duty cycle is modulated based on the inductor’s peak current value. This cycle-by-cycle control of the inductor current emulates a controlled current source. As a result, the inductor’s pole frequency is shifted beyond the gain bandwidth of the regulator. System stability is provided with the addition of a simple series capacitorresistor from COMP to GND. This pole-zero combination serves to tailor the desired response of the closed-loop system. The basic regulator loop consists of a power modulator (composed of the regulator’s pulse-width modula-
Compensation Design Guidelines
tor, compensation ramp, control circuitry, MOSFETs, and inductor), the capacitive output filter and load, an output feedback divider, and a voltage-loop error amplifier with its associated compensation circuitry. See Figure 2 for a graphical representation. The power modulator’s transfer function with respect to VCOMP is: R LOAD × I L VOUT = = R LOAD × G MOD VCOMP IL G MOD where IL is the average inductor current, GMOD is the power modulator’s transconductance, and RLOAD is the equivalent load resistance value.
FEEDBACK DIVIDER VOUT
ERROR AMPLIFIER
POWER MODULATOR COMPENSATION RAMP
OUTPUT FILTER AND LOAD
VIN
R1
*CFF VFB
FB COMP
C
gMC
QHS L VCOMP PWM COMPARATOR CONTROL LOGIC QLS
IL DCR IOUT
VOUT
ESR COUT
RLOAD
R2
gM
ROUT
RC
CC VCOMP GMOD VOUT IL ROUT = REF
10
AVEA(dB)/20
gM
NOTE: THE GMOD STAGE SHOWN ABOVE MODELS THE AVERAGE CURRENT OF THE INDUCTOR, IL, INJECTED INTO THE OUTPUT LOAD, IOUT, e.g., IL = IOUT. SUCH CAN BE USED TO SIMPLIFY/MODEL THE MODULATION/CONTROL/POWER STAGE CIRCUITRY SHOWN WITHIN THE BOXED AREA.
*CFF IS OPTIONAL, DESIGNED TO EXTEND THE REGULATOR’S GAIN BANDWIDTH AND INCREASED PHASE MARGIN FOR SOME LOW-DUTY CYCLE APPLICATIONS.
Figure 2. Peak Current-Mode Regulator Transfer Model
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MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
The peak current-mode controller’s modulator gain is attenuated by the equivalent divider ratio of the load resistance and the current-loop gain. GMOD becomes: G MOD = gMC × 1 R LOAD 1+ × K × (1- D) - 0.5 fSW x L S where:
G FF (s) = sC FFR1 + 1 R2 × R1 + R2 sC FF (R1||R2) + 1
GEA (s) = 10 AVEA(dB)/20 ×
where RLOAD = VOUT/IOUT(MAX), fSW is the switching frequency, L is the output inductance, D is the duty cycle (VOUT/VIN), and KS is the slope compensation factor calculated as: V ×f × L × gMC K S = 1 + SLOPE SW VIN - VOUT where VSLOPE = 130mV and gMC = 150A/V. The power modulator’s dominant pole is a function of the parallel effects of the load resistance and the currentloop gain’s equivalent impedance. Assuming that ESR of the output capacitor is much smaller than the parallel combination of the load and the current loop, fPMOD can be calculated as: fPMOD = [K S × (1- D) - 0.5] 1 + 2π × C OUT × R LOAD 2π × fSW × L × C OUT
sC CR C + 1 10 AVEA(dB)/20 sC C +1 gM G FILTER (s) = R LOAD sC OUTESR + 1
-1
K × (1- D) - 0.5 1 sC OUT +S +1 2π × R LOAD 2π × fSW × L 1 G SAMPLING (s) = +1 2 s s + (π × f ) 2 π × fSW × Q C
SW
×
1 where Q C = π × [K S × (1- D) - 0.5]
The dominant poles and zeros of the transfer loop gain are: fP1 fP1, fP2, and fZ1). RC becomes: R LOAD × K S[(1- D) - 0.5] 1 + L × fSW R1 + R2 × RC = R2 gM × gMC × R LOAD 1 × 2π × fCO × C OUT × ESR + K S[(1- D) - 0.5] 1 + R LOAD L × fSW where KS is calculated as: V ×f × L × gMC K S = 1 + SLOPE SW VIN - VOUT and gM = 1.2mS, gMC = 150A/V, and VSLOPE = 130mV.
1ST ASYMPTOTE R2 x (R1 + R2)-1 x 10AVEA(dB)/20 x gMC x RLOAD x {1 + RLOAD x [KS x (1 – D) – 0.5] x (L x fSW)-1}-1 2ND ASYMPTOTE R2 x (R1 + R2)-1 x gM x (2GCC)-1 x gMC x RLOAD x {1 + RLOAD x [KS x (1 – D) – 0.5] x (L x fSW)-1}-1 GAIN 3RD ASYMPTOTE R2 x (R1 + R2)-1 x gM x (2GCC)-1 x gMC x RLOAD x {1 + RLOAD x [KS x (1 – D) – 0.5] x (L x fSW)-1}-1 x (2GCOUT x {RLOAD-1 + [KS(1 – D) – 0.5] x (L x fSW)-1}-1)-1 4TH ASYMPTOTE R2 x (R1 + R2)-1 x gM x RC x gMC x RLOAD x {1 + RLOAD x [KS x (1 – D) – 0.5] x (L x fSW)-1}-1 x (2GCOUT x {RLOAD-1 + [KS(1 – D) – 0.5] x (L x fSW)-1}-1)-1 3RD POLE 2ND ZERO 0.5 x fSW (2GCOUTESR)-1 UNITY 1ST POLE [2GCC(10AVEA(dB)/20 x gM-1)]-1 1ST ZERO (2GCCRC)-1 FREQUENCY fCO
dB
2ND POLE fPMOD*
5TH ASYMPTOTE R2 x (R1 + R2)-1 x gM x RC x gMC x RLOAD x {1 + RLOAD x [KS x (1 – D) – 0.5] x (L x fSW)-1}-1 x [(2GCOUT x {RLOAD-1 + [KS(1 – D) – 0.5] x (L x fSW)-1}-1)-1 x (0.5 x fSW)2 x (2Gf)-2
NOTE: ROUT = 10AVEA(dB)/20 x gM-1 *fPMOD = [2GCOUT x (ESR + {RLOAD-1 + [KS(1 – D) – 0.5] x (L x fSW)-1}-1)]-1 WHICH FOR ESR > C OUT × VOUT × I SS (24A - ILOAD ) × VFB
Optionally, for low duty-cycle applications, the addition of a phase-leading capacitor (CFF in Figure 2) helps mitigate the phase lag of the damped half-frequency double pole. Adding a second zero near to but below the desired crossover frequency increases both the closed-loop phase margin and the regulator’s unity-gain bandwidth (crossover frequency). Select the capacitor as follows: C FF = 1 2π × fCO × (R1 || R2)
An external tracking reference with steady-state value between 0V and (VIN - 2.5V) can be applied to SS/REFIN. In this case, connect an RC network from the external tracking reference and SS/REFIN, as shown in Figure 4. The recommended value for RSS is approximately 330I. RSS is needed to ensure that, during hiccup period, SS/REFIN can be pulled down internally.
RSS SS/REFIN CSS
Using CFF, the zero-pole order is adjusted as follows: fP1 < fP2 < fZ1 < 1/ [2πC FFR1] < 1/ 2πC FF (R1|| R2) < fP3 < fZ2 The soft-start feature ramps up the output voltage slowly, reducing input inrush current during startup. Size the CSS capacitor to achieve the desired soft-start time, tSS, using: I ×t C SS = SS SS VFB
VREF_EXT
MAX15118
Setting the Soft-Start Time
Figure 4. RC Network for External Reference at SS/REFIN
Table 1 provides values for various outputs based on the typical operating circuit.
Design Examples
Table1.SuggestedComponentValues(seetheTypicalOperatingCircuits)
VIN(V) 3.3 3.3 3.3 3.3 3.3 5 5 5 5 5 5 VOUT(V) 0.8 1.2 1.5 1.8 2.5 0.8 1.2 1.5 1.8 2.5 3.3 L(μH) 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.22 0.22 0.22 LIR(A/A) 0.22 0.28 0.30 0.30 0.22 0.25 0.34 0.39 0.29 0.32 0.28 C15(nF) 6.8 4.7 3.3 3.3 3.3 6.8 4.7 3.3 3.3 3.3 2.2 R3(kI) 2.94 2.21 3.83 4.22 5.62 2.94 2.21 3.83 3.92 5.1 4.64 C14(pF) 22 22 22 22 22 22 22 22 22 22 22 R1(kI) 1.78 5.36 8.06 10.7 16.9 1.78 5.36 8.06 10.7 16.9 24.3 R2(kI) 5.36 5.36 5.36 5.36 5.36 5.36 5.36 5.36 5.36 5.36 5.36
Note: CIN, COUT, and other components are the same as in the standard MAX15118 Evaluation Kit.
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MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
The MAX15118 is available in a 28-bump WLP package and can dissipate up to 3.26W at TA = +70NC. When the die temperature exceeds +150NC, the thermal shutdown protection is activated (see the Thermal Shutdown Protection section).
Power Dissipation
PART MAX15118EWI+
Ordering Information
TEMPRANGE -40NC to +85NC PIN-PACKAGE 28 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Careful PCB layout is critical to achieve clean and stable operation. It is highly recommended to duplicate the MAX15118 Evaluation Kit (EV kit) layout for optimum performance. The MAX15118 EV kit board has a small, quiet, ground-shape SGND on the back side below the IC. This ground is the return for the control circuitry, especially the return of the compensation components. This SGND is returned to the IC ground through vias close to the ground bumps of the IC. If deviation is necessary, follow these guidelines for good PCB layout: 1) Connect a single ground plane immediately adjacent to the GND bumps of the IC. 2) Place capacitors on IN and SS/REFIN as close as possible to the IC and the corresponding pad using direct traces. 3) Keep the high-current paths as short and wide as possible. Keep the path of switching current short and minimize the loop area formed by LX, the output capacitors, and the input capacitors. 4) An electrolytic capacitor is strongly recommended for damping when there is significant distance between the input power supply and the MAX15118. 5) Connect IN, LX, and GND separately to a large copper area to help cool the IC to further improve efficiency. 6) Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close as possible to the IC. 7) Route high-speed switching nodes (such as LX and BST) away from sensitive analog areas (such as FB and COMP).
Layout Procedure
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 28 WLP (2.10mm x 3.56mm) PACKAGE CODE W282B3Z+1 OUTLINE NO. 21-0577 LAND PATTERNNO. Refer to Application Note1891
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MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
Typical Operating Circuits (continued)
R7 4.7I
PGOOD
VEN < 0.4V = OFF 1.4V < VEN < VIN = ON CONNECT SKIP TO EN TO ENABLE SKIP MODE CONNECT SKIP TO GND FOR PWM MODE
D6 C6 A6 D4
EN SKIP PGOOD AIN
BST
A1
LX LX LX
A2 A3 A4 B2 B4 C2 C4
C13 0.47µF
R8 1I C18 4700pF
R5 100kI VIN 2.7V TO 5.5V C4 22µF C3 22µF C2 22µF C1 22µF
R12 10I
2.2µF
A5 C19 10µF C30 10µF B5 C5 D5 B6 C7 D7 C16 0.1µF R3 3.83kI ±1% C15 3.3nF
IN IN IN IN N.C. SS/REFIN COMP
U1 MAX15118
LX LX LX LX
GND GND GND GND GND GND GND GSNS
B1 B3 C1 C3 D1 D2 D3 A7
S
L1 0.22µH
C14 22pF
C7 150µF
C8 150µF
C9 150µF
C10 150µF
C20 10µF
VOUT 1.5V 0 TO 18A
470I
S
S
R
FB
B7 R2 5.36kI ±1%
R1 8.06kI ±1%
S SMALL-SIGNAL GND (SGND) CONNECT TO PGND ONLY ON COMPONENT LAYER AT VIA NEXT TO U1.
R
R REMOTE SENSE GND (RGND) CONNECT TO PGND ONLY AT THE LOAD. POWER GND (PGND) TOP LAYER GND FLOOD, SYSTEM GND.
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MAX15118 High-Efficiency, 18A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches
Revision History
REVISION NUMBER 0 REVISION DATE 6/11 Initial release DESCRIPTION PAGES CHANGED —
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
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©
23
2011 Maxim Integrated Products
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