MAX1531

19-2866; Rev 0; 5/03 Multiple-Output Power-Supply Controllers for LCD Monitors General Description The MAX1530/MAX1531 multiple-output power-supply controllers generate all the supply rails for thin-film transistor (TFT) liquid-crystal display (LCD) monitors. Both devices include a high-efficiency, fixed-frequency, step-down regulator. The low-cost, all N-channel, synchronous topology enables operation with efficiency as high as 93%. High-frequency operation allows the use of small inductors and capacitors, resulting in a compact solution. The MAX1530 includes three linear regulator controllers and the MAX1531 includes five linear regulator controllers for supplying logic and LCD bias voltages. A programmable startup sequence enables easy control of the regulators. The MAX1530/MAX1531 include soft-start functions to limit inrush current during startup. An internal stepdown converter current-limit function and a versatile overcurrent shutdown protect the power supplies against fault conditions. The MAX1530/MAX1531 use a currentmode control architecture, providing fast load transient response and easy compensation. An internal linear regulator provides MOSFET gate drive and can be used to power small external loads. The MAX1530/MAX1531 can operate from inputs as high as 28V and are well suited for LCD monitor and TV applications running directly from AC/DC wall adapters. Both devices are available in a small (5mm x 5mm), ultra-thin (0.8mm), 32-pin QFN package and operate over the -40°C to +85°C temperature range. Features o 4.5V to 28V Input Voltage Range o 250kHz/500kHz Current-Mode Step-Down Converter Small Inductor/Capacitors No Sense Resistor o Three Positive Linear Regulator Controllers One Positive and One Negative Additional Controller (MAX1531) Small Input and Output Capacitors o Timed Reset Output o Uncommitted Overcurrent Protection (MAX1531) o Soft-Start for All Regulators o Programmable Input Undervoltage Comparator o Programmable Startup Sequencing MAX1530/MAX1531 Minimal Operating Circuit VP VIN VIN VN VL CSH CSL VIN = 12V BST IN VOUT 3.3V/1.5A DH LX DL PGND EN ILIM FREQ VL AGND VL DRV4 FBL4 VSOURCE 10V/500mA Applications LCD Monitors and TVs Automotive LCDs MAX1530 FB COMP Ordering Information PART MAX1530ETJ MAX1531ETJ TEMP RANGE -40°C to +85°C -40°C to +85°C PIN-PACKAGE 32 Thin QFN 32 Thin QFN VLOGIC 2.5V/500mA VOUT RESET VIN RSTIN DRV2 FBL2 DRV1 FBL1 ONL2 ONL3 ONL4 ONL5 VN DRV3 VGON 25V FBL3 DRV5 FBL5 VGOFF -9V VGAMMA 9.7V VL SEQ Pin Configuration appears at end of data sheet. VP VL ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Multiple-Output Power-Supply Controllers for LCD Monitors MAX1530/MAX1531 ABSOLUTE MAXIMUM RATINGS IN, DRV1, DRV2, DRV3, DRV4, CSH, CSL to AGND .....................................................-0.3V to +30V DRV5 to VL .............................................................-28V to +0.3V CSH to CSL ..............................................................-0.3V to +6V VL to AGND ..............................................................-0.3V to +6V PGND to AGND...................................................................±0.3V LX to BST..................................................................-6V to +0.3V BST to AGND..........................................................-0.3V to +36V DH to LX .....................................................-0.3V to (BST + 0.3V) DL to PGND ..................................................-0.3V to (VL + 0.3V) SEQ, ONL2, ONL3, ONL4, ONL5, COMP, ILIM to AGND............................................-0.3V to (VL + 0.3V) RSTIN, RESET, EN, FB, FBL1, FBL2, FBL3, FBL4, FBL5, FREQ to AGND.....................................................-0.3V to +6V VL Short Circuit to AGND ...........................................Momentary Continuous Power Dissipation (TA = +70°C) 32-Pin Thin QFN (derate 21.3mW/°C above +70°C) ...1702mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VIN = 12V, VEN = VSEQ = 5V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER GENERAL Operating Input Voltage Range Quiescent Supply Current IC Disable Supply Current VL REGULATOR VL Output Voltage VL Undervoltage Lockout Threshold CONTROL AND SEQUENCE SEQ, FREQ Input Logic High Level SEQ, FREQ Input Logic Low Level SEQ, FREQ Input Leakage Current ONL_ Input Threshold ONL_ Source Current ONL_ Input Leakage Current ONL_ Input Discharge Clamp Resistance EN Input Threshold EN Input Leakage Current FAULT DETECTION FB, FBL1, FBL2, FBL3, FBL4 Undervoltage Fault Trip Level FBL5 Undervoltage Fault Trip Level FB, FBL1, FBL2, FBL3, FBL4 falling, 25mV hysteresis FBL5 rising, 25mV hysteresis 1.081 300 1.114 400 1.147 500 V mV ONL_ rising, 25mV hysteresis SEQ = EN = VL, VONL _ = 0 to 1.24V SEQ = EN = VL, ONL_ = VL SEQ = 0 EN rising, 5% hysteresis -1 1.201 1.8 -500 800 1.201 -50 1500 1.238 1.238 2.0 2.0 0.6 +1 1.275 2.2 +500 3000 1.275 +50 V V µA V µA nA Ω V nA 5.5V < VIN < 28V, 0 < IVL < 30mA VL rising, 3% hysteresis 4.75 3.2 5 3.5 5.25 3.8 V V (Note 1) VFB = VFBL1 = VFBL2 = VFBL3 = VFBL4 = 1.5V, VFBL5 = 0 EN = AGND 4.5 1.7 200 28.0 3.0 400 V mA µA CONDITIONS MIN TYP MAX UNITS 2 _______________________________________________________________________________________ Multiple-Output Power-Supply Controllers for LCD Monitors ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 12V, VEN = VSEQ = 5V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Comparator Bandwidth Duration to Trigger Fault Latch Overcurrent Protection Threshold Overcurrent Sense CommonMode Range CSH Input Current CSL Input Current Overcurrent Sense Filter RC Time Constant THERMAL PROTECTION Thermal Shutdown RESET FUNCTION RSTIN Reset Trip Level RSTIN Input Leakage Current Comparator Bandwidth Reset Timeout Period RESET Output Low Level RESET Output High Leakage ERROR AMPLIFIER FB Regulation Voltage Transconductance Voltage Gain Minimum Duty Cycle FB Input Leakage Current FB Input Common-Mode Range COMP Output Minimum Voltage COMP Output Maximum Voltage Current-Sense Amplifier Voltage Gain Current-Limit Threshold (Default Mode) Current-Limit Threshold (Adjustable Mode) ILIM Input Dual Mode™ Threshold OSCILLATOR Switching Frequency Maximum Duty Cycle FREQ = AGND FREQ = VL FREQ = AGND FREQ = VL 200 425 75 75 250 500 80 80 300 575 88 88 kHz % VFB = 1.5V (Note 2) VFB = 1.5V VFB = 1.175V VIN - VLX PGND - LX, ILIM = VL PGND - LX, VILIM = 1.25V 2.75 190 190 3.0 -50 -0.1 1 3 3.5 250 250 3.5 4.0 310 310 4.00 FB to COMP FB to COMP 1.223 70 1.238 100 200 15 +50 +1.5 1.253 140 V µS V/V % nA V V V V/V mV mV V IRESET = -1mA VRESET = 5V STEP-DOWN CONTROLLER 102 RSTIN falling, 25mV hysteresis VRSTIN = 1.5V 1.081 -50 10 128 154 0.4 1 1.114 1.147 +50 V nA kHz ms V µA Temperature rising, 15°C hysteresis 160 °C For EN, FB, FBL_ For FB, FBL_ (VCSH - VCSL) VCSH, VCSL VCSH = 2.7V to 28V VCSL = VCSH = 12V -50 50 51 270 2.7 CONDITIONS MIN TYP 10 64 300 77 330 28.0 100 +50 MAX UNITS kHz ms mV V µA nA µs MAX1530/MAX1531 Dual Mode is a trademark of Maxim Integrated Products, Inc. _______________________________________________________________________________________ 3 Multiple-Output Power-Supply Controllers for LCD Monitors MAX1530/MAX1531 ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 12V, VEN = VSEQ = 5V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SOFT-START Step Size Period FET DRIVERS DH, DL On-Resistance DH, DL Output Drive Current LX, BST Leakage Current Sourcing or sinking, VDH or VDL = VVL / 2 VBST = VLX = VIN = 28V LINEAR REGULATOR CONTROLLERS POSITIVE LINEAR REGULATOR (LR1) FBL1 Regulation Voltage FBL1 Input Bias Current FBL1 Effective Load Regulation Error (Transconductance) FBL1 Line Regulation Error DRV1 Sink Current DRV1 Off-Leakage Current FBL1 Input Common-Mode Range Soft-Start Step Size Soft-Start Period VDRV1 = 5V, IDRV1 = 100µA VFBL1 = 1.5V VDRV1 = 5V, IDRV1 = 100µA to 2mA IDRV1 = 100µA, 5.5V < VIN < 28V VFBL1 = 1.175V, VDRV1 = 5V VFBL1 = 1.5V, VDRV1 = 28V (Note 2) Measured at FBL1 FREQ = GND FREQ = VL VDRV_ = 5V, IDRV_ = 100µA VFBL _ = 1.5V VDRV_ = 5V, IDRV_ = 50µA to 1mA IDRV_ = 100µA, 5.5V < VIN < 28V VFBL_ = 1.175V, VDRV_ = 5V VFBL _ = 1.5V, VDRV_ = 28V (Note 2) Measured at FBL_ -0.1 1.238 / 32 2 4 0.1 10 +1.5 1.226 -50 -1.5 -0.1 1.238 / 32 1024 / fOSC 2048 / fOSC 1.245 1.264 +50 -2 5 3 10 0.1 10 +1.5 1.226 -50 -1.5 1.245 1.264 +50 -2 5 V nA % mV mA µA V V s 3 0.5 20 10 Ω A µA Measured at FB FREQ = GND FREQ = VL 1.238 / 32 1024 / fOSC 2048 / fOSC V s CONDITIONS MIN TYP MAX UNITS POSITIVE LINEAR REGULATORS (LR2 AND LR3) FBL_ Regulation Voltage FBL_ Input Bias Current FBL_ Effective Load Regulation Error (Transconductance) FBL_ Line Regulation Error DRV_ Sink Current DRV_ Off-Leakage Current FBL_ Input Common-Mode Range Soft-Start Step Size V nA % mV mA µA V V 4 _______________________________________________________________________________________ Multiple-Output Power-Supply Controllers for LCD Monitors MAX1530/MAX1531 ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 12V, VEN = VSEQ = 5V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Soft-Start Period FREQ = GND FREQ = VL VDRV4 = 5V, IDRV4 = 500µA VFBL4 = 1.5V VDRV4 = 5V, IDRV4 = 500µA to 10mA IDRV4 = 500µA, 5.5V < VIN < 28V VFBL4 = 1.175V, VDRV4 = 5V VFBL4 = 1.5V, VDRV4 = 28V (Note 2) Measured at FBL4 FREQ = GND FREQ = VL VDRV5 = -10V, IDRV5 = 100µA VFBL5 = 0 VDRV5 = -10V, IDRV5 = 50µA to 1mA IDRV5 = 100µA, 5.5V < VIN < 28V VFBL5 = 200mV, VDRV5 = -10V VFBL5 = 0, VDRV5 = -20V (Note 2) Measured at FBL5 FREQ = AGND FREQ = VL -0.1 1.238 / 32 1024 / fOSC 2048 / fOSC 2 9 0.1 10 +1.5 100 -50 -1.5 -0.1 1.238 / 32 1024 / fOSC 2048 / fOSC 125 150 +50 -2 5 10 28 0.1 10 +1.5 1.226 -50 -1.5 CONDITIONS MIN TYP 1024 / fOSC 2048 / fOSC 1.245 1.264 +50 -2 5 MAX UNITS s POSITIVE LINEAR REGULATOR (LR4) FBL4 Regulation Voltage FBL4 Input Bias Current FBL4 Effective Load Regulation Error (Transconductance) FBL4 Line Regulation Error DRV4 Sink Current DRV4_Off-Leakage Current FBL4 Input Common-Mode Range Soft-Start Step Size Soft-Start Period V nA % mV mA µA V V s NEGATIVE LINEAR REGULATOR (LR5) FBL5 Regulation Voltage FBL5 Input Bias Current FBL5 Effective Load Regulation Error (Transconductance) FBL5 Line Regulation Error DRV5 Source Current DRV5 Off-Leakage Current FBL5 Input Common-Mode Range Soft-Start Step Size Soft-Start Period mV nA % mV mA µA V V s ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VIN = 12V, VEN = VSEQ = 5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 3) PARAMETER GENERAL Operating Input Voltage Range VL REGULATOR VL Output Voltage VL Undervoltage Lockout Threshold 5.5V < VIN < 28V, 0 < IVL < 30mA VL rising, 3% hysteresis 4.75 3.2 5.25 3.8 V V (Note 1) 4.5 28.0 V CONDITIONS MIN TYP MAX UNITS _______________________________________________________________________________________ 5 Multiple-Output Power-Supply Controllers for LCD Monitors MAX1530/MAX1531 ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 12V, VEN = VSEQ = 5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 3) PARAMETER CONTROL AND SEQUENCE ONL_ Input Threshold EN Input Threshold FAULT DETECTION FB, FBL1, FBL2, FBL3, FBL4 Fault Trip Level FBL5 Fault Trip Level Overcurrent Protection Threshold RESET FUNCTION RSTIN Reset Trip Level ERROR AMPLIFIER FB Regulation Voltage Current-Limit Threshold (Default Mode) Current-Limit Threshold (Adjustable Mode) PGND - LX, ILIM = VL PGND - LX, VILIM = 1.25V LINEAR REGULATOR CONTROLLERS POSITIVE LINEAR REGULATOR (LR1) FBL1 Regulation Voltage FBL1 Input Bias Current FBL_ Regulation Voltage FBL_ Input Bias Current FBL4 Regulation Voltage FBL4 Input Bias Current FBL5 Regulation Voltage FBL5 Input Bias Current DRV5 Source Current VDRV1 = 5V, IDRV1 = 100µA VFBL1 = 1.5V VDRV_ = 5V, IDRV_ = 100µA VFBL_ = 1.5V VDRV4 = 5V, IDRV4 = 500µA VFBL4 = 1.5V VDRV5 = -10V, IDRV5 = 100µA VFBL5 = 0 VFBL5 = 200mV, VDRV5 = -10V 1.220 -50 1.220 -50 1.220 -50 100 -50 2 1.270 +50 1.270 +50 1.270 +50 150 +50 V nA V nA V nA mV nA mA 1.215 170 170 1.260 330 330 V mV mV RSTIN falling, 25mV hysteresis STEP-DOWN CONTROLLER 1.081 1.147 V FB, FBL1, FBL2, FBL3, FBL4 falling, 25mV hysteresis FBL5 rising, 25mV hysteresis (VCSH - VCSL) 1.081 300 270 1.147 500 330 V mV mV ONL_ rising, 25mV hysteresis EN rising, 5% hysteresis 1.201 1.201 1.275 1.275 V V CONDITIONS MIN TYP MAX UNITS POSITIVE LINEAR REGULATORS (LR2 AND LR3) POSITIVE LINEAR REGULATOR (LR4) NEGATIVE LINEAR REGULATOR (LR5) Note 1: Operating supply range is guaranteed by VL line regulation test for the range of 5.5V to 28V. Between 4.5V and 5.5V, the VL regulator might be in dropout; however, the part continues to operate properly. Note 2: Guaranteed by design and not production tested. Note 3: Specifications to -40°C are guaranteed by design and not production tested. 6 _______________________________________________________________________________________ Multiple-Output Power-Supply Controllers for LCD Monitors Typical Operating Characteristics (Circuit of Figure 1; including R5, R6, and D2; TA = +25°C, unless otherwise noted.) STEP-DOWN EFFICIENCY vs. LOAD CURRENT fSW = 500kHz 90 EFFICIENCY (%) VIN = 12V 80 VIN = 20V MAX1530 toc01 MAX1530/MAX1531 STEP-DOWN LOAD REGULATION MAX1530 toc02 SWITCHING FREQUENCY vs. LOAD CURRENT 515 510 FREQUENCY (kHz) 505 500 495 490 485 MAX1530 toc03 100 0 520 OUTPUT-VOLTAGE ERROR (%) -0.04 -0.08 70 -0.12 60 50 0 300 600 900 1200 1500 LOAD CURRENT (mA) -0.16 0 300 600 900 1200 1500 LOAD CURRENT (mA) 480 0 300 600 900 1200 1500 LOAD CURRENT (mA) STEP-DOWN REGULATOR LOAD TRANSIENT MAX1530 toc04 STEP-DOWN REGULATOR SWITCHING WAVEFORM MAX1530 toc05 STEP-DOWN REGULATOR SOFT-START MAX1530 toc06 A A 0A B 3.3V 0V B 3.3V A 0V B 0V C C 0A 0A 40µs/div A: LOAD CURRENT, 1A/div B: OUTPUT VOLTAGE, 200mV/div, AC-COUPLED C: INDUCTOR CURRENT, 1A/div 2µs/div A: LX, 10V/div B: OUTPUT VOLTAGE, 20 mV/div, AC-COUPLED C: INDUCTOR CURRENT, 1A/div C 0A 1ms/div A: EN, 2V/div B: OUTPUT VOLTAGE, 2V/div C: INDUCTOR CURRENT, 1A/div VL LOAD REGULATION MAX1530 toc07 STARTUP SEQUENCE MAX1530 toc08 LR1 BASE CURRENT vs. DRV1 VOLTAGE A B C BASE CURRENT (mA) 12 VFBL1 = 1.175V MAX1530 toc09 0 15 -0.1 VL OUTPUT ERROR (%) -0.2 D E 9 -0.3 6 -0.4 F G 3 -0.5 0 5 10 15 20 25 30 4ms/div LOAD CURRENT (mA) 0 0 10 2 4 6 8 E: VGAMMA, 20V/div A: VL, 10V/div DRV1 VOLTAGE (V) B: VOUT, 5V/div F: VGOFF, 20V/div C: VLOGIC, 5V/div G: VGON, 40V/div D: VSOURCE, 20V/div _______________________________________________________________________________________ 7 Multiple-Output Power-Supply Controllers for LCD Monitors MAX1530/MAX1531 Typical Operating Characteristics (continued) (Circuit of Figure 1; including R5, R6, and D2; TA = +25°C, unless otherwise noted.) LR1 NORMALIZED LOAD REGULATION MAX1530 toc10 LR1 NORMALIZED LINE REGULATION MAX1530 toc11 LR1 LOAD TRANSIENT MAX1530 toc12 0 0.2 0 -0.2 -0.4 -0.6 A 2.5V VOLTAGE ERROR (%) -0.5 -1.0 OUTPUT-VOLTAGE ERROR (%) -1.5 B -0.8 200mA LOAD CURRENT 0mA 6 40µs/div A: LR1 OUTPUT VOLTAGE, 100mV/div, AC-COUPLED B: LR1 LOAD CURRENT, 500mA/div -2.0 0 100 200 300 400 500 LOAD CURRENT (mA) -1.0 2 3 4 INPUT VOLTAGE (V) 5 LR2/LR3 BASE CURRENT vs. DRV2/DRV3 VOLTAGE MAX1530 toc13 LR2 NORMALIZED LOAD REGULATION MAX1530 toc14 LR2 NORMALIZED LINE REGULATION MAX1530 toc15 5 VFBL2 = VFBL3 = 1.175V 4 BASE CURRENT (mA) 0 0.2 0 -0.2 -0.4 -0.6 -0.8 20mA LOAD CURRENT -1.0 -0.3 VOLTAGE ERROR (%) 3 -0.6 2 -0.9 1 -1.2 0 0 1 2 3 4 5 DRV2/DRV3 VOLTAGE (V) -1.5 0 10 20 30 40 50 LOAD CURRENT (mA) OUTPUT-VOLTAGE ERROR (%) 9 13 17 INPUT VOLTAGE (V) 21 25 LR3 NORMALIZED LOAD REGULATION MAX1530 toc16 LR3 NORMALIZED LINE REGULATION MAX1530 toc17 LR4 BASE CURRENT vs. DRV VOLTAGE VFBL4 = 1.175V 25 BASE CURRENT (mA) 20 15 10 5 MAX1530 toc18 0 0.2 0 -0.2 -0.4 -0.6 -0.8 20mA LOAD CURRENT 30 VOLTAGE ERROR (%) -0.5 -1.0 -1.5 -2.0 0 4 8 12 16 20 LOAD CURRENT (mA) OUTPUT-VOLTAGE ERROR (%) -1.0 24 28 32 INPUT VOLTAGE (V) 36 40 0 0 2 4 6 8 10 DRV4 VOLTAGE (V) 8 _______________________________________________________________________________________ Multiple-Output Power-Supply Controllers for LCD Monitors Typical Operating Characteristics (continued) (Circuit of Figure 1; including R5, R6, and D2; TA = +25°C, unless otherwise noted.) MAX1530/MAX1531 LR4 NORMALIZED LOAD REGULATION MAX1530 toc19 LR4 NORMALIZED LINE REGULATION MAX1530 toc20 LR4 LOAD TRANSIENT MAX1530 toc21 0 -0.1 VOLTAGE ERROR (%) -0.2 -0.3 -0.4 -0.5 -0.6 0 100 200 300 400 0.2 0 -0.2 -0.4 -0.6 -0.8 200mA LOAD CURRENT -1.0 OUTPUT-VOLTAGE ERROR (%) A 10V B 0mA 25 40µs/div A: LR4 OUTPUT VOLTAGE, 100mV/div, AC-COUPLED B: LR4 LOAD CURRENT, 500mA/div 500 9 13 17 INPUT VOLTAGE (V) 21 LOAD CURRENT (mA) LR4 PULSED LOAD TRANSIENT MAX1530 toc22 MAX1531 OVERCURRENT PROTECTION (CSH, CSL) MAX1530 toc23 LR5 BASE CURRENT vs. DRV5 VOLTAGE VFBL5 = 0V A MAX1530 toc24 10 A 10V B BASE CURRENT (mA) 8 6 C B 0A 10µs/div A: LR4 OUTPUT VOLTAGE, 100mV/div, AC-COUPLED B: LR4 LOAD CURRENT, 1A/div D 20µs/div C: VRESET, 5V/div D: VCSH - VCSL, 500mV/div 4 2 0 0 1 2 3 4 5 DRV5 VOLTAGE (V) A: VLX, 10V/div B: VOUT, 5V/div _______________________________________________________________________________________ 9 Multiple-Output Power-Supply Controllers for LCD Monitors MAX1530/MAX1531 Typical Operating Characteristics (continued) (Circuit of Figure 1; including R5, R6, and D2; TA = +25°C, unless otherwise noted.) LR5 NORMALIZED LOAD REGULATION MAX1530 toc25 LR5 NORMALIZED LINE REGULATION 20mA LOAD CURRENT OUTPUT-VOLTAGE ERROR (%) 0.8 0.6 0.4 0.2 0 -0.2 MAX1530 toc26 0 1.0 -0.2 VOLTAGE ERROR (%) -0.4 -0.6 -0.8 -1.0 0 10 20 30 40 50 LOAD CURRENT (mA) -25 -21 -17 INPUT VOLTAGE (V) -13 -9 Pin Description PIN MAX1530 1 MAX1531 1 NAME FUNCTION Gamma Linear Regulator (LR2) Base Drive. Open drain of an internal N-channel MOSFET. Connect DRV2 to the base of an external PNP pass transistor to form a positive linear regulator. (See the Pass Transistor Selection section.) Gamma Linear Regulator (LR2) Feedback Input. FBL2 regulates at 1.245V nominal. Connect FBL2 to the center tap of a resistive voltage-divider between the LR2 output and AGND to set the output voltage. Place the divider close to the FBL2 pin. Gate-On Linear Regulator (LR3) Feedback Input. FBL3 regulates at 1.245V nominal. Connect FBL3 to the center tap of a resistive voltage-divider between the LR3 output and AGND to set the output voltage. Place the divider close to the FBL3 pin. Gate-On Linear Regulator (LR3) Base Drive. Open drain of an internal N-channel MOSFET. Connect DRV3 to the base of an external PNP pass transistor to form a positive linear regulator. (See the Pass Transistor Selection section.) No Connection. Not internally connected. Adjustable Reset Input. RESET asserts low when the monitored voltage is less than the reset trip threshold. RESET goes to a high-impedance state only after the monitored voltage remains above the reset trip threshold for the duration of the reset timeout period. Connect RSTIN to the center tap of a resistive voltage-divider between the monitored output voltage and AGND to set the reset trip threshold. The internal RSTIN threshold of 90% of 1.238V allows direct connection of RSTIN to any of the device’s positive feedback pins. DRV2 2 2 FBL2 3 3 FBL3 4 5–10, 18, 19 4 — DRV3 N. C. 11 11 RSTIN 10 ______________________________________________________________________________________ Multiple-Output Power-Supply Controllers for LCD Monitors Pin Description (continued) PIN MAX1530 MAX1531 NAME FUNCTION Open-Drain Reset Output. RESET asserts low when the monitored voltage is less than the reset trip threshold. RESET goes to a high-impedance state only after the monitored voltage remains above the reset trip threshold for the duration of the reset timeout period. RESET also asserts low when VL is less than the VL undervoltage lockout threshold, EN is low, or the thermal, overcurrent or undervoltage fault latches are set. Step-Down Regulator Compensation Input. A pole-zero pair must be added to compensate the control loop by connecting a series resistor and capacitor from COMP to AGND. (See the Compensation Design section.) Step-Down Regulator Feedback Input. FB regulates at 1.238V nominal. Connect FB to the center tap of a resistive voltage-divider between the step-down regulator output and AGND to set the output voltage. Place the divider close to the FB pin. Step-Down Regulator Current-Limit Control Input. Connect this dual-mode input to VL to set the current-limit threshold to its default value of 250mV. The overcurrent comparator compares the voltage across the low-side N-channel MOSFET with the current-limit threshold. Connect ILIM to the center tap of a resistive voltage-divider between VL and AGND to adjust the current-limit threshold to other values. In adjustable mode, the actual current-limit threshold is 1/5th of the voltage at ILIM over a 0.25V to 3.0V range. The dualmode threshold for switchover to the 250mV default value is approximately 3.5V. Gamma Linear Regulator (LR2) Enable Input. When EN is above its enable threshold, VL is above its UVLO threshold, and ONL2 is greater than the internal reference, LR2 is enabled. Drive ONL2 with a logic signal or, for automatic sequencing, connect a capacitor from ONL2 to AGND. If SEQ is high, EN is above its threshold, and VL is above its UVLO threshold, an internal 2µA (typ) current source charges the capacitor. Otherwise, an internal switch discharges the capacitor. Connecting various capacitors to each ONL_ pin allows the programming of the startup sequence. Gate-On Linear Regulator (LR3) Enable Input. When EN is above its enable threshold, VL is above its UVLO threshold, and ONL3 is greater than the internal reference, LR3 is enabled. Drive ONL3 with a logic signal or, for automatic sequencing, connect a capacitor from ONL3 to AGND. If SEQ is high, EN is above its threshold, and VL is above its UVLO threshold, an internal 2µA (typ) current source charges the capacitor. Otherwise, an internal switch discharges the capacitor. Connecting various capacitors to each ONL_ pin allows the programming of the startup sequence. Power Ground Low-Side Gate Driver Output. DL drives the synchronous rectifier of the step-down regulator. DL swings from PGND to VL. DL remains low until VL rises above the UVLO threshold. Step-Down Regulator Current-Sense Input. The IC’s current-sense amplifier inputs for current-mode control connect to IN and LX. Connect IN and LX directly to the high-side Nchannel MOSFET drain and source, respectively. The low-side current-limit comparator inputs connect to LX and PGND to sense voltage across a low-side N-channel MOSFET. MAX1530/MAX1531 12 12 RESET 13 13 COMP 14 14 FB 15 15 ILIM 16 16 ONL2 17 17 ONL3 20 21 20 21 PGND DL 22 22 LX ______________________________________________________________________________________ 11 Multiple-Output Power-Supply Controllers for LCD Monitors MAX1530/MAX1531 Pin Description (continued) PIN MAX1530 23 24 25 26 MAX1531 23 24 25 26 NAME DH BST SEQ FREQ FUNCTION High-Side Gate Driver Output. DH drives the main switch of the step-down regulator. DH swings from LX to BST. Step-Down Regulator Boostrap Capacitor Connection for High-Side Gate Driver. Connect a 0.1µF ceramic capacitor from BST to LX. Sequence Control Input for LR2, LR3, LR4, and LR5. Controls the current sources and switches that charge and discharge the capacitors connected to the ONL_ pins. Oscillator Frequency Select Input. Connect FREQ to VL for 500kHz operation. Connect FREQ to AGND for 250kHz operation. Main Input Voltage (+4.5V to 28V). Bypass IN to AGND with a 1µF ceramic capacitor close to the pins. IN powers the VL linear regulator. Connect IN to the drain of the highside MOSFET (for current sense) through a 1Ω resistor. Internal 5V Linear Regulator Output. Connect a minimum 1µF ceramic capacitor from VL to AGND. Place the capacitor close to the pins. VL can supply up to 30mA for gate drive and external loads. VL remains active when EN is low. Analog Ground Enable Input. This general-purpose on/off control input has an accurate 1.238V (typ) rising threshold with 5% hysteresis. This allows EN to monitor an input voltage level or other analog parameter. If EN is less than its threshold, then the main step-down and all linear regulators are turned off. VL and the internal reference remain active when EN is low. The rising edge of EN clears any latched faults except for a thermal fault, which is cleared only by cycling the input power. An internal filter with a 10µs time constant prevents short glitches from accidentally clearing the fault latch. Low-Voltage Logic Linear Regulator (LR1) Feedback Input. FBL1 regulates at 1.245V nominal. Connect FBL1 to the center tap of a resistive voltage-divider between LR1 output AGND to set the output voltage. Place the divider close to the FBL1 pin. LR1 starts automatically after the step-down converter soft-start ends. Low-Voltage Logic Linear Regulator (LR1) Base Drive. Open drain of an internal N-channel MOSFET. Connect DRV1 to the base of an external PNP pass transistor. (See the Pass Transistor Selection section.) Overcurrent Protection Positive Input. CSH is also the supply input for the overcurrent sense block. CSH and CSL can be used to sense any current in the application circuit and to shut the device down in an overcurrent condition. This feature is typically used to protect the main input or the input to one of the linear regulators since they do not have their own current limits. Insert an appropriate sense resistor in series with the protected input and connect CSH and CSL to its positive and negative terminals. The controller sets the fault latch when VCSH - VCSL exceeds the 300mV (typ) overcurrent threshold. An internal lowpass filter prevents large currents of short duration (less than 50µs) or noise glitches from setting the latch. If the overcurrent protection is not used, connect CSH and CSL to VL. Overcurrent Protection Negative Input. See CSH above. 27 27 IN 28 29 28 29 VL AGND 30 30 EN 31 31 FBL1 32 32 DRV1 — 5 CSH — 6 CSL 12 ______________________________________________________________________________________ Multiple-Output Power-Supply Controllers for LCD Monitors Pin Description (continued) PIN MAX1530 — MAX1531 7 MAX1530/MAX1531 NAME FUNCTION Source Drive Linear Regulator (LR4) Feedback Input. FBL4 regulates at 1.245V nominal. Connect FBL4 to the center tap of a resistive voltage-divider between the LR4 output and AGND to set the output voltage. Place the divider close to the FBL4 pin. Source Drive Linear Regulator (LR4) Base Drive. Open drain of an internal N-channel MOSFET. Connect DRV4 to the base of an external PNP pass transistor to form a positive linear regulator. (See the Pass Transistor Selection section.) Gate-Off Linear Regulator (LR5) Feedback Input. FBL5 regulates at 125mV nominal. Connect FBL5 to the center tap of a resistive voltage-divider between the LR5 output and the internal 5V linear regulator output (VL) to set the output voltage. Place the divider close to the FBL5 pin. Gate-Off Linear Regulator (LR5) Base Drive. Open drain of an internal P-channel MOSFET. Connect DRV5 to the base of an external NPN pass transistor to form a negative linear voltage regulator. (See the Pass Transistor Selection section.) Source Drive Linear Regulator (LR4) Enable Input. When EN is above its enable threshold, VL is above its UVLO threshold, and ONL4 is greater than the internal reference, LR4 is enabled. Drive ONL4 with a logic signal or, for automatic sequencing, connect a capacitor from ONL4 to AGND. If SEQ is high, EN is above its threshold, and VL is above its UVLO threshold, an internal 2µA (typ) current source charges the capacitor. Otherwise, an internal switch discharges the capacitor. Connecting various capacitors to each ONL_ pin allows the programming of the startup sequence. Gate-Off Linear Regulator (LR5) Enable Input. When EN is above its enable threshold, VL is above its UVLO threshold, and ONL5 is greater than the internal reference, LR5 is enabled. Drive ONL5 with a logic signal or, for automatic sequencing, connect a capacitor from ONL5 to AGND. If SEQ is high, EN is above its threshold, and VL is above its UVLO threshold, an internal 2µA (typ) current source charges the capacitor. Otherwise, an internal switch discharges the capacitor. Connecting various capacitors to each ONL_ pin allows the programming of the startup sequence. FBL4 — 8 DRV4 — 9 FBL5 — 10 DRV5 — 18 ONL4 — 19 ONL5 ______________________________________________________________________________________ 13 Multiple-Output Power-Supply Controllers for LCD Monitors MAX1530/MAX1531 VIN = 12V C3 4.7µF 25V R4 20.0kΩ 1% R3 124kΩ 1% D1 R5* 10Ω 24 BST C5 0.1µF IN R12 1Ω C1 1µF 30 EN IN 27 VL 5V/30mA C4 1µF 28 VL DH 23 N1-A L1 10µH C7 22µF 6.3V N1-B R2 10.7kΩ 1% C23 150pF VOUT 3.3V/1.5A R1 17.8kΩ 1% 26 FREQ LX 22 R6* 10Ω 25 R7 100kΩ SEQ DL RESET 20 29 32 21 12 16 R14 121kΩ 1% R15 68.1kΩ 1% R16 43.2kΩ 1% C11 0.1µF VIN C20 0.1µF Q2 VGAMMA 9.7V/50mA C12 0.47µF R18 68.1kΩ 1% R19 10kΩ 1% R17 6.8kΩ D2* ONL2 PGND AGND R8 6.8kΩ C22 2.2µF 17 ONL3 MAX1531 DRV1 Q1 FBL1 31 18 ONL4 RSTIN 19 ONL5 FB COMP ILIM 1 11 14 13 15 D3 DRV2 VIN C14 0.1µF FBL2 DRV3 4 LX Q3 Q6 3 IN R26 10.5kΩ 1% D5 C17 0.1µF 8 DRV4 DRV5 10 LX R28 90.9kΩ 1% R29 48.7kΩ 1% VL D6 Q5 R27 6.8kΩ C18 0.1µF R25 200kΩ 1% C16 0.47µF C8 0.1µF C6 0.1µF R24 6.8kΩ D4 C15 0.1µF R11 100kΩ C10 470pF R10 10kΩ 1% R9 10kΩ 1% C9 10µF 6.3V VL VLOGIC 2.5V/500mA R12 300kΩ C2, OPEN R13 150kΩ 2 VGON 25V/20mA 6 R20 0.5Ω 1% C21 2.2µF VIN 5 R21 1.5kΩ Q4 VSOURCE 10V/500mA C13 4.7µF 16V R22 75kΩ 1% R23 10.7kΩ 1% FBL3 CSL CSH 7 FBL4 FBL5 9 VGOFF -9V/50mA C19 0.47µF *OPTIONAL Figure 1. MAX1531 Standard Application Circuit 14 ______________________________________________________________________________________ Multiple-Output Power-Supply Controllers for LCD Monitors MAX1530/MAX1531 VIN = 12V C3 4.7µF 25V R4 20.0kΩ 1% VL 5V/30mA 28 C4 1µF VL DH 23 R3 124kΩ 1% D1 R5* 10Ω 24 BST 30 EN IN C5 0.1µF IN 27 C1 1µF N1-A L1 10µH C7 22µF C23 6.3V 150pF N1-B C22 2.2µF VOUT 3.3V/1.5A R1 17.8kΩ 1% R2 10.7kΩ 1% R12 1Ω 26 FREQ LX 22 R6* 10Ω 25 R7 100kΩ SEQ DL RESET ONL2 PGND AGND 20 29 32 21 12 16 D2* R14 121kΩ 1% 17 C11 0.1µF ONL3 MAX1530 R8 6.8kΩ DRV1 Q1 5 6 7 8 FBL1 31 N.C. N.C. N.C. N.C. FB RSTIN 11 14 R11 100kΩ C10 470pF R10 10kΩ 1% R9 10kΩ 1% C9 10µF 6.3V VL R12 300kΩ C2, OPEN R13 150kΩ VLOGIC 2.5V/500mA VIN C20 0.1µF Q2 VGAMMA 9.7V/50mA R17 6.8kΩ COMP 13 15 ILIM 1 R18 68.1kΩ 1% C12 0.47µF R19 10kΩ 1% DRV2 VIN R24 6.8kΩ DRV3 4 R22 75kΩ 1% R23 10.7kΩ 1% C13 4.7µF Q4 C21 2.2µF 2 FBL2 FBL3 9 10 N.C. N.C. N.C. N.C. 3 19 18 VSOURCE 10V/500mA *OPTIONAL Figure 2. MAX1530 Standard Application Circuit ______________________________________________________________________________________ 15 Multiple-Output Power-Supply Controllers for LCD Monitors MAX1530/MAX1531 Table 1. Selected Component List DESIGNATION C3 C7 C9 C12, C19* C13 C21, C22 D1, D6* D2 DESCRIPTION 4.7µF, 25V X7R ceramic capacitor (1210) TDK C3225X7R1E475K 22µF, 6.3V X7R ceramic capacitor TDK C3216X7R0J226M 10µF, 6.3V X5R ceramic capacitor TDK C2012X5R0J106M 0.47µF, 16V X7R ceramic capacitors (0805) TDK C2012X7R1C474K 4.7µF, 16V X7R ceramic capacitor TDK C3216X7R1C475K 2.2µF, 25V X7R ceramic capacitors (1206) TDK C3216X7R1C475M 100mA, 30V Schottky diodes (SOD523) Central Semiconductor CMOSH-3 100mA, 75V, small-signal switching diode, SOT23 Fairchild Semiconductor MMBD4148 Q1, Q4 DESIGNATION D3*, D4*, D5* L1 DESCRIPTION 200mA, 25V dual Schottky diodes (SOT23) Fairchild BAT54S 10µH, 2.3A (DC) inductor Sumida CDR7D28MN-100 2.5A, 30V dual N-channel MOSFET (6-pin Super SOT) Fairchild FDC6561AN 3A, 60V low-saturation PNP bipolar transistors (SOT-223) Fairchild NZT660A 200mA, 40V PNP bipolar transistors (SOT23) Fairchild MMBT3906 200mA, 40V NPN bipolar transistors (SOT23) Fairchild MMBT3904 N1 Q2, Q3* Q5*, Q6* *For MAX1531 only. Table 2. Component Suppliers SUPPLIER Central Semi Fairchild Sumida TDK PHONE 516-435-1110 888-522-5372 847-956-0666 847-803-6100 FAX 516-435-1824 972-910-8036 847-956-0702 847-390-4405 WEBSITE www.centralsemi.com www.fairchildsemi.com www.sumida.com www.components.tdk.com Standard Application Circuit The standard application circuit (Figure 1) of the MAX1531 is a complete power-supply system for TFT LCD monitors. The circuit generates a 3.3V/1.5A main output, a 2.5V/500mA output for the timing controller and digital sections of source/gate drive ICs, a 10V/500mA source drive supply voltage, a 9.7V/50mA gamma reference, a 25V/20mA gate-on voltage, and a -10V/50mA gate-off voltage. The input voltage is 12V ±10%. Table 1 lists the selected components and Table 2 lists the component suppliers. The standard application circuit (Figure 2) of the MAX1530 is similar to the MAX1531 application circuit except that gate-on and gate-off voltages are eliminated. Detailed Description The MAX1530/MAX1531 power-supply controllers provide logic and bias power for LCD monitors. Figure 3 shows the IC functional diagram. The main step-down controller employs a current-mode PWM control method to ease compensation requirements and provide excellent load- and line-transient response. The use of synchronous rectification yields excellent efficiency. The MAX1530 includes three analog gain blocks to control three auxiliary positive linear regulators, and the MAX1531 includes five analog gain blocks to control four positive and one negative linear regulators. Use the positive gain blocks to generate low-voltage rails directly from the input voltage or the main step-down converter output, or higher voltages using charge 16 ______________________________________________________________________________________ Multiple-Output Power-Supply Controllers for LCD Monitors MAX1530/MAX1531 FREQ EN RSTIN RESET THERMAL OSC VLOK VL TIMER REF VREF MAX1531 IN VL GND CLOCK SLOPE COMP FB ILIM COMP FB ILIM PGND STEP-DOWN CONTROLLER IN DH LX DL SS DONE DC-DC EN FLTM HIGH-SIDE DRIVER BST DH LX VL DL LOW-SIDE DRIVER PGND DRV3 ONL2 ONL3 ONL4 ONL5 SEQ DRV1 VREF SOFTSTART SEQUENCE ON2 ON3 ON4 ON5 FLTM SEQ FLT3 LDO3EN SOFTSTART VREF FBL3 LR3 0.9VREF DRV4 EN LR1 FLT1 0.9VREF LDO4EN LR4 FLT4 300mV FLTCS 0.9VREF DRV5 VREF SOFTSTART LDO2EN LR2 FLT2 0.9VREF FLT5 400mV LDO5EN LR5 SOFTSTART VREF FBL4 FAULT LOGIC SOFTSTART VREF FBL1 CSH CSL DRV2 FBL2 FBL5 EN VLOK Figure 3. IC Functional Diagram ______________________________________________________________________________________ 17 Multiple-Output Power-Supply Controllers for LCD Monitors ∑ CURRENT SENSE AND CURRENT LIMIT IN SLOPE SS DONE DC-DC EN VREF FB COMP CLOCK SOFTSTART R GM PWM COMP S Q DH Q DL ILIM CURRENT LIMIT FAULT COMPARATOR LX PGND FLTM 0.9VREF During the second half of the cycle, the high-side MOSFET turns off and the low-side N-channel MOSFET turns on. Now the inductor releases the stored energy as its current ramps down, providing current to the output. The output capacitor stores charge when the inductor current exceeds the load current and discharges when the inductor current is lower, smoothing the voltage across the load. Under overload conditions, when the inductor current exceeds the selected current limit (see Current Limit Circuit ), the high-side MOSFET is not turned on at the rising edge of the clock and the lowside MOSFET remains on to let the inductor current ramp down. Under light-load conditions, the MAX1530/MAX1531 maintain a constant switching frequency to minimize cross-regulation errors in applications that use a transformer. The low-side gate-drive waveform is the complement of the high-side gate-drive waveform, which causes the inductor current to reverse under light loads. Current-Sense Amplifier The MAX1530/MAX1531s’ current-sense circuit amplifies the current-sense voltage generated by the highside MOSFET ’ s on-resistance. This amplified current-sense signal and the internal slope compensation signal are summed together and fed into the PWM comparator’s inverting input. Place the high-side MOSFET near the controller, and connect IN and LX to the MOSFET using Kelvin-sense connections to guarantee current-sense accuracy and improve stability. Current-Limit Circuit The MAX1530/MAX1531 include two current-limit circuits that use the two MOSFETs’ on-resistances as current-sensing elements (Figure 4). The high-side MOSFET’s voltage is used with a fixed 400mV (typ) current-limit threshold during the high-side on-times. The low-side MOSFET’s voltage is used with an adjustable current-limit threshold during the low-side on-times. Using both circuits together ensures that the current is always measured and controlled. The high-side MOSFET current limit employs a peak current limit. If the voltage across the high-side MOSFET, measured from IN to LX, exceeds the 400mV threshold during an on-time, the high-side MOSFET turns off and the low-side MOSFET turns on. The low-side MOSFET current-limit circuit employs a “valley” current limit. If the voltage across the low-side MOSFET, measured from LX to PGND, exceeds the low-side threshold at the end of a low-side on-time, the low-side MOSFET remains on and the high-side MOSFET stays off for the entire next cycle. MAX1530/MAX1531 Figure 4. Step-Down Controller Block Diagram pumps attached to the switching node or extra windings coupled to the step-down converter inductor. The negative gain block (MAX1531) can be used in conjunction with a charge pump or coupled winding to generate the LCD gate-off voltage or other negative supplies. Step-Down Controller The MAX1530/MAX1531 include step-down controllers that use a fixed-frequency current-mode PWM control scheme (Figure 4). An internal transconductance amplifier establishes an integrated error voltage at the COMP pin. The heart of the current-mode PWM controller is an open-loop comparator that compares an integrated voltage-feedback signal with an amplified current-sense signal plus a slope-compensation ramp. At each rising edge of the internal clock, the high-side MOSFET turns on until the PWM comparator trips or the maximum duty cycle is reached. During this on-time, current ramps up through the inductor, sourcing current to the output and storing energy in a magnetic field. The current-mode feedback system regulates the peak inductor current as a function of the output voltage error signal. Since the average inductor current is nearly the same as the peak inductor current (assuming that the inductor value is relatively high to minimize ripple current), the circuit acts as a switch-mode transconductance amplifier. That pushes the output LC filter pole, normally found in a voltage-mode PWM, to a higher frequency. To preserve loop stability, the slopecompensation ramp is summed into the main PWM comparator. 18 ______________________________________________________________________________________ Multiple-Output Power-Supply Controllers for LCD Monitors The ILIM pin is a dual-mode input. When ILIM is connected to VL, a default low-side current limit of 250mV (typ) is used. If ILIM is connected to a voltage between 250mV and 3V, the low-side current limit is typically 1/5th the ILIM voltage. The MAX1530/MAX1531s’ current limits are comparatively inaccurate, since the maximum load current is a function of the MOSFETs’ on-resistances and the inductor value, as well as the accuracy of the two thresholds. However, using MOSFET current sensing reduces both cost and circuit size and increases efficiency, since sense resistors are not needed. MOSFET Gate Drivers (DH, DL) The DH and DL drivers are optimized for driving moderate-size high-side and low-side MOSFETs. Adaptive dead-time circuits monitor the DL and DH drivers and prevent either FET from turning on until the other is fully off. This algorithm allows operation without shootthrough with a wide range of MOSFETs, minimizing delays and maintaining efficiency. When the gates are turning off, there must be low-resistance, low-inductance paths from the gate drivers to the MOSFET gates for the adaptive dead-time circuit to work properly. Otherwise, the sense circuitry in the MAX1530/ MAX1531 interpret the MOSFET gate as "off" while gate charge actually remains. Use short, wide traces measuring less than 50 squares (at least 20 mil wide if the MOSFET is 1in from the device). It is advantageous to slow down the turn-on of both gate drivers if there is noise coupling between the switching regulator and the linear regulators. The noise coupling can result in excessive switching ripple on the linear regulator outputs. Slowing down the turn-on of the gate drivers proves to be an effective way of reducing the output ripple. Take care to ensure that the turnoff times are not affected at the same time. As explained above, slowing down the turn-off times may result in shoot-through problems. In Figure 1, a 10Ω resistor (R5) is inserted in series with the BST pin to slow down the turn-on of the high-side MOSFET (N1-B) without affecting the turn-off. A 10Ω resistor (R6) is also inserted between DL and the gate of the low-side MOSFET (N1-A) to slow its turn-on. Because the gate resistor would slow down the turn-off time, connect a switching diode (D2) (such as 1N4148) in parallel with the gate resistor as shown in Figure 1 to prevent potential shoot-through. High-Side Gate-Drive Supply (BST) A flying-capacitor bootstrap circuit generates gatedrive voltage for the high-side N-channel switch (Figure 1). The capacitor C5 between BST and LX is alternately charged from the VL supply and placed parallel to the high-side MOSFET’s gate-source terminals. On startup, the synchronous rectifier (low-side MOSFET) forces LX to ground and charges the boost capacitor from VL through diode D1. On the second half-cycle, the switch-mode power supply turns on the high-side MOSFET by closing an internal switch between BST and DH. This provides the necessary gate-to-source voltage to turn on the high-side switch, an action that boosts the 5V gate-drive signal above the input voltage. Oscillator Frequency Selection (FREQ) The FREQ pin can be used to select the switching frequency of the step-down regulator. Connect FREQ to VL for 500kHz operation. Connect FREQ to AGND for 250kHz operation. The 500kHz operation minimizes the size of the inductor and capacitors. The 250kHz operation improves efficiency by 2% to 3%. MAX1530/MAX1531 Linear Regulator Controllers The MAX1530/MAX1531 include three positive linear regulator controllers, LR1, LR2, and LR3. These linear regulator controllers can be used with external pass transistors to regulate supplies for TFT LCDs. The MAX1531 includes an additional positive linear regulator controller (LR4) and a negative linear regulator controller (LR5). Low-Voltage Logic Regulator Controller (LR1) LR1 is an analog gain block with an open-drain Nchannel output. It drives an external PNP pass transistor with a 6.8kΩ base-to-emitter resistor. Its guaranteed base drive sink current is at least 3mA. The regulator including transistor Q1 in Figure 1 uses a 10µF output capacitor and is designed to deliver 500mA at 2.5V. LR1 is typically used to generate low-voltage logic supplies for the timing controller and the digital sections of the TFT LCD source/gate driver ICs. LR1 is enabled when the soft-start of the main stepdown regulator is complete. (See the Startup Sequence (ONL_,SEQ) section.) Each time it is enabled, the controller goes through a soft-start routine that ramps up its internal reference DAC. (See the Soft-Start section.) Gamma Regulator Controller (LR2) LR2 is an analog gain block with an open-drain Nchannel output. It drives an external PNP pass transistor with a 6.8kΩ base-to-emitter resistor. Its guaranteed base drive sink current is at least 2mA. The regulator including transistor Q2 in Figure 1 uses a 0.47µF output capacitor and is designed to deliver 50mA at 9.7V. ______________________________________________________________________________________ 19 Multiple-Output Power-Supply Controllers for LCD Monitors MAX1530/MAX1531 LR2 is typically used to generate the TFT LCD gamma reference voltage, which is usually 0.3V below the source drive supply voltage. LR2 is enabled when the step-down regulator is enabled and the voltage on ONL2 exceeds ONL2 input threshold (1.238V typ). (See the S tartup Sequence (ONL_,SEQ) section.) Each time it is enabled, the controller goes through a soft-start routine that ramps up its internal reference DAC. (See the Soft-Start section). Linear Regulator Controller (LR3) LR3 is an analog gain block with an open-drain Nchannel output. It drives an external PNP pass transistor with a 6.8kΩ base-to-emitter resistor. Its guaranteed base drive sink current is at least 2mA. The regulator, including Q3 in Figure 1, uses a 0.47µF output capacitor and is designed to deliver 20mA at 25V. The regulator including Q3 in Figure 2 uses a 4.7µF output capacitor and is designed to deliver 500mA at 10V. For the MAX1531 (Figure 1), LR3 is typically used to generate the TFT LCD gate driver’s gate-on voltage. A sufficient input voltage can be produced using a charge-pump circuit as shown in Figure 1. Note that the voltage rating of the DRV3 output is 28V. If higher voltages are present, an external cascode NPN transistor (Q6) should be used with the emitter connected to DRV3, the base to VIN (which is the connection point of C1 and R12 in Figure 1), and the collector to the base of the PNP pass transistor (Figure 1). For the MAX1530 (Figure 2), LR3 is typically used to generate the TFT LCD source drive supply voltage. The input for this regulator can come directly from the input supply, be produced from an external step-up regulator, or from an extra winding coupled to the main step-down regulator inductor. LR3 is enabled when the step-down regulator is enabled and the voltage on ONL3 exceeds the ONL3 input threshold (1.238V typ). (See the Startup Sequence (ONL_,SEQ) section.) Each time it is enabled, the controller goes through a soft-start routine that ramps up its internal reference DAC. (See the Soft-Start section.) Source Drive Regulator Controller (LR4) (MAX1531 Only) LR4 is an analog gain block with an open-drain Nchannel output. It drives an external PNP pass transistor with a 1.5kΩ base-to-emitter resistor. Its guaranteed base drive sink current is at least 10mA. The regulator including Q4 in Figure 1 uses a 4.7µF output capacitor and is designed to deliver 500mA at 10V. The regulator’s fast transient response allows it to handle brief peak currents up to 2A. LR4 is typically used to generate the TFT LCD source drive supply voltage. The input for this regulator can come directly from the input supply, be produced from an external step-up regulator, or from an extra winding coupled to the main step-down regulator inductor. LR4 is enabled when the step-down regulator is enabled and the voltage on ONL4 exceeds the ONL4 input threshold (1.238V typ). (See the S tartup Sequence (ONL_,SEQ) section.) Each time it is enabled, the regulator goes through a soft-start routine that ramps up its internal reference DAC from 0V to 1.238V (typ). (See the Soft-Start section.) The standard application circuit in Figure 1 powers the LR4 regulator directly from the input supply and uses the MAX1531’s general-purpose overcurrent protection function to protect the input supply from excessive load currents. (See the Overcurrent Protection section.) Gate-Off Regulator Controller (LR5) (MAX1531 Only) LR5 is an analog gain block with an open-drain P-channel output. It drives an external NPN pass transistor with a 6.8kΩ base-to-emitter resistor. Its guaranteed base drive sink current is at least 2mA. The regulator including Q5 in Figure 1 uses a 0.47µF output capacitor and is designed to deliver 10mA at -10V. LR5 is typically used to generate the TFT LCD gate driver’s gate-off voltage. A negative input voltage can be produced using a charge-pump circuit as shown in Figure 1. Use as many stages as necessary to obtain the required output voltage. LR5 is enabled when the step-down regulator is enabled and the voltage on ONL5 exceeds the ONL5 input threshold (1.238V typ). (See the S tartup Sequence (ONL_,SEQ) section.) Each time it is enabled, the regulator goes through a soft-start routine that ramps down its internal reference DAC from VL to 125mV (typ). (See the Soft-Start section.) Internal 5V Linear Regulator (VL) All MAX1530/MAX1531 functions, except the thermal sensor, are internally powered from the on-chip, lowdropout 5V regulator. The maximum regulator input voltage (VIN) is 28V. Bypass the regulator’s output (VL) with at least a 1µF ceramic capacitor to AGND. The VIN-to-VL dropout voltage is typically 200mV, so when VIN is less than 5.2V, VL is typically VIN - 200mV. The internal linear regulator can source up to 30mA to supply the device, power the low-side gate driver, charge the external boost capacitor, and supply small external loads. When driving particularly large MOSFETs, little or no regulator current may be available for external 20 ______________________________________________________________________________________ Multiple-Output Power-Supply Controllers for LCD Monitors loads. For example, when switched at 500kHz, large MOSFETs with a total of 40nC total gate charge would require 40nC × 500kHz, which is approximately 20mA. MAX1530/MAX1531 EN > 1.24V AND VL > 3.5V SEQ = HIGH On/Off Control (EN) The EN pin has an accurate 1.238V (typ) rising threshold with 5% hysteresis. The accurate threshold allows it to be used to monitor the input voltage or other analog signals of interest. If VEN voltage is less than its threshold, then the step-down regulator and all linear regulators are turned off. VL and the internal reference remain active when EN is low to allow an accurate EN threshold. A rising edge on the pin clears any latched faults except for a thermal fault, which is cleared only by cycling the input power. STEP-DOWN REGULATOR STARTUP SEQUENCE BLOCK ENABLED ONL_ CURRENT SOURCES ON STEP-DOWN SOFT-START DONE LR1 STARTUP ONL2 > 1.24V ONL3 > 1.24V ONL4 > 1.24V ONL5 > 1.24V LR2 STARTUP LR3 STARTUP LR4 STARTUP LR5 STARTUP Figure 5. Startup Conditions ONLa ONLb ONLc ONLd Undervoltage Lockout If VL drops below 3.4V (typ), the MAX1530/MAX1531 assume that the supply voltage is too low to make valid decisions. Therefore, the undervoltage lockout (UVLO) circuitry turns off all the internal bias supplies. Switching is inhibited, and the DL and DH gate drivers are forced low. After VL rises above 3.5V (typ), the fault and thermal shutdown latches are cleared and startup begins if EN is above its threshold. R3 150kΩ R2 75kΩ R1 51kΩ C1 0.1µF SEQ 5V ONLa ONLb ONLc ONLd Startup Sequence (ONL_, SEQ) The MAX1530/MAX1531 are not enabled unless all four of the following conditions are met: 1) VL exceeds the UVLO threshold, 2) EN is above 1.238V, 3) the fault latch is not set, and 4) the thermal shutdown latch is not set. After all four conditions are met, the step-down controller starts switching and enables soft-start (Figure 5). After the step-down regulator soft-start is done, the lowvoltage logic linear regulator controller (LR1) soft-starts. The remaining linear regulator controllers and the sequence block that can be used to control them are enabled at the same time as the step-down regulator. The SEQ logic input is used in combination with the ONL_ pins to control the startup sequence. When SEQ is high and the sequence block is enabled, each ONL_ pin sources 2µA (typ). When the voltage on an ONL_ pin reaches 1.238V (typ), its respective linear regulator controller (LR_) is enabled. When SEQ is low or the sequence block is not enabled, each ONL_ pin is connected to ground through a 1.5kΩ internal MOSFET. The sequence block allows the user to program the startup of LR2 to LR5 in any desired sequence. If no capacitor is placed on an ONL_ pin, its LR_ controller starts immediately after the sequence block is enabled and SEQ goes high. Placing a 1.5nF capacitor on an ONL_ pin provides about 1ms delay for the respective 1.238V ONL_ 0V OFF LRa OFF LRb OFF LRc LRd OFF 16ms ON OFF ON OFF ON OFF ON OFF Figure 6. Single-Capacitor Sequence Configuration LR_ controller. Placing different size capacitors on each ONL_ pin allows any arbitrary startup sequence. An arbitrary startup sequence can also be created with a single capacitor (Figure 6). Capacitor C1, together with the 8µA current (2µA per ONL_ pin), is chosen to provide the desired delay for the controller that starts last (ONLd). Using 0.1µF for C1 provides about 16ms 21 ______________________________________________________________________________________ Multiple-Output Power-Supply Controllers for LCD Monitors MAX1530/MAX1531 total delay. Because of the 6µA current flowing through R1 (51kΩ), the voltage on ONLc is 0.31V greater than the voltage on ONLd and it crosses the 1.238V threshold and enables its LR_ controller about 4ms before ONLd’s controller. Similarly, the 4µA current through R2 (75kΩ) and the 2µA current through R3 (150kΩ) cause their LR_ controllers to each start about 4ms before the next one. Any desired sequence and delay can be programmed by calculating the charge rate of C1 and voltage drops across R1 through R3. entire fault timer duration, the MAX1530/MAX1531 set the fault latch, shutting down all the regulator outputs. Undervoltage faults do not turn off VL. Once the fault condition is removed, cycling the input voltage or applying a rising edge on SEQ or EN clears the fault latch and reactivates the device. Thermal Protection The thermal protection limits total power dissipation in the MAX1530/MAX1531. If the junction temperature exceeds +160°C, a thermal sensor immediately sets the thermal fault latch, shutting off all the IC ’ s outputs including VL, allowing the device to cool down. The only way to clear the thermal fault latch is to cycle the input voltage after the device cools down by at least 15°C. Overcurrent Protection Block (CSH, CSL) (MAX1531 Only) The MAX1531 includes an uncommitted overcurrent protection block that can be used to measure any input or output current, using a current-sense resistor or other sense element. If the measured current exceeds the overcurrent protection threshold (300mV typ), the MAX1531 immediately sets the undervoltage fault latch, shutting down all the regulator outputs. Overcurrent faults do not turn off VL. An internal lowpass filter prevents large current transients of short duration (less than 50µs) from setting the latch. Once the overcurrent condition is removed, cycling the input voltage clears the fault latch and reactivates the device. A rising edge on SEQ or EN also clears the fault latch. In Figure 1’s circuit, the overcurrent protection is used with the LR4 source driver regulator since that regulator is powered directly from the input supply and has no current limit of its own. The current-sense resistor is placed in series with the input supply, before the linear regulator’s external PNP pass transistor. CSH and CSL are connected to the positive and negative sides of the sense resistor. Soft-Start The soft-start function controls the slew rate of the output voltages and reduces inrush currents during startup. Each regulator (step-down, LR1 to LR5) goes through a soft-start routine after it is enabled. During soft-start, the reference voltage for each positive regulator gradually ramps up from 0V to the internal reference in 32 steps. The reference voltage of the negative regulator ramps down from VL to 125mV in 32 steps. The total soft-start period for each regulator is 1024 clock cycles for 250kHz switching frequency and 2048 clock cycles for 500kHz switching frequency. Reset The MAX1530/MAX1531 include an open-drain timed microprocessor supervisor function to ensure proper startup of digital circuits. The RESET output asserts low whenever RSTIN is less than the RSTIN trip threshold. RESET also asserts low when VL is less than the VL UVLO threshold, EN is low, or the thermal, undervoltage or overcurrent fault latches are set. RESET enters the high-impedance state only after RSTIN remains above the trip threshold for the duration of the reset timeout period. The state of RESET has no effect on other portions of the IC. The RSTIN threshold (1.114V typ) is designed to allow RSTIN to directly connect to any of the MAX1530/ MAX1531s’ feedback input pins, eliminating the need for an additional resistive divider. Typically, RSTIN is connected to FB or FBL1 to monitor the supply voltage for digital logic ICs, but it can be used to monitor any desired output voltage or it can even be used as a general-purpose comparator. Design Procedures Main Step-Down Regulator Inductor Selection Three key inductor parameters must be specified: inductance value (L), peak current (IPEAK), and DC resistance (RDC). The following equation includes a constant, LIR, which is the ratio of peak-to-peak inductor ripple current to DC load current. A higher LIR value allows smaller inductance, but results in higher losses and higher ripple. A good compromise between size and losses is typically found at a 30% ripple current to Fault Protection Undervoltage Protection After its soft-start is done, if the output of the main stepdown regulator or any of the linear-regulator outputs (LR1 to LR5) are below 90% of their normal regulation point, the MAX1530/MAX1531 activate an internal fault timer. If the fault condition remains continuously for the 22 ______________________________________________________________________________________ Multiple-Output Power-Supply Controllers for LCD Monitors load current ratio (LIR = 0.3), which corresponds to a peak inductor current 1.15 times the DC load current: L= VOUT × (VIN − VOUT ) VIN × fSW × ILOAD(MAX) × LIR RDS(ON) is not specified at a suitable temperature, use the maximum room temperature specification and add 0.5% per °C for the RDS(ON) increase with temperature: IPEAK × RDS(ON)_ HOT < 340mV To ensure stable operation of the current-mode PWM, the minimum current-sense ripple signal should exceed 12mV. Since this value depends on the minimum RDS(ON) of the high-side MOSFET, which is not typically a specified parameter, a good rule of thumb is to choose the typical room temperature RDS(ON) about 2 times the amount needed for this: IRIPPLE × RDS(ON)_ TYP > 24mV For example, Figure 1’s circuit is designed for 1.5A and uses a dual MOSFET (N1) for both the high-side and low-side MOSFETs. Its maximum RDS(ON) at room temperature is 145mΩ and an estimate of its maximum RDS(ON) at our chosen maximum temperature of +85°C is 188mΩ. Since the inductor ripple current is 0.5A, the peak current through the MOSFET is 1.75A. So the maximum peak current-sense signal is 330mV, which is less than 340mV. Using the typical RDS(ON) of 113mΩ and the ripple current of 0.5A, the current ripple signal for the PWM is 56mV, much greater than the required 24mV. The RDS(ON) of the low-side MOSFET (also N1) provides current-limit information during the low-side ontime that inhibits a high-side on-time if the MOSFET voltage is too high. The voltage is measured across the low-side MOSFET from PGND to LX and the threshold is set by ILIM. To use the preset 250mV (typ) threshold, connect ILIM to VL and choose a MOSFET with RDS(ON) low enough that the “valley” current does not generate more than 190mV across the MOSFET, even when the MOSFET is hot. If the MOSFET’s RDS(ON) is not specified at a suitable temperature, use the maximum room temperature specification and add 0.5% per °C for the RDS(ON) increase with temperature: IVALLEY = IOUT − IRIPPLE / 2 IVALLEY × RDS(ON)_ HOT < 190mV MAX1530/MAX1531 where ILOAD(MAX) is the maximum DC load current, and the switching frequency fSW is 500kHz when FREQ is tied to VL, and 250kHz when FREQ is tied to AGND. The exact inductor value is not critical and can be adjusted to make trade-offs among size, cost, and efficiency. Lower inductor values minimize size and cost, but they also increase the output ripple and reduce the efficiency due to higher peak currents. On the other hand, higher inductor values increase efficiency, but at some point increased resistive losses due to extra turns of wire will exceed the benefit gained from lower AC current levels. The inductor’s saturation current must exceed the peak inductor current. The peak current can be calculated by: V × (VIN − VOUT ) IRIPPLE = OUT fSW × L × VIN I IPEAK = ILOAD(MAX) + RIPPLE 2 The inductor’s DC resistance should be low for good efficiency. Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, though powdered iron is inexpensive and can work well at 250kHz. Shielded-core geometries help keep noise, EMI, and switching waveform jitter low. MOSFET Selection and Current-Limit Setting The MAX1530/MAX1531s’ step-down controller drives two external logic-level N-channel MOSFETs. Since the RDS(ON) of each MOSFET is used as a sense resistor to provide current-sense signals to the PWM, their RDS(ON) values are important considerations in component selection. The RDS(ON) of the high-side MOSFET (N1) provides an inductor current-sense signal for current-mode operation and also provides a crude maximum current limit during the high-side on-time that prevents runaway currents if the inductor saturates. The MOSFET voltage is measured across the high-side MOSFET from VIN to LX and is limited to 400mV (typ). To ensure the desired output current with sufficient margin, choose a MOSFET with RDS(ON) low enough that the peak current does not generate more than 340mV across the MOSFET, even when the MOSFET is hot. If the MOSFET ’ s If the MOSFET’s RDS(ON) is lower than necessary, there is no need to adjust the current-limit threshold using ILIM. If the MOSFET’s RDS(ON) is too high, adjust the current-limit threshold using a resistive-divider between ______________________________________________________________________________________ 23 Multiple-Output Power-Supply Controllers for LCD Monitors MAX1530/MAX1531 VL and AGND at ILIM. The threshold is approximately 1/5th the voltage on ILIM over a range of 0.25V to 3V: IVALLEY × RDS(ON)_ HOT < 0.2 × VILIM × (1− K) the voltage drop across the capacitor’s ESR caused by the current into and out of the capacitor: VRIPPLE = VRIPPLE(ESR) + VRIPPLE(C) VRIPPLE(ESR) = IRIPPLE × RESR K is the accuracy of the current-limit threshold, which is 20% when the threshold is 250mV. For example, Figure 1’s N1 MOSFET has a maximum RDS(ON) at room temperature of 145mΩ and an estimate of its maximum at our chosen maximum temperature of +85 ° C is 188m Ω . Since the inductor ripple current is 0.5A, the valley current through the MOSFET is 1.25A. So the maximum valley current-sense signal is 235mV, which is too high to work with the 190mV minimum of the default current-limit threshold. Adding a divider at ILIM (R12 and R13) adjusts the ILIM voltage to 1.7V and the current-limit threshold to 340mV, providing more than adequate margin for threshold accuracy. Input Capacitor The input filter capacitor reduces peak currents drawn from the power source and reduce noise and voltage ripple on the input caused by the regulator’s switching. It is usually selected according to input ripple current requirements and voltage rating, rather than capacitance value. The input voltage and load current determine the RMS input ripple current (IRMS): IRMS = ILOAD × VOUT × (VIN − VOUT ) VIN VRIPPLE(C) = IRIPPLE 8 × COUT × fSW The worst case is IRMS = 0.5 × ILOAD, which occurs at VIN = 2 × VOUT. For most applications, ceramic capacitors are used because of their high ripple current and surge current capabilities. For long-term reliability, choose an input capacitor that exhibits less than +10°C temperature rise at the RMS input current corresponding to the maximum load current. Output Capacitor The output capacitor and its equivalent series resistance (ESR) affect the regulator’s loop stability, output ripple voltage, and transient response. The Compensation Design section discusses the output capacitance requirement based on the loop stability. This section deals with how to determine the output capacitance and ESR needs according to the ripple voltage and load transient requirements. The output voltage ripple has two components: variations in the charge stored in the output capacitor, and 24 where COUT is the output capacitance, and RESR is the ESR of the output capacitor. In Figure 1’s circuit, the inductor ripple current is 0.5A. Assume the voltage-ripple requirement is 2% (peak-to-peak) of the 3.3V output, which corresponds to 66mV total peak-to-peak ripple. Assuming that the ESR ripple component and the capacitive ripple component each should be less than 50% of the 66mV total peak-to-peak ripple, then the ESR should be less than 66m Ω and the output capacitance should be more than 7.6µF to meet the total ripple requirement. A 22µF ceramic capacitor with ESR (including PC board trace resistance) of 10mΩ is selected for the standard application circuit in Figure 1, which easily meets the voltage ripple requirement. The step-down regulator’s output capacitance and ESR also affect the voltage undershoot and overshoot when the load steps up and down abruptly. The undershoot and overshoot have three components: the voltage steps caused by ESR, the voltage undershoot and overshoot due to the current-mode control’s AC load regulation, and the voltage sag and soar due to the finite capacitance and inductor slew rate. The amplitude of the ESR steps is a function of the load step and the ESR of the output capacitor: VESR _ STEP = ∆ILOAD × RESR The amplitude of the sag due to the finite output capacitance and inductor slew rate is a function of the load step, the output capacitor value, the inductor value, the input-to-output voltage differential, and the maximum duty cycle: VSAG _ LC = L × (∆ILOAD )2 2 × COUT × (VIN(MIN) × DMAX - VOUT ) The amplitude of the undershoot due to the AC load regulation is a function of the high-side MOSFET RDS(ON), the gain of the current-sense amplifier AVCS, the change of the slope compensation during the undershoot (∆SCUNDER), the transconductance of the error ______________________________________________________________________________________ Multiple-Output Power-Supply Controllers for LCD Monitors amplifier gm, the compensation resistor RCOMP, the FB regulation VFB, and the output voltage set point VOUT:  A VCS × RDS(ON) × ∆ILOAD  VOUT ×    + ∆SCUNDER  VUNDER _ AC = VFB × RCOMP × gm Use the following to calculate the slope compensation change during the sag:   V ∆SCUNDER = 437.5mV ×  DUNDER - OUT  VIN   where DUNDER is the duty cycle at the valley of the sag, which is usually 50%. The actual undershoot is always equal to or bigger than the worst of VESR_STEP, VSAG_LC, and VUNDER_AC. The amplitude of the soar due to the finite output capacitance and inductor slew rate is a function of the load step, the output capacitor value, the inductor value, and the output voltage: VSOAR _ LC = L × (∆ILOAD )2 2 × COUT × VOUT Operating Characteristics is 170mV. The voltage soar due to finite capacitance and inductor slew rate is 155mV, and the voltage overshoot due to the AC load regulation is 167mV. The total overshoot seen the in the Typical Operating Characteristics is 200mV. Compensation Design The step-down controller of the MAX1530/MAX1531 uses a peak current-mode control scheme that regulates the output voltage by forcing the required current through the inductor. The MAX1530/MAX1531 use the voltage across the high-side MOSFET ’ s R DS(ON) to sense the inductor current. Using the current-sense amplifier’s output signal and the amplified feedback voltage sensed at FB, the control loop sets the peak inductor current by: IPEAK = (VOUT - VOUT(SET) ) × VFB × A VEA VOUT(SET) × RDS(ON) × A VCS MAX1530/MAX1531 where VFB = 1.238V is the FB regulation voltage, AVCS is the gain of the current-sense amplifier (3.5 typical), AVEA is the DC gain of the error amplifier (2000 typ), VOUT(SET) is the output voltage set point, and RDS(ON) is the on-resistance of the high-side MOSFET. The total DC loop gain (ADC) is approximately: ADC = VFB × RLE × A VEA VOUT(SET) × RDS(ON) × A VCS The amplitude of the overshoot due to the AC load regulation is:  A VCS × RDS(ON) × ∆ILOAD  VOUT ×    + ∆SCOVER  VFB × RCOMP × gm RLE is the equivalent load resistance, given by: V  L× f OUT SW  RLE =    ||   ILOAD(MAX)   n × D' - D  In the above equation, D’ = 1 - D, n is a factor determined by the slope compensation mc and the inductor current ramp m1, as shown below: n = 1+ mC m1 VOVER _ AC = where ∆SCOVER is the change of the slope compensation during the overshoot, given by: V  ∆SCOVER = 437.5mV ×  OUT - DOVER   VIN  where DOVER is the duty cycle at the peak of the overshoot, which is typically 0%. Similarly, the actual overshoot is always equal to or bigger than the worst of V ESR_STEP , V SOAR_LC , and VOVER_AC. Given the component values in the circuit of Figure 1, during a 1.5A step load transient, the voltage step due to capacitor ESR is negligible. The voltage sag due to finite capacitance and inductor slew rate is 81mV, and the voltage undershoot due to the AC load regulation is 170mV. The total undershoot seen in the T ypical The slope compensation of the MAX1530/MAX1531 is 219mV/µs. The inductor current ramp is a function of the input voltage, output voltage, inductance, high-side MOSFET on-resistance RDS(ON), and the gain of the current-sense amplifier AVCS, and is: m1 = VIN - VOUT × RDS(ON) × A VCS L ______________________________________________________________________________________ 25 Multiple-Output Power-Supply Controllers for LCD Monitors MAX1530/MAX1531 Current-mode control has the effect of splitting the complex pole pair of the output LC filter into a single low-frequency pole and a single high-frequency pole. The low-frequency current-mode pole depends on output capacitor COUT and the equivalent load resistance RLE, given by the following: fPOLE(LOW) = 1 2π × RLE × COUT Unnecessarily high bandwidth can increase noise sensitivity while providing little benefit. Good transient response with low amounts of output capacitance is achieved with a crossover frequency between 20kHz and 100kHz. The series compensation capacitor (C10) generates a dominant pole that sets the desired crossover frequency. Determine C10 using the following expression: C10 ≈ gm × ADC 2π × fCROSSOVER × A VEA The high-frequency current-mode pole is given by: fPOLE(HIGH) = fSW 2π × n × D' where gm is the error amplifier’s transconductance (100µS typ). 2) The compensation resistor R11, together with capacitor C10, provides a zero that is used to cancel the low-frequency current-mode pole. Determine R11 using the following expression: R11 ≈ 1 2π × fPOLE(LOW) × C10 The COMP pin, which is the output of the IC’s internal transconductance error amplifier, is used to stabilize the control loop. A series resistor (R11) and capacitor (C10) are connected between COMP and AGND to form a pole-zero pair. Another pole-zero pair can be added by connecting a feed-forward capacitor (C23) in parallel with feedback resistor R1. The compensation resistor and capacitors are selected to optimize the loop stability. The compensation capacitor (C10) creates a dominant pole at very low frequency (a few hertz). The zero formed by R11 and C10 cancels the low-frequency current-mode pole. The zero formed by R1 and C23 cancels the high-frequency current-mode pole and introduces a preferable higher frequency pole. In applications where ceramic capacitors are used, the ESR zero is usually not a concern because the ESR zero occurs at very high frequency. If the ESR zero does not occur at a frequency at least one decade above the crossover, connect a second parallel capacitor (C2) between COMP and AGND to cancel the ESR zero. The component values shown in the standard application circuits (Figure 1 and 2) yield stable operation and fast transient response over a broad range of input-to-output voltages. To design a compensation network for other components or applications, use the following procedure to achieve stable operation: 1) Select the crossover frequency f CROSSOVER (bandwidth) to be 1/5th the switching frequency fSW or less: f fCROSSOVER ≤ SW 5 3) Because the error amplifier has limited output current (16µA typ), small values of R11 can prevent the error amplifier from providing an immediate COMP voltage change required for good transient response with minimal output capacitance. If the calculated R11 value is less than 100kΩ, use 100kΩ and recalculate C10 using the following formula: C10 ≈ 1 2π × fPOLE(LOW) × 100kΩ Changing C10 also changes the crossover frequency; the new crossover frequency is: fCROSSOVER = gm × ADC 2π × C10 × A VEA The calculated crossover frequency should be less than 1/5th the switching frequency. There are two ways to lower the crossover frequency if the calculated value is greater than 1/5th the switching frequency: increase the high-side MOSFET R DS(ON ), or increase the output capacitance. Increasing RDS(ON) reduces the DC loop gain, which results in lower crossover frequency. Increasing output capacitance reduces the frequency of the lower low-frequency current-mode pole, which also results in lower crossover frequency. The following formula gives the 26 ______________________________________________________________________________________ Multiple-Output Power-Supply Controllers for LCD Monitors crossover frequency as a function the MOSFET RDS(ON) and the output capacitance: fCROSSOVER = gm × VFB × R11 2π × A VCS × VOUT(SET) × COUT × RDS(ON) 5) For most applications using tantalum or polymer capacitors, the output capacitor’s ESR forms a second zero that occurs either below or close to the crossover frequency. The zero must be cancelled with a pole. Verify the frequency of the output capacitor’s ESR zero, which is: fZERO(ESR) = 1 2π × COUT × RESR MAX1530/MAX1531 Change one or both of these circuit parameters to obtain the desired crossover. Recalculate ADC and repeat steps 1 to 3 after making the changes. 4) If fPOLE(HIGH) is less than the crossover frequency, cancel the pole with a feed-forward zero. Determine the value of C23 (feedback capacitor) using the following: C23 ≈ 1 2π × fPOLE(HIGH) × R1 where RESR is the ESR of the output capacitor COUT. If the output capacitor’s ESR zero does not occur well after the crossover, add the parallel compensation capacitor (C2) to form another pole to cancel the ESR zero. Calculate the value of C2 using: C2 ≈ C10 2π × fZERO(ESR) × R11 × C10 - 1 C23 also forms a secondary pole with R1 and R2 given by the following: fPOLE _ SEC = 1 2π × (R1 || R2) × C23 The frequency of this pole should be above the crossover frequency for loop stability. The position of this pole is related to the high-frequency currentmode pole, which is determined by the inductor current ramp signal. The inductor current ramp signal must satisfy the following condition to ensure the pole occurs above the crossover frequency: m1 > 2π × D' × R2 × fCROSSOVER × mC R1+ R2) × fSW - 2π × D' × R2 × fCROSSOVER ( Applications using ceramic capacitors usually have ESR zeros that occur at least one decade above the crossover. Since the ESR zero of ceramic capacitors has little effect on the loop stability, it does not need to be cancelled. The following is an example. In the circuit of Figure 1, the input voltage is 12V, the output voltage is set to 3.3V, the maximum load current is 1.5A, the typical onresistance of the high-side MOSFET is 100mΩ, and the inductor is 10µH. The calculated equivalent load resistance is 1.67Ω. The DC loop gain is: ADC ≈ 1.238V × 1.67Ω × 2000 = 4180 3.3V × 100mΩ × 3.5 If the frequency of the secondary pole is below the crossover frequency, the frequency of the secondary pole must be moved higher, or the crossover frequency must be moved lower. There are two ways to increase the frequency of the secondary pole: increase the high-side MOSFET RDS(ON), or reduce the step-down inductance, L. As explained before, for given input and output voltages, the current ramp signal is proportional to the high-side MOSFET RDS(ON), and inversely proportional to the inductance. If the pole occurs below the crossover frequency, the current feedback signal is too small. Increasing RDS(ON) or reducing the inductance can increase the current feedback signal. To lower the crossover frequency, use the methods described in step 3. Repeat steps 1 to 4 after making the changes. If the chosen crossover frequency is 20kHz (step 1): C10 ≈ 100µS × 4180 ≈ 1.7nF 2π × 20kHz × 2000 With a 22µF output capacitor, the output pole of the step-down regulator is (step 2): fPOLE(OUT) = Calculate R11 using: R11 ≈ 1 = 22kΩ 2π × 4.3kHz × 1.7nF 1 = 4.3kHz 2π × 22µF × 1.67Ω ______________________________________________________________________________________ 27 Multiple-Output Power-Supply Controllers for LCD Monitors MAX1530/MAX1531 Because R11 is less than 100kΩ, use 100kΩ for R11 and recalculate C10 as (step 3): C10 ≈ 1 = 370pF 2π × 4.3kHz × 100kΩ Charge Pumps Selecting the Number of Charge-Pump Stages For highest efficiency, always choose the lowest number of charge-pump stages that meet the output requirement. The number of positive charge-pump stages is given by: V +V −V NPOS = POS DROPOUT IN VIN − 2 × VD where NPOS is the number of positive charge-pump stages, VPOS is the positive charge-pump output, VIN is the input voltage of the step-down regulator, VD is the forward voltage drop of the charge-pump diode, and VDROPOUT is the dropout margin for the linear regulator. Use VDROPOUT = 0.3V. The number of negative charge-pump stages is given by: NNEG = −VNEG + VDROPOUT VIN − 2 × VD Use the standard value of 470pF for C10 and recalculate the crossover frequency as: fCROSSOVER ≈ 100µS × 4180 = 70.8kHz 2π × 470pF × 2000 Since the crossover frequency is less than 1/5th the switching frequency, 470pF is an acceptable value for C10. Because the high-frequency pole of the current-mode control is at 64kHz, the feed-forward capacitor is (step 4): C23 ≈ 1 = 140pF 2π × 64kHz × 17.8kΩ Use a standard value of 150pF for C23. The pole formed by C23, R1 and R2 occur at 159kHz, above the 70.8kHz crossover frequency. Because a ceramic output capacitor is used in the circuit of Figure1, the ESR zero occurs well above the crossover frequency, so no additional compensation capacitor (C2) is needed (step 5). Output Voltage Selection The MAX1530/MAX1531 step-down regulator’s output voltage can be adjusted by connecting a resistive voltage-divider from the output to AGND with the center tap connected to FB (Figure 1). Select R2 in the 5kΩ to 50kΩ range. Calculate R1 with the following equation: V  R1 = R2 ×  OUT − 1  VFB  where VFB = 1.238V, and VOUT may vary from 1.238V to approximately 0.6 × VIN (VIN is up to 28V). Boost-Supply Diode A signal diode, such as the 1N4148, works well in most applications. If the input voltage goes below 6V, use a small 100mA Schottky diode for slightly improved efficiency and dropout characteristics. Do not use power diodes, such as the 1N5817 or 1N4001, since high junction capacitance can charge up VL to excessive voltages. where NNEG is the number of negative charge-pump stages, VNEG is the negative charge-pump output, VIN is the input voltage of the step-down regulator, VD is the forward voltage drop of the charge-pump diode, and VDROPOUT is the dropout margin for the linear regulator. Use VDROPOUT = 0.3V. The above equations are derived based on the assumption that the first stage of the positive charge pump is connected to VIN and the first stage of the negative charge pump is connected to ground. Sometimes fractional stages are more desirable for better efficiency. This can be done by connecting the first stage to VOUT or another available supply. If the first stage of the positive charger pump is powered from the output of the step-down regulator VOUT, then the equation becomes: NPOS = −VPOS + VDROPOUT − VOUT VIN − 2 × VD If the first stage of the negative charge pump is powered from the output of the step-down regulator VOUT, then the equation becomes: NNEG = −VNEG + VDROPOUT + VOUT VIN − 2 × VD 28 ______________________________________________________________________________________ Multiple-Output Power-Supply Controllers for LCD Monitors Flying Capacitors Increasing the flying capacitor value lowers the effective source impedance and increases the output current capability. Increasing the capacitance indefinitely has a negligible effect on output current capability because the internal switch resistance and the diode impedance place a lower limit on the source impedance. A 0.1µF ceramic capacitor works well in most low-current applications. The voltage rating for a given flying capacitor (CX) must exceed the following: VCX > N x VIN where N is the stage number in which the flying capacitor appears, and VIN is the input voltage of the stepdown regulator. Charge-Pump Output Capacitors Increasing the output capacitance or decreasing the ESR reduces the charge pump output ripple voltage and the peak-to-peak transient voltage. With ceramic capacitors, the output voltage ripple is dominated by the capacitance value. Use the following equation to approximate the required capacitor value: COUT ≥ ILOAD 2fOSCVRIPPLE VGOFF to VL with the center tap connected to FBL5 (Figure 1). Select R29 in the 10k Ω to 30k Ω range. Calculate R28 with the following equation: R28 = R29 × (VFBL5 − VGOFF ) /(VL − VFBL5 ) where VFBL5 = 125mV and VL = 5.0V. Pass Transistor Selection The pass transistor must meet specifications for DC current gain (hFE), collector-emitter saturation voltage, and power dissipation. The transistor’s current gain limits the guaranteed maximum output current to:  V ILOAD(MAX) =  IDRV − BE  × hFE RBE   where IDRV is the minimum guaranteed base drive current, VBE is the base-emitter voltage of the pass transistor, and RBE is the pullup resistor connected between the transistor’s base and emitter. Furthermore, the transistor’s current gain increases the linear regulator’s DC loop gain (see the S tability Requirements section), which may destabilize the output. Therefore, transistors with current gain over 300 at the maximum output current can be difficult to stabilize and are not recommended unless the high gain is needed to meet the load current requirements. The transistor’s saturation voltage at the maximum output current determines the minimum input-to-output voltage differential that the linear regulator supports. Also, the package’s power dissipation limits the usable maximum input-to-output voltage differential. The maximum power dissipation capability of the transistor’s package and mounting must exceed the actual power dissipation in the device. The power dissipation equals the maximum load current (ILOAD(MAX)) times the maximum input-to-output voltage differential: P = ILOAD(MAX) × (VLRIN(MAX) − VLROUT ) where VLRIN(MAX) is the maximum input voltage of the linear regulator, and VLROUT is the output voltage of the linear regulator. Output Voltage Ripple Ideally, the output voltage of a linear regulator should not contain any ripple. In the MAX1530/MAX1531, the step-down regulator’s switching noise can couple to the linear regulators, creating output voltage ripple. Following the PC board layout guidelines in the PC Board Layout and Grounding section can significantly reduce noise coupling. If there is still an unacceptable 29 MAX1530/MAX1531 [ ] where VRIPPLE is the peak-to-peak value of the output ripple. Charge-Pump Rectifier Diodes Use low-cost silicon switching diodes with a current rating equal to or greater than 2 times the average charge-pump input current. If it helps avoid an extra stage, some or all of the diodes can be replaced with Schottky diodes with an equivalent current rating. Linear Regulator Controllers Output Voltage Selection Adjust the positive linear regulator (LR1 to LR4) output voltages by connecting a resistive voltage-divider from the output to AGND with the center tap connected to FBL_ (Figure 1). Select the lower resistor of the divider in the 10kΩ to 30kΩ range. Calculate the upper resistor with the following equation: RUPPER = RLOWER × VOUT _ / VFBL _ − 1 [( ) ] where VFBL_ is 1.238V (typ). Adjust the negative linear regulator (LR5) output voltage by connecting a resistive voltage-divider from ______________________________________________________________________________________ Multiple-Output Power-Supply Controllers for LCD Monitors MAX1530/MAX1531 amount of ripple after the PC board layout has been optimized, consider increasing output capacitance. Adding more capacitance does not eliminate the ripple, but proportionally reduces the amplitude of the ripple. If increasing the output capacitance is not desirable because of space or cost concerns, then consider slowing the turn-on of the step-down DC-to-DC MOSFETs. Slower turn-on leads to smoother LX rising and falling edges and consequently reduces the switching noise. When slowing down MOSFET turn-on, ensure the turn-off time is not affected. Otherwise, the adaptive dead-time circuitry may not work properly and shoot-through may occur. See the MOSFET Gate Drivers section for details on how to slow down the turn-on of both DH and DL. Stability Requirements The MAX1530/MAX1531 linear-regulator controllers use an internal transconductance amplifier to drive an external pass transistor. The transconductance amplifier, the pass transistor, the base-emitter resistor, and the output capacitor determine loop stability. The following applies equally to all linear regulators in the MAX1530 and MAX1531. Any differences are highlighted where appropriate. The transconductance amplifier regulates the output voltage by controlling the pass transistor’s base current. The total DC loop gain is approximately:  4  I ×h  A V(LR) ≈   × 1+ BIAS FE  × VREF ILOAD   VT   where VT is 26mV at room temperature, ILOAD is the output current of the linear regulator, VREF is the linear regulator’s internal reference voltage, and IBIAS is the current through the base-to-emitter resistor (RBE). Each of the linear regulator controllers is designed for a different maximum output current so they have different output drive currents and different bias currents (IBIAS). Each controller ’ s bias current can be found in the Electrical Characteristics . The current listed in the Conditions column for the FBL_ regulation voltage specification is the individual controller’s bias current. The base-to-emitter resistor for each controller should be chosen to set the correct IBIAS: RBE = VBE IBIAS amplifier delay, the pass transistor’s input capacitance, and the stray capacitance at the feedback node create additional poles in the system, and the output capacitor’s ESR generates a zero. For proper operation, use the following steps to ensure the linear regulator’s stability: 1) First, calculate the dominant pole set by the linear regulator’s output capacitor and the load resistor: fPOLE(LR) = 1 2πCLRRLOAD where CLR is the output capacitance of the linear regulator and RLOAD is the load resistance corresponding to the maximum load current. The unity-gain crossover of the linear regulator is: f CROSSOVER = A V(LDO)f POLE(LDO) 2) The pole created by the internal amplifier delay is about 1MHz: fPOLE( AMP) ≅ 1MHz 3) Next, calculate the pole set by the transistor’s input capacitance, the transistor’s input resistance, and the base-to-emitter pullup resistor: fPOLE(CIN ) = 1 2πCIN (RBE || RIN ) where CIN = gm h , RIN = Rπ = FE , gm is the 2πfT gm transconductance of the pass transistor, and fT is the transition frequency. Both parameters can be found in the transistor’s data sheet. Because RBE is much greater than RIN, the above equation can be simplified: fPOLE(CIN ) ≈ 1 2πCINRIN The equation can be further simplified: f fPOLE(CIN ) = T hFE The output capacitor and the load resistance create the dominant pole in the system. However, the internal 30 ______________________________________________________________________________________ Multiple-Output Power-Supply Controllers for LCD Monitors 4) Next, calculate the pole set by each linear regulator ’ s feedback resistance and the capacitance (CFBL_) between FBL_ and AGND (approximately 5pF including stray capacitance): 1 2πCFBL1(R9 || R10) 1 fPOLE(FBL2) = 2πCFBL2 (R18 || R19) 1 fPOLE(FBL3) = 2πCFBL3 (R25 || R26) 1 fPOLE(FBL4) = and 2πCFBL4 (R22 || R23) 1 fPOLE(FBL5) = 2πCFBL5 (R28 || R29) fPOLE(FBL1) = 5) Next, calculate the zero caused by the output capacitor’s ESR: fESR _ ZERO = 1 2πCLRRESR (islands) together at only one location, which is a via connected to the backside pad of the device. All voltage-feedback dividers should be connected to the analog ground island. The step-down regulator’s input and output capacitors, and the charge pump components should be a wide power ground plane. The power ground plane should be connected to the power ground pin (PGND) with a wide trace. Maximizing the width of the power ground traces improves efficiency, and reduces output voltage ripple and noise spikes. All other ground connections, such as the VL and IN pin bypass capacitor and the linear regulator output capacitors, should be star-connected to the backside of the device with wide traces. Make no other connections between these separate ground planes. 3) Place the IN pin and VL pin bypass capacitors within 5mm from the IC and connect them to their respective pins with short, direct connections. 4) Since both MOSFETs are used for current sensing, care must be taken to ensure that noise and DC errors do not corrupt the sense signals. Place both MOSFETs close to the IC. Connect PGND to the source of the low-side MOSFET with a short, wide trace. Connect DL to the gate of the low-side MOSFET with a short, wide trace. Ensure that the traces from DL to low-side MOSFET to PGND total no more than 50 squares. Connect LX close to the connection point between the low-side and highside MOSFETs with a short, wide trace. Connect DH to the gate of the high-side MOSFET with a short, wide trace. Ensure that the traces from DH to high-side MOSFET to LX total no more than 50 squares (50 squares corresponds to 20 mils wide if the total trace is 1in long). 5) Place all feedback voltage-divider resistors as close to their respective feedback pins as possible. The divider’s center trace should be kept short. Placing the resistors far away causes their FB traces to become antennas that can pick up switching noise. Care should be taken to avoid running any feedback trace near LX or the switching nodes in the charge pumps. 6) Minimize the length and maximize the width of the traces between the output capacitors and the load for best transient responses. 7) Minimize the size of the LX node while keeping it wide and short. Keep the LX node away from feedback nodes and analog ground. Use DC traces as shield if necessary. MAX1530/MAX1531 where RESR is the equivalent series resistance of CLR. 6) To ensure stability, choose CLR large enough so that the crossover occurs well before the poles and zero calculated in steps 2) to 5). The poles in steps 3) and 4) generally occur at several megahertz and using ceramic capacitors ensures the ESR zero occurs at several megahertz as well. Placing the crossover below 500kHz is sufficient to avoid the amplifier-delay pole and generally works well, unless unusual component choices or extra capacitances move the other poles or zero below 1MHz. PC Board Layout and Grounding Careful PC board layout is important for proper operation. Use the following guidelines for good PC board layout: 1) Place the high-power components of the step-down regulator (input capacitors, MOSFETs, inductor, and output capacitors) first, with any grounded connections adjacent. Connect these components with short, wide traces. Avoid using vias in the high-current paths. If vias are unavoidable, use many vias in parallel to reduce resistance and inductance. 2) Create islands for the analog ground (AGND), power ground (PGND), and individual linear regulator grounds. Connect all these ground areas ______________________________________________________________________________________ 31 Multiple-Output Power-Supply Controllers for LCD Monitors MAX1530/MAX1531 Pin Configuration DRV1 AGND FBL1 FREQ EN Chip Information TRANSISTOR COUNT: 5600 PROCESS: BiCMOS VL IN 32 31 30 29 28 27 26 25 24 23 22 21 SEQ DRV2 FBL2 FBL3 DRV3 CSH* CSL* FBL4* DRV4* 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 BST DH LX DL PGND ONL5* ONL4* ONL3 MAX1530 MAX1531 20 19 18 17 9 RSTIN COMP ILIM FB DRV5* FBL5* * = N.C. FOR MAX1530 THIN QFN 32 ______________________________________________________________________________________ RESET ONL2 Multiple-Output Power-Supply Controllers for LCD Monitors Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX1530/MAX1531 0.15 C A D2 C L D b D2/2 0.10 M C A B PIN # 1 I.D. D/2 0.15 C B k PIN # 1 I.D. 0.35x45 E/2 E2/2 E (NE-1) X e C L E2 k L DETAIL A e (ND-1) X e C L C L L L e 0.10 C A 0.08 C e C A1 A3 PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm APPROVAL DOCUMENT CONTROL NO. REV. 21-0140 C 1 2 COMMON DIMENSIONS EXPOSED PAD VARIATIONS NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm APPROVAL DOCUMENT CONTROL NO. REV. 21-0140 C 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. QFN THIN.EPS