19-2861; Rev 3; 2/07
KIT ATION EVALU LE B AVAILA
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
General Description
The MAX1540A/MAX1541 dual pulse-width modulation (PWM) controllers provide the high efficiency, excellent transient response, and high DC-output accuracy necessary for stepping down high-voltage batteries to generate low-voltage chipset and RAM power supplies in notebook computers. The Maxim proprietary Quick-PWM™ controllers are free running, constant on-time with input feed forward. This configuration provides ultra-fast transient response, wide input-output (I/O) differential range, low supply current, and tight load-regulation characteristics. The controllers can accurately sense the inductor current across an external current-sense resistor in series with the output to ensure reliable overload and inductor saturation protection. Alternatively, the controllers can use the synchronous rectifier itself or lossless inductor current-sensing methods to provide overload protection with lower power dissipation. For a single step-down PWM controller with inductorsaturation protection, external-reference input voltage, and dynamically selectable output voltages, refer to the MAX1992/MAX1993 data sheet.
Features
♦ Inductor-Saturation Protection ♦ Accurate Differential Current-Sense Inputs ♦ Dual Ultra-High-Efficiency Quick-PWMs with 100ns Load-Step Response ♦ MAX1540A 1.8V/1.2V Fixed or 0.7V to 5.5V Adjustable Output (OUT1) 2.5V/1.5V Fixed or 0.7V to 5.5V Adjustable Output (OUT2) Fixed 5V, 100mA Linear Regulator ♦ MAX1541 External Reference Input (REFIN1) Dynamically Selectable Output Voltage—0.7V to 5.5V (OUT1) 2.5V/1.8V Fixed or 0.7V to 5.5V Adjustable Output (OUT2) Optional Power-Good and Fault Blanking During Transitions Fixed 5V or Adjustable 100mA Linear Regulator ♦ 1% VOUT Accuracy over Line and Load ♦ 2V to 28V Battery Input Range ♦ 170kHz to 620kHz Selectable Switching Frequency ♦ Overvoltage/Undervoltage-Protection Option ♦ 1.7ms Digital Soft-Start ♦ Drives Large Synchronous-Rectifier FETs ♦ 2V ±0.7% Reference Output ♦ Separate Power-Good Window Comparators
MAX1540A/MAX1541
Applications
Notebook Computers Core/I/O Supplies as Low as 0.7V 0.7V to 5.5V Supply Rails CPU/Chipset/GPU with Dynamic Voltage Core Supplies (MAX1541) DDR Memory Termination (MAX1541) Active Termination Buses (MAX1541)
Pin Configurations
LDOOUT LDOON BST1 V+
TOP VIEW
24
23
22
21
20
19
18
Ordering Information
DH1
17
GND
DL1
DL2
LX1
25 26 27 28 29 30 31 32
16 15 14 13
BST2 LX2 DH2
PART MAX1540AETJ MAX1540AETJ+ MAX1541ETL MAX1541ETL+
TEMP RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C
PINPACKAGE 32 Thin QFN 5mm x 5mm 32 Thin QFN 5mm x 5mm 40 Thin QFN 6mm x 6mm 40 Thin QFN 6mm x 6mm
PKG CODE T3255-4 T3255-4 T4066-5
PGOOD1 OUT1
FB1 CSN1
CSP1
PGOOD2 OUT2
FB2
MAX1540A
12 11 10 9
ON2 ON1
CSN2 CSP2
1
2
3
4
5
6
7 ILIM2
OVP/UVP
ILIM1
SKIP
LSAT
TON
T4066-5
+Denotes a lead-free package. Quick-PWM is a trademark of Maxim Integrated Products, Inc.
THIN QFN
A "+" SIGN WILL REPLACE THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES.
Pin Configurations continued at end of data sheet. 1
________________________________________________________________ Maxim Integrated Products
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
VCC
REF
8
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
ABSOLUTE MAXIMUM RATINGS
V+, LDOON to GND ...............................................-0.3V to +28V LDOOUT to GND (MAX1540A, Note 1)....................-0.3V to +6V LDOOUT to GND (MAX1541, Note 1) ....................-0.3V to +28V VDD to GND (MAX1541, Note 1) ..............................-0.3V to +6V VCC, ON_ to GND.....................................................-0.3V to +6V SKIP, PGOOD_ to GND............................................-0.3V to +6V FB_, CSP_, ILIM_ to GND.........................................-0.3V to +6V TON, OVP/UVP, LSAT to GND ...................-0.3V to (VCC + 0.3V) REF, OUT_ to GND.....................................-0.3V to (VCC + 0.3V) LDOIN to GND (MAX1541).....................................-0.3V to +28V REFIN1, GATE, OD, FBLDO to GND (MAX1541).....-0.3V to +6V FBLANK, CC1 to GND (MAX1541).............-0.3V to (VCC + 0.3V) DL_ to GND (Note 1) ..................................-0.3V to (VDD + 0.3V) CSN_ to GND ............................................................-2V to +30V DH_ to LX_..................................................-0.3V to (BST + 0.3V) LX_ to GND................................................................-2V to +30V BST_ to LX_ ..............................................................-0.3V to +6V REF Short Circuit to GND ...........................................Continuous Continuous Power Dissipation (TA = +70°C) 32-Pin 5mm x 5mm Thin QFN (derated 21.3mW/°C above +70°C).............................................................1702mW 40-Pin 6mm x 6mm Thin QFN (derated 26.3mW/°C above +70°C).............................................................2105mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C
Note 1: For the MAX1540A, the gate-driver input supply (VDD) is internally connected to the fixed 5V linear-regulator output (LDOOUT), and the linear-regulator input supply (LDOIN) is internally connected to the battery voltage input (V+).
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER INPUT SUPPLIES (Note 1) VIN Input Voltage Range VBIAS VLDOIN MAX1540A: battery voltage, V+ > VLDOOUT MAX1541: battery voltage, V+ > VLDOOUT VCC, VDD (MAX1541) MAX1541: LDO input supply, VLDOIN > VLDOOUT FB1 and FB2 forced above the regulation point, LSAT = GND Quiescent Supply Current (VCC) ICC FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC, VLSAT > 0.5V FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC MAX1540A: FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC, VLDOON = V+ = 28V MAX1541: ON1 or ON2 = VCC, VLDOON = V+ = 28V Quiescent Supply Current (LDOIN, MAX1541 Only) Standby Supply Current (VCC) ILDOIN FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC, VLDOON = V+ = 28V ON1 = ON2 = GND, VLDOON = V+ = 28V ILOAD + COUT V dt Adding a capacitor across REFIN1 and GND filters noise and controls the rate of change of the REFIN1
The maximum input voltage for the linear regulator is 28V, while the minimum input voltage is determined by the 800mV (max) dropout voltage (V LDOIN(MIN) = VLDOOUT + VDROPOUT) at 50mA load. Bypass the linear regulator’s output (LDOOUT) with a 4.7µF or greater capacitor, providing at least 1µF per 5mA of internal and external load on the linear regulator. The LDO can source up to 100mA for powering the controller or supplying a small external load. For the MAX1540A, the linear regulator provides the 5V bias supply that powers the gate drivers and analog controller (Figure 1), providing stand-alone capability. The linear regulator’s input is internally connected to the battery voltage input (LDOIN = V+), and the gatedriver input supply is internally connected to the linear regulator’s output (VDD = LDOOUT). Figure 13 is the internal linear-regulator functional diagram. For the MAX1541, the linear regulator supports Dual Mode operation to allow the selection of a 5V output voltage without requiring external components (Figure 1). Connect FBLDO to GND for a fixed 5.0V output. The linear regulator’s output voltage can be adjusted from 1.25V to 5.5V using a resistive voltage-divider (Figure 12). The MAX1541 regulates FBLDO to a 1.25V feedback voltage. The adjusted output voltage is: ⎛ R11 ⎞ VLDOOUT = VFBLDO ⎜1+ ⎟ ⎝ R12 ⎠ where VFBLDO = 1.25V. If unused, disable the MAX1541 linear regulator by connecting LDOON to GND.
______________________________________________________________________________________
33
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
+5V BIAS SUPPLY INPUT (VIN)* 7V TO 20V CIN (2) 4.7μF
C1 1μF VDD V+
DBST NH1 DH1 BST1 CBST1 0.1μF LX1 DL1 L1 1.8μH NL1 DL1 SKIP CSP1 RCS1 15mΩ OUTPUT 1 VOUT(HIGH) = 1.5V VOUT(LOW) = 1.0V CSN1 OUT1 COUT1 470μF FB1 CCC1 47pF CC1 CREF 0.22μF REF CILIM1 470pF R2 100kΩ ILIM1 R3 49.9kΩ CILIM2 470pF R4 100kΩ ILIM2 R5 49.9kΩ
MAX1541
DH2 BST2
DBST NH2
CBST 0.1μF LX2 DL2 GND CSP2 RCS2 15mΩ CSN2 OUT2 FB2 OVP/UVP COUT2 220μF OUTPUT 2 VOUT2 = 2.5V NL2 DL2 L2 4.3μH
R9 VOUT(LOW) = VREF (R8 + R9 ) VOUT(HIGH) = VREF
(
)
(R9 + R10) [R8 + (R9 + R10)]
LSAT TON LDOON ON1 ON2
OPEN (ILIM(VAL) x 1.75) REF (485kHz/355kHz) ON
OFF R1 20Ω +5V BIAS SUPPLY
VCC C2 1μF R6 100kΩ R7 100kΩ
PGOOD1 VOUT(LOW) GATE VOUT(HIGH) OPEN (ENABLED, 140μs) REF R8 75kΩ R9 75kΩ OD CREFIN 470pF EP R10 150kΩ R12 20kΩ LDOIN FBLANK REFIN1 LDOOUT R11 32.4kΩ FBLDO C4 22μF C3 4.7μF PGOOD2 R13 10Ω
POWER-GOOD
+5V BIAS SUPPLY
LDO OUTPUT VLDOOUT = 3.3V
POWER GROUND SEE TABLE 1 FOR COMPONENT SPECIFICATIONS. ANALOG GROUND *LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE.
Figure 12. MAX1541 Standard Application Circuit 34 ______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
V+ *LDOIN INTERNAL LDOIN OPTION BETWEEN THE MAX1540A/MAX1541 LDOOUT INTERNAL VDD OPTION BETWEEN THE MAX1540A/MAX1541 *VDD FIXED 5V
VL REG AND REF LDOON
GATE DRIVER AND ERROR AMP
*FBDLO
INTERNAL FBLDO OPTION BETWEEN THE MAX1540A/MAX1541
0.2V *MAX1541 ONLY.
Figure 13. Internal Linear-Regulator Functional Diagram
Design Procedure
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: • Input voltage range: The maximum value (VIN(MAX)) must accommodate the worst-case, high AC-adapter voltage. The minimum value (VIN(MIN)) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. • Maximum load current: There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components.
•
Switching frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. Inductor operating point: This choice provides trade-offs between size vs. efficiency and transient response vs. output ripple. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output ripple due to increased ripple currents. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further sizereduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. When pulse skipping (SKIP low and light loads), the inductor value also determines the load-current value at which PFM/PWM switchover occurs.
35
•
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
Inductor Selection
The switching frequency and inductor operating point determine the inductor value as follows: L= VIN × fSW x ILOAD(MAX) × LIR VOUT (VIN - VOUT )
Setting the Current Limit
The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half the ripple current; therefore: ⎛ VOUT (VIN(MIN) - VOUT ) ⎞ ILIM(VAL) > ILOAD(MAX) - ⎜ ⎟ 2VIN(MIN) fSW L ⎠ ⎝ where ILIM(VAL) equals the minimum valley current-limit threshold voltage divided by the current-sense resistance (RSENSE). For the 50mV default setting, the minimum valley current-limit threshold is 40mV. Connect ILIM_ to VCC for a default 50mV valley currentlimit threshold. In adjustable mode, the valley currentlimit threshold is precisely 1/10th the voltage seen at ILIM_. For an adjustable threshold, connect a resistive divider from REF to analog ground (GND) with ILIM_ connected to the center tap. The external 250mV to 2V adjustment range corresponds to a 25mV to 200mV valley current-limit threshold. When adjusting the current limit, use 1% tolerance resistors and a divider current of approximately 10µA to prevent significant inaccuracy in the valley current-limit tolerance. The current-sense method (Figure 14) and magnitude determine the achievable current-limit accuracy and power loss (Table 9). Typically, higher current-sense voltage limits provide tighter accuracy, but also dissipate more power. Most applications employ a valley current-sense voltage (VLIM(VAL)) of 50mV to 100mV, so the sense resistor may be determined by: RSENSE = VLIM(VAL) / ILIM(VAL) For the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in Figure 14a. This configuration constantly monitors the inductor current, allowing accurate valley current-limiting and inductor-saturation protection. For low-output-voltage applications that require higher efficiency, the current-sense resistor can be connected between the source of the low-side MOSFET (NL_) and power ground (Figure 14b) with CSN_ connected to the drain of NL_ and CSP_ connected to power ground. In this configuration, the additional current-sense resistance only dissipates power when NL_ is conducting current. Inductor-saturation protection must be disabled with this configuration (LSAT = GND) since the inductor current is only properly sensed when the lowside MOSFET is turned on.
For example: ILOAD(MAX) = 4A, VIN = 12V, VOUT2 = 2.5V, fSW = 355kHz, 30% ripple current or LIR = 0.3: L= 2.5V × (12V - 2.5V) = 4.65μH 12V × 355kHz x 4 A × 0.3
Find a low-loss inductor with the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): ⎛ LIR ⎞ IPEAK = ILOAD(MAX) ⎜1 + ⎟ ⎝ 2⎠ Most inductor manufacturers provide inductors in standard values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc. Also look for nonstandard values, which can provide a better compromise in LIR across the input voltage range. If using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values.
Transient Response
The inductor ripple current also impacts transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the ontime and minimum off-time:
⎡⎛ V ⎤ ×K⎞ L(ΔILOAD(MAX) )2 ⎢⎜ OUT ⎟ + t OFF(MIN) ⎥ ⎢ ⎥ ⎣⎝ VIN ⎠ ⎦ VSAG = ⎡⎛ ( VIN - VOUT ) × K ⎞ ⎤ 2COUT × VOUT ⎢⎜ ⎟ - t OFF(MIN) ⎥ VIN ⎢⎝ ⎥ ⎠ ⎣ ⎦
where t OFF(MIN) is the minimum off-time (see the Electrical Characteristics) and K is from Table 3. The amount of overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as: VSOAR
36
(ΔILOAD(MAX) )2L ≈
2COUT × VOUT
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
For high-power applications that do not require highaccuracy current sensing or inductor-saturation protection, the MAX1540A/MAX1541 can use the low-side MOSFET’s on-resistance as the current-sense element (RSENSE = RDS(ON)) by connecting CSN_ to the drain of NL_ and CSP_ to the source of NL_ (Figure 14c). Use the worst-case maximum value for RDS(ON) from the MOSFET data sheet, and add some margin for the rise in RDS(ON) with temperature. A good general rule is to allow 0.5% additional resistance for each °C of temperature rise. Inductor-saturation protection must be disabled with this configuration (LSAT = GND) since the inductor current is only properly sensed when the lowside MOSFET is turned on. Alternatively, high-power applications that require inductor saturation can constantly detect the inductor current by connecting a series RC circuit across the inductor (Figure 14d) with an equivalent time constant: L = CEQ × REQ RL where RL is the inductor’s series DC resistance. In this configuration, the current-sense resistance is equivalent to the inductor’s DC resistance (RSENSE = RL). Use the worst-case inductance and RL values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load. In all cases, ensure an acceptable valley current-limit threshold voltage and inductor-saturation configurations despite inaccuracies in sense-resistance values. For processor-core voltage converters and other applications where the output is subject to violent load transients, the output capacitor’s size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: RESR ≤ VSTEP ΔILOAD(MAX)
MAX1540A/MAX1541
In applications without large and fast load transients, the output capacitor’s size often depends on how much ESR is needed to maintain an acceptable level of output voltage ripple. The output ripple voltage of a stepdown controller equals the total inductor ripple current multiplied by the output capacitor’s ESR. Therefore, the maximum ESR required to meet ripple specifications is: VRIPPLE RESR ≤ ΔILOAD(MAX) × LIR The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OS-CONs, polymers, and other electrolytics). When using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). However, lowcapacity filter capacitors typically have high-ESR zeros that may affect the overall stability (see the OutputCapacitor Stability Considerations section).
Output Capacitor Selection
The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements.
Table 9. Current-Sense Configurations
METHOD a) Output current-sense resistor CURRENT-SENSE ACCURACY High INDUCTOR-SATURATION PROTECTION Allowed (highest accuracy) Not allowed (LSAT = GND) Not allowed (LSAT = GND) Allowed CURRENT-SENSE POWER LOSS (EFFICIENCY) RSENSE x IOUT2
⎛ VOUT ⎞ 2 ⎜1- V ⎟ × RSENSE × IOUT ⎝ IN ⎠
b) Low-side current-sense resistor
High
c) Low-side MOSFET on-resistance d) Equivalent inductor DC resistance
Low Low
No additional loss No additional loss
______________________________________________________________________________________
37
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
VIN DH LX CIN L RSENSE VOUT COUT
MAX1540A DL MAX1541
GND CONNECT TO PREFERRED LSAT SETTING CSP LSAT CSN
a) OUTPUT SERIES RESISTOR SENSING DH LX CIN
VIN
L VOUT COUT
MAX1540A DL MAX1541
CSN RSENSE
DISABLE LSAT
CSP LSAT GND
b) LOW-SIDE SERIES RESISTOR SENSING
VIN DH LX CSN COUT CIN L VOUT
MAX1540A DL MAX1541
DISABLE LSAT CSP LSAT GND DH LX CIN
VIN INDUCTOR L RL VOUT COUT REQ CEQ
c) LOW-SIDE MOSFET SENSING
MAX1540A DL MAX1541
GND
CONNECT TO PREFERRED LSAT SETTING
CSP LSAT CSN RBIAS = REQ
d) LOSSLESS INDUCTOR SENSING
Figure 14. Current-Sense Configurations
38
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
Output-Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation: f fESR ≤ SW π where: fESR = 1 2πRESR COUT
Input-Capacitor Selection
The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents:
MAX1540A/MAX1541
IRMS =
X=1 VIN
Σ
2
I2OUTX VOUTX (VIN - VOUTX)
For a typical 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum and OS-CON capacitors in widespread use at the time of publication have typical ESR zero frequencies of 25kHz. In the design example used for inductor selection, the ESR needed to support 25mVP-P ripple is 25mV/1.2A = 20.8mΩ. One 220µF/4V Sanyo polymer (TPE) capacitor provides 15mΩ (max) ESR. This results in a zero at 48kHz, well within the bounds of stability. Do not put high-value ceramic capacitors directly across the feedback sense point without taking precautions to ensure stability. Large ceramic capacitors can have a high-ESR zero frequency and cause erratic, unstable operation. However, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point, which should be as close as possible to the inductor. Unstable operation manifests itself in two related but distinctly different ways: double pulsing and fast-feedback loop instability. Double pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This “fools” the error comparator into triggering a new cycle immediately after the 400ns minimum offtime period has expired. Double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to monitor simultaneously the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot.
For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to power-up surge currents typical of systems with a mechanical switch or connector in series with the input. If the MAX1540A/MAX1541 are operated as the second stage of a two-stage power conversion system, tantalum input capacitors are acceptable. In either configuration, choose a capacitor that has less than 10°C temperature rise at the RMS input current for optimal reliability and lifetime.
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Ideally, the losses at VIN(MIN) should be roughly equal to the losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher, consider increasing the size of NH. Conversely, if the losses at VIN(MAX) are significantly higher, consider reducing the size of NH. If VIN does not vary over a wide range, maximum efficiency is achieved by selecting a high-side MOSFET (NH) that has conduction losses equal to the switching losses. Choose a low-side MOSFET (NL) that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., 8-pin SO, DPAK, or D2PAK), and is reasonably priced. Ensure that the MAX1540A/MAX1541 DL_ gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic drain-to-gate capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems may occur. Switching losses are not an issue for the low-side MOSFET since it is a zero-voltage switched device when used in the step-down topology.
______________________________________________________________________________________
39
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
Power-MOSFET Dissipation
Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at minimum input voltage: ⎛V ⎞ PD (NH Resistance) = ⎜ OUT ⎟ (ILOAD )2 × RDS(ON) VIN ⎠ ⎝ Generally, use a small high-side MOSFET to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often restricts how small the MOSFET can be. The optimum occurs when the switching losses equal the conduction (R DS(ON) ) losses. High-side switching losses do not become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFETs (NH) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: PD (NH The absolute worst case for MOSFET power dissipation occurs under heavy overload conditions that are greater than ILOAD(MAX) but are not high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, “overdesign” the circuit to tolerate: ⎛V (V − VOUT ) ⎞ ILOAD = IVALLEY(MAX) + ⎜ OUT IN ⎟ 2VIN fSW L ⎝ ⎠ where I VALLEY(MAX) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and sense-resistance variation. The MOSFETs must have a relatively large heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward-voltage drop low enough to prevent the low-side MOSFET’s body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3 the load current. This diode is optional and can be removed if efficiency is not critical.
Applications Information
Step-Down Converter Dropout Performance
The output-voltage adjustable range for continuousconduction operation is restricted by the nonadjustable minimum off-time one-shot. For best dropout performance, use the slower (200kHz) on-time setting. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor. This error is greater at higher frequencies (Table 3). Also, keep in mind that transient-response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the VSAG equation in the Design Procedure section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (ΔIDOWN) as much as it ramps up during the on-time (ΔIUP). The ratio h = ΔIUP/ΔIDOWN indicates the controller’s ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle, and V SAG greatly increases unless additional output capacitance is used.
(VIN(MAX) )2 CRSS × fSW × ILOAD Switching) =
IGATE
where CRSS is the reverse transfer capacitance of NH, and IGATE is the peak gate-drive source/sink current (1A typ). Switching losses in the high-side MOSFET can become a heat problem when maximum AC adapter voltages are applied due to the squared term in the switchingloss equation (C ✕ VIN2 ✕ fSW). If the high-side MOSFET chosen for adequate R DS(ON) at low-battery voltages becomes extraordinarily hot when subjected to VIN(MAX), consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum battery voltage:
⎡⎛V ⎞⎤ PD (NL Resistance) = ⎢1- ⎜ OUT ⎟ ⎥ (ILOAD )2 × RDS(ON) ⎢ ⎝ VIN(MAX) ⎠ ⎥ ⎣ ⎦
40
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
A reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between VSAG, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: VIN(MIN) = VOUT + VDROP1 ⎛ h × t OFF(MIN) ⎞ 1- ⎜ ⎟ K ⎝ ⎠ put voltages, it can produce three or more output voltages if required by using discrete logic or a DAC. Figure 15 shows an application circuit providing four voltage levels using discrete logic. Switching resistors in and out of the resistor network changes the voltage at REFIN1. An edge-detection circuit is added to generate a 1µs pulse on GATE to trigger the fault blanking and forced-PWM operation. When using PWM mode (SKIP = VCC or open) on the main controller, the edgedetection circuit is only required if fault blanking is enabled. Otherwise, leave OD unconnected.
MAX1540A/MAX1541
where V DROP1 is the parasitic voltage drop in the charge path (see the On-Time One-Shot (TON) section), tOFF(MIN) is from the Electrical Characteristics, and K is taken from Table 3. The absolute minimum input voltage is calculated with h = 1. If the calculated VIN(MIN) is greater than the required minimum input voltage, then operating frequency must be reduced or output capacitance added to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate VSAG to be sure of adequate transient response. Dropout Design Example • • • • • • VOUT2 = 2.5V fSW = 355kHz K = 3.0µs, worst-case KMIN = 3.3µs tOFF(MIN) = 500ns VDROP1 = 100mV h = 1.5 VIN(MIN) = 2.5V + 0.1V = 3.47V ⎛ 1.5 × 500ns ⎞ 1- ⎜ ⎟ ⎝ 3.0μs ⎠
Active Bus Termination (MAX1541 OUT1 Only)
Active-bus-termination power supplies generate a voltage rail that tracks a set reference. They are required to source and sink current. DDR memory architecture requires active bus termination. In DDR memory architecture, the termination voltage is set at exactly half the memory supply voltage. Configure the main MAX1541 controller (OUT1) to generate the termination voltage using a resistive voltage-divider at REFIN1. In such an application, the main MAX1541 controller (OUT1) must be kept in PWM mode (SKIP = VCC or open) in order for it to source and sink current. Figure 16 shows the main MAX1541 controller configured as a DDR termination regulator. Connect GATE and FBLANK to GND when unused.
REF R4 R1 REFIN1 R3 A GND R2
B
Calculating again with h = 1 and the typical K-factor value (K = 3.3µs) gives the absolute limit of dropout: VIN(MIN) = 2.5V + 0.1V = 3.06V ⎛ 1 × 500ns ⎞ 1- ⎜ ⎟ ⎝ 3.3μs ⎠
C1
MAX1541
Therefore, VIN must be greater than 3.06V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 3.47V.
1.5kΩ
1000pF GATE
Multi-Output Voltage Settings (MAX1541 OUT1 Only)
While the main MAX1541 controller (OUT1) is optimized to work with applications that require two dynamic out-
1.5kΩ
1000pF
Figure 15. Multi-Output Voltage Settings ______________________________________________________________________________________ 41
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
VDDQ VCC SKIP 10kΩ DH1 LX1 REFIN1 10nF 10kΩ DL1 COUT VIN CIN L RSENSE V VTT = DDQ 2
MAX1541 GND
CSP1 OD GATE FBLANK CSN1 OUT1 FB1 VDDQ = DDR MEMORY SUPPLY VOLTAGE VTT = TERMINATION SUPPLY VOLTAGE
Figure 16. Active Bus Termination
Voltage Positioning
In applications where fast load transients occur, the output voltage changes instantly by ESRCOUT x ΔILOAD. Voltage positioning allows the use of fewer output capacitors for such applications, and maximizes the output voltage AC and DC tolerance window in tight-tolerance applications. Figure 17 shows the connection of OUT_ and FB_ in voltage-positioned and nonvoltage-positioned circuits. In nonvoltage-positioned circuits, the MAX1540A/ MAX1541 regulate at the output capacitor. In voltagepositioned circuits, the MAX1540A/MAX1541 regulate on the inductor side of the current-sense resistor. VOUT_ is reduced to: VOUT(VPS) = VOUT(NO LOAD) - RSENSE x ILOAD Figure 18 shows the voltage-positioning transient response.
PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. • Minimize current-sensing errors by connecting CSP_ and CSN_ directly across the current-sense resistor (RSENSE_). When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. Route high-speed switching nodes (BST_, LX_, DH_, and DL_) away from sensitive analog areas (REF, FB_, CSP_, CSN_).
•
•
PC Board Layout Guidelines
Careful PC board layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 19). If possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. Follow these guidelines for good PC board layout: • Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. • Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PC boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing
Layout Procedure
1) Place the power components first, with ground terminals adjacent (NL _ source, CIN, COUT_, and DL _ anode). If possible, make all these connections on the top layer with wide, copper-filled areas. 2) Mount the controller IC adjacent to the low-side MOSFET, preferably on the back side opposite NL _ and NH_ in order to keep LX_, GND, DH_, and the DL_ gate-drive lines short and wide. The DL_ and DH_ gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC) to keep the driver impedance low and for proper adaptive dead-time sensing.
42
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
R1 +5V BIAS SUPPLY C2 VCC C1 V+ BST_ NH DH_ CBST L1 RSENSE VOLTAGE-POSITIONED OUTPUT (VOUT(VPS)) COUT CIN VDD DBST INPUT (VIN)
MAX1540A LX_ MAX1541
DL_ GND
NL
DL
CSP_ OUT_ FB CSN_
VOUT(VPS) = VOUT(NO LOAD) - RSENSEIOUT
Figure 17. Voltage Positioning
VOLTAGE POSITIONING THE OUTPUT
ESR VOLTAGE STEP (ISTEP x RESR) 1.4 A VOUT
CAPACITIVE SOAR (dV/dt = IOUT/COUT)
1.4 B CAPACITIVE SAG (dV/dt = IOUT/COUT) RECOVERY
50mV/div A. CONVENTIONAL CONVERTER B. VOLTAGE-POSITIONED OUTPUT
ILOAD
Figure 18. Voltage-Positioning Transient Response
______________________________________________________________________________________
43
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
VIA TO POWER GROUND
CONNECT THE EXPOSED PAD TO ANALOG GROUND VIA TO VCC BYPASS CAPACITOR MAX1540A TOP LAYER
CONNECT GND AND PGND TO THE CONTROLLER AT ONE POINT ONLY AS SHOWN VIA TO VCC PIN VIA TO REF BYPASS CAPACITOR VIA TO REF PIN MAX1540A BOTTOM LAYER
KELVIN-SENSE VIAS UNDER THE SENSE RESISTOR (REFER TO EVALUATION KIT)
DUAL N-CHANNEL MOSFET INDUCTOR
SINGLE N-CHANNEL MOSFETS
INDUCTOR DH LX DL COUT COUT CIN OUTPUT OUTPUT GROUND INPUT CIN
COUT GROUND
INPUT
HIGH-POWER LAYOUT
LOW-POWER LAYOUT
Figure 19. PC Board Layout
3) Group the gate-drive components (BST_ diode and capacitor, VDD bypass capacitor) together near the controller IC. 4) Make the DC-DC controller ground connections as shown in Figures 1 and 12. This diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go, and an analog ground plane for sensitive analog components. The analog ground plane and power ground plane must meet only at a single point directly at the IC.
5) Connect the output power planes directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the load as is practical.
Chip Information
TRANSISTOR COUNT: 8612 PROCESS: BiCMOS
44
______________________________________________________________________________________
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
Pin Configurations (continued)
LDOOUT LDOON FBLDO LDOIN BST1 V+
MAX1540A/MAX1541
TOP VIEW
30
29
28
27
26
25
24
23
22
21 20 19 18 17 16
GND
DL1
DL2
VDD
LX1 DH1 PGOOD1 OUT1 FB1
31 32 33 34 35 36 37 38 39 40 10
BST2 LX2 DH2 PGOOD2 OUT2
CSN1 CSP1
FBLANK
MAX1541
15 14 13 12 11
FB2 CSN2
CSP2
ON2 ON1
OD REFIN1
2
3
4
5
6
7
1
8 ILIM1
OVP/UVP
ILIM2
LSAT
SKIP
GATE
9
TON
THIN QFN
A "+" SIGN WILL REPLACE THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES.
______________________________________________________________________________________
CC1
VCC
REF
45
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
21-0140
K
1
2
46
______________________________________________________________________________________
QFN THIN.EPS
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX1540A/MAX1541
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
21-0140
K
2
2
______________________________________________________________________________________
47
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
48
______________________________________________________________________________________
QFN THIN.EPS
Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX1540A/MAX1541
Revision History
Pages changed at Rev 3: 1, 10–15, 18, 20, 21, 22, 24, 34, 46–49
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 49 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.