MAX16031_10

19-0870; Rev 2; 6/10 KIT ATION EVALU ABLE AVAIL EEPROM-Based System Monitors with Nonvolatile Fault Memory General Description Features o Supply Voltage Operating Range of 2.85V to 14V o Monitors Up to Eight Voltages (Single-Ended or Pseudo-Differential) with 1% Accuracy o EEPROM-Configurable Limits Two Undervoltage and Two Overvoltage Two Overtemperature Two Overcurrent o High-Side Current-Sense Amplifier with Overcurrent Output (MAX16031 Only) o Monitors Up to Three Temperatures (1 Internal/2 Remote) o Nonvolatile Fault Memory Stores Fault Conditions for Later Retrieval o Two Additional Configurable Fault Outputs o Two Configurable GPIOs o SMBus/I2C-Compatible Interface with ALERT Output and Bus Timeout Function o JTAG Interface o 7mm x 7mm, 48-Pin TQFN Package MAX16031/MAX16032 The MAX16031/MAX16032 EEPROM-configurable system monitors feature an integrated 10-bit analog-todigital converter (ADC) designed to monitor voltages, temperatures, and current in complex systems. These EEPROM-configurable devices allow enormous flexibility in selecting operating ranges, upper and lower limits, fault output configuration, and operating modes with the capability of storing these values within the device. The MAX16031 monitors up to eight voltages, three temperatures (one internal/two external remote temperature diodes), and a single current. The MAX16032 monitors up to six voltages and two temperatures (one internal/one remote temperature diode). Each of these monitored parameters is muxed into the ADC and written to its respective register that can be read back through the SMBus™ and JTAG interface. Measured values are compared to the user-configurable upper and lower limits. For voltage measurements, there are two undervoltage and two overvoltage limits. For current and temperature, there are two sets of upper limits. Whenever the measured value is outside its limits, an alert signal is generated to notify the processor. Independent outputs are available for overcurrent, overtemperature, and undervoltage/overvoltage that are configured to assert on assigned channels. There are also undedicated fault outputs that are configured to offer a secondary limit for temperature, current, or voltage fault or provide a separate overvoltage output. During a major fault event, such as a system shutdown, the MAX16031/MAX16032 automatically copy the internal ADC registers into the nonvolatile EEPROM registers that then are read back for diagnostic purposes. The MAX16031/MAX16032 offer additional GPIOs that are used for voltage sequencing, additional fault outputs, a manual reset input, or read/write logic levels. A separate current-sense amplifier with an independent output allows for fast shutoff during overcurrent conditions. The MAX16031/MAX16032 are available in a 7mm x 7mm TQFN package and are fully specified from -40°C to +85°C. Ordering Information PART MAX16031ETM+ MAX16032ETM+ TEMP RANGE -40°C to +85°C -40°C to +85°C PIN-PACKAGE 48 TQFN-EP* 48 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Pin Configuration N.C. (DXN2) N.C. (DXP2) N.C. (CS+) N.C. (CS-) DXN1 DXP1 N.C. N.C. N.C. VCC 38 VCC 37 36 ABP 35 GND 34 DBP 33 TDO 32 N.C. 31 N.C. 30 N.C. 29 TDI 28 TCK 27 TMS EP 13 GND 14 GPIO1 15 GPIO2 16 RBP 17 SDA 18 SCL 19 A0 20 A1 21 ALERT 22 OVERT 23 N.C. (OVERC) 24 FAULT2 26 RESET 25 FAULT1 IN1 48 IN2 1 IN3 2 IN4 3 N.C. 4 N.C. 5 N.C. 6 N.C. 7 GND 8 47 46 45 44 43 42 41 40 39 + MAX16031 MAX16032 Applications Servers Storage Systems Telecom Workstations Networking IN5 9 IN6 10 N.C. (IN7) 11 N.C. (IN8) 12 ( ) MAX16031 ONLY SMBus is a trademark of Intel Corp. TQFN ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Selector Guide PART MAX16031ETM+ MAX16032ETM+ VOLTAGE MONITORS SINGLE ENDED 8 6 DIFFERENTIAL 4 3 TEMPERATURE SENSORS INT 1 1 EXT 2 1 CURRENTSENSE AMPS 1 — FAULT GPIOs OUTPUTS 4 4 2 2 Typical Application Circuit 5V DC-DC EN 1.5V DC-DC 3.3V DC-DC EN 12V BUS 2.5V DC-DC EN 0.9V LINEAR 1.8V DC-DC EN 1.2V DC-DC 5V 1.5V 3.3V 1.2V 2.5V 0.9V 1.8V 3.3V AUX CS+ VCC 1µ F CS- IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 ALERT SCL SDA GPIO1 INT SCL SDA RESET µC DXP1 RESET SYSTEM RESET MAX16031 DXN1 DXP2 FAULT1 FAULT2 OVERT OVERC TO FAN CONTROL DXN2 ABP 1µ F 1µF DBP 2.2µF RBP GND A0 A1 TMS TCK TDI TDO GPIO2 WARNING INDICATORS TMS SYSTEM JTAG HEADER TCK TDI TDO MANUAL RESET SWITCH TO OTHER JTAG DEVICES 2 _______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory ABSOLUTE MAXIMUM RATINGS VCC to GND ............................................................-0.3V to +15V IN_, FAULT_, SCL, SDA, OVERT to GND.................-0.3V to +6V A0, A1, TCK, TMS, TDI to GND ................................-0.3V to +6V OVERC, RESET, GPIO_, ALERT to GND..................-0.3V to +6V RBP, ABP, DBP to GND ...-0.3V to lower of (6V and VCC + 0.3V) TDO, DXP1, DXP2 to GND..........................-0.3V to VDBP + 0.3V CS+, CS- to GND ...................................................-0.3V to +30V (CS+ - CS-) ............................................................................±5V DXN1, DXN2 to GND.............................................-0.3V to +0.8V SDA, ALERT Current ...........................................-1mA to +50mA DXN1, DXN2 Current ............................................................1mA Input/Output Current (all except DXN1, DXN2, SDA, and ALERT) ..................20mA Continuous Power Dissipation (TA = +70°C) 48-Pin, 7mm x 7mm TQFN (derate 27.8mW/°C above +70°C) ........................2222.2mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature .....................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+250°C Soldering Temperature (reflow) .......................................+260°C MAX16031/MAX16032 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = 2.9V to 14V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1) PARAMETER Operating Voltage Range Undervoltage Lockout Undervoltage Lockout Hysteresis Supply Current ADC DC ACCURACY Resolution Total Unadjusted Error Integral Nonlinearity Differential Nonlinearity ADC Total Monitoring Cycle Time tCYCLE Eight supply inputs, three temperatures, and current sense Register map bit set to 00 (LSB = 5.46mV) ADC IN_ Voltage Ranges Register map bit set to 01 (LSB = 2.73mV) Register map bit set to 10 (LSB = 1.36mV) Reference Voltage IN_ ANALOG INPUT Absolute Input Voltage Range (Referenced to GND) Input Impedance 0 30 50 5.6 80 V kΩ VRBP 1.306 TA = -40°C to +85°C 1 1 80 5.6 2.8 1.4 1.4 1.414 V V 100 10 0.9 Bits % FSR LSB LSB µs SYMBOL VCC VUVLO VUVLOHYS ICC Static (EEPROM not accessed) Minimum voltage at VCC to access the digital interfaces 100 3 5 CONDITIONS MIN 2.90 TYP MAX 14.00 2.8 UNITS V V mV mA _______________________________________________________________________________________ 3 EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.9V to 14V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1) PARAMETER Input Hysteresis RESET OUTPUT r20h[5:3] = 000; from MR going high r20h[5:3]= 001 r20h[5:3]= 010 Reset Timeout Period tRP r20h[5:3]= 011 r20h[5:3]= 100 r20h[5:3]= 101 r20h[5:3]= 110 r20h[5:3]= 111 TEMPERATURE MEASUREMENTS Internal Sensor Measurement Error External Remote Diode Temperature Measurement Error Temperature Measurement Resolution Temperature Measurement Noise External Diode Drive High External Diode Drive Low Diode Drive Current Ratio DXN_ Impedance to GND Power-Supply Rejection CURRENT SENSE CS+ Input Voltage Range Input Bias Current VCS+ ICS+ ICSVCS+ = VCSVCS- = VCS+ A = 48 Primary Current-Sense Differential Thresholds Primary Current-Sense Threshold VCSTH VCS+ - VCSA = 24 A = 12 A=6 CSHYS Percent of VCSTH r5Ch[1:0] = 00 Secondary Overcurrent Threshold Timeout r5Ch[1:0] = 01 r5Ch[1:0] = 10 r5Ch[1:0] = 11 3.6 14.4 57.6 21.5 45 92 190 3 14 3 25 50 100 200 0.5 50 4 16 64 4.4 17.6 70.4 ms 28 25 8 28.5 55 108 210 % µs mV V µA PSR Internal sensor, DC condition Internal sensor (Note 2) (Note 2) ±3 ±5 0.5 0.1 84 6 14 1.8 0.1 kΩ °C/V °C °C °C °C µA µA 22.5 2.25 9 36 144 576 1152 2304 25 2.5 10 40 160 640 1280 2560 27.5 2.75 11 44 176 704 1408 2816 ms µs SYMBOL CONDITIONS Percent of programmed threshold r5Ch[5] = 0 r5Ch[5] = 1 MIN TYP 0.78 1.17 MAX UNITS % 4 _______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.9V to 14V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1) PARAMETER Current-Sense Analog Input Range SYMBOL CONDITIONS A=6 VCS+ - VCSA = 12 A = 24 A = 48 VSENSE = 150mV, (A = 6 only) ADC Current-Sense Measurement Accuracy VSENSE = 50mV, (A = 6, 12 only) VSENSE = 25mV VSENSE = 10mV Gain Accuracy Common-Mode Rejection Ratio Power-Supply Rejection Ratio OVERC Output Leakage Current OVERC Output Low Voltage OVERC Propagation Delay SMBus INTERFACE (SCL, SDA) Logic-Input Low Voltage Logic-Input High Voltage Input Leakage Current Output Low Voltage Input Capacitance ALERT, FAULT_, and GPIO_ Output Low Voltage ALERT, FAULT_, and GPIO_ Leakage Current GPIO_ (INPUT) Logic-Low Voltage Logic-High Voltage SMBus ADDRESS (A0 and A1) Address Logic-Low Address Logic-High High-Impedance Leakage Current Input Leakage Current Maximum current to achieve highimpedance logic level 0 to 3V, VCC = 3V 1.4 -1 -12 +1 +12 0.4 V V µA µA GPIO_ voltage falling GPIO_ voltage rising 2.0 0.8 V V VOL CIN VIL VIH Input voltage falling Input voltage rising GND or 5.5V (VCC = 5.5V) VSCL, VSDA ISINK = 3mA 5 2.0 -1 +1 0.4 0.8 V V µA V pF CMRRCS PSRRCS IOVERCLKG VOLOVERC tOVERC IOUT = 3mA VSENSE - VCSTH > 10% x VCSTH VSENSE = 20mV to 100mV, VCS+ = 12V, A = 6 VCS+ > 4V -3 80 80 1 0.4 5 -4 -10 MIN TYP 232 116 58 29 ±0.2 ±1.2 ±2 ±10 +3 % dB dB µA V µs +4 +10 % MAX UNITS MAX16031/MAX16032 mV ALERT, FAULT_, AND GPIO_ OUTPUTS ISINK = 3mA V ALERT, V FAULT, VGPIO_ = 5.5V or GND -1 0.4 +1 V µA _______________________________________________________________________________________ 5 EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.9V to 14V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1) PARAMETER SMBus TIMING (see Figure 1) Serial-Clock Frequency Bus Free Time Between STOP and START Conditions START Condition Setup Time START Condition Hold Time STOP Condition Setup Time Clock Low Period Clock High Period Data Setup Time Output Fall Time Data Hold Time Minimum Pulse Width Ignored SMBus Timeout JTAG INTERFACE (see Figure 2) TDI, TMS, TCK Logic-Low Input Voltage TDI, TMS, TCK Logic-High Input Voltage TDO Logic-Output Low Voltage TDO Logic-Output High Voltage TDO Leakage Current TDI, TMS Pullup Resistors I/O Capacitance TCK Clock Period TCK High/Low Time TCK to TMS, TDI Setup Time TCK to TMS, TDI Hold Time TCK to TDO Delay TCK to TDO High-Impedance Delay MISCELLANEOUS Power-On Delay Single-Byte EEPROM Write Cycle Delay tD-PO (Note 4) 4 11 ms ms RJPU CI/O t1 t2, t3 t4 t5 t6 t7 (Note 3) 60 15 35 500 500 500 VIL VIH VOL VOH Input voltage falling Input voltage rising ISINK = 4mA ISOURCE = 1mA TDO high impedance Pullup to VDBP 2.2 -10 6.5 10 50 1000 +10 16 2.2 0.4 0.4 V V V V µA kΩ pF ns ns ns ns ns ns tTIMEOUT SCL time low for reset 25 fSCL tBUF tSU:STA tHD:STA tSU:STO tLOW tHIGH tSU:DAT tOF tHD:DAT CBUS = 10pF to 400pF From 50% SCL falling to SDA change 0.3 30 35 1.3 0.6 0.6 0.6 1.3 0.6 100 250 0.9 400 kHz µs µs µs µs µs µs ns ns µs ns ms SYMBOL CONDITIONS MIN TYP MAX UNITS Note 1: Limits to -40°C are guaranteed by design. Note 2: Guaranteed by design. Note 3: TCK stops either high or low. Note 4: An additional cycle is required when writing to configuration memory for the first time. 6 _______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 SDA tBUF tSU:STA tLOW SCL tHIGH tHD:STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD:DAT tHD:STA tSU:STO tSU:DAT Figure 1. SMBus Interface Timing Diagram t1 t2 t3 TCK t4 t5 TDI, TMS t6 t7 TDO TRI-STATE ONLY Figure 2. JTAG Interface Timing Diagram _______________________________________________________________________________________ 7 EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Typical Operating Characteristics (Typical values are at VCC = 3.3V, TA = +25°C, unless otherwise noted.) VCC SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE MAX16031 toc01 NORMALIZED IN_ THRESHOLD vs. TEMPERATURE MAX16031 toc02 NORMALIZED RESET TIMEOUT PERIOD vs. TEMPERATURE NORMALIZED RESET TIMEOUT PERIOD 1.04 1.03 1.02 1.01 1.00 0.99 0.98 0.97 0.96 MAX16031 toc03 3.0 2.5 2.0 ICC (mA) 1.5 1.0 0.5 0 0 2 4 6 8 10 12 TA = -40°C TA = +25°C TA = +85°C 1.03 1.02 1.01 1.00 0.99 0.98 0.97 1.05 NORMALIZED IN_ THRESHOLD 0.95 -40 -15 10 35 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) TEMPERATURE (°C) 14 VCC (V) OUTPUT VOLTAGE LOW vs. SINK CURRENT MAX16031 toc04 ADC INTEGRAL NONLINEARITY vs. INPUT VOLTAGE 0.40 0.30 0.20 ADC INL (LSB) MAX16031 toc05 ADC DIFFERENTIAL NONLINEARITY vs. INPUT VOLTAGE MAX16031 toc06 400 350 OUTPUT VOLTAGE LOW (mV) 300 250 200 150 100 50 0 0 1 2 3 4 5 6 7 SINK CURRENT (mA) 0.50 0.15 0.10 0.05 ADC DNL (LSB) 0 -0.05 -0.10 -0.15 -0.20 0.10 0 -0.10 -0.20 -0.30 -0.40 -0.50 0 128 256 384 512 640 768 896 1024 INPUT VOLTAGE (DIGITAL CODE) 0 128 256 384 512 640 768 896 1024 INPUT VOLTAGE (DIGITAL CODE) NOISE HISTOGRAM MAX16031 toc07 REFERENCE VOLTAGE vs. TEMPERATURE 1.48 REFERENCE VOLTAGE (V) 1.46 1.44 1.42 1.40 1.38 1.36 1.34 1.32 1.30 MAX16031 toc08 1000 900 800 COUNTS (THOUSANDS) 700 600 500 400 300 200 100 0 507 508 509 510 511 512 513 ADC OUTPUT CODE ADC HALF-SCALE VOLTAGE INPUT 1.50 -40 -15 10 35 60 85 TEMPERATURE (°C) 8 _______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory Typical Operating Characteristics (continued) (Typical values are at VCC = 3.3V, TA = +25°C, unless otherwise noted.) MAX16031/MAX16032 INTERNAL TEMPERATURE SENSOR ACCURACY vs. TEMPERATURE MAX16031 toc09 TEMPERATURE ERROR vs. REMOTE DIODE TEMPERATURE MAX16031 toc10 TEMPERATURE ERROR vs. LEAKAGE RESISTANCE 15 10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 1 PATH = DXP TO GND MAX16031 toc11 3 TEMP SENSOR ACCURACY (°C) 2 1 0 -1 -2 -3 -35 -10 15 40 65 5 4 TEMPERATURE ERROR (°C) 3 2 1 0 -1 -2 -3 -4 -5 TEMPERATURE ERROR (°C) PATH = DXP TO VCC (+5V) 90 -30 -15 0 15 30 45 60 75 90 105 10 LEAKAGE RESISTANCE (MΩ) 100 TEMPERATURE (°C) REMOTE DIODE TEMPERATURE (°C) TEMPERATURE ERROR vs. DXP-DXN CAPACITANCE MAX16031 toc12 CURRENT-SENSE ACCURACY vs. VSENSE MAX16031 toc13 CURRENT-SENSE PRIMARY THRESHOLD vs. VSENSE OVERDRIVE CURRENT-SENSE PRIMARY THRESHOLD (µs) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 20 40 60 80 100 MAX16031 toc14 0 -1 TEMPERATURE ERROR (°C) -2 -3 -4 -5 -6 -7 -8 -9 -10 0 1 2 3 4 5 6 7 8 9 DXP-DXN CAPACITANCE (nF) 8 CURRENT-SENSE ACCURACY (%) 6 4 2 0 -2 -4 0 2.0 23 46 69 92 115 138 161 184 207 230 VSENSE (mV) VSENSE OVERDRIVE (mV) _______________________________________________________________________________________ 9 EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Pin Description PIN MAX16031 MAX16032 NAME FUNCTION Supply Monitor Input 2. IN2 is internally sampled by the ADC. It is configurable for unipolar/ bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN1 and IN2 form the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage range. Supply Monitor Input 3. IN3 is internally sampled by the ADC. It is configurable for unipolar/ bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN3 and IN4 form the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage range. Supply Monitor Input 4. IN4 is internally sampled by the ADC. It is configurable for unipolar/ bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN3 and IN4 form the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage range. 1 1 IN2 2 2 IN3 3 3 IN4 4–7, 30, 31, 32, 39, 40, 47 8, 13, 35 4–7, 11, 12, 23, 30, 31, 32, 39, 40–44, 47 8, 13, 35 N.C. No Connection. Leave unconnected. Do not use. GND Ground. Connect all GND pins together. Supply Monitor Input 5. IN5 is internally sampled by the ADC. It is configurable for unipolar/ bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN5 and IN6 form the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage range. Supply Monitor Input 6. IN6 is internally sampled by the ADC. It is configurable for unipolar/ bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN5 and IN6 form the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage range. Supply Monitor Input 7. IN7 is internally sampled by the ADC. It is configurable for unipolar/ bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN7 and IN8 form the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage range. Supply Monitor Input 8. IN8 is internally sampled by the ADC. It is configurable for unipolar/ bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN7 and IN8 form the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage range. Configurable General-Purpose Input/Output 1 Configurable General-Purpose Input/Output 2 ADC Reference Bypass. RBP is an internally generated 1.4V reference for the ADC. Bypass RBP to GND with a 2.2µF capacitor. Do not use RBP to power any additional circuitry. SMBus Serial-Data, Open-Drain Input/Output SMBus Serial-Clock Input SMBus Address Input 0. Connect to DBP, GND, or leave unconnected to select the desired device address. SMBus Address Input 1. Connect to DBP, GND, or leave unconnected to select the desired device address. 9 9 IN5 10 10 IN6 11 — IN7 12 — IN8 14 15 16 17 18 19 20 14 15 16 17 18 19 20 GPIO1 GPIO2 RBP SDA SCL A0 A1 10 ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory Pin Description (continued) PIN MAX16031 MAX16032 NAME FUNCTION SMBus Alert Open-Drain Output. ALERT follows the SMBALERT# signal functionality described in Appendix A of the SMBus 2.0 Specification. ALERT asserts when the device detects a fault, thereby interrupting the host processor to query which device on the serial bus detected faults. Overtemperature, Open-Drain Output. OVERT asserts when an overtemperature condition is detected. Overcurrent, Open-Drain Output. OVERC asserts when the primary overcurrent threshold is exceeded. MAX16031/MAX16032 21 21 ALERT 22 23 24 25 26 27 28 29 33 34 36 37, 38 41 42 43 44 45 46 22 — 24 25 26 27 28 29 33 34 36 37, 38 — — — — 45 46 OVERT OVERC FAULT2 Configurable Open-Drain Fault Output 2 FAULT1 Configurable Open-Drain Fault Output 1 RESET TMS TCK TDI TDO DBP ABP VCC CSCS+ DXN2 DXP2 DXN1 DXP1 Configurable Open-Drain Reset Output JTAG Test Mode Select Input. Internally pulled up to VDBP with a 10kΩ resistor. JTAG Test Clock Input JTAG Test Data Input. Internally pulled up to VDBP with a 10kΩ resistor. JTAG Test Data Output Internal Digital Voltage Regulator Output. Connect a 1µF bypass capacitor from DBP to GND. Do not use DBP to power external circuitry. Internal Analog Voltage Regulator Output. Connect a 1µF bypass capacitor from ABP to GND. Do not use ABP to power external circuitry. Device Power Supply. Bypass VCC to GND with a 1µF capacitor. Current-Sense Negative Input. Must be biased between 3V to 28V for proper operation. Current-Sense Positive Input. Must be biased between 3V to 28V for proper operation. Remote Diode 2 Negative Input. If remote sensing is not used, connect DXP2 to DXN2. Remote Diode 2 Positive Input. If remote sensing is not used, connect DXP2 to DXN2. Remote Diode 1 Negative Input. If remote sensing is not used, connect DXP1 to DXN1. Remote Diode 1 Positive Input. If remote sensing is not used, connect DXP1 to DXN1. Supply Monitor Input 1. IN1 is internally sampled by the ADC. It is configurable for unipolar/ bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN1 and IN2 form the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage range. Exposed Pad. Connect EP to ground. EP is internally connected to GND. Do not use as the main ground connection. 48 48 IN1 — — EP ______________________________________________________________________________________ 11 EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Functional Diagram VCC INTERNAL TEMPERATURE SENSOR CIRCUITRY OSCILLATOR ANALOG REGULATOR DIGITAL REGULATOR ABP DBP IN1 10-BIT ADC 1.4V INTERNAL REFERENCE RBP INPUT RANGE SELECTION REGISTERS IN2 IN3 IN4 IN5 IN6 *IN7 *IN8 INPUT RANGE SELECTION INPUT RANGE SELECTION INPUT RANGE SELECTION INPUT RANGE SELECTION INPUT RANGE SELECTION INPUT RANGE SELECTION INPUT RANGE SELECTION EEPROM SMBus SERIAL INTERFACE MULTIPLEXER FAULT COMPARATORS FAULT1 FAULT2 OVERT RESET GPIO1 GPIO2 SDA SCL ALERT A0 A1 DXP1 DXN1 *DXP2 *DXN2 EXTERNAL TEMPERATURE SENSOR CIRCUITRY JTAG SERIAL INTERFACE TMS TCK TDI TDO *CS+ *CS- CURRENT-SENSE AMPLIFIER/ COMPARATOR MAX16031/ MAX16032 OVERC *MAX16031 ONLY 12 ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory Table 1. Address Map REGISTER ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h EEPROM MEMORY ADDRESS — — — — — — — — — — — — — — — — — — — — — — — 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h READ/ WRITE R R R R R R R R R R R R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W IN1 ADC Result Register (MSB) IN1 ADC Result Register (LSB) IN2 ADC Result Register (MSB) IN2 ADC Result Register (LSB) IN3 ADC Result Register (MSB) IN3 ADC Result Register (LSB) IN4 ADC Result Register (MSB) IN4 ADC Result Register (LSB) IN5 ADC Result Register (MSB) IN5 ADC Result Register (LSB) IN6 ADC Result Register (MSB) IN6 ADC Result Register (LSB) IN7 ADC Result Register (MSB)* IN7 ADC Result Register (LSB)* IN8 ADC Result Register (MSB)* IN8 ADC Result Register (LSB)* Internal Temperature Sensor ADC Result Register (MSB) Internal Temperature Sensor ADC Result Register (LSB) Remote Temperature Sensor 1 ADC Result Register (MSB) Remote Temperature Sensor 1 ADC Result Register (LSB) Remote Temperature Sensor 2 ADC Result Register (MSB) Remote Temperature Sensor 2 ADC Result Register (LSB) Current-Sense ADC Result Register Voltage Monitoring Input ADC Range Selection (IN1–IN4) Voltage Monitoring Input ADC Range Selection (IN5–IN8) Current-Sense Gain/Primary Threshold and Remote Temperature Sensor 1 Gain Trim Voltage Monitoring Input Enable Internal/Remote Temperature Sensor, Current Sense, and ALERT Enables and Remote Temperature Sensor 1 Offset Trim Voltage Monitoring Input Single-Ended/Differential and Unipolar/Bipolar Selection FAULT1 Dependency Selection FAULT2 Dependency Selection OVERT Dependency Selection RESET Dependency and Timeout Selection RESET IN1–IN8 Dependency Selection GPIO1 Configuration GPIO1 Dependency Selection GPIO2 Configuration DESCRIPTION MAX16031/MAX16032 13 ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 1. Address Map (continued) REGISTER ADDRESS 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah EEPROM MEMORY ADDRESS A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh READ/ WRITE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W GPIO2 Dependency Selection IN1 Primary Undervoltage Threshold IN1 Primary Overvoltage Threshold IN1 Secondary Undervoltage Threshold IN1 Secondary Overvoltage Threshold IN2 Primary Undervoltage Threshold IN2 Primary Overvoltage Threshold IN2 Secondary Undervoltage Threshold IN2 Secondary Overvoltage Threshold IN3 Primary Undervoltage Threshold IN3 Primary Overvoltage Threshold IN3 Secondary Undervoltage Threshold IN3 Secondary Overvoltage Threshold IN4 Primary Undervoltage Threshold IN4 Primary Overvoltage Threshold IN4 Secondary Undervoltage Threshold IN4 Secondary Overvoltage Threshold IN5 Primary Undervoltage Threshold IN5 Primary Overvoltage Threshold IN5 Secondary Undervoltage Threshold IN5 Secondary Overvoltage Threshold IN6 Primary Undervoltage Threshold IN6 Primary Overvoltage Threshold IN6 Secondary Undervoltage Threshold IN6 Secondary Overvoltage Threshold IN7 Primary Undervoltage Threshold* IN7 Primary Overvoltage Threshold* IN7 Secondary Undervoltage Threshold* IN7 Secondary Overvoltage Threshold* IN8 Primary Undervoltage Threshold* IN8 Primary Overvoltage Threshold* IN8 Secondary Undervoltage Threshold* IN8 Secondary Overvoltage Threshold* Internal Temperature Sensor Primary Overtemperature Threshold (MSB) Internal Temperature Sensor Secondary Overtemperature Threshold (MSB) Remote Temperature Sensor 1 Primary Overtemperature Threshold Remote Temperature Sensor 1 Secondary Overtemperature Threshold Remote Temperature Sensor 2 Primary Overtemperature Threshold DESCRIPTION 14 ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory Table 1. Address Map (continued) REGISTER ADDRESS 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h–7Fh — — — — — — — — — — — — — — — EEPROM MEMORY ADDRESS CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h–FFh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh READ/ WRITE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W — R/W R/W — R R R R R R R R R R R R R R R DESCRIPTION Remote Temperature Sensor 2 Secondary Overtemperature Threshold Overcurrent Secondary Threshold Remote Temperature Sensor Primary/Secondary Overtemperature Threshold (LSBs). External Temperature Sensor 2 Offset Trim Remote Temperature Sensor 1/2 Primary/Secondary Overtemperature Threshold (LSBs) Remote Temperature Sensor 2 Gain Trim Remote Temperature Sensor Short/Open Status IN1–IN8 Primary Threshold Fault Status IN1–IN8 Secondary Threshold Fault Status Temperature/Current Threshold Fault Status Remote Temperature Sensor Short/Open Fault Mask IN1–IN8 Primary Threshold Fault Mask IN1–IN8 Secondary Threshold Fault Mask Temperature/Current Threshold Fault Mask IN1–IN8 Primary Undervoltage Faults Triggering Fault EEPROM IN1–IN8 Primary Overvoltage Faults Triggering Fault EEPROM Temperature/Current Faults Triggering Fault EEPROM Temperature Filter Selection and Postboot Fault Mask Time Threshold Fault Options and Overcurrent Fault Timeout Reserved Customer Firmware Version EEPROM and Configuration Lock Reserved IN1–IN8 Primary Threshold Fault Status at Time of Fault IN1–IN8 Secondary Threshold Fault Status at Time of Fault Temperature/Current Threshold Fault Status at Time of Fault IN1 Conversion Result at Time of Fault IN2 Conversion Result at Time of Fault IN3 Conversion Result at Time of Fault IN4 Conversion Result at Time of Fault IN5 Conversion Result at Time of Fault IN6 Conversion Result at Time of Fault IN7 Conversion Result at Time of Fault* IN8 Conversion Result at Time of Fault* Internal Temperature Sensor Conversion Result at Time of Fault Remote Temperature Sensor 1 Conversion Result at Time of Fault Remote Temperature Sensor 2 Conversion Result at Time of Fault* Current-Sense Conversion Result at Time of Fault* MAX16031/MAX16032 *MAX16031 only. ______________________________________________________________________________________ 15 EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Detailed Description Getting Started The MAX16031/MAX16032 contain both I2C/SMBus and JTAG serial interfaces for accessing registers and EEPROM. Use only one interface at any given time. For more information on how to access the internal memory through these interfaces, see the I2C/SMBus-Compatible Serial Interface and JTAG Serial Interface sections. This data sheet uses a specific convention for referring to bits within a particular address location. As an example, r15h[3:0] refers to bits 3 through 0 in register with address 15 hexadecimal. The factory-default values at power-on reset (POR) for all EEPROM locations are zeros. POR occurs when VCC reaches the undervoltage lockout (UVLO) of 2.8V. At POR, the device begins a boot-up sequence. During the boot-up sequence, all monitored inputs are masked from initiating faults and EEPROM contents are copied to the respective register locations. The boot-up sequence takes up to 1.81ms. Monitoring is disabled for up to 16s past the boot-up sequence by programming r5Bh[3:0] (see the Miscellaneous Settings section). RESET is low during boot-up and remains low after boot-up for its programmed timeout period after all monitored channels are within their respective thresholds. The MAX16031/MAX16032 monitor up to eight voltages, up to one current, and up to three temperatures. After boot-up, an internal multiplexer cycles through each input. At each multiplexer stop, the 10-bit ADC converts the analog parameter to a digital result and stores the result in a register. Each time the multiplexer completes a cycle, internal logic compares the conversion results to the thresholds stored in memory. When a conversion violates a programmed threshold, the conversion is configured to generate a fault. Logic outputs are programmed to depend on many combinations of faults. Additionally, faults are programmed to trigger a fault log, whereby all fault information is automatically written to EEPROM. Voltage Monitoring The MAX16031 provides eight inputs, IN1–IN8, for voltage monitoring. The MAX16032 provides six inputs, IN1–IN6, for voltage monitoring. Each input voltage range is programmable through r17h[7:0] and r18h[7:0] (see Table 2). Voltage monitoring for each input is enabled through r1Ah[7:0] (see Table 2). There are four programmable thresholds per voltage monitor input: primary undervoltage, secondary undervoltage, primary overvoltage, and secondary overvoltage. All voltage thresholds are 8 bits wide. Only the 8 most significant bits of the conversion result are compared to the thresholds. See the Miscellaneous Settings section to set the amount of hysteresis for the thresholds. See Table 1 for an address map of all voltage monitor input threshold registers. ADC inputs are configurable for two different modes: pseudo-differential and single-ended (see Table 3). In pseudo-differential mode, two inputs make up a differential pair. Psuedo-differential conversions are performed by taking a single-ended conversion at each input of a differential pair and then subtracting the results. The pseudo-differential mode is selectable for unipolar or bipolar operation. Unipolar differential operation allows only positive polarities of differential voltages. Bipolar differential operation allows negative and positive polarities of differential voltages. Bipolar conversions are in two’s complement format. For example, Table 2. Input Monitor Ranges and Enables REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION IN1 Voltage Range Selection: 00 = 5.6V, 01 = 2.8V 10 = 1.4V, 11 = Reserved IN2 Voltage Range Selection: 00 = 5.6V, 01 = 2.8V 10 = 1.4V, 11 = Reserved IN3 Voltage Range Selection: 00 = 5.6V, 01 = 2.8V 10 = 1.4V, 11 = Reserved IN4 Voltage Range Selection: 00 = 5.6V, 01 = 2.8V 10 = 1.4V, 11 = Reserved [1:0] [3:2] 17h 97h [5:4] [7:6] 16 ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 2. Input Monitor Ranges and Enables (continued) REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION [1:0] IN5 Voltage Range Selection: 00 = 5.6V, 01 = 2.8V 10 = 1.4V, 11 = Reserved IN6 Voltage Range Selection: 00 = 5.6V, 01 = 2.8V 10 = 1.4V, 11 = Reserved IN7 Voltage Range Selection: 00 = 5.6V, 01 = 2.8V 10 = 1.4V, 11 = Reserved IN8 Voltage Range Selection: 00 = 5.6V, 01 = 2.8V 10 = 1.4V, 11 = Reserved IN1 Monitoring Enable: 0 = IN1 monitoring disabled 1 = IN1 monitoring enabled IN2 Monitoring Enable: 0 = IN2 monitoring disabled 1 = IN2 monitoring enabled IN3 Monitoring Enable: 0 = IN3 monitoring disabled 1 = IN3 monitoring enabled IN4 Monitoring Enable: 0 = IN4 monitoring disabled 1 = IN4 monitoring enabled IN5 Monitoring Enable: 0 = IN5 monitoring disabled 1 = IN5 monitoring enabled IN6 Monitoring Enable: 0 = IN6 monitoring disabled 1 = IN6 monitoring enabled IN7 Monitoring Enable: 0 = IN7 monitoring disabled 1 = IN7 monitoring enabled IN8 Monitoring Enable: 0 = IN8 monitoring disabled 1 = IN8 monitoring enabled [3:2] 18h 98h [5:4] [7:6] [0] [1] [2] [3] 1Ah 9Ah [4] [5] [6] [7] ______________________________________________________________________________________ 17 EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 a -1V differential input (range of 5.6V) gives a decimal code of -183, which is 1101001001 in two’s complement binary form. In single-ended mode, conversions are performed between a single input and ground. When single-ended mode is selected, conversions are always unipolar regardless of r1Ch[7:4]. The singleended and pseudo-differential ADC mode equations are shown below. Unipolar single-ended mode: ⎛ VIN− ⎞ X ADC = INT ⎜ × 1024⎟ ⎝ VRANGE ⎠ where XADC is the resulting code in decimal, VIN- is the voltage at a voltage monitoring input, and VRANGE is the selected range programmed in r17h and r18h. Bipolar/unipolar pseudo-differential mode: ⎛ VIN+ ⎞ ⎞ ⎛ VIN− X ADC = INT ⎜ × 1024⎟ − INT ⎜ × 1024 ⎝ VRANGE ⎠ ⎠ ⎝ VRANGE where XADC is the resulting code in decimal, VIN+ is the voltage at a positive input of a differential voltage monitoring input pair, VIN- is the voltage at a negative input of a differential voltage monitoring input pair, and VRANGE is the selected ADC IN_ voltage range programmed in r17h and r18h. Table 3. IN1–IN8 ADC Input Mode Selection REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION [0] IN1/IN2 Single-Ended/Pseudo-Differential: 0 = IN1 and IN2 conversions are single-ended. 1 = IN1 and IN2 conversions are pseudo-differential (IN1 to IN2). IN3/IN4 Single-Ended/Pseudo-Differential: 0 = IN3 and IN4 conversions are single-ended. 1 = IN3 and IN4 conversions are pseudo-differential (IN3 to IN4). IN5/IN6 Single-Ended/Pseudo-Differential: 0 = IN5 and IN6 conversions are single-ended. 1 = IN5 and IN6 conversions are pseudo-differential (IN5 to IN6). IN7/IN8 Single-Ended/Pseudo-Differential: 0 = IN7 and IN8 conversions are single-ended. 1 = IN7 and IN8 conversions are pseudo-differential (IN7 to IN8). IN1/IN2 Unipolar/Bipolar: 0 = IN1 and IN2 conversions are unipolar. 1 = IN1 and IN2 conversions are bipolar (two’s complement). IN3/IN4 Unipolar/Bipolar: 0 = IN3 and IN4 conversions are unipolar. 1 = IN3 and IN4 conversions are bipolar (two’s complement). IN5/IN6 Unipolar/Bipolar: 0 = IN5 and IN6 conversions are unipolar. 1 = IN5 and IN6 conversions are bipolar (two’s complement). IN7/IN8 Unipolar/Bipolar: 0 = IN7 and IN8 conversions are unipolar. 1 = IN7 and IN8 conversions are bipolar (two’s complement). [1] [2] [3] 1Ch 9Ch [4] [5] [6] [7] 18 ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory Current Monitoring The MAX16031 provides current-sense inputs CS+/CSand a current-sense amplifier for current monitoring (see Figure 3). There are two programmable currentsense thresholds: primary overcurrent and secondary overcurrent. For fast fault detection, the primary overcurrent threshold is implemented with an analog comparator connected to the OVERC output. The primary threshold equation is: I TH = VCSTH RSENSE of the sense resistor. See Table 4 for a description of r19h. The ADC output for a current-sense conversion is: V × AV X ADC = SENSE × 28 VRBP MAX16031/MAX16032 ( − 1 ) where XADC is the 8-bit decimal ADC result, VSENSE is VCS+ - VCS-, AV is the current-sense voltage gain set by r19h[1:0], and VRBP is the reference voltage at RBP (1.4V typical). OVERC is latched when the primary overcurrent threshold is exceeded by programming r5Ch[4]. The latch is cleared by writing a ‘1’ to r53h[6]. OVERC depends only on the primary overcurrent threshold. Other fault outputs are programmed to depend on the secondary overcurrent threshold. The secondary overcurrent threshold is implemented through ADC conversions and digital comparisons. The secondary overcurrent threshold contains programmable time delay options located in r5Ch[1:0]. Primary and secondary currentsense faults are enabled/disabled through r1Bh[3]. where ITH is the current threshold to be set, VCSTH is the threshold set by r19h[1:0], and RSENSE is the value VMON CS+ RSENSE CS+ *AV TO ADC MUX Temperature Monitoring VL MAX16031 LOAD OVERC + + *VCSTH *ADJUSTABLE BY r19h [1:0] Figure 3. Current-Sense Block Diagram The MAX16031 provides two sets of remote diode inputs, DXP1/DXN1 and DXP2/DXN2, and one internal temperature sensor. The MAX16032 provides one set, DXP1/DXN1, and one internal temperature sensor. Calibration registers provide adjustments for gain and offset to accommodate different types of remote diodes. The internal temperature sensor circuitry is factory trimmed. In addition to offset/gain trimming, a programmable lowpass filter is provided. See Figure 4 for the block diagram of the temperature sensor circuitry. The remote diode is actually a diode-connected transistor. See Application Notes AN1057 and AN1944 for information on error budget and several transistor manufacturers. Table 4. Overcurrent Primary Threshold and Remote Temperature Sense Gain Trim REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION 19h 99h [1:0] Overcurrent Primary Threshold and Current-Sense Gain Setting: 00 = 200mV threshold, AV = 6V/V 01 = 100mV threshold, AV = 12V/V 10 = 50mV threshold, AV = 24V/V 11 = 25mV threshold, AV = 48V/V Remote Temperature Sensor 1 Gain Trim. Note bit 6 is inverted. Remote Temperature Sensor 1 Gain Trim Not used [7:2] 4Fh CFh [5:0] [7:6] ______________________________________________________________________________________ 19 EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 ABP Table 5. Temperature Data Format TEMPERATURE (°C) +128 DIGITAL CODE 1100000000 1011111010 1011010000 1000110011 1000000000 0111101100 0101101010 0100111000 0100000000 0000000000 ILOW IHIGH +125 +100 +25.5 - DXP_ TO ADC MUX 0 -10 -75 -100 -128 Diode fault VBIAS ~ 100mV DXN_ IBIAS + ABP Reading ADC Results Figure 4. Remote Temperature Sensor Amplifier Circuitry The ADC converts the internal sensor and remote sensor amplifier outputs. Each time the ADC converts all enabled parameters, the temperature conversions are compared to the temperature threshold registers (r46h to r4Bh and r4Dh). Unlike the voltage input comparators, the temperature threshold comparators are 10 bits wide. OVERT is the designated output for temperature faults, although other outputs are programmed to depend on temperature faults as well. See the Programmable Inputs/Outputs section for more information on programming output dependencies. See the Faults section for more information on setting temperature fault thresholds. The remote temperature sensor amplifier detects a short or open between DXP_ and DXN_. The detection of these events is programmed to cause a fault. Temperature thresholds and conversions are in a two’s complement temperature format, where 1 LSB corresponds to 0.5°C. The data format for temperature conversions is illustrated in Table 5. Offset and gain errors for remote temperature sensor measurements are user-trimmed through gain registers r19h[7:2]/r4Fh[5:0] and offset registers r1Bh[7:5]/r4D[6:4], as shown in Tables 4 and 6. The gain value trims the high (56µA) drive current source to compensate for the n-factor of the remote diode. The offset value is multiplied by 4 and added to the conversion result numerically. The MAX16031/MAX16032 contain an internal lowpass filter at DXN_ and DXP_ to reduce noise. See the Miscellaneous Settings section for more information on programming the filter cutoff frequency. ADC conversion results are read from the ADC conversion registers through the I2C/SMBus-compatible or JTAG interfaces (see Table 7). These registers are also used for fault threshold comparison. Voltage monitoring thresholds are compared with only the first 8 MSBs of the conversion results. Programmable Inputs/Outputs The MAX16031 provides two general fault outputs, FAULT1 and FAULT2, one reset output RESET, one temperature fault output OVERT, one current fault output OVERC, two general-purpose inputs/outputs GPIO1 and GPIO2, and one SMBALERT#-compatible output ALERT . The MAX16032 provides the same except OVERC. All outputs are open drain and require pullup resistors. Fault outputs do not latch except for OVERC, which either latches or does not latch depending on the configuration bit in r5Ch. Individual fault flag bits, however, latch (see the Faults section) and must be cleared one bit at a time by writing a byte containing all zeros except for a single ‘1’ in the bit to be cleared. The general outputs, FAULT1 and FAULT2, are identical in functionality and are programmed to depend on overvoltage, undervoltage, overtemperature, and overcurrent parameters. See r1Dh and r1Eh in Table 8 for more detailed information regarding the general fault output dependencies. The reset output RESET provides many programmable output dependencies as well as reset timeouts. See r20h and r21h in Table 8 for detailed information on RESET output dependencies and timeouts. The temperature fault output OVERT indicates temperature-related faults. OVERT is programmed to depend on any primary temperature threshold and/or the remote diode open/short flags. OVERT latches low dur- 20 ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 6. Temperature Sensor Fault Enable, Current-Sense Fault Enable, SMBALERT# Enable, and Temperature Offset Trim REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION [0] Internal Temperature Sensor Faults Enable: 0 = Internal temperature sensor faults disabled 1 = Internal temperature sensor faults enabled Remote Temperature Sensor 1 Faults Enable: 0 = Remote temperature sensor 1 faults disabled 1 = Internal temperature sensor 1 faults enabled Remote Temperature Sensor 2 Faults Enable: 0 = Remote temperature sensor 2 faults disabled 1 = Remote temperature sensor 2 faults enabled Current-Sense Fault Enable: 0 = Current-sense faults disabled 1 = Current-sense faults enabled SMBALERT# Enable (ALERT): 0 = SMBALERT# disabled 1 = SMBALERT# enabled Remote Temperature Sensor 1 Offset Trim: Offset = 4 × X, where X is the two’s-complement 3-bit temperature code (1 LSB = 0.5°C). Since X is multiplied by 4, the offset LSB size is 2°C, allowing a total offset adjustment of ±6°C. Internal Temperature Sensor Primary Overtemperature Threshold LSB Internal Temperature Sensor Secondary Overtemperature Threshold LSB Remote Temperature Sensor 2 Offset Trim: Offset = 4 × X, where X is the two’s-complement 3-bit temperature code (1 LSB = 0.5°C). Since X is multiplied by 4, the offset LSB size is 2°C, allowing a total offset adjustment of ±6°C. Not used. [1] [2] 1Bh 9Bh [3] [4] [7:5] [1:0] [3:2] 4Dh CDh [6:4] [7] ing diode open/short fault conditions, and the corresponding diode open/short flags must be cleared to release the latch. See r1Fh in Table 8 for more information on OVERT output dependencies. The current fault output OVERC indicates overcurrent events. OVERC only depends on the primary analog overcurrent threshold. See the Current Monitoring section for more information about the current-sense amplifier and the primary threshold. The secondary overcurrent threshold is set digitally and is used by other outputs. The secondary threshold also has a programmable timeout option (see Miscellaneous Settings section). GPIO1 and GPIO2 are programmable as logic inputs, manual reset inputs, logic outputs, or fault dependent outputs. See r22h–r25h in Table 8 for more detailed information on GPIO1/GPIO2 functionality. GPIO1 and GPIO2 assert low when configured as a fault output. ALERT is an SMBALERT#-compatible fault interrupt output. When enabled, it is logically ANDed with outputs RESET, FAULT1, FAULT2, OVERT, OVERC, and GPIO1/GPIO2 (only if enabled as fault outputs). When any fault output is asserted, ALERT also asserts, interrupting the SMBus master to query the fault. The master needs to answer MAX16031/MAX16032 with a specific SMBus command (ARA) to retrieve the slave address of the interrupting device. See the I2C/SMBusCompatible Serial Interface section for more details. 21 ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 7. ADC Conversion Registers REGISTER ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h EEPROM MEMORY ADDRESS — — — — — — — — — — — — — — — — — — — — — — — BIT RANGE [7:0] [1:0] [7:2] [7:0] [1:0] [7:2] [7:0] [1:0] [7:2] [7:0] [1:0] [7:2] [7:0] [1:0] [7:2] [7:0] [1:0] [7:2] [7:0] [1:0] [7:2] [7:0] [1:0] [7:2] [7:0] [1:0] [7:2] [7:0] [1:0] [7:2] [7:0] [1:0] [7:2] [7:0] DESCRIPTION IN1 ADC Conversion Result (MSB) IN1 ADC Conversion Result (LSB) Reserved IN2 ADC Conversion Result (MSB) IN2 ADC Conversion Result (LSB) Reserved IN3 ADC Conversion Result (MSB) IN3 ADC Conversion Result (LSB) Reserved IN4 ADC Conversion Result (MSB) IN4 ADC Conversion Result (LSB) Reserved IN5 ADC Conversion Result (MSB) IN5 ADC Conversion Result (LSB) Reserved IN6 ADC Conversion Result (MSB) IN6 ADC Conversion Result (LSB) Reserved IN7 ADC Conversion Result (MSB) IN7 ADC Conversion Result (LSB) Reserved IN8 ADC Conversion Result (MSB) IN8 ADC Conversion Result (LSB) Reserved Internal Temperature Sensor ADC Conversion Result (MSB) Internal Temperature Sensor ADC Conversion Result (LSB) Reserved Remote Temperature Sensor 1 ADC Conversion Result (MSB) Remote Temperature Sensor 1 ADC Conversion Result (LSB) Reserved Remote Temperature Sensor 2 ADC Conversion Result (MSB) Remote Temperature Sensor 2 ADC Conversion Result (LSB) Reserved Current-Sense ADC Conversion Result 22 ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 8. Output Dependencies REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE [0] [1] [2] [3] 1Dh 9Dh [4] [5] [6] [7] [0] [1] [2] [3] 1Eh 9Eh [4] [5] [6] [7] [0] 1Fh 9Fh [1] [2] DESCRIPTION 1 = FAULT1 depends on the secondary undervoltage thresholds of all enabled IN1–IN8. 1 = FAULT1 depends on the primary overvoltage thresholds of all enabled IN1–IN8. 1 = FAULT1 depends on the secondary overvoltage thresholds of all enabled IN1–IN8. 1 = FAULT1 depends on the secondary overtemperature threshold of the internal temperature sensor. 1 = FAULT1 depends on the secondary overtemperature threshold of remote temperature sensor 1. 1 = FAULT1 depends on the secondary overtemperature threshold of remote temperature sensor 2. 1 = FAULT1 depends on the secondary overcurrent threshold. Reserved 1 = FAULT2 depends on the secondary undervoltage thresholds of all enabled IN1–IN8. 1 = FAULT2 depends on the primary overvoltage thresholds of all enabled IN1–IN8. 1 = FAULT2 depends on the secondary overvoltage thresholds of all enabled IN1–IN8. 1 = FAULT2 depends on the secondary overtemperature threshold of the internal temperature sensor. 1 = FAULT2 depends on the secondary overtemperature threshold of remote temperature sensor 1. 1 = FAULT2 depends on the secondary overtemperature threshold of remote temperature sensor 2. 1 = FAULT2 depends on the secondary overcurrent threshold. Reserved 1 = OVERT depends on the primary overtemperature threshold of the internal temperature sensor. 1 = OVERT depends on the primary overtemperature threshold of the remote temperature sensor 1. 1 = OVERT depends on the primary overtemperature threshold of the remote temperature sensor 2. ______________________________________________________________________________________ 23 EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 8. Output Dependencies (continued) REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION 1 = OVERT depends on the diode short flag of remote temperature sensor 1. OVERT latches when the diode is shorted. Clear the latch by writing to r50h. 1 = OVERT depends on the diode open flag of remote temperature sensor 1. OVERT latches when the diode is open. Clear the latch by writing to r50h. 1 = OVERT depends on the diode short flag of remote temperature sensor 2. OVERT latches when the diode is shorted. Clear the latch by writing to r50h. 1 = OVERT depends on the diode open flag of remote temperature sensor 2. OVERT latches when the diode is open. Clear the latch by writing to r50h. Reserved RESET Configuration: 000 = RESET has no dependencies; asserts during boot and boot-up timeout and then deasserts indefinitely. 001 = RESET depends on the primary undervoltage thresholds at inputs that are selected by r21h[7:0]. 010 = RESET depends on the primary overvoltage thresholds at inputs that are selected by r21h[7:0]. 011 = RESET depends on both the primary undervoltage and overvoltage thresholds at those inputs that are selected by r21h[7:0]. 100 = RESET depends on the primary undervoltage thresholds at inputs that are selected by r21h[7:0] and the internal temperature sensor primary overtemperature threshold. 101 = RESET depends on both the primary undervoltage and overvoltage thresholds at those inputs that are selected by r21h[7:0] and the internal temperature sensor primary overtemperature threshold. 110 = RESET depends on the primary undervoltage thresholds at inputs that are selected by r21h[7:0] and each internal/remote temperature sensor primary overtemperature threshold. 111 = RESET depends on both the primary undervoltage and overvoltage thresholds at those inputs that are selected by r21h[7:0] and each internal/remote temperature sensor primary overtemperature threshold. RESET Timeout: 000 = 25µs 001 = 2.5ms 010 = 10ms 011 = 40ms 100 = 160ms 101 = 640ms 110 = 1280ms 111 = 2560ms Reserved [3] [4] 1Fh 9Fh [5] [6] [7] [2:0] 20h A0h [5:3] [7:6] 24 ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 8. Output Dependencies (continued) REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE [0] [1] [2] 21h A1h [3] [4] [5] [6] [7] DESCRIPTION 1 = RESET depends on IN1 with thresholds defined by r20h[2:0]. 1 = RESET depends on IN2 with thresholds defined by r20h[2:0]. 1 = RESET depends on IN3 with thresholds defined by r20h[2:0]. 1 = RESET depends on IN4 with thresholds defined by r20h[2:0]. 1 = RESET depends on IN5 with thresholds defined by r20h[2:0]. 1 = RESET depends on IN6 with thresholds defined by r20h[2:0]. 1 = RESET depends on IN7 with thresholds defined by r20h[2:0]. 1 = RESET depends on IN8 with thresholds defined by r20h[2:0]. GPIO1 Output Dependencies: 000 = GPIO1 is a digital input that is read from r22h[7]. 001 = GPIO1 is a digital manual reset input that asserts RESET when asserted. The state of GPIO1 is read from r22h[7]. 010 = GPIO1 is a digital output that is written to through r22h[6]. 011 = GPIO1 is a digital fault output that depends on conditions selected by r23h[6:0]. 100 = GPIO1 is a digital output that depends on primary thresholds at the input selected by r22h[5:3]. 101 =GPIO1 is a digital output that depends on primary thresholds at the input selected by r22h[5:3] and on conditions selected by r23h[6:0]. 110 = Reserved 111 = Reserved GPIO1 Single-Input Primary Threshold Voltage Monitor (r22h[2:0] = 100 or 101 only). GPIO1 asserts low when any primary threshold of this input is exceeded: 000 = IN1 001 = IN2 010 = IN3 011 = IN4 100 = IN5 101 = IN6 110 = IN7 111 = IN8 GPIO1 Output (write to this bit): 1 = GPIO1 is set high if GPIO1 is configured as an output. 0 = GPIO1 is set low if GPIO1 is configured as an output. GPIO1 Input State (read from this bit): 1 = Indicates that GPIO1 is high regardless if GPIO1 is set as an output or input. 0 = Indicates that GPIO1 is low regardless if GPIO1 is set as an output or input. [2:0] 22h A2h [5:3] [6] [7] ______________________________________________________________________________________ 25 EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 8. Output Dependencies (continued) REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE [0] [1] [2] [3] 23h A3h [4] [5] [6] [7] DESCRIPTION 1 = GPIO1 depends on the secondary undervoltage thresholds of all enabled IN1–IN8. 1 = GPIO1 depends on the primary overvoltage thresholds of all enabled IN1–IN8. 1 = GPIO1 depends on the secondary overvoltage thresholds of all enabled IN1–IN8. 1 = GPIO1 depends on the secondary overtemperature threshold of the internal temperature sensor. 1 = GPIO1 depends on the secondary overtemperature threshold of remote temperature sensor 1. 1 = GPIO1 depends on the secondary overtemperature threshold of remote temperature sensor 2. 1 = GPIO1 depends on the secondary overcurrent threshold. Reserved GPIO2 Output Dependencies: 000 = GPIO2 is a digital input that is read from r24h[7]. 001 = GPIO2 is a digital manual reset input that asserts RESET when asserted. The state of GPIO2 is read from r24h[7]. 010 = GPIO2 is a digital output that is written to through r24h[6]. 011 = GPIO2 is a digital fault output that depends on conditions selected by r25h[6:0]. 100 = GPIO2 is a digital output that depends on primary thresholds at the input selected by r24h[5:3]. 101 = GPIO2 is a digital output that depends on primary thresholds at the input selected by r24h[5:3] and on conditions selected by r25h[6:0]. 110 = Reserved 111 = Reserved GPIO2 Single-Input Primary Threshold Voltage Monitor (r24h[2:0] = 100 or 101 only). GPIO2 asserts low when the primary threshold of this input is exceeded: 000 = IN1 001 = IN2 010 = IN3 011 = IN4 100 = IN5 101 = IN6 110 = IN7 111 = IN8 GPIO2 Output (write to this bit): 1 = GPIO2 is set high if GPIO2 is configured as an output. 0 = GPIO2 is set low if GPIO2 is configured as an output. GPIO2 Input (read from this bit): 1 = Indicates that GPIO2 is high regardless if GPIO2 is set as an output or input. 0 = Indicates that GPIO2 is low regardless if GPIO2 is set as an output or input. [2:0] 24h A4h [5:3] [6] [7] 26 ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 8. Output Dependencies (continued) REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE [0] [1] [2] [3] 25h A5h [4] [5] [6] [7] DESCRIPTION 1 = GPIO2 depends on the secondary undervoltage thresholds of all enabled IN1–IN8. 1 = GPIO2 depends on the primary overvoltage thresholds of all enabled IN1–IN8. 1 = GPIO2 depends on the secondary overvoltage thresholds of all enabled IN1–IN8. 1 = GPIO2 depends on the secondary overtemperature threshold of the internal temperature sensor. 1 = GPIO2 depends on the secondary overtemperature threshold of remote temperature sensor 1. 1 = GPIO2 depends on the secondary overtemperature threshold of remote temperature sensor 2. 1 = GPIO2 depends on the secondary overcurrent threshold. Reserved Faults The MAX16031/MAX16032 offer many configurable options for detecting and managing system faults. Fault thresholds are set in r26h–r4Eh, as shown in Table 9. Any threshold that is configured to cause a fault can be masked at any time from causing a fault by setting bits in r54h–r57h, as shown in Table 10. Fault flags indicate the fault status of a particular input. The fault flag of any monitored input in the device can be read at any time from r50h–r53h, as shown in Table 11. Clear a fault flag by writing a ‘1’ to the appropriate bit in the flag register. Table 9. Fault Thresholds REGISTER ADDRESS 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h EEPROM MEMORY ADDRESS A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h BIT RANGE [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] DESCRIPTION IN1 Primary Undervoltage Threshold IN1 Primary Overvoltage Threshold IN1 Secondary Undervoltage Threshold IN1 Secondary Overvoltage Threshold IN2 Primary Undervoltage Threshold IN2 Primary Overvoltage Threshold IN2 Secondary Undervoltage Threshold IN2 Secondary Overvoltage Threshold IN3 Primary Undervoltage Threshold IN3 Primary Overvoltage Threshold IN3 Secondary Undervoltage Threshold IN3 Secondary Overvoltage Threshold IN4 Primary Undervoltage Threshold IN4 Primary Overvoltage Threshold ______________________________________________________________________________________ 27 EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 9. Fault Thresholds (continued) REGISTER ADDRESS 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch EEPROM MEMORY ADDRESS B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh BIT RANGE [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [1:0] [3:2] [6:4] [7] [1:0] 4Eh CEh [3:2] [5:3] [7:6] DESCRIPTION IN4 Secondary Undervoltage Threshold IN4 Secondary Overvoltage Threshold IN5 Primary Undervoltage Threshold IN5 Primary Overvoltage Threshold IN5 Secondary Undervoltage Threshold IN5 Secondary Overvoltage Threshold IN6 Primary Undervoltage Threshold IN6 Primary Overvoltage Threshold IN6 Secondary Undervoltage Threshold IN6 Secondary Overvoltage Threshold IN7 Primary Undervoltage Threshold IN7 Primary Overvoltage Threshold IN7 Secondary Undervoltage Threshold IN7 Secondary Overvoltage Threshold IN8 Primary Undervoltage Threshold IN8 Primary Overvoltage Threshold IN8 Secondary Undervoltage Threshold IN8 Secondary Overvoltage Threshold Internal Temperature Sensor Primary Overtemperature Threshold MSB (2 LSBs are in r4Dh[1:0]). Internal Temperature Sensor Secondary Overtemperature Threshold MSB (2 LSBs are in r4Dh[3:2]). Remote Temperature Sensor 1 Primary Overtemperature Threshold MSB (2 LSBs are in r4Eh[1:0]). Remote Temperature Sensor 1 Secondary Overtemperature Threshold MSB (2 LSBs are in r4Eh[3:2]). Remote Temperature Sensor 2 Primary Overtemperature Threshold MSB (2 LSBs are in r4Eh[5:4]). Remote Temperature Sensor 2 Secondary Overtemperature Threshold MSB (2 LSBs are in r4Eh[7:6]). Current-Sense Secondary Threshold Internal Temperature Sensor Primary Overtemperature Threshold LSB Internal Temperature Sensor Secondary Overtemperature Threshold LSB Remote Temperature Sensor 2, Offset Trim Not used Remote Temperature Sensor 1 Primary Overtemperature Threshold LSB Remote Temperature Sensor 1 Secondary Overtemperature Threshold LSB Remote Temperature Sensor 2 Primary Overtemperature Threshold LSB Remote Temperature Sensor 2 Secondary Overtemperature Threshold LSB 4Dh CDh 28 ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 10. Fault Masks REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE [0] [1] 54h D4h [2] [3] [7:4] [0] [1] [2] 55h D5h [3] [4] [5] [6] [7] [0] [1] [2] 56h D6h [3] [4] [5] [6] [7] [0] [1] [2] 57h D7h [3] [4] [5] [6] [7] DESCRIPTION 1 = Short-circuit detection at remote temperature sensor 1 is masked. 1 = Open-circuit detection at remote temperature sensor 1 is masked. 1 = Short-circuit detection at remote temperature sensor 2 is masked. 1 = Open-circuit detection at remote temperature sensor 2 is masked. Not used. 1 = IN1 primary overvoltage and undervoltage faults are masked. 1 = IN2 primary overvoltage and undervoltage faults are masked. 1 = IN3 primary overvoltage and undervoltage faults are masked. 1 = IN4 primary overvoltage and undervoltage faults are masked. 1 = IN5 primary overvoltage and undervoltage faults are masked. 1 = IN6 primary overvoltage and undervoltage faults are masked. 1 = IN7 primary overvoltage and undervoltage faults are masked. 1 = IN8 primary overvoltage and undervoltage faults are masked. 1 = IN1 secondary overvoltage and undervoltage faults are masked. 1 = IN2 secondary overvoltage and undervoltage faults are masked. 1 = IN3 secondary overvoltage and undervoltage faults are masked. 1 = IN4 secondary overvoltage and undervoltage faults are masked. 1 = IN5 secondary overvoltage and undervoltage faults are masked. 1 = IN6 secondary overvoltage and undervoltage faults are masked. 1 = IN7 secondary overvoltage and undervoltage faults are masked. 1 = IN1 secondary overvoltage and undervoltage faults are masked. 1 = Internal temperature sensor primary overtemperature fault masked. 1 = Remote temperature sensor 1 primary overtemperature fault masked. 1 = Remote temperature sensor 2 primary overtemperature fault masked. 1 = Internal temperature sensor secondary overtemperature fault masked. 1 = Remote temperature sensor 1 secondary overtemperature fault masked. 1 = Remote temperature sensor 2 secondary overtemperature fault masked. 1 = Current-sense primary overcurrent fault masked. 1 = Current-sense secondary overcurrent fault masked. ______________________________________________________________________________________ 29 EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 11. Fault Flags REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE [0] [1] 50h D0h [2] [3] [7:4] [0] [1] [2] 51h D1h [3] [4] [5] [6] [7] [0] [1] [2] 52h D2h [3] [4] [5] [6] [7] [0] [1] [2] [3] 53h D3h [4] [5] [6] [7] DESCRIPTION 1 = Short circuit detected at remote temperature sensor 1. 1 = Open circuit detected at remote temperature sensor 1. 1 = Short circuit detected at remote temperature sensor 2. 1 = Open circuit detected at remote temperature sensor 2. Not used. 1 = IN1 conversion result exceeds primary overvoltage or undervoltage thresholds. 1 = IN2 conversion result exceeds primary overvoltage or undervoltage thresholds. 1 = IN3 conversion result exceeds primary overvoltage or undervoltage thresholds. 1 = IN4 conversion result exceeds primary overvoltage or undervoltage thresholds. 1 = IN5 conversion result exceeds primary overvoltage or undervoltage thresholds. 1 = IN6 conversion result exceeds primary overvoltage or undervoltage thresholds. 1 = IN7 conversion result exceeds primary overvoltage or undervoltage thresholds. 1 = IN8 conversion result exceeds primary overvoltage or undervoltage thresholds. 1 = IN1 conversion result exceeds secondary overvoltage or undervoltage thresholds. 1 = IN2 conversion result exceeds secondary overvoltage or undervoltage thresholds. 1 = IN3 conversion result exceeds secondary overvoltage or undervoltage thresholds. 1 = IN4 conversion result exceeds secondary overvoltage or undervoltage thresholds. 1 = IN5 conversion result exceeds secondary overvoltage or undervoltage thresholds. 1 = IN6 conversion result exceeds secondary overvoltage or undervoltage thresholds. 1 = IN7 conversion result exceeds secondary overvoltage or undervoltage thresholds. 1 = IN8 conversion result exceeds secondary overvoltage or undervoltage thresholds. 1 = Internal temperature sensor conversion exceeds its primary overtemperature threshold. 1 = Remote temperature sensor 1 conversion exceeds its primary overtemperature threshold. 1 = Remote temperature sensor 2 conversion exceeds its primary overtemperature threshold. 1 = Internal temperature sensor conversion exceeds its secondary overtemperature threshold. 1 = Remote temperature sensor 1 conversion exceeds its secondary overtemperature threshold. 1 = Remote temperature sensor 2 conversion exceeds its secondary overtemperature threshold. 1 = Current-sense conversion exceeds its primary overcurrent threshold. 1 = Current-sense conversion exceeds its secondary overcurrent threshold. 30 ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 12. Fault Log Dependency REGISTER ADDRESS EEPROM BIT MEMORY RANGE ADDRESS [0] [1] [2] 58h D8h [3] [4] [5] [6] [7] [0] [1] [2] 59h D9h [3] [4] [5] [6] [7] [0] [1] 5Ah DAh [2] [3] [7:4] DESCRIPTION 1 = Fault log triggered when IN1 is below its primary undervoltage threshold. 1 = Fault log triggered when IN2 is below its primary undervoltage threshold. 1 = Fault log triggered when IN3 is below its primary undervoltage threshold. 1 = Fault log triggered when IN4 is below its primary undervoltage threshold. 1 = Fault log triggered when IN5 is below its primary undervoltage threshold. 1 = Fault log triggered when IN6 is below its primary undervoltage threshold. 1 = Fault log triggered when IN7 is below its primary undervoltage threshold. 1 = Fault log triggered when IN8 is below its primary undervoltage threshold. 1 = Fault log triggered when IN1 is above its primary overvoltage threshold. 1 = Fault log triggered when IN2 is above its primary overvoltage threshold. 1 = Fault log triggered when IN3 is above its primary overvoltage threshold. 1 = Fault log triggered when IN4 is above its primary overvoltage threshold. 1 = Fault log triggered when IN5 is above its primary overvoltage threshold. 1 = Fault log triggered when IN6 is above its primary overvoltage threshold. 1 = Fault log triggered when IN7 is above its primary overvoltage threshold. 1 = Fault log triggered when IN8 is above its primary overvoltage threshold. 1 = Fault log triggered when current sense is above its primary overcurrent threshold. 1 = Fault log triggered when internal temperature sensor is above its overtemperature threshold. 1 = Fault log triggered when remote temperature sensor 1 is above its overtemperature threshold. 1 = Fault log triggered when remote temperature sensor 2 is above its overtemperature threshold. Not used. Fault Logging If a specific input threshold is critical to the operation of the system, an automatic fault log is configured to trigger a transfer of fault information to EEPROM. The fault log dependencies are configured through r58h–r5Ah, as shown in Table 12. Logged fault information is read from EEPROM locations r80h–r8Eh, as shown in Table 13. Once a fault log event occurs, the fault log feature is locked and must be reset to enable a new fault log to be stored. Write a ‘1’ to r5Fh[1] to reset the fault log. Fault information always contains the fault flag registers and is configured to also include the ADC result registers through r5Ch[7] (see the Miscellaneous Settings section). All stored ADC results are the 8 MSBs of the result. Miscellaneous Settings Table 14 shows several miscellaneous programmable items. Register r5Bh contains boot-up timeout and remote temperature sensor filter cutoff settings. Register r5Ch[1:0] sets the secondary overcurrent threshold timeout, which is the amount of delay after an overcurrent condition before the overcurrent condition becomes a fault. All voltage thresholds include two selectable hysteresis options programmed by r5Ch[5]. When r5Ch[6] = 1, the conditions programmed to cause a fault log event must happen for two consecutive ADC cycles rather than just one to provide an improvement in noise immunity. Register r5Ch[7] controls whether the ADC result registers are stored in EEPROM after a fault log. Register r5Eh provides storage space for a user-defined configuration or firmware version number. Register r5Fh[0] locks and unlocks the EEPROM and register set. Register r5Fh[1] indicates whether a fault log event occurred and the corresponding fault information is locked in EEPROM. Further fault log conditions will not write new fault information to the fault EEPROM until a ‘1’ is written to r5Fh[1]. ______________________________________________________________________________________ 31 EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 13. Fault Log EEPROM REGISTER ADDRESS — — — — — — — — — — — — — — — EEPROM MEMORY ADDRESS 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh BIT RANGE [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] DESCRIPTION Copy of r51h[7:0] at the time the fault log was triggered. Copy of r52h[7:0] at the time the fault log was triggered. Copy of r53h[7:0] at the time the fault log was triggered. IN1 conversion result at the time the fault log was triggered. IN2 conversion result at the time the fault log was triggered. 8 MSBs only. IN3 conversion result at the time the fault log was triggered. 8 MSBs only. IN4 conversion result at the time the fault log was triggered. 8 MSBs only. IN5 conversion result at the time the fault log was triggered. 8 MSBs only. IN6 conversion result at the time the fault log was triggered. 8 MSBs only. IN7 conversion result at the time the fault log was triggered. 8 MSBs only. IN8 conversion result at the time the fault log was triggered. 8 MSBs only. Internal temperature sensor conversion result at the time the fault log was triggered. 8 MSBs from 10-bit ADC conversion. Remote temperature sensor 1 conversion result at the time the fault log was triggered. 8 MSBs from 10-bit ADC conversion. Remote temperature sensor 2 conversion result at the time the fault log was triggered. 8 MSBs from 10-bit ADC conversion. Current-sense conversion result at the time the fault log was triggered. I2C/SMBus-Compatible Serial Interface The MAX16031/MAX16032 feature an I2C/SMBus-compatible 2-wire (SDA and SCL) serial interface for communication with a master device. All possible communication formats are shown in Figure 5. The slave address and SMBALERT# are described further in the following subsections. Figure 1 shows a detailed 2-wire interface timing diagram. For descriptions of the I2C and SMBus protocol and terminology, refer to the I 2 C-Bus Specification Version 2.1 and the System Management Bus (SMBus) Specification Version 2.0. The MAX16031/MAX16032 allow 2-wire communication up to 400kHz. SDA and SCL require external pullup resistors. SMBALERT# SMBALERT# is an optional interrupt signal defined in Appendix A of the SMBus Specification. The MAX16031/MAX16032 provide output ALERT as this interrupt signal. If enabled, ALERT asserts if any one of the following outputs asserts: F AULT1 , F AULT2 , RESET, OVERT, or OVERC. Additionally, if a GPIO_ is configured for a fault output, a fault at this output also causes ALERT to assert. ALERT deasserts when all fault conditions are removed (i.e., when all fault outputs are high). Typically ALERT is connected to all other SMBALERT# open-drain signals in the system, creating a wired-OR function with all SMBALERT# outputs. When the master is interrupted by its SMBALERT# input, it stops or finishes the current bus transfer and places an alert response address (ARA) on the bus. The slave that pulled the SMBALERT# signal low acknowledges the ARA and places its own address on the bus, identifying itself to the master as the slave that caused the interrupt. The 7-bit ARA is ‘0001100’ and the R/W bit is a don’t care. Slave Address The slave address inputs, A0 and A1, are each capable of detecting three different states, allowing nine identical devices to share the same serial bus. Connect A0 and A1 to GND, DBP, or leave as not connected (N.C.). See Table 15 for a listing of all possible 7-bit address input connections and their corresponding serial-bus addresses. 32 ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Send Byte Format S ADDRESS 7 bits R/W ACK 0 COMMAND 8 bits Data Byte: Presets the internal address pointer or represents a command. ACK P Receive Byte Format S ADDRESS 7 bits R/W ACK 1 DATA 8 bits Data Byte: Data is read from the location pointed to by the internal address pointer. NACK P Slave Address: Address of the slave on the serial interface bus. Slave Address: Address of the slave on the serial interface bus. Write Byte Format S ADDRESS 7 bits R/W ACK 0 COMMAND 8 bits Command Byte: Sets the internal address pointer. ACK DATA 8 bits Data Byte: Data is written to the locations set by the internal address pointer. ACK P SMBALERT# S ADDRESS 0001100 R/W ACK D.C. DATA 8 bits Slave Address: Slave places its own address on the serial bus. NACK P Slave Address: Address of the slave on the serial interface bus. Alert Response Address: Only the device that interrupted the master responds to this address. Read Byte Format S SLAVE ADDRESS 7 bits R/W ACK 0 COMMAND 8 bits Command Byte: Sets the internal address pointer. ACK SR SLAVE ADDRESS 7 bits R/W ACK 1 DATA BYTE NACK 8 bits Data Byte: Data is written to the locations set by the internal address pointer. P Slave Address: Address of the slave on the serial interface bus. Block Write Format S ADDRESS 7 bits WR ACK 0 COMMAND 8 bits Command Byte: FAh ACK BYTE COUNT = N 8 bits ACK DATA BYTE 1 ACK DATA BYTE … ACK DATA BYTE N ACK 8 bits 8 bits 8 bits P Slave to master Master to slave Slave Address: Address of the slave on the serial interface bus. Data Byte: Data is written to the locations set by the internal address pointer. Block Read Format S ADDRESS 7 bits WR ACK 0 COMMAND 8 bits Command Byte: FBh ACK SR ADDRESS 7 bits WR ACK 1 BYTE COUNT = N 8 bits ACK DATA BYTE N ACK DATA BYTE … ACK DATA BYTE N NACK 8 bits 8 bits 8 bits P Slave Address: Address of the slave on the serial interface bus. Slave Address: Address of the slave on the serial interface bus. Data Byte: Data is read from the locations set by the internal address pointer. S = START Condition P = STOP Condition Sr = Repeated START Condition D.C. = Don’t Care ACK = Acknowledge, SDA pulled low during rising edge of SCL. NACK = Not acknowledge, SDA left high during rising edge of SCL. All data is clocked in/out of the device on rising edges of SCL. = SDA transitions from high to low during period of SCL. = SDA transitions from low to high during period of SCL. Figure 5. Communication Formats ______________________________________________________________________________________ 33 EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 14. Miscellaneous Settings REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION Postboot Timeout (all faults and outputs masked): 0h = No timeout 1h = 0.974ms 2h = 2.030ms 3h = 3.978ms 4h = 8.038ms 5h = 15.99ms 6h = 31.99ms 7h = 63.99ms 8h = 128ms 9h = 256.0ms Ah = 512ms Bh = 1024ms Ch = 2048ms Dh = 4096ms Eh = 8192ms Fh = 16384ms Temperature Sensor Lowpass Filter Cutoff: 000 = No filter 001 = 2.53Hz 010 = 5.06Hz 011 = 10.1Hz 100 = 20.2Hz 101 = 40.5Hz 110 = 81Hz 111 = 162Hz Not used. Overcurrent Secondary Threshold Timeout: 00 = No delay 01 = 3.98ms 10 = 16ms 11 = 64ms Latch OVERC: 0 = No latch 1 = Latched after assertion Not used. Threshold Hysteresis (all thresholds): 0 = 0.78% 1 = 1.17% [3:0] 5Bh DBh [6:4] [7] [1:0] 5Ch DCh [2] [4:3] [5] 34 ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory Table 14. Miscellaneous Settings (continued) REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION MAX16031/MAX16032 [6] 5Ch DCh [7] Consecutive Faults on Primary Thresholds: 0 = Fault occurs after primary threshold is exceeded one time (normal operation). 1 = Fault occurs after primary threshold is exceeded twice. Fault Log ADC Conversions Option: 0 = When a fault log is triggered, only fault flags are saved in EEPROM. 1 = When a fault log is triggered, fault flags and ADC conversion results (8 MSBs) are saved in EEPROM. Firmware Version. 8 bits of memory for user-defined firmware version number. Configuration Lock: Write a ‘1’ to r5Fh[0] to toggle this register bit. 0 = Register and EEPROM configuration unlocked. 1 = Register and EEPROM configuration locked. Fault Log EEPROM Lock Flag (set automatically after fault log is triggered): Write a ‘1’ to r5Fh[1] to toggle this register bit. 0 = EEPROM is not locked. A triggered fault log stores fault information to EEPROM. 1 = A fault log has been triggered. Write a ‘1’ to this bit to clear the flag and allow a new fault log to be triggered. Not used. 5Eh DEh [7:0] [0] 5Fh DFh [1] [7:2] Table 15. Setting the I2C/SMBus Slave Address A1 GND GND GND N.C. N.C. N.C. DBP DBP DBP A0 GND N.C. DBP GND N.C. DBP GND N.C. DBP BUS ADDRESS 0011000 0011001 0011010 0101001 0101010 0101011 1001100 1001111 1001110 JTAG Serial Interface The MAX16031/MAX16032 contain an IEEE 1149.1- compliant JTAG port in addition to the I2C/SMBus-compatible serial bus. Either interface may be used to access internal memory; however, only one interface is allowed to run at a time. All digital I/Os on the MAX16031/MAX16032 are IEEE 1149.1 boundary-scan compliant, and contain the typical JTAG boundary scan cells that allow the inputs/outputs to be polled or forced high/low using standard JTAG instructions. The MAX16031/MAX16032 contain extra JTAG instructions and registers not included in the JTAG specification that provide access to internal memory. The extra instructions are: LOAD ADDRESS, WRITE, READ, REBOOT, SAVE, and USERCODE. The extra registers are: memory address, memory write, memory read, and user-code data. See Figure 6 for a block diagram of the JTAG interface. Special Commands The MAX16031/MAX16032 provide software reboot and fault log commands. A software reboot initiates the boot-up sequence, which normally occurs at POR. During boot-up, EEPROM configuration data is copied to registers. To initiate a software reboot, send 0xFC using the send byte format. A software-initiated fault log is functionally the same as a hardware-initiated fault log. During a fault log, ADC registers and fault information are logged in EEPROM. To trigger a software initiated fault log, send 0xFD using the send byte format. Test Access Port (TAP) Controller State Machine The TAP controller is a finite state machine that responds to the logic level at TMS on the rising edge of TCK. See Figure 7 for a diagram of the finite state machine. Test-Logic-Reset: At power-up, the TAP controller is in the test-logic-reset state. The instruction register contains the IDCODE instruction. All system logic of the device operates normally. 35 ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 REGISTERS AND EEPROM 01101 01100 MEMORY WRITE REGISTER [LENGTH = 8 BITS] MEMORY READ REGISTER [LENGTH = 8 BITS] MEMORY ADDRESS REGISTER [LENGTH = 8 BITS] BOUNDARY SCAN REGISTER [LENGTH = 198 BITS] USER CODE REGISTER [LENGTH = 32 BITS] IDENTIFICATION REGISTER [LENGTH = 32 BITS] BYPASS REGISTER [LENGTH = 1 BIT] VDBP INSTRUCTION REGISTER [LENGTH = 5 BITS] RPU TDI TMS TCK TEST ACCESS PORT (TAP) CONTROLLER MUX 2 TDO 01010 01001 01000 MUX 1 00001 00010 00100 COMMAND DECODER 01101 01100 SAVE REBOOT 00000 11111 Figure 6. JTAG Block Diagram Run-Test/Idle: The run-test/idle state is used between scan operations or during specific tests. The instruction register and test data registers remain idle. Select-DR-Scan: All test data registers retain their previous state. With TMS low, a rising edge of TCK moves the controller into the capture-DR state and initiates a scan sequence. TMS high during a rising edge on TCK moves the controller to the select-IR-scan state. Capture-DR: Data are parallel-loaded into the test data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected test data register does not allow parallel loads, the test data register remains at its current value. On the rising edge of TCK, the controller goes to the shift-DR state if TMS is low or it goes to the exit1-DR state if TMS is high. 36 Shift-DR: The test data register selected by the current instruction is connected between TDI and TDO and shifts data one stage toward its serial output on each rising edge of TCK while TMS is low. On the rising edge of TCK, the controller goes to the exit1-DR state if TMS is high. Exit1-DR: While in this state, a rising edge on TCK puts the controller in the update-DR state. A rising edge on TCK with TMS low puts the controller in the pause-DR state. Pause-DR: Shifting of the test data registers is halted while in this state. All test data registers retain their previous state. The controller remains in this state while TMS is low. A rising edge on TCK with TMS high puts the controller in the exit2-DR state. ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 1 TEST-LOGIC-RESET 0 0 RUN-TEST/IDLE 1 SELECT-DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 1 0 0 1 0 1 1 SELECT-IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 0 0 1 0 1 Figure 7. TAP Controller State Diagram Exit2-DR: A rising edge on TCK with TMS high while in this state puts the controller in the update-DR state. A rising edge on TCK with TMS low enters the Shift-DR state. Update-DR: A falling edge on TCK while in the updateDR state latches the data from the shift register path of the test data registers into a set of output latches. This prevents changes at the parallel output because of changes in the shift register. On the rising edge of TCK, the controller goes to the run-test/idle state if TMS is low or it goes to the select-DR-scan state if TMS is high. Select-IR-Scan: All test data registers retain their previous state. The instruction register remains unchanged during this state. With TMS low, a rising edge on TCK moves the controller into the capture-IR state. TMS high during a rising edge on TCK puts the controller back into the test-logic-reset state. Capture-IR: Use the capture-IR state to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of TCK. If TMS is high on the rising edge of TCK, the controller enters the exit1-IR state. If TMS is low on the rising edge of TCK, the controller enters the shift-IR state. Shift-IR: In this state, the shift register in the instruction register is connected between TDI and TDO and shifts data one stage for every rising edge of TCK toward the TDO serial output while TMS is low. The parallel outputs of the instruction register as well as all test data registers remain at their previous states. A rising edge on TCK with TMS high moves the controller to the exit1-IR state. A rising edge on TCK with TMS low keeps the controller in the shift-IR state while moving data one stage through the instruction shift register. ______________________________________________________________________________________ 37 EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Exit1-IR: A rising edge on TCK with TMS low puts the controller in the pause-IR state. If TMS is high on the rising edge of TCK, the controller enters the update-IR state. Pause-IR: Shifting of the instruction shift register is halted temporarily. With TMS high, a rising edge on TCK puts the controller in the exit2-IR state. The controller remains in the pause-IR state if TMS is low during a rising edge on TCK. Exit2-IR: A rising edge on TCK with TMS high puts the controller in the update-IR state. The controller loops back to shift-IR if TMS is low during a rising edge of TCK in this state. Update-IR: The instruction code that has been shifted into the instruction shift register is latched to the parallel outputs of the instruction register on the falling edge of TCK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on TCK with TMS low puts the controller in the run-test/idle state. With TMS high, the controller enters the select-DR-scan state. SAMPLE/PRELOAD: This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of the device are sampled at the boundary scan test data register without interfering with the normal operation of the device by using the capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into the boundary scan test data register through TDI using the shift-DR state. BYPASS: When the BYPASS instruction is latched into the instruction register, TDI connects to TDO through the 1-bit bypass test data register. This allows data to pass from DTDI to TDO without affecting the device’s normal operation. EXTEST: This instruction allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction register, the following actions occur. Once enabled through the update-IR state, the parallel outputs of all digital outputs are driven. The boundary scan test data register is connected between TDI and TDO. The capture-DR samples all digital inputs into the boundary scan test data register. IDCODE: When the IDCODE instruction is latched into the parallel instruction register, the identification test data register is selected. The device identification code is loaded into the identification test data register on the rising edge of TCK following entry into the capture-DR state. Shift-DR is used to shift the identification code out serially through TDO. During test-logic-reset, the identification code is forced into the instruction register. The ID code always has a 1 in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. See Table 17. Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 5 bits in length. When the TAP controller enters the shift-IR state, the instruction shift register is connected between TDI and TDO. While in the shift-IR state, a rising edge on TCK with TMS low shifts the data one stage toward the serial output at TDO. A rising edge on TCK in the exit1-IR state or the exit2-IR state with TMS high moves the controller to the update-IR state. The falling edge of that same TCK latches the data in the instruction shift register to the instruction register parallel output. Instructions supported by the MAX16031/MAX16032 and their respective operational binary codes are shown in Table 16. Table 16. JTAG Instruction Set INSTRUCTION BYPASS IDCODE SAMPLE/PRELOAD EXTEST USERCODE LOAD ADDRESS READ DATA WRITE DATA REBOOT SAVE BINARY CODE 11111 00000 00001 00010 00100 01000 01001 01010 01100 01101 Bypass Identification Boundary scan Boundary scan User-code data Memory address Memory read Memory write Resets the device Stores current fault information in EEPROM SELECTED REGISTER/ACTION 38 ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 17. 32-Bit Identification Code MSB Version (4 bits) 0000 Device ID (16 bits) 0000000000000001 Manufacturer ID (11 bits) 00011001011 Fixed value (1 bit) 1 LSB Table 18. 32-Bit User-Code Data MSB D.C. (don’t cares) 00000000000000000 I2C/SMBus Slave Address See Table 15 User identification (firmware version) r5Eh[7:0] contents SAVE: This is an extension to the standard IEEE 1149.1 instruction set that triggers a fault log. When the SAVE instruction is latched into the instruction register, the MAX16031/MAX16032 copy fault information from registers to EEPROM. USERCODE: When the USERCODE instruction is latched into the parallel instruction register, the usercode data register is selected. The device user code is loaded into the user-code data register on the rising edge of TCK following entry into the capture-DR state. Shift-DR is used to shift the user code out serially through TDO. See Table 18. LOAD ADDRESS: This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the MAX16031/MAX16032. When the LOAD ADDRESS instruction is latched into the instruction register, TDI connects to TDO through the 8-bit memory address test data register during the shift-DR state. READ: This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the MAX16031/MAX16032. When the READ instruction is latched into the instruction register, TDI connects to TDO through the 8-bit memory read test data register during the shift-DR state. WRITE: This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the MAX16031/MAX16032. When the WRITE instruction is latched into the instruction register, TDI connects to TDO through the 8-bit memory write test data register during the shift-DR state. REBOOT: This is an extension to the standard IEEE 1149.1 instruction set to initiate a software-controlled reset to the MAX16031/MAX16032. When the REBOOT instruction is latched into the instruction register, the MAX16031/MAX16032 reset and immediately begin their boot-up sequence. Boundary Scan The boundary scan feature allows access to all the digital I/O connections of the MAX16031/MAX16032. If the sample/preload or the EXTEST instruction is loaded into the instruction register, TDI connects to TDO through the 198-bit boundary scan register. Each digital I/O pin corresponds to 1 bit (or 2 bits, in the case of the A0 and A1 pins) of the boundary scan register. The rest of the boundary scan bits are reserved and are loaded with zeros. When the sample/preload instruction is executed, the current state of the digital outputs is latched into the boundary scan register and is shifted out through TDO. This instruction may be executed without interrupting normal operation of the part. When the EXTEST instruction is executed, the boundary scan register bits supersede the normal functionality of the I/O pins: an output mirrors the state of the corresponding boundary scan register bit. Table 19 lists the function of each boundary scan register bit. Since the I2C address select pins have three possible states, 2 boundary scan register bits are required to represent them. These bits are defined in Table 20. Applications Information Layout and Bypassing Bypass VCC, DBP, and ABP each with a 1µF capacitor to GND. Bypass RBP with a 2.2µF capacitor to GND. Avoid routing digital return currents through a sensitive analog area, such as an analog supply input return path or ABP’s bypass capacitor ground connection. Use dedicated analog and digital ground planes. ______________________________________________________________________________________ 39 EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 19. Boundary Cell Order BOUNDARY CELL NO. 0–147 148 149 150 151 152 153 154 155 156 157–182 183 184 185 186 187 188 189 190 191–197 DESCRIPTION/PIN Reserved GPIO1 (output) GPIO2 (output) SDA (output) ALERT FAULT2 FAULT1 OVERT RESET OVERC Reserved GPIO2 (input) GPIO1 (input) SDA (input) A0b A0a A1b A1a SCL Reserved Table 20. Address Pin State Decode A0A A0B 00 01 10 11 A0 PIN STATE High impedance Low High Not defined Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 48 TQFN-EP PACKAGE CODE T4877-6 OUTLINE NO. 21-0144 LAND PATTERN NO. 90-0132 40 ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory Revision History REVISION NUMBER 0 1 2 REVISION DATE 7/07 10/07 6/10 Initial release Revised the Ordering Information. Revised the Pin Description. DESCRIPTION PAGES CHANGED — 1 11 MAX16031/MAX16032 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 41 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.