MAX16056

19-4686; Rev 0; 6/09 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts General Description The MAX16056–MAX16059 are ultra-low-current 125nA (typ) microprocessor (µP) supervisory circuits that monitor a single system supply voltage. These devices assert an active-low reset signal whenever the V CC supply voltage drops below the factory-trimmed reset threshold, manual reset is pulled low, or the watchdog timer runs out (MAX16056/MAX16058). The reset output remains asserted for an adjustable reset timeout period after V CC rises above the reset threshold. Factorytrimmed reset threshold voltages are offered from 1.575V to 4.625V in approximately 100mV increments (see Table 1). These devices feature adjustable reset and watchdog timeout using external capacitors. The MAX16056/ MAX16058 contain a watchdog timer with a watchdog select input (WDS) that multiplies the watchdog timeout period by 128. The MAX16057/MAX16059 do not have the watchdog feature. The MAX16056–MAX16059 are available in either pushpull or open-drain output-type configurations (see the Ordering Information and Selector Guide). These devices are fully specified over the -40°C to +125°C automotive temperature range. The MAX16056/MAX16058 are available in the 8-pin TDFN package, and the MAX16057/ MAX16059 are available in the 6-pin TDFN package. Features o Ultra-Low 125nA (typ) Supply Current o 1.1V to 5.5V Operating Supply Range o Factory-Set Reset Threshold Options from 1.575V to 4.625V in Approximately 100mV Increments o Capacitor-Adjustable Reset Timeout o Capacitor-Adjustable Watchdog Timeout (MAX16056/MAX16058) o Watchdog Timer Capacitor Open Detect Function o Optional Watchdog Disable Function (MAX16056/MAX16058) o Manual Reset Input o Guaranteed RESET Valid for VCC ≥ 1.1V o Push-Pull or Open-Drain RESET Output Options o Power-Supply Transient Immunity o Small, 3mm x 3mm TDFN Package MAX16056–MAX16059 Ordering Information PART PINPACKAGE RESET OUTPUT Push-Pull Push-Pull Open-Drain Open-Drain WATCHDOG TIMER Yes No Yes No MAX16056ATA_ _+T 8 TDFN-EP* MAX16057ATT_ _+T MAX16059ATT_ _+T 6 TDFN-EP* 6 TDFN-EP* MAX16058ATA_ _+T 8 TDFN-EP* Applications Portable/Battery-Powered Equipment PDAs/Cell Phones MP3 Players/Pagers Glucose Monitors/Patient Monitors Metering/HVAC Automotive Infotainment Typical Operating Circuit appears at end of data sheet. Note: All devices are specified over the -40°C to +125°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed pad. “_ _” represents the two number suffix needed when ordering the reset threshold voltage value (see Table 1). Standard versions and their package top marks are shown in Table 3 at the end of data sheet. Pin Configurations TOP VIEW VCC 8 WDS 7 WDI 6 SRT 5 VCC 6 N.C. 5 SRT 4 MAX16056 MAX16058 *EP 1 2 3 SWT 4 MR *CONNECT EXPOSED PAD TO GND. 1 MAX16057 MAX16059 *EP 2 GND 3 MR RESET GND RESET TDFN TDFN ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts MAX16056–MAX16059 ABSOLUTE MAXIMUM RATINGS VCC to GND ..............................................................-0.3V to +6V SRT, SWT, WDS, MR, WDI, to GND ...........-0.3V to (VCC + 0.3V) RESET (Push-Pull) to GND .........................-0.3V to (VCC + 0.3V) RESET (Open-Drain) to GND ...................................-0.3V to +6V Input Current (all pins) .................................................... ±20mA Output Current (RESET) ................................................. ±20mA Continuous Power Dissipation (TA = +70°C) 6-Pin TDFN (derate 23.8mW/°C above +70°C) .........1905mW 8-Pin TDFN (derate 24.4mW/°C above +70°C) .........1951mW Junction-to-Ambient Thermal Resistance (θJA) (Note 1) 6-Pin TDFN ...................................................................42°C/W 8-Pin TDFN ...................................................................41°C/W Junction-to-Case Thermal Resistance (θJC) (Note 1) 6-Pin TDFN .....................................................................9°C/W 8-Pin TDFN .....................................................................8°C/W Operating Temperature Range .........................-40°C to +125°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature .....................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = 1.2V to 5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 2) PARAMETER Supply Voltage SYMBOL VCC CONDITIONS TA = 0°C to +125°C TA = -40°C to 0°C VCC = 5.0V, TA = -40°C to +85°C VCC = 3.3V, TA = -40°C to +85°C VCC > VTH + 150mV, no load, reset output deasserted (Note 3) VCC = 1.8V, TA = -40°C to +85°C VCC = 5.0V, TA = -40°C to +125°C VCC = 3.3V, TA = -40°C to +125°C VCC = 1.8V, TA = -40°C to +125°C VCC < VTH, no load, reset output asserted TA = +25°C VCC Reset Threshold VTH VCC falling (see Table 1) TA = -40°C to +125°C VTH 1.5% VTH 2.5% 0.5 80 10.5 14.18 17.0 MIN 1.1 1.2 142 132 125 142 132 125 7 TYP MAX 5.5 5.5 210 185 175 nA 430 415 400 15 VTH + 1.5% V VTH + 2.5% % µs ms µA UNITS V Supply Current ICC Hysteresis VCC to Reset Delay Reset Timeout Period VHYST tRD tRP VCC rising VCC falling from (VTH + 100mV) to (VTH - 100mV) at 10mV/µs CSRT = 2700pF 2 _______________________________________________________________________________________ 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts ELECTRICAL CHARACTERISTICS (continued) (VCC = 1.2V to 5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 2) PARAMETER SRT Ramp Current SRT Ramp Threshold Watchdog Timeout Clock Period SYMBOL IRAMP1 VRAMP1 tWDPER CONDITIONS TA = -40°C to VSRT = 0V to VRAMP1, +125°C VCC = 1.6V to 5V TA = +25°C VCC = 1.6V to 5V (VRAMP rising) TA = +25°C TA = -40°C to +125°C TA = -40°C to VSWT = 0V to VRAMP2, +125°C VCC = 1.6V to 5V TA = +25°C VCC = 1.6V to 5V (VRAMP2 rising) VCC ≥ 1.0V, ISINK = 50µA VOL VCC ≥ 2.7V, ISINK = 1.2mA VCC ≥ 4.5V, ISINK = 3.2mA RESET Output Voltage VOH MAX16056/MAX16057 VCC ≥ 1.8V, ISOURCE = 200µA VCC ≥ 2.25V, ISOURCE = 500µA VCC ≥ 4.5V, ISOURCE = 800µA RESET Output-Leakage Current, Open Drain ILKG VIH Input-Logic Levels VIL MR Minimum Pulse Width MR Glitch Rejection MR to RESET Delay WDI Minimum Pulse Width Input Leakage Current tMRD (Note 4) MR, WDI, WDS is connected to GND or VCC 150 -100 +100 tMPW 1 200 250 VCC > VTH, reset not asserted, VRESET = 5.5V (MAX16058/MAX16059) 0.7 x VCC 0.3 x VCC µs ns ns ns nA 0.8 x VCC 0.8 x VCC 0.8 x VCC 1.0 µA MIN 197 210 1.173 5 3.5 197 210 1.173 TYP 240 240 1.235 6.4 6.4 240 240 1.235 MAX 282 270 1.297 8 9.5 282 nA 270 1.297 0.3 0.3 0.4 V V V ms UNITS nA MAX16056–MAX16059 SWT Ramp Current SWT Ramp Threshold IRAMP2 VRAMP2 V Note 2: Devices are production tested at TA = +25°C. Specifications over temperature limits are guaranteed by design. Note 3: WDI input period is 1s with tRISE and tFALL < 50ns. Note 4: Guaranteed by design, not production tested. _______________________________________________________________________________________ 3 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts MAX16056–MAX16059 Typical Operating Characteristics (VCC = 2.5V, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX16056 toc01 SUPPLY CURRENT vs. TEMPERATURE RESET IS NOT ASSERTED VTH = 1.575V VCC = 5.5V VCC = 3.3V tRP (S) 200 150 100 VCC = 2.5V 50 VCC = 1.8V MAX16056 toc02 RESET TIMEOUT PERIOD vs. CSRT 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 MAX16056 toc03 10.0 VTH = 2.23V 350 300 SUPPLY CURRENT (nA) 250 2.0 ICC (FA) 1.0 TA = +125NC TA = +85NC TA = -40NC TA = +25NC 0.1 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC (V) 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (NC) 0 50 100 150 CSRT (nF) 200 250 300 NORMALIZED RESET TIMEOUT PERIOD vs. TEMPERATURE MAX16056 toc04 NORMALIZED WATCHDOG TIMEOUT PERIOD vs. TEMPERATURE 1.04 1.03 NORMALIZED tRP 1.02 1.01 1.00 0.99 0.98 0.97 0.96 0.95 1 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (NC) MAX16056 toc05 MAXIMUM VCC TRANSIENT DURATION vs. RESET THRESHOLD OVERDRIVE MAX16056 toc06 1.10 1.08 1.06 NORMALIZED tRP 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 1.05 1000 TRANSIENT DURATION (Fs) RESET OCCURS ABOVE THIS LINE 100 10 VCC FALLING FROM VTH + 100mV 10 100 RESET THRESHOLD OVERDRIVE (mV) 1000 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (NC) NORMALIZED RESET THRESHOLD VOLTAGE vs. TEMPERATURE MAX16056 toc07 VCC TO RESET DELAY vs. TEMPERATURE VCC = VTH + 100mV TO VTH - 100mV 110 100 tRD (Fs) 90 80 70 60 50 MAX16056 toc08 1.020 1.015 1.010 NORMALIZED VTH 1.005 1.000 0.995 0.990 0.985 0.980 120 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (NC) -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (NC) 4 _______________________________________________________________________________________ 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts Typical Operating Characteristics (continued) (VCC = 2.5V, TA = +25°C, unless otherwise noted.) MAX16056–MAX16059 RESET OUTPUT-LOW VOLTAGE vs. SINK CURRENT MAX16056 toc09 RESET OUTPUT-HIGH VOLTAGE vs. SOURCE CURRENT MAX16056 toc10 SUPPLY CURRENT vs. WATCHDOG SWITCHING FREQUENCY 0.9 0.8 SUPPLY CURRENT (FA) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 MAX16056 toc11 0.30 0.25 0.20 VOL (V) VCC = 1.8V 0.15 0.10 0.05 0 0 VCC = 2.5V 0.50 OUTPUT-HIGH VOLTAGE (VCC-VOH) (V) 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 VCC = 2.5V VCC = 3.3V VCC = 1.8V 1.0 VCC = 3.3V 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ISINK (mA) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 ISOURCE (mA) 0.01 0.1 1 10 100 1000 10,000 WATCHDOG SWITCHING FREQUENCY (kHz) MANUAL RESET DELAY vs. TEMPERATURE 268 266 264 tMRD (ns) 262 260 258 256 254 252 250 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (NC) MAX16056 toc12 MANUAL RESET DELAY MAX16056 toc13 270 MR 1V/div RESET 1V/div 200ns/div RESET SINK CAPABILITY vs. SUPPLY VOLTAGE MAX16056 toc14 RESET SOURCE CAPABILITY vs. SUPPLY VOLTAGE VRESET = 0.8 x VCC 3.5 SOURCE CURRENT (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 MAX16056 toc15 10 9 8 SINK CURRENT (mA) 7 6 5 4 3 2 1 0 0 0.5 1.0 1.5 2.0 VCC (V) 2.5 3.0 3.5 VRESET = 0.3V 4.0 4.0 VCC (V) _______________________________________________________________________________________ 5 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts MAX16056–MAX16059 Pin Description PIN MAX16056/ MAX16058 MAX16057/ MAX16059 NAME FUNCTION 1 1 RESET Push-Pull or Open-Drain Reset Output. RESET asserts whenever VCC drops below the selected reset threshold voltage (VTH) or manual reset is pulled low. RESET remains low for the reset timeout period after all reset conditions are deasserted, and then goes high. The watchdog timer triggers a reset pulse (tRP) whenever a watchdog fault occurs (MAX16056/MAX16058). Ground Watchdog Timeout Input. Connect a capacitor between SWT and GND to set the basic watchdog timeout period (tWD). Determine the period by the formula tWD = Floor[CSWT x 5.15 x 106/6.4ms] x 6.4ms + 3.2ms (Note 5) with tWD in seconds and CSWT in Farads, or use Table 2. Extend the basic watchdog timeout period by using the WDS input. Connect SWT to ground to disable the watchdog timer function. The value of the capacitor must be between 2275pF and 0.54µF to have a valid watchdog timeout period. Manual-Reset Input. Drive MR low to manually reset the device. RESET remains asserted for the reset timeout period after MR is released. There is no internal pullup on MR. MR must not be left unconnected. Connect MR to VCC if not used. Reset Timeout Input. Connect a capacitor from SRT to GND to select the reset timeout period. Determine the period as follows: tRP = 5.15 x 106 x CSRT with tRP in seconds and CSRT in Farads, or use Table 2. The value of the capacitor must be between 39pF and 4.7µF. Watchdog Input. A falling transition must occur on WDI within the selected watchdog timeout period or a reset pulse occurs. The watchdog timer clears when a falling transition occurs on WDI or whenever RESET is asserted. Connect SWT to ground to disable the watchdog timer function. Watchdog Select Input. WDS selects the watchdog timeout mode. Connect WDS to ground to select normal mode. The watchdog timeout period is tWD. Connect WDS to VCC to select extended mode, multiplying the basic timeout period (tWD) by a factor of 128. A change in the state of WDS clears the watchdog timer. Supply Voltage. VCC is the power-supply input and the input for fixed threshold VCC monitor. For noisy systems, bypass VCC with a 0.1µF capacitor to GND. No Connection. Not internally connected. Exposed Pad. Connect EP to GND or leave unconnected. 2 2 GND 3 — SWT 4 3 MR 5 4 5 6 — WDI 7 — WDS 8 — — 6 5 — VCC N.C. EP Note 5: Floor: take the integral value. 6 _______________________________________________________________________________________ 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts Detailed Description The MAX16056–MAX16059 are ultra-low-current 125nA (typ) µP supervisory circuits that monitor a single system supply voltage. These devices assert an active-low reset signal whenever the VCC supply voltage drops below the factory-trimmed reset threshold, manual reset is pulled low, or the watchdog timer runs out (MAX16056/MAX16058). The reset output remains asserted for an adjustable reset timeout period after VCC rises above the reset threshold. The reset and watchdog delay periods are adjustable using external capacitors. Watchdog Timer The MAX16056/MAX16058’s watchdog timer circuitry monitors the µP’s activity. If the µP does not toggle (high-to-low) the watchdog input (WDI) within the capacitor-adjustable watchdog timeout period (tWD), RESET asserts for the reset timeout period (tRP). The internal watchdog timer is cleared by: 1) any event that asserts RESET, by 2) a falling transition at WDI (that can detect pulses as short as 150ns) or by 3) a transition (high-to-low or low-to-high) at WDS. While reset is asserted, the watchdog timer remains cleared and does not count. As soon as reset deasserts, the watchdog timer resumes counting. There are two modes of watchdog operation, normal mode and extended mode. In normal mode (Figure 2), the watchdog timeout period is determined by the value of the capacitor connected between SWT and ground. In extended mode (Figure 3), the watchdog timeout period is multiplied by 128. For example, in extended mode, a 0.33µF capacitor gives a watchdog timeout period of 212s (see Table 2). To disable the watchdog timer function, connect SWT to ground. When VCC ramps above VTH + VHYST, the value of the external SWT capacitor is sampled after RESET goes high. When sampling is finished, the capacitor value is stored in the device and is used to set watchdog timeout. If RESET goes low before sampling is finished, the device interrupts sampling, and sampling is restarted when RESET goes high again. If the external SWT capacitor is less than 470pF, the sampling result sets the watchdog timeout to zero. This causes the watchdog to assert RESET continuously after sampling is finished. If a PCB manufacturing defect caused the connection to CSWT to be broken, the capacitance is very low and RESET is continuously asserted. If the external SWT capacitor is greater than 5600pF, the sampling result sets the watchdog timeout to be infinite, disabling the watchdog function. MAX16056–MAX16059 RESET Output The MAX16056–MAX16059 µP supervisory circuits assert a reset to prevent code-execution errors during powerup, power-down, and brownout conditions. The reset output is guaranteed to be valid for VCC down to 1.1V. When VCC falls below the reset threshold, the RESET output asserts low. Once VCC exceeds the reset threshold plus the hysteresis, an internal timer keeps the reset output asserted for the capacitor-adjusted reset timeout period (tRP), then after this interval the reset output deasserts (see Figure 1). The reset function features immunity to power-supply voltage transients. Manual-Reset Input (MR) Many µP-based products require manual-reset capability, allowing the operator, a test technician, or external logic circuitry to initiate a reset. The MAX16056– MAX16059 feature an MR input. A logic-low on MR asserts a reset. RESET remains asserted while MR is low and for the timeout period, tRP, after MR returns high. Connect MR to VCC if unused. MR can be driven with CMOS logic levels or with open-drain/collector outputs (with a pullup resistor). Connect a normally open momentary switch from MR to GND and a resistor from MR to VCC to implement a manual-reset function; external debounce circuitry is not required. If MR is driven by long cables or the device is used in a noisy environment, connect a 0.1µF capacitor from MR to GND to provide additional noise immunity. _______________________________________________________________________________________ 7 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts MAX16056–MAX16059 VTH + VHYST VCC tRP tRP VTH tMRD RESET tRD tMPW MR Figure 1. RESET Timing Relationship VCC WDI 0V VCC RESET 0V NORMAL MODE (WDS = GND) tWD tRP Figure 2. Watchdog Timing Diagram, Normal Mode, WDS = GND VCC WDI 0V VCC RESET 0V EXTENDED MODE (WDS = VCC) tRP tWD x 128 Figure 3. Watchdog Timing Diagram, Extended Mode, WDS = VCC 8 _______________________________________________________________________________________ 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts Applications Information Selecting the Reset Timeout Capacitor The reset timeout period is adjustable to accommodate a variety of µP applications. To adjust the reset timeout period (tRP), connect a capacitor (CSRT) between SRT and ground. The reset timeout capacitor is calculated as follows: CSRT = tRP/(5.15 x 106) with tRP in seconds and CSRT in Farads. CSRT must be a low-leakage (< 10nA) type capacitor. A ceramic capacitor with low temperature coefficient dielectric (i.e., X7R) is recommended. accuracy by substituting the minimum, typical, and maximum values into the equation. For example, if CSWT = 100nF where tWDPER (min) = 3.2ms, tWDPER (typ) = 6.4ms, tWDPER (max) = 9.5ms. MAX16056–MAX16059 Transient Immunity For applications with higher slew rates on VCC during power-up, additional bypass capacitance may be required. tWDMIN = Floor[100 x 10-9 x 1.173/(282 x 10-9)/9.5ms] x 3.2ms + 0.5 x 3.2ms = 141.7ms tWDNOM = Floor[100 x 10-9 x 1.235/(240 x 10-9)/6.4ms] + 0.5 x 6.4ms = 515.2ms tWDMAX = Floor[100 x 10-9 x 1.297/(197 x 10-9)/3.5ms] x 9.5ms + 0.5 x 9.5ms = 1790.75ms The MAX16056–MAX16059 are relatively immune to short-duration supply voltage transients, or glitches on VCC. The Maximum VCC Transient Duration vs. Reset Threshold Overdrive graph in the Typical Operating Characteristics shows this transient immunity. The area below the curve of the graph is the region where these devices typically do not generate a reset pulse. This graph was generated using a falling pulse applied to VCC, starting 100mV above the actual reset threshold (VTH) and ending below this threshold (reset threshold overdrive). As the magnitude of the transient increases, the maximum allowable pulse width decreases. Typically, a 100mV VCC transient duration of 40µs or less does not cause a reset. Selecting Watchdog Timeout Capacitor The watchdog timeout period is adjustable to accommodate a variety of µP applications. With this feature, the watchdog timeout can be optimized for software execution. The programmer can determine how often the watchdog timer should be serviced. Adjust the watchdog timeout period (tWD) by connecting a capacitor (CSWT) between SWT and GND. For normal mode operation, calculate the watchdog timeout as follows: tWD = Floor[CSWT x 5.15 x 106/6.4ms] x 6.4ms + 3.2ms with tWD in seconds and CSWT in Farads. (Floor: take the integral value) (Figures 2 and 3) The maximum tWD is 296s. If the capacitor sets tWD greater than the 296s, tWD = infinite and the watchdog timer is disabled. CSWT must be a low-leakage (< 10nA) type capacitor. A ceramic capacitor with low temperature coefficient dielectric (i.e., X7R) is recommended. Using the MAX16056–MAX16059 for Reducing System Power Consumption Using the RESET output to control an external p-channel MOSFET to control the on-time of a power supply can result in lower system power consumption in systems that can be regularly put to sleep. By tying the WDI input to ground, the RESET output becomes a low-frequency clock output. When RESET is low, the MOSFET is turned on and power is applied to the system. When RESET is high, the MOSFET is turned off and no power is consumed by the system. This effectively reduces the shutdown current of the system to zero (Figure 4). Watchdog Timeout Accuracy The watchdog timeout period is affected by the SWT ramp current (IRAMP2) accuracy, the SWT ramp threshold (VRAMP2) and the watchdog timeout clock period (tWDPER). In the equation above, the constant 5.15 x 106 is equal to VRAMP2/IRAMP2, and 6.4ms equals the watchdog timeout clock period. Calculate the timeout _______________________________________________________________________________________ 9 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts MAX16056–MAX16059 BAT 1MΩ 0.1µF VCC 0.1µF VCC1 RESET MR MAX16056 WDI µP MANUAL POWER-ON SWT CSWT CSRT SRT GND WDS VCC RESET VCC1 tRP tWD tRP Figure 4. Using MAX16056–MAX16059 to Reduce System Power Consumption 10 ______________________________________________________________________________________ 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts Interfacing to Other Voltages for Logic Compatibility The open-drain RESET output can be used to interface to a µP with other logic levels. The open-drain output is connected to a voltage from 0V to 5.5V as shown in Figure 5. Generally, the pullup resistor connected to RESET connects to the supply voltage that is being monitored at the device’s VCC input. However, some systems use the open-drain output to level-shift from the supervisor’s monitored supply to another supply voltage. As the supervisor’s VCC decreases, so does the device’s ability to sink current at RESET. Ensuring a Valid RESET Down to VCC = 0V (Push-Pull RESET) When VCC falls below 1.1V, the current-sinking capability of RESET decreases drastically. The high-impedance CMOS logic inputs connected to RESET can drift to undetermined voltages. This presents no problems in most applications, since most µPs and other circuitry do not operate with VCC below 1.1V. In those applications where RESET must be valid down to 0, add a pulldown resistor between the MAX16056/MAX16057 push-pull RESET output and GND. The resistor sinks any stray leakage currents, holding RESET low (Figure 6). Choose a pulldown resistor that accommodates leakages, such that RESET is not significantly loaded and is capable of pulling to GND. The external pulldown cannot be used with the open-drain RESET output of the MAX16058/MAX16059. MAX16056–MAX16059 5V VCC 3.3V VCC VCC VCC MAX16058 MAX16059 100kΩ µP RESET RESET MAX16056 MAX16057 RESET 2MΩ GND GND GND Figure 5. Interfacing with Other Voltage Levels Figure 6. Ensuring RESET Valid to VCC = GND ______________________________________________________________________________________ 11 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts MAX16056–MAX16059 Table 1. Threshold Suffix Guide SUFFIX 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 225 22 21 20 19 18 17 16 VCC THRESHOLD FALLING (V) MIN 4.509 4.388 4.266 4.193 4.095 3.998 3.900 3.802 3.705 3.608 3.510 3.413 3.315 3.218 3.120 2.998 2.925 2.852 2.730 2.633 2.559 2.438 2.340 2.255 2.180 2.133 2.048 1.950 1.853 1.755 1.623 1.536 TYP 4.625 4.500 4.375 4.300 4.200 4.100 4.000 3.900 3.800 3.700 3.600 3.500 3.400 3.300 3.200 3.075 3.000 2.925 2.800 2.700 2.625 2.500 2.400 2.313 2.235 2.188 2.100 2.000 1.900 1.800 1.665 1.575 MAX 4.741 4.613 4.484 4.408 4.305 4.203 4.100 3.998 3.895 3.793 3.690 3.588 3.485 3.383 3.280 3.152 3.075 2.998 2.870 2.768 2.691 2.563 2.460 2.371 2.290 2.243 2.153 2.050 1.948 1.845 1.707 1.614 12 ______________________________________________________________________________________ 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts MAX16056–MAX16059 Table 2. Capacitor Selection Guide CAPACITANCE (pF) 39 47 56 68 82 100 120 150 180 220 270 330 390 470 560 680 820 1000 1200 1500 1800 2200 2700 3300 3900 4700 5600 6800 8200 10,000 12,000 15,000 18,000 14.18 16.99 20.1 24.21 28.84 35.00 42.23 51.5 61.8 77.25 92.7 16 16 22.4 22.4 28.8 35.2 41.6 54.4 60.8 80 92.8 1641 1641 2460 2460 3280 4099 4918 6556 7376 9833 11,472 Indeterminate (0, 9.6, or 16) Indeterminate (0, 1228.8, or 1636) Not recommended 0 (no capacitor is connected) tRP (ms) tWD (ms) tWD x 128 (ms) ______________________________________________________________________________________ 13 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts MAX16056–MAX16059 Table 2. Capacitor Selection Guide (continued) CAPACITANCE (pF) 22,000 27,000 33,000 39,000 47,000 56,000 68,000 82,000 100,000 120,000 150,000 180,000 220,000 270,000 330,000 390,000 470,000 680,000 820,000 1,000,000 1,500,000 2,200,000 3,300,000 4,700,000 tRP (ms) 113.3 139.05 169.95 200.85 242.05 288.4 350.2 422.3 515 618 772.5 927 1133 1390.5 1699.5 2008.5 2420.5 3502 4223 5150 7725 11,330 16,995 24,205 Infinite (watchdog is disabled) Indeterminate (may be infinite and watchdog is disabled) tWD (ms) 112 137.6 169.6 201.6 240 291.2 348.8 419.2 515.2 617.6 771.2 924.8 1129.6 1392 1699.2 2006.4 2416 tWD x 128 (ms) 13,929 17,206 21,302 25,398 30,313 36,867 44,240 53,251 65,539 78,646 98,307 117,968 144,182 177,769 217,091 256,412 308,841 14 ______________________________________________________________________________________ 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts MAX16056–MAX16059 Table 3. Standard Versions PART MAX16056ATA17+ MAX16056ATA23+ MAX16056ATA26+ MAX16056ATA29+ MAX16056ATA31+ MAX16056ATA46+ MAX16057ATT17+ MAX16057ATT23+ MAX16057ATT26+ MAX16057ATT29+ MAX16057ATT36+ MAX16057ATT41+ MAX16058ATA16+ MAX16058ATA22+ MAX16058ATA26+ MAX16058ATA29+ MAX16058ATA31+ MAX16058ATA44+ MAX16059ATT16+ MAX16059ATT22+ MAX16059ATT26+ MAX16059ATT29+ MAX16059ATT31+ MAX16059ATT44+ TOP MARK BKZ BLA BLB BLC BLD BLE ATQ ATR ATS ATT AUC AUD BLF BLG BLH BLI BLJ BLK ATW ATX ATY ATZ AUA AUB ______________________________________________________________________________________ 15 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts MAX16056–MAX16059 Typical Operating Circuit BAT 1MΩ 0.1µF VCC VCC RESET MR MAX16056 WDI µP MANUAL RESET SWT CSWT CSRT SRT GND WDS Chip Information PROCESS: BiCMOS PACKAGE TYPE 8 TDFN-EP 6 TDFN-EP Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE CODE T833-2 T633-2 DOCUMENT NO. 21-0137 21-0137 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.