MAX9877AERP

19-4651; Rev 0; 5/09 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier General Description The MAX9877A combines a high-efficiency Class D audio power amplifier with a stereo Class AB capacitorless DirectDrive® headphone amplifier. Maxim’s 3rd generation, filterless Class D amplifier with active emissions limiting* technology provides Class AB performance with Class D efficiency. The MAX9877A delivers up to 725mW from a 3.7V supply into an 8Ω load with 87% efficiency to extend battery life. The filterless modulation scheme combined with active emissions limiting circuitry and spread-spectrum modulation** greatly reduces EMI while eliminating the need for output filtering used in traditional Class D devices. The stereo Class AB headphone amplifier in the MAX9877A uses Maxim’s patented DirectDrive architecture, that produces a ground-referenced output from a single supply, eliminating the need for large DC-blocking capacitors, saving cost, space, and component height. The device utilizes a user-defined input architecture, three preamplifier gain settings, an input mixer, volume control, comprehensive click-and-pop suppression, and I2C control. A bypass mode feature disables the integrated Class D amplifier and utilizes an internal DPST switch to allow an external amplifier to drive the speaker that is connected at the outputs of the MAX9877A. The MAX9877A is available in a thermally efficient, space-saving 20-bump MaxFilm package. KIT ATION EVALU ABLE AVAIL Features o Low Emissions, Filterless Class D Amplifier Achieves Better than 10dB Margin Under EN55022 Class B Limits o Low RF Susceptibility Design Rejects TDMA Noise from GSM Radios o Input Mixer with User-Defined Input Mode o 725mW Speaker Output (RSPK = 8Ω, PVDD = 3.7V) o 53mW Headphone Output (RHP = 16Ω, VDD = 3.7V) o Low 0.05% THD+N at 1kHz (Class D Power Amplifier) o Low 0.016% THD+N at 1kHz (Headphone Amplifier) o 87% Efficiency (RSPK = 8Ω, POUT = 750mW) o 1.6Ω Analog Switch for Speaker Amplifier Bypass o High Speaker Amplifier PSRR (72dB at 217Hz) o High Headphone Amplifier PSRR (84dB at 217Hz) o I2C Control o Hardware and Software Shutdown Mode o Click-and-Pop Suppression o Current-Limit and Thermal Protection o Available in a Space-Saving, 2.5mm x 2.0mm MaxFilm Package MAX9877AERP Ordering Information PART MAX9877AERP+T TEMP RANGE -40°C to +85°C PIN-PACKAGE 20 MaxFilm (5x4) Applications Cell Phones Portable Multimedia Players *U.S. Patent #7,190,225. **U.S. Patent #6,847,257. +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. Simplified Block Diagram SINGLE SUPPLY 2.7V TO 5.25V Pin Configuration TOP VIEW (BUMP SIDE DOWN) 1 2 3 4 5 PREAMPLIFIER VOLUME CONTROL A HPR HPL VSS C1N C1P MIXER/MUX B VDD BIAS SDA RXIN+ OUT+ VOLUME CONTROL I2C INTERFACE C INB2 INB1 SCL PGND PVDD BYPASS D INA2 INA1 GND RXINOUT- MAX9877A MaxFilm ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP ABSOLUTE MAXIMUM RATINGS VDD, PVDD to PGND ..............................................-0.3V to +5.5V VDD to PVDD ..........................................................-0.3V to +0.3V VSS to PGND .........................................................-5.5V to +0.3V C1N to PGND..............................................(VSS - 0.3V) to +0.3V C1P to PGND ...........................................-0.3V to (PVDD + 0.3V) HPL, HPR to VSS (Note 1) ......-0.3V to the lower of (PVDD - (VSS + 0.3V)) or +9V HPL, HPR to PVDD (Note 2) ......+0.3V to the higher of (VSS - (PVDD - 0.3V)) or -9V GND to PGND.....................................................................±0.3V INA1, INA2, INB1, INB2, BIAS..................................-0.3V to +4V SDA, SCL...............................................................-0.3V to +5.5V All Other Pins to GND...............................-0.3V to (PVDD + 0.3V) Continuous Current In/Out of PVDD, PGND, OUT_.........±800mA Continuous Current In/Out of HPR and HPL .....................140mA Continuous Current In/Out of RXIN+ and RXIN- ...............150mA Continuous Input Current VSS ...........................................100mA Continuous Input Current (all other pins) .........................±20mA Duration of OUT_ Short Circuit to GND or PVDD ........Continuous Duration of Short Circuit Between OUT+ and OUT- ..Continuous Duration of HP_ Short Circuit to GND or PVDD ..........Continuous Continuous Power Dissipation (TA = +70°C) 20-Bump MaxFilm, 5 x 4, Multilayer Board (derate 13.0mW/°C above +70°C) ..................................1.04W Junction Temperature ......................................................+150°C Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Note 1: HPR and HPL should be limited to no more than 9V above VSS, or above PVDD + 0.3V, whichever limits first. Note 2: HPR and HPL should be limited to no more than 9V below PVDD, or below VSS - 0.3V, whichever limits first. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 3.3V. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER Supply Voltage Range SYMBOL CONDITIONS OSC = 00 OSC = 10 OSC = 00 OSC = 10 OSC = 00 OSC = 10 MIN 2.7 5.6 5.5 6.6 5.7 10.4 9.3 10 10 10 17.5 25 11 3 21 5.5 2.30 0.820 0.230 VP-P 80 31 8 ms ms 22 µA 16.0 11.0 mA TYP MAX 5.25 9.0 UNITS V VDD, PVDD Guaranteed by PSRR test HP mode, OUTMODE = 2 Quiescent Current IDD SPK mode, OUTMODE = 7 SPK + HP mode, OUTMODE = 9 Shutdown Current ISHDN ISHDN = IVDD + IPVDD; SHDN = 0; VSDA = VSCL = logic-high OSC = 00 Time from shutdown to full operation OSC = 01 OSC = 10 Turn-On Time tON BIAS Release Time tBR After forcing BIAS low, time from BIAS released to I2C reset TA = +25°C, preamp gain = 0dB or +9dB TA = +25°C, preamp gain = +20dB Preamp = 0dB Input Resistance RIN kΩ Maximum Input Signal Swing Preamp = +9dB Preamp = +20dB 2 _______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier ELECTRICAL CHARACTERISTICS (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 3.3V. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER Common-Mode Rejection Ratio Input DC Voltage Bias Voltage VBIAS TA = +25°C (volume at mute) Output Offset Voltage VOS TA = +25°C (Volume at 0dB, OUTMODE = 1, ∆IN_ = 0) Peak voltage, TA = +25°C, A-weighted, 32 samples per second, volume at mute (Note 4) Into shutdown Out of shutdown PVDD = VDD = 2.7V to 5.5V f = 217Hz, 100mVP-P ripple f = 1kHz, 100mVP-P ripple f = 20kHz, 100mVP-P ripple ZSPK = 8Ω + 68µH, VDD = 3.7V ZSPK = 8Ω + 68µH, VDD = 3.3V Output Power (Note 5) POUT THD+N ≤ 1% ZSPK = 8Ω + 68µH, VDD = 3.0V ZSPK = 4Ω + 33µH, VDD = 3.7V ZSPK = 4Ω + 33µH, VDD = 3.0V Total Harmonic Distortion Plus Noise THD+N f = 1kHz, POUT = 350mW, TA = +25°C, ZSPK = 8Ω + 68µH A-weighted, OUTMODE = 1, 3, 4, 6 Signal-to-Noise Ratio SNR A-weighted, OUTMODE = 7, 9 ∆IN_ = 0 (single-ended) ∆IN_ = 1 (differential) ∆IN_ = 0 (single-ended) ∆IN_ = 1 (differential) 50 SPEAKER AMPLIFIER (OUTMODE = 1) ±0.5 ±1.5 -70 dBV -70 76 72 dB 68 55 725 560 465 825 770 0.05 92 94 88 92 dB % mW ±4 mV SYMBOL CMRR CONDITIONS Preamp = 0dB fIN = 1kHz (differential input mode) IN_ inputs Preamp = +9dB Preamp = +20dB 1.22 1.13 MIN TYP 47 49 42 1.3 1.2 1.38 1.27 V V dB MAX UNITS MAX9877AERP Click-and-Pop Level KCP Power-Supply Rejection Ratio (Note 4) PSRR TA = +25°C, PVDD = VDD _______________________________________________________________________________________ 3 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP ELECTRICAL CHARACTERISTICS (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 3.3V. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER SYMBOL CONDITIONS Spread-spectrum modulation mode, OSC = 00 Output Frequency Fixed-frequency mode, OSC = 01 Fixed-frequency mode, OSC = 10 Current Limit Efficiency Speaker Gain Output Noise HEADPHONE AMPLIFIERS (OUTMODE = 2) Output Offset Voltage VOS TA = +25°C (volume at mute) TA = +25°C (volume at 0dB) Peak voltage, TA = +25°C, A-weighted, 32 samples per second. volume at mute (Note 4) Into shutdown Out of shutdown PVDD = VDD = 2.7V to 5.25V f = 217Hz, VRIPPLE = 100mVP-P f = 1kHz, VRIPPLE = 100mVP-P f = 20kHz, VRIPPLE = 100mVP-P Output Power Headphone Gain Channel-to-Channel Gain Tracking Total Harmonic Distortion Plus Noise THD+N POUT AV TA = +25°C, HPL to HPR, volume at 0dB, OUTMODE = 2, 5; ∆IN_ = 0 RHP = 32Ω (POUT = 10mW, f = 1kHz) RHP = 16Ω (POUT = 10mW, f = 1kHz), TA = +25°C A-weighted, OUTMODE = 2, 3, 5, 6; RHP = 16Ω Signal-to-Noise Ratio SNR A-weighted, RHP = 16Ω, OUTMODE = 8, 9 ∆IN_ = 0 (single-ended) ∆IN_ = 1 (differential) ∆IN_ = 0 (single-ended) ∆IN_ = 1 (differential) THD+N ≤ 1% RHP = 16Ω RHP = 32Ω -0.4 70 ±0.15 ±1.6 -80 dBV -80 85 84 dB 80 62 53 27 0 ±0.3 0.016 0.03 98 98 96 96 dB % +0.4 ±2.5 mW dB % ±0.6 mV η AV A-weighted, OUTMODE = 1, ∆IN_ = 0 (Note 4) POUT = 600mW, f = 1kHz 11.5 MIN TYP 1176 ±60 1100 700 1.5 87 12.0 63 12.5 A % dB µVRMS kHz MAX UNITS Click-and-Pop Level KCP Power-Supply Rejection Ratio (Note 4) PSRR TA = +25°C, PVDD = VDD 4 _______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier ELECTRICAL CHARACTERISTICS (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 3.3V. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER Slew Rate Capacitive Drive Crosstalk SYMBOL SR CL HPL to HPR, HPR to HPL, f = 20Hz to 20kHz Spread-spectrum modulation mode, OSC = 00 Charge-Pump Frequency Fixed-frequency mode, OSC = 01 Fixed-frequency mode, OSC = 10 VOLUME CONTROL Minimum Setting Maximum Setting Preamp Gain _VOL = 1 _VOL = 31 PGAIN_ = 00 Input A or B PGAIN_ = 01 PGAIN_ = 10 Mute Attenuation Zero-Crossing Detection Timeout ANALOG SWITCH On-Resistance RON IRXIN_ = 20mA, RXIN_ = 0V and VDD, BYPASS = 1 VDIF = 2VP-P, VCM = VDD/2, f = 1kHz, BYPASS = 1, TA = +25°C TA = +25°C TA = TMIN to TMAX Series resistance is 9.1Ω per switch No series resistors 0.05 0.3 1.6 4.5 Ω 5.2 0.25 % f = 1kHz, _VOL = 0 ZCD = 1 Speaker Headphone -75 0 0 9 20 100 110 60 dB ms dB dB dB 430 220 CONDITIONS MIN TYP 0.35 100 65 588 ±30 550 350 670 500 kHz MAX UNITS V/µs pF dB MAX9877AERP Total Harmonic Distortion Off-Isolation DIGITAL INPUTS Input-Voltage High (SDA, SCL) Input-Voltage Low (SDA, SCL) Input-Voltage Low (BIAS) Input Hysteresis (SDA, SCL) SDA, SCL Input Capacitance Input Leakage Current BIAS Pullup Current Output Low Voltage SDA Output Fall Time SDA DIGITAL OUTPUTS (SDA Open Drain) VOL tOF VH VL VBL VHYS CIN IIN IBIAS BYPASS = 0, RXIN+ and RXIN- to GND = 50Ω, ZSPK = 8Ω + 68µH, f = 10kHz, referred to speaker output signal 1.4 88 dB V 0.4 0.15 80 4 V V mV pF +1.0 94 µA µA 0.4 250 V ns SDA, SCL ISINK = 3mA VH(MIN) to VL(MAX) bus capacitance = 10pF to 400pF, ISINK = 3mA _______________________________________________________________________________________ 5 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP ELECTRICAL CHARACTERISTICS (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. SDA and SCL pullup voltage = 3.3V. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER 2-WIRE INTERFACE TIMING External Pullup Voltage Range: SDA and SCL Serial Clock Frequency Bus Free Time Between STOP and START Conditions START Condition Hold START Condition Setup Time Clock Low Period Clock High Period Data Setup Time Data Hold Time Maximum Receive SCL/SDA Rise Time Maximum Receive SCL/SDA Fall Time Setup Time for STOP Condition Capacitive Load for Each Bus Line fSCL tBUF tHD:STA tSU:STA tLOW tHIGH tSU:DAT tHD:DAT tR tF tSU:STO Cb 0.6 400 1.7 DC 1.3 0.6 0.6 1.3 0.6 100 0 900 300 300 3.6 400 V kHz µs µs µs µs µs ns ns ns ns µs pF SYMBOL CONDITIONS MIN TYP MAX UNITS Note 3: All devices are 100% production tested at room temperature. All temperature limits are guaranteed by design. Note 4: Amplifier inputs are AC-coupled to GND. Note 5: Output levels higher than 825mW are not recommended for extended durations. Production tested with ZSPK = 8Ω + 68µH only. 6 _______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP Typical Operating Characteristics (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) GENERAL SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX9877A toc01 SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX9877A toc02 SUPPLY CURRENT vs. SUPPLY VOLTAGE HEADPHONE AND SPEAKER INPUTS AC-COUPLED TO GND OUTMODE = 9 VSDA = VSCL = 3.3V MAX9877A toc03 9 HEADPHONE ONLY INPUTS AC-COUPLED TO GND OUTMODE = 8 VSDA = VSCL = 3.3V fOSC = 1176kHz SREAD-SPECTRUM MODE 10 9 SUPPLY CURRENT (mA) 8 7 6 fOSC = 700kHz 5 4 fOSC = 1100kHz SPEAKER ONLY INPUTS AC-COUPLED TO GND OUTMODE = 7 VSDA = VSCL = 3.3V fOSC = 1176kHz SPREAD-SPECTRUM MODE 13 12 SUPPLY CURRENT (mA) 11 10 fOSC = 700kHz 9 8 7 fOSC = 1176kHz SPREAD-SPECTRUM MODE fOSC = 1100kHz 2.5 3.0 3.5 4.0 4.5 5.0 8 SUPPLY CURRENT (mA) 7 6 fOSC = 1100kHz fOSC = 700kHz 4 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SHUTDOWN CURRENT vs. SUPPLY VOLTAGE MAX9877A toc04 VOLUME ATTENUATION vs. _VOL CONTROL CODE MAX9877A toc05 14 13 SHUTDOWN CURRENT (µA) 12 11 10 9 8 7 2.5 3.0 3.5 4.0 4.5 5.0 INPUTS AC-COUPLED TO GND VSDA = VSCL = 3.3V 20 0 VOLUME ATTENUATION (dB) -20 -40 -60 -80 -100 -120 fIN = 1kHz MEASURED AT HPL AND HPR 35 30 25 20 15 10 5 0 5.5 SUPPLY VOLTAGE (V) _VOL CONTROL CODE _______________________________________________________________________________________ 7 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP Typical Operating Characteristics (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) SPEAKER AMPLIFIER TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX9877A toc06 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX9877A toc07 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY VDD = PVDD = 3V ZSPK = 8Ω + 68µH MAX9877A toc08 10 10 10 VDD = PVDD = 3.7V ZSPK = 8Ω + 68µH VDD = PVDD = 3.7V ZSPK = 4Ω + 33µH DASHED LINES ARE LIMITED BY THE ABS. MAX RATINGS THD+N (%) POUT = 200mW POUT = 675mW 0.1 THD+N (%) POUT = 1100mW THD+N (%) 1 1 1 POUT = 425mW 0.1 0.1 POUT = 650mW POUT = 200mW 0.01 10 100 1k FREQUENCY (Hz) 10k 100k 0.01 10 100 1k FREQUENCY (Hz) 10k 100k 0.01 10 100 1k FREQUENCY (Hz) 10k 100k TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX9877A toc09 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX9877A toc10 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER VDD = PVDD = 5V ZSPK = 8Ω + 68µH fIN = 6kHz fIN = 20Hz MAX9877A toc11 10 VDD = PVDD = 3V ZSPK = 4Ω + 33µH 1 10 VDD = PVDD = 3.7V POUT = 200mW ZSPK = 8Ω + 68µH fOSC = 700kHz THD+N (%) POUT = 700mW 0.1 POUT = 250mW 0.01 10 100 1k FREQUENCY (Hz) 10k 100k THD+N (%) 0.1 fOSC = 1176kHz THD+N (%) 0.1 fOSC = 1100kHz 1 1 0.01 10 100 1k FREQUENCY (Hz) 10k 100k 0.01 0 0.5 fIN = 1kHz 1.0 OUTPUT POWER (W) 1.5 2.0 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER MAX9877A toc12 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER VDD = PVDD = 3.7V ZSPK = 8Ω + 68µH MAX9877A toc13 10 VDD = PVDD = 5V ZSPK = 4Ω + 33µH DASHED LINES ARE LIMITED BY THE ABS. MAX RATINGS fIN = 20Hz fIN = 6kHz 10 1 THD+N (%) THD+N (%) 1 fIN = 20Hz 0.1 fIN = 1kHz fIN = 1kHz fIN = 6kHz 0.1 0.01 0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT POWER (W) 0.01 0 200 400 600 800 1000 OUTPUT POWER (mW) 8 _______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier Typical Operating Characteristics (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER MAX9877A toc14 MAX9877AERP TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER MAX9877A toc15 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER VDD = PVDD = 3V ZSPK = 4Ω + 33µH DASHED LINES ARE LIMITED BY THE ABS. MAX RATINGS fIN = 20Hz fIN = 6kHz 0.1 fIN = 1kHz MAX9877A toc16 10 VDD = PVDD = 3.7V ZSPK = 4Ω + 33µH DASHED LINES ARE LIMITED BY THE ABS. MAX RATINGS fIN = 20Hz 10 10 VDD = PVDD = 3V ZSPK = 8Ω + 68µH THD+N (%) fIN = 6kHz THD+N (%) fIN = 20Hz 0.1 0.1 fIN = 1kHz 0.01 0 0.5 1.0 1.5 OUTPUT POWER (W) fIN = 6kHz fIN = 1kHz THD+N (%) 0.01 1 1 1 0.01 0 200 400 600 OUTPUT POWER (mW) 0 0.2 0.4 0.6 0.8 1.0 1.2 OUTPUT POWER (W) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER VDD = PVDD = 3.7V fIN = 1kHz ZSPK = 8Ω + 68µH MAX9877A toc17 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER MAX9877A toc18 EFFICIENCY vs. OUTPUT POWER 90 80 EFFICIENCY (%) 70 60 50 40 30 VDD = PVDD = 5V fIN = 1kHz DASHED LINES ARE LIMITED BY THE ABS. MAX RATINGS 0 0.5 1.0 1.5 2.0 2.5 3.0 ZSPK = 8Ω + 68µH ZSPK = 4Ω + 33µH MAX9877A toc19 1 1 fOSC = 1100kHz fOSC = 700kHz 100 THD+N (%) fOSC = 1176kHz SSM 0.1 THD+N (%) 0.1 fOSC = 1176kHz SSM VDD = PVDD = 3.7V fIN = 6kHz ZSPK = 8Ω + 68µH 0.01 fOSC = 700kHz fOSC = 1100kHz 0.01 0 200 400 600 800 OUTPUT POWER (mW) 0 200 20 10 0 800 400 600 OUTPUT POWER (mW) OUTPUT POWER (W) EFFICIENCY vs. OUTPUT POWER MAX9877A toc20 EFFICIENCY vs. OUTPUT POWER 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 2.0 0 200 400 VDD = PVDD = 3.7V fIN = 1kHz ZSPK = 8Ω + 68µH 600 800 1000 fOSC = 1176kHz AND 1100kHz fOSC = 700kHz MAX9877A toc21 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 0.5 1.0 OUTPUT POWER (W) 1.5 VDD = PVDD = 3.7V fIN = 1kHz DASHED LINES ARE LIMITED BY THE ABS. MAX RATINGS ZSPK = 8Ω + 68µH ZSPK = 4Ω + 33µH 100 OUTPUT POWER (mW) _______________________________________________________________________________________ 9 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP Typical Operating Characteristics (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) EFFICIENCY vs. OUTPUT POWER MAX9877A toc22 OUTPUT POWER vs. SUPPLY VOLTAGE MAX9877A toc23 OUTPUT POWER vs. SUPPLY VOLTAGE 1.8 1.6 OUTPUT POWER (W) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1% THD+N 10% THD+N VDD = PVDD ZSPK = 8Ω + 68µH MAX9877A toc24 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 200 400 600 800 VDD = PVDD = 3V fIN = 1kHz DASHED LINES ARE LIMITED BY THE ABS. MAX RATINGS ZSPK = 8Ω + 68µH ZSPK = 4Ω + 33µH 3.5 3.0 OUTPUT POWER (W) 2.5 2.0 1.5 1.0 0.5 0 1% THD+N VDD = PVDD ZSPK = 4Ω + 33µH DASHED LINES ARE LIMITED BY THE ABS. MAX RATINGS 10% THD+N 2.0 1000 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 OUTPUT POWER (mW) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) OUTPUT POWER vs. LOAD RESISTANCE MAX9877A toc25 OUTPUT POWER vs. LOAD RESISTANCE MAX9877A toc26 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY -10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 VDD = PVDD = 3.7V VRIPPLE = 100mVP-P INPUTS AC-COUPLED TO GND MAX9877A toc27 1.8 1.6 1.4 OUTPUT POWER (W) 1.2 1.0 0.8 0.6 1% THD+N 0.4 10% THD+N VDD = PVDD = 3.7V fIN = 1kHz ZSPK = LOAD + 68µH 1.2 1.0 OUTPUT POWER (W) 0.8 0.6 0.4 1% THD+N 0.2 VDD = PVDD = 3V fIN = 1kHz ZSPK = LOAD + 68µH 0 10% THD+N 0.2 0 0 10 20 30 40 50 60 70 80 90 100 LOAD RESISTANCE (Ω) 0 0 10 20 30 40 50 60 70 80 90 100 LOAD RESISTANCE (Ω) -100 10 100 1k FREQUENCY (Hz) 10k 100k IN-BAND OUTPUT SPECTRUM MAX9877A toc28 IN-BAND OUTPUT SPECTRUM fOSC = 700kHz fIN = 1kHz MAX9877A toc29 0 -20 AMPLITUDE (dBV) -40 -60 -80 -100 -120 -140 0 fOSC = 1100kHz fIN = 1kHz 0 -20 AMPLITUDE (dBV) -40 -60 -80 -100 -120 -140 5 10 FREQUENCY (kHz) 15 20 0 5 10 FREQUENCY (kHz) 15 20 10 ______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP Typical Operating Characteristics (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) IN-BAND OUTPUT SPECTRUM MAX9877A toc30 WIDEBAND OUTPUT SPECTRUM -10 -20 AMPLITUDE (dBV) -30 -40 -50 -60 -70 -80 fOSC = 1100kHz INPUTS AC-COUPLED TO GND MAX9877A toc31 0 -20 AMPLITUDE (dBV) -40 -60 -80 -100 -120 -140 0 5 10 FREQUENCY (kHz) 15 fOSC = 1176kHz fIN = 1kHz 0 -90 -100 20 0.1 1 10 100 FREQUENCY (MHz) WIDEBAND OUTPUT SPECTRUM MAX9877A toc32 WIDEBAND OUTPUT SPECTRUM -10 -20 AMPLITUDE (dBV) -30 -40 -50 -60 -70 -80 -90 -100 fOSC = 1176kHz INPUTS AC-COUPLED TO GND MAX9877A toc33 0 -10 -20 AMPLITUDE (dBV) -30 -40 -50 -60 -70 -80 -90 -100 fOSC = 700kHz INPUTS AC-COUPLED TO GND 0 0.1 1 10 100 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) HARDWARE SHUTDOWN RESPONSE MAX9877A toc34 SOFTWARE SHUTDOWN ON- AND OFF-RESPONSE MAX9877A toc35 VBIAS 500mV/div VSDA 2V/div OUT+ - OUT1V/div OUT+ - OUT1V/div 20ms/div 20ms/div ______________________________________________________________________________________ 11 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP Typical Operating Characteristics (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) HEADPHONE AMPLIFIER TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX9877A toc36 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX9877A toc37 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY VDD = PVDD = 3V RHP = 32Ω MAX9877A toc38 0 VDD = PVDD = 3.7V RHP = 32Ω 1 1 VDD = PVDD = 3.7V RHP = 16Ω THD+N (%) THD+N (%) POUT = 20mW 0.01 THD+N (%) 0.1 0.1 0.1 POUT = 10mW 0.01 POUT = 10mW 0.01 0.001 10 100 POUT = 20mW 1k FREQUENCY (Hz) 10k 100k 0.001 10 100 1k POUT = 40mW 10k 100k POUT = 20mW 0.001 10 100 1k FREQUENCY (Hz) 10k 100k FREQUENCY (Hz) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX9877A toc39 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER MAX9877A toc40 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER VDD = PVDD = 3.7V RHP = 16Ω MAX9877A toc41 1 VDD = PVDD = 3V RHP = 16Ω 10 VDD = PVDD = 3.7V RHP = 32Ω 10 1 0.1 THD+N (%) THD+N (%) THD+N (%) fIN = 20Hz 0.1 1 fIN = 20Hz AND 1kHz 0.1 POUT = 15mW 0.01 0.01 POUT = 30mW 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0.001 0 10 20 30 40 OUTPUT POWER (mW) fIN = 1kHz fIN = 6kHz 0.01 fIN = 6kHz 0.001 0 10 20 30 40 50 60 70 OUTPUT POWER (mW) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER MAX9877A toc42 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER VDD = PVDD = 3V RHP = 16Ω MAX9877A toc43 10 VDD = PVDD = 3V RHP = 32Ω 10 1 THD+N (%) THD+N (%) fIN = 20Hz 0.1 1 fIN = 20Hz AND 1kHz 0.1 0.01 fIN = 1kHz 0.001 0 10 20 30 40 OUTPUT POWER (mW) fIN = 6kHz 0.01 fIN = 6kHz 0.001 0 10 20 30 40 50 60 OUTPUT POWER (mW) 12 ______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP Typical Operating Characteristics (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) POWER DISSIPATION vs. OUTPUT POWER MAX9877A toc44 POWER DISSIPATION vs. OUTPUT POWER MAX9877A toc45 OUTPUT POWER vs. SUPPLY VOLTAGE 45 40 OUTPUT POWER (mW) 35 30 25 20 15 10 5 0 150 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1% THD+N 10% THD+N fIN = 1kHz RHP = 32Ω MAX9877A toc46 350 300 POWER DISSIPATION (mW) 250 RHP = 16Ω 200 150 100 50 0 0 50 100 RHP = 32Ω VDD = PVDD = 3.7V fIN = 1kHz POUT = PHPL + PHPR 250 50 POWER DISSIPATION (mW) 200 RHP = 16Ω 150 100 VDD = PVDD = 3V fIN = 1kHz POUT = PHPL + PHPR 100 50 RHP = 32Ω 0 150 0 50 OUTPUT POWER (mW) OUTPUT POWER (mW) SUPPLY VOLTAGE (V) OUTPUT POWER vs. SUPPLY VOLTAGE MAX9877A toc47 OUTPUT POWER vs. LOAD RESISTANCE MAX9877A toc48 OUTPUT POWER vs. LOAD RESISTANCE 90 80 OUTPUT POWER (mW) 70 60 50 40 30 20 10% THD+N VDD = PVDD = 3V fIN = 1kHz MAX9877A toc49 100 90 80 OUTPUT POWER (mW) 70 60 50 40 30 20 10 0 2.5 3.0 3.5 4.0 4.5 5.0 1% THD+N 10% THD+N fIN = 1kHz RHP = 16Ω 100 90 80 OUTPUT POWER (mW) 70 60 50 40 30 20 10 0 1% THD+N 10 20 30 40 50 60 70 80 10% THD+N VDD = PVDD = 3.7V fIN = 1kHz 100 10 0 90 100 10 1% THD+N 20 30 40 50 60 70 80 90 100 5.5 SUPPLY VOLTAGE (V) LOAD RESISTANCE (Ω) LOAD RESISTANCE (Ω) OUTPUT POWER vs. LOAD RESISTANCE MAX9877A toc50 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY VDD = PVDD = 3.7V VRIPPLE = 100mVP-P RHP = 32Ω INPUTS AC-COUPLED TO GND MAX9877A toc51 100 90 80 OUTPUT POWER (mW) 70 60 50 40 30 20 10 0 10 20 30 40 50 60 70 80 C1 = C2 = 0.47µF C1 = C2 = 2.2µF VDD = PVDD = 3V OSC = 10 fIN = 1kHz 1% THD+N 0 -10 -20 -30 -40 PSRR (dB) -50 -60 -70 -80 -90 -100 -110 -120 HPL 10 100 HPR 90 100 1k FREQUENCY (Hz) 10k 100k LOAD RESISTANCE (Ω) ______________________________________________________________________________________ 13 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP Typical Operating Characteristics (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) OUTPUT SPECTRUM MAX9877A toc52 OUTPUT SPECTRUM VDD = PVDD = 3.7V fIN = 1kHz RHP = 16Ω MAX9877A toc53 0 -20 AMPLITUDE (dBV) -40 -60 -80 -100 -120 -140 0 5 10 FREQUENCY (kHz) 15 VDD = PVDD = 3.7V fIN = 1kHz RHP = 32Ω 0 -20 AMPLITUDE (dBV) -40 -60 -80 -100 -120 -140 20 0 5 10 FREQUENCY (kHz) 15 20 CROSSTALK vs. FREQUENCY MAX9877A toc54 COMMON-MODE REJECTION RATIO vs. FREQUENCY 70 +9dB 60 CMRR (dB) 50 40 30 20 +20dB 0dB MAX9877A toc55 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 10 100 HPL TO HPR VDD = PVDD = 3.7V VINA_ = 1VP-P RHP = 16Ω 80 CROSSTALK (dB) HPR TO HPL 10 0 1k FREQUENCY (Hz) 10k 100k 10 100 VDD = PVDD = 3.7V CMRR = 20log(ADM/ACM) 1k FREQUENCY (Hz) 10k 100k HARDWARE SHUTDOWN RESPONSE MAX9877A toc56 SOFTWARE SHUTDOWN ON- AND OFF-REPSONSE MAX9877A toc57 VBIAS 500mV/div VBIAS 500mV/div HPL 500mV/div HPL 500mV/div HPR 500mV/div HPR 500mV/div 20ms/div 20ms/div 14 ______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP Typical Operating Characteristics (continued) (VDD = PVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, volume controls = 0dB, OSC = 00, BYPASS = 0, SHDN = 1. Speaker loads (ZSPK) connected between OUT+ and OUT-. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞. C1 = C2 = CBIAS = 1µF. TA = +25°C, unless otherwise noted.) ANALOG SWITCH TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER MAX9877A toc58 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER MAX9877A toc59 10 EXTERNAL CLASS AB AMPLIFIER CONNECTED DIRECTLY TO RXIN+ AND RXIN1 THD+N (%) f = 1kHz 10 1 THD+N (%) f = 20Hz AND 1kHz 0.1 0.1 f = 20Hz f = 6kHz 0.01 f = 6kHz EXTERNAL CLASS AB AMPLIFIER CONNECTED WITH 9Ω RESISTORS IN SERIES WITH RXIN+ AND RXIN- 0.01 0 25 50 75 100 OUTPUT POWER (mW) 0.001 0 10 20 30 40 50 60 70 80 OUTPUT POWER (mW) ______________________________________________________________________________________ 15 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP Pin Description PIN A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 C2 C3 C4 C5 D1 D2 D3 D4 D5 NAME HPR HPL VSS C1N C1P VDD BIAS SDA RXIN+ OUT+ INB2 INB1 SCL PGND PVDD INA2 INA1 GND RXINOUTRight Headphone Output Left Headphone Output Headphone Amplifier Negative Power Supply. Bypass with a 1µF capacitor to PGND. Charge-Pump Flying Capacitor Negative Terminal. Connect a 1µF capacitor between C1P and C1N. Charge-Pump Flying Capacitor Positive Terminal. Connect a 1µF capacitor between C1P and C1N. Analog Supply. Connect to PVDD. Bypass with a 1µF capacitor to GND. Common-Mode Bias. Bypass to GND with a 1µF capacitor. Pulse low to reset the part and place in shutdown (see the Typical Application Circuit). Serial-Data Input. Connect a pullup resistor from SDA to a 1.7V to 3.6V supply. Receiver Bypass Positive Input Positive Speaker Output Input B2. Right input or positive input (see the Differential Input Configuration (∆IN_) section). Input B1. Left input or negative input (see the Differential Input Configuration (∆IN_) section). Serial-Clock Input. Connect a pullup resistor from SCL to a 1.7V to 3.6V supply. Power Ground Class D and Charge-Pump Power Supply. Bypass with a 1µF capacitor to PGND. Input A2. Right input or positive input (see the Differential Input Configuration (∆IN_) section). Input A1. Left input or negative input (see the Differential Input Configuration (∆IN_) section). Analog Ground Receiver Bypass Negative Input Negative Speaker Output FUNCTION Detailed Description Signal Path The MAX9877A signal path consists of flexible inputs, signal mixing, volume control, and output amplifiers (Figure 1). The inputs can be configured for single-ended or differential signals (Figure 2). The internal preamplifiers feature three programmable gain settings of 0dB, +9dB, and +20dB. Following preamplification, the input signals are mixed, volume adjusted, and routed to the headphone and speaker amplifiers based on the output mode configuration (see Table 7). The volume control stages provide up to 75dB attenuation. The headphone amplifier is configured as a unity-gain buffer while the speaker amplifier provides +12dB of additional gain. When an input is configured as mono differential it can be routed to the speaker or to both headphones. When an input is stereo, it is mixed to mono without attenuation for the speaker and kept stereo for the headphones. When the application does not require the use of both INA_ and INB_, the SNR of the MAX9877A is improved by deselecting the unused input through the I2C output mode register and AC-coupling the unused inputs to ground with a 330pF capacitor. The 330pF capacitor and the input resistance to the MAX9877A form a highpass filter preventing audible noise from coupling into the outputs. 16 ______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP 0dB INA2 INA1 INPUT A 0dB/+9dB/+20dB MIXER AND MUX INPUT B 0dB/+9dB/+20dB -75dB TO 0dB OUT+ +12dB OUT-75dB TO 0dB -75dB TO 0dB HPR 0dB HPL INB2 INB1 Figure 1. Signal Path STEREO SINGLE-ENDED IN_2 (R) R TO MIXER IN_1 (L) L DIFFERENTIAL IN_2 (+) IN_1 (-) TO MIXER Figure 2. Differential and Stereo Single-Ended Input Configurations ______________________________________________________________________________________ 17 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP Volume Control and Mute The MAX9877A features three volume control registers (see Table 4) allowing independent volume control of mono speaker and stereo headphone amplifier outputs. Each volume control register has 31 steps providing 0 to 75dB (typ) of attenuation and a mute function. active emissions limiting circuitry actively limits the dV/dt of the rising and falling edge transitions, providing reduced EMI emissions, while maintaining up to 87% efficiency. In addition to active emission limiting, the MAX9877A features a patented spread-spectrum modulation mode that flattens the wideband spectral components. Proprietary techniques ensure that the cycle-to-cycle variation of the switching period does not degrade audio reproduction or efficiency (see the T ypical Operating Characteristics). Select spread-spectrum modulation mode through the I2C interface (Table 6). In spread-spectrum modulation mode, the switching frequency varies randomly by ±60kHz around the center frequency (1.176MHz). The effect is to reduce the peak energy at harmonics of the switching frequency. Above 10MHz, the wideband spectrum looks like white noise for EMI purposes (see Figure 4). Class D Speaker Amplifier The MAX9877A integrates a filterless Class D amplifier that offers much higher efficiency than Class AB without the typical disadvantages. The high efficiency of a Class D amplifier is due to the switching operation of the output stage transistors. In a Class D amplifier, the output transistors act as currentsteering switches and consume negligible additional power. Any power loss associated with the Class D output stage is mostly due to the I2R loss of the MOSFET on-resistance, and quiescent current overhead. The theoretical best efficiency of a linear amplifier is 78%, however, that efficiency is only exhibited at peak output power. Under normal operating levels (typical music reproduction levels), efficiency falls below 30%, whereas the MAX9877A still exhibits 70% efficiency under the same conditions (Figure 3). Ultra-Low EMI Filterless Output Stage In traditional Class D amplifiers, the high dV/dt of the rising and falling edge transitions results in increased EMI emissions, which requires the use of external LC filters or shielding to meet EN55022 electromagneticinterference (EMI) regulation standards. Limiting the dV/dt normally results in decreased efficiency. Maxim’s Speaker Current Limit Most applications will not enter current limit unless the output is short circuited or connected incorrectly. When the output current of the speaker amplifier exceeds the current limit (1.5A, typ) the MAX9877A disables the outputs for approximately 250µs. At the end of 250µs, the outputs are re-enabled, if the fault condition still exists, the MAX9877A will continue to disable and reenable the outputs until the fault condition is removed. Bypass Mode The integrated DPST analog audio switch allows the MAX9877A’s Class D amplifier to be bypassed. In bypass mode, the Class D amplifier is automatically disabled allowing an external amplifier to drive the speaker connected between OUT+ and OUT- through RXIN+ and RXIN- (see the Typical Application Circuit). The bypass switch is enabled at startup. The switch can be opened or closed even when the MAX9877A is in software shutdown (see the I2C Register Description section). Unlike discrete solutions, the switch design reduces coupling of Class D switching noise to the RXIN_ inputs. This eliminates the need for a costly T-switch. The bypass switch is typically used with two 9.1Ω resistors connected to each input. These resistors, in combination with the switch on-resistance and an 8Ω load, approximate the 32Ω load expected by the external amplifier. Although not required, using the resistors optimizes THD+N. Drive RXIN+ and RXIN- with a low-impedance source to minimize noise on the pins. In applications that do not require the bypass mode, leave RXIN+ and RXINunconnected. MAX9877A EFFICIENCY vs. IDEAL CLASS EFFICIENCY 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 0.25 0.50 0.75 1.00 OUTPUT POWER (W) VDD = PVDD = 3.7V (MAX9877A) VSUPPLY = 3.7V (IDEAL CLASS AB) IDEAL CLASS AB MAX9877A MAX9877A fig03 100 Figure 3. MAX9877A Efficiency vs. Class AB Efficiency 18 ______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP 40 TEST LIMIT 35 AMPLITUDE (dBµV/m) 30 25 20 MAX9877A OUTPUT 15 10 5 30 60 80 100 120 140 160 180 200 220 240 260 280 300 FREQUENCY (MHz) TEST LIMIT 40 AMPLITUDE (dBµV/m) 35 25 MAX9877A OUTPUT 20 15 10 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 FREQUENCY (MHz) Figure 4. EMI with 152mm of Speaker Cable DirectDrive Headphone Amplifier Traditional single-supply headphone amplifiers have outputs biased at a nominal DC voltage (typically half the supply). Large coupling capacitors are needed to block this DC bias from the headphone. Without these capacitors, a significant amount of DC current flows to the headphone, resulting in unnecessary power dissipation and possible damage to both the headphone and headphone amplifier. Maxim’s patented DirectDrive architecture uses a charge pump to create an internal negative supply voltage. This allows the headphone outputs of the MAX9877A to be biased at GND while operating from a single supply (Figure 5). Without a DC component, there is no need for the large DC-blocking capacitors. Instead of two large (220µF, typ) capacitors, the MAX9877A charge pump requires two small ceramic capacitors, conserving board space, reducing cost, and improving the frequency response of the headphone amplifier. See the Output Power vs. Load Resistance graph in the Typical Operating Characteristics for details of the possible capacitor sizes. There is a low DC voltage on the amplifier outputs due to amplifier offset. However, the offset of the MAX9877A is typically ±0.15mV, which, when combined with a 32Ω load, results in less than 10µA of DC current flow to the headphones. In addition to the cost and size disadvantages of the DC-blocking capacitors required by conventional headphone amplifiers, these capacitors limit the amplifier’s low-frequency response and can distort the audio signal. Previous attempts at eliminating the output-coupling capacitors involved biasing the headphone return (sleeve) to the DC bias voltage of the headphone amplifiers. This method raises some issues: ______________________________________________________________________________________ 19 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP 1) The sleeve is typically grounded to the chassis. Using the midrail biasing approach, the sleeve must be isolated from system ground, complicating product design. 2) During an ESD strike, the amplifier’s ESD structures are the only path to system ground. Thus, the amplifier must be able to withstand the full energy from an ESD strike. 3) When using the headphone jack as a line out to other equipment, the bias voltage on the sleeve may conflict with the ground potential from other equipment, resulting in possible damage to the amplifiers. The MAX9877A features a low-noise charge pump. The switching frequency of the charge pump is 1/2 of the Class D switching frequency, regardless of the operating mode. When the Class D amplifiers are operated in spread-spectrum mode, the charge pump also switches with a spread-spectrum pattern. The nominal switching frequency is well beyond the audio range, and thus does not interfere with audio signals. The switch drivers feature a controlled switching speed that minimizes noise generated by turn-on and turn-off transients. By limiting the switching speed of the charge pump, the di/dt noise VDD caused by the parasitic trace inductance is minimized. Although not typically required, additional high-frequency noise attenuation can be achieved by increasing the size of C2 (see the Typical Application Circuit). The charge pump is active only in headphone modes. Headphone Current Limit The headphone amplifier current is limited to 140mA (typ). The current limit clamps the output current, which appears as clipping when the maximum current is exceeded. Shutdown Mode The MAX9877A features two ways of entering low-power shutdown. The hardware shutdown function is controlled by pulsing BIAS low for 1ms. While BIAS is low the amplifiers are shut down. Following an 80ms reset period, the MAX9877A reverts to its power-on-reset condition. Pull BIAS low using an open-drain output that is not pulled up with a resistor (see the Typical Application Circuit). The open-drain output leakage must not exceed 100nA and must be able to sink at least 1mA. The device can also be placed in shutdown mode by writing to the SHDN bit in the Output Control Register. Click-and-Pop Suppression The MAX9877A features click-and-pop suppression that eliminates audible transients from occurring at startup and shutdown. Use the following procedure to start up the MAX9877A: 1) Configure the desired output mode and preamplifier gain. 2) Set the SHDN bit to 1 to start up the amplifier. 3) Wait 10ms for the startup time to pass. 4) Increase the output volume to the desired level. To disable the device simply set SHDN to 0. During the startup period, the MAX9877A precharges the input capacitors to prevent clicks and pops. If the output amplifiers have been programmed to be active they are held in shutdown until the precharge period is complete. When power is initially applied to the MAX9877A, the power-on-reset state of all three volume control registers is mute. For most applications, the volume can be set to the desired level once the device is active. If the clickand-pop is too high, step through intermediate volume settings with zero-crossing detection disabled. Stepping through higher volume settings has a greater impact on click-and-pop than lower volume settings. For the lowest possible click-and-pop, start up the device at minimum volume and then step through each volume setting until the desired setting is reached. Disable zerocrossing detection if no input signal is expected. VDD/2 GND CONVENTIONAL AMPLIFIER BIASING SCHEME +VDD GND DirectDrive AMPLIFIER BIASING SCHEME -VDD (VSS) Figure 5. Traditional Amplifier Output vs. MAX9877A DirectDrive Output 20 ______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier I2C Interface The MAX9877A is controlled through five I2C programmable registers. Table 1 shows the MAX9877A’s complete register map. Tables 2, 3, and 5 show the individual registers. MAX9877AERP I2C Address The slave address of the MAX9877A is 1001101R/(W). Table 1. Register Map REGISTER Input Mode Control Speaker Volume Control Left Headphone Volume Control Right Headphone Volume Control Output Mode Control REGISTER ADDRESS 0x00 POR STATE 0x40 B7 0 B6 ZCD B5 ∆INA B4 ∆INB B3 B2 B1 B0 PGAINA PGAINB 0x01 0x00 0 0 0 SVOL (Table 4) 0x02 0x00 0 0 0 HPLVOL (Table 4) 0x03 0x00 0 0 0 HPRVOL (Table 4) 0x04 0x49 SHDN BYPASS OSC (Table 6) OUTMODE (Table 7) Table 2. Input Mode Control REGISTER 0x00 B7 0 B6 ZCD B5 ∆INA B4 ∆INB B3 PGAINA B2 B1 PGAINB B0 I2C Register Description Zero-Crossing Detection (ZCD) Zero-crossing detection limits distortion in the output signal during volume transitions by delaying the transition until the mixer output crosses the internal bias voltage. A timeout period (typically 60ms) forces the volume transition if the mixer output signal does not cross the bias voltage. 1 = Zero-crossing detection is enabled. 0 = Zero-crossing detection is disabled. 1 = IN_ is configured as a mono differential input with IN_2 as the positive and IN_1 as the negative input. 0 = IN_ is configured as a stereo single-ended input with IN_2 as the right and IN_1 as the left input. Differential Input Configuration (∆IN_) The inputs INA_ and INB_ can be configured for mono differential or stereo single-ended operation. Preamplifier Gain (PGAIN_) The preamplifier gain of INA_ and INB_ can be programmed by writing to PGAIN_. 00 = 0dB 01 = +9dB 10 = +20dB 11 = Reserved ______________________________________________________________________________________ 21 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP Table 3. Speaker/Left Headphone/Right Headphone Volume Control REGISTER 0x01 0x02 0x03 B7 0 0 0 B6 0 0 0 B5 0 0 0 B4 B3 B2 B1 B0 SVOL (Table 4) HPLVOL (Table 4) HPRVOL (Table 4) Volume Control The device has a separate volume control for left headphone, right headphone, and speaker amplifiers. The total system gain is a combination of the input gain, the volume control, and the output amplifier gain. Table 4 shows the volume settings for each volume control. Table 4. Volume Control Settings CODE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 _VOL B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GAIN (dB) MUTE -75 -71 -67 -63 -59 -55 -51 -47 -44 -41 -38 -35 -32 -29 -26 CODE 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 _VOL B4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GAIN (dB) -23 -21 -19 -17 -15 -13 -11 -9 -7 -6 -5 -4 -3 -2 -1 0 Table 5. Output Mode Control REGISTER 0x04 B7 SHDN B6 BYPASS B5 B4 B3 B2 B1 B0 OSC (Table 6 ) OUTMODE (Table 7) Shutdown (SHDN) 1 = MAX9877A operational. 0 = MAX9877A in low-power shutdown mode. SHDN is an active-low shutdown bit that overrides all settings and places the entire device in low-power shutdown mode. The I2C interface is fully active in this shutdown mode and bypass mode remains operational. All register settings are preserved while in shutdown. 22 ______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier Bypass Mode (BYPASS) 1 = MAX9877A bypass switches are closed and the Class D amplifier is disabled. 0 = Bypass mode disabled. This mode does not control headphone operation. Output Configuration (OUTMODE) The MAX9877A has a stereo DirectDrive headphone amplifier and a mono Class D amplifier. Table 7 shows how each of the output amplifiers can be configured and connected to the input signals. For simplicity, not all possible combinations of ∆INA and ∆INB are shown. MAX9877AERP Table 6. Oscillator Modes OSC B1 0 0 1 1 B0 0 1 0 1 CLASS D OSCILLATOR MODE (kHz) 1176, spread spectrum 1100, fixed frequency 700, fixed frequency Reserved CHARGE-PUMP OSCILLATOR MODE (kHz) 588, spread spectrum 550, fixed frequency 350, fixed frequency Table 7. Output Modes OUTMODE ∆IN_ = 0 (THE SINGLE-ENDED INPUT SIGNALS ARE DEFINED AS IN_1 = LEFT AND IN_2 = RIGHT) B0 0 1 0 1 0 1 0 1 0 1 INA1+INA2 — INA1+INA2 INB1+INB2 — INB1+INB2 INA1+INA2 +INB1+INB2 — INA1+INA2 +INB1+INB2 SPK LEFT HP Reserved — INA1 INA1 — INB1 INB1 — INA1+INB1 INA1+INB1 Reserved — INA2 INA2 — INB2 INB2 — INA2+INB2 INA2+INB2 INA∆ — INA∆ INB∆ — INB∆ INA∆+INB∆ — INA∆+INB∆ RIGHT HP ∆IN_ = 1 (THE DIFFERENTIAL INPUT SIGNAL IS DEFINED AS IN_∆ = IN_2 - IN_1) SPK LEFT HP Reserved — INA∆ INA∆ — INB∆ INB∆ — INA∆ +INB∆ INA∆ +INB_ Reserved — INA∆ INA∆ — INB∆ INB∆ — INA∆ +INB∆ INA∆ +INB∆ RIGHT HP MODE B3 0 1 2 3 4 5 6 7 8 9 10–15 0 0 0 0 0 0 0 0 1 1 B2 0 0 0 0 1 1 1 1 0 0 B1 0 0 1 1 0 0 1 1 0 0 — = Amplifier Off ______________________________________________________________________________________ 23 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier I2C Interface Specification The MAX9877A features an I2C/SMBus™-compatible, 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX9877A and the master at clock rates up to 400kHz. Figure 6 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. The master device writes data to the MAX9877A by transmitting the proper slave address followed by the register address and then the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted to the MAX9877A is 8 bits long and is followed by an acknowledge clock pulse. A master reading data from the MAX9877A transmits the proper slave address followed by a series of nine SCL pulses. The MAX9877A transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START (S) or REPEATED START (Sr) condition, a not acknowledge, and a STOP (P) condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500 Ω, is required on SDA. SCL operates only as an input. A pullup resistor, MAX9877AERP typically greater than 500Ω, is required on SCL if there are multiple masters on the bus, or if the single master has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9877A from high voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the S TART and STOP Conditions section). START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 7). A START condition from the master signals the beginning of a transmission to the MAX9877A. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. SDA tSU:DAT tLOW SCL tHD:STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD:DAT tSU:STA tBUF tSU:STA tSU:STO Figure 6. 2-Wire Interface Timing Diagram S Sr P SCL SDA Figure 7. START, STOP, and REPEATED START Conditions SMBus is a trademark of Intel Corp. 24 ______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier Early STOP Conditions The MAX9877A recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. Slave Address The MAX9877A is preprogrammed with a slave address of 1001101R/(W). The address is defined as the seven most significant bits (MSBs) followed by the Read/Write bit. Setting the Read/Write bit to 1 configures the MAX9877A for read mode. Setting the Read/Write bit to 0 configures the MAX9877A for write mode. The address is the first byte of information sent to the MAX9877A after the START condition. Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX9877A uses to handshake receipt each byte of data when in write mode (see Figure 8). The MAX9877A pulls down SDA during the entire mastergenerated 9th clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master may retry communication. The master pulls down SDA during the ninth clock cycle to acknowledge receipt of data when the MAX9877A is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the MAX9877A, followed by a STOP condition. MAX9877AERP Write Data Format A write to the MAX9877A includes transmission of a START condition, the slave address with the R/W bit set to 0, one byte of data to configure the internal register address pointer, one or more bytes of data, and a STOP condition. Figure 9 illustrates the proper frame format for writing one byte of data to the MAX9877A. Figure 10 illustrates the frame format for writing n-bytes of data to the MAX9877A. The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX9877A. The MAX9877A acknowledges receipt of the address byte during the master-generated 9th SCL pulse. START CONDITION SCL 1 2 CLOCK PULSE FOR ACKNOWLEDGMENT 8 NOT ACKNOWLEDGE 9 SDA ACKNOWLEDGE Figure 8. Acknowledge ACKNOWLEDGE FROM MAX9877A B7 ACKNOWLEDGE FROM MAX9877A S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9877A REGISTER ADDRESS A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P B6 B5 B4 B3 B2 B1 B0 Figure 9. Writing One Byte of Data to the MAX9877A ______________________________________________________________________________________ 25 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier The second byte transmitted from the master configures the MAX9877A’s internal register address pointer. The pointer tells the MAX9877A where to write the next byte of data. An acknowledge pulse is sent by the MAX9877A upon receipt of the address pointer data. The third byte sent to the MAX9877A contains the data that will be written to the chosen register. An acknowledge pulse from the MAX9877A signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential registers within one continuous frame. Figure 10 illustrates how to write to multiple registers with one frame. The master signals the end of transmission by issuing a STOP condition. Register addresses greater than 0x04 are reserved. Do not write to these addresses. contents of register 0x00. Transmitted data is valid on the rising edge of SCL. The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read will be from register 0x00. The address pointer can be preset to a specific register before a read command is issued. The master presets the address pointer by first sending the MAX9877A‘s slave address with the R/W bit set to 0 followed by the register address. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The MAX9877A then transmits the contents of the specified register. The address pointer autoincrements after transmitting the first byte. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figure 11 illustrates the frame format for reading one byte from the MAX9877A. Figure 12 illustrates the frame format for reading multiple bytes from the MAX9877A. MAX9877AERP Read Data Format Send the slave address with the R/W bit set to 1 to initiate a read operation. The MAX9877A acknowledges receipt of its slave address by pulling SDA low during the 9th SCL clock pulse. A START command followed by a read command resets the address pointer to register 0x00. The first byte transmitted from the MAX9877A will be the ACKNOWLEDGE FROM MAX9877A ACKNOWLEDGE FROM MAX9877A S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9877A REGISTER ADDRESS A B7 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX9877A B7 B6 B5 B4 B3 B2 B1 B0 DATA BYTE 1 1 BYTE A DATA BYTE n 1 BYTE A P AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 10. Writing n-Bytes of Data to the MAX9877A NOT ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MAX9877A S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9877A REGISTER ADDRESS A ACKNOWLEDGE FROM MAX9877A Sr SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTO-INCREMENT INTERNAL REGISTER ADDRESS POINTER A P REPEATED START Figure 11. Reading One Indexed Byte of Data from the MAX9877A 26 ______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP ACKNOWLEDGE FROM MAX9877A S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9877A REGISTER ADDRESS A ACKNOWLEDGE FROM MAX9877A Sr SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P REPEATED START Figure 12. Reading n-Bytes of Indexed Data from the MAX9877A Applications Information Filterless Class D Operation Traditional Class D amplifiers require an output filter to recover the audio signal from the amplifier’s output. The filters add cost, increase the solution size of the amplifier, and can decrease efficiency and THD+N performance. The traditional PWM scheme uses large differential output swings (2 x VDD(P-P)) and causes large ripple currents. Any parasitic resistance in the filter components results in a loss of power, lowering the efficiency. The MAX9877A does not require an output filter. The device relies on the inherent inductance of the speaker coil and the natural filtering of both the speaker and the human ear to recover the audio component of the square-wave output. Eliminating the output filter results in a smaller, less costly, more efficient solution. Because the frequency of the MAX9877A output is well beyond the bandwidth of most speakers, voice coil movement due to the square-wave frequency is very small. Although this movement is small, a speaker not designed to handle the additional power can be damaged. For optimum results, use a speaker with a series inductance > 10µH. Typical 8Ω speakers exhibit series inductances in the 20µH to 100µH range. MAX9877A OUTOUT+ Figure 13. Optional Ferrite Bead Filter AC-coupling capacitor allows the amplifier to automatically bias the signal to an optimum DC level. Assuming zero source impedance, the -3dB point of the highpass filter is given by: f−3dB = 1 2πRINCIN Choose CIN so that f-3dB is well below the lowest frequency of interest. Use capacitors whose dielectrics have low-voltage coefficients, such as tantalum or aluminum electrolytic. Capacitors with high-voltage coefficients, such as ceramics, may result in increased distortion at low frequencies. Component Selection Optional Ferrite Bead Filter In applications where speaker leads exceed 20mm, additional EMI suppression can be achieved by using a filter constructed from a ferrite bead and a capacitor to ground. A ferrite bead with low DC resistance, highfrequency (> 1.176MHz) impedance of 100Ω to 600Ω, and rated for at least 1A should be used. The capacitor value varies based on the ferrite bead chosen and the actual speaker lead length. Select the capacitor value based on EMI performance. Input Capacitor An input capacitor, CIN, in conjunction with the input impedance of the MAX9877A forms a highpass filter that removes the DC bias from an incoming signal. The BIAS Capacitor BIAS is the output of the internally generated DC bias voltage. The BIAS bypass capacitor, CBIAS, reduces power supply and other noise sources at the common-mode bias node. Bypass BIAS with a 1µF capacitor to GND. Charge-Pump Capacitor Selection Use capacitors with an ESR less than 100mΩ for optimum performance. Low-ESR ceramic capacitors minimize the output resistance of the charge pump. Most surfacemount ceramic capacitors satisfy the ESR requirement. For best performance over the extended temperature range, select capacitors with an X7R dielectric. Flying Capacitor (C1) The value of the flying capacitor (C1) affects the output resistance of the charge pump. A C1 value that is too small degrades the device’s ability to provide sufficient current drive, which leads to a loss of output voltage. 27 ______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP Increasing the value of C1 reduces the charge-pump output resistance to an extent. Above 1µF, the on-resistance of the switches and the ESR of C1 and C2 dominate. Output Holding Capacitor (C2) The output capacitor value and ESR directly affect the ripple at VSS. Increasing the value of C2 reduces output ripple. Likewise, decreasing the ESR of C2 reduces both ripple and output resistance. Lower capacitance values can be used in systems with low maximum output power levels. See the Output Power vs. Load Resistance graph in the Typical Operating Characteristics. PVDD Bulk Capacitor (C3) In addition to the recommended PVDD bypass capacitance, bulk capacitance equal to C3 should be used. Place the bulk capacitor as close to the device as possible. -10 -30 EFFICIENCY (dBµ) -50 -70 -90 -110 -130 -150 10 100 1k FREQUENCY (Hz) 10k 100k NOISE FLOOR MAX9877A THRESHOLD OF HEARING RF SUSCEPTIBILITY MAX9877A fig14 Supply Bypassing, Layout, and Grounding Proper layout and grounding are essential for optimum performance. Use wide traces for the power-supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Wide traces also aid in moving heat away from the package. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any switching noise from coupling into the audio signal. Connect PGND and GND together at a single point on the PCB. Route all traces that carry switching transients away from GND and the traces/components in the audio signal path. Connect PVDD to a 2.7V to 5.25V source. Bypass PVDD to the PGND pin with a 1µF ceramic capacitor. Additional bulk capacitance should be used to prevent power-supply pumping. Place the bypass capacitors as close to the MAX9877A as possible. Connect VDD to PVDD. Bypass VDD to GND with a 1µF capacitor. Place the bypass capacitors as close to the MAX9877A as possible. Figure 14. MAX9877A Susceptibility to a GSM Cell Phone Radio ceptibility to RF noise and prevent RF signals from being demodulated into audible noise. Trace lengths should be kept below 1/4 the wavelength of the RF frequency of interest. Minimizing the trace lengths prevents them from functioning as antennas and coupling RF signals into the MAX9877A. The wavelength λ in meters is given by: where c = 3 x interest. Route audio signals on middle layers of the PCB to allow ground planes above and below shield them from RF interference. Ideally the top and bottom layers of the PCB should primarily be ground planes to create effective shielding. Additional RF immunity can also be obtained from relying on the self-resonant frequency of capacitors as it exhibits the frequency response similar to a notch filter. Depending on the manufacturer, 10pF to 20pF capacitors typically exhibit self resonance at RF frequencies. These capacitors, when placed at the input pins, can effectively shunt the RF noise at the inputs of the MAX9877A. For these capacitors to be effective, they must have a low-impedance, low-inductance path to the ground plane. Do not use microvias to connect to the ground plane as these vias do not conduct well at RF frequencies. 108 λ = c/f m/s, and f = the RF frequency of RF Susceptibility GSM radios transmit using time-division multiple access (TDMA) with 217Hz intervals. The result is an RF signal with strong amplitude modulation at 217Hz that is easily demodulated by audio amplifiers. Figure 14 shows the susceptibility of the MAX9877A to a transmitting GSM radio placed in close proximity. Although there is measurable noise at 217Hz and its harmonics, the noise is well below the threshold of hearing using typical headphones. In RF applications, improvements to both layout and component selection decreases the MAX9877A’s sus- 28 ______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MaxFilm Applications Information For the latest application details on MaxFilm construction, dimensions, tape carrier information, PCB techniques, bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability testing results, refer to the Application Note: UCSP—A Wafer-Level Chip-Scale Package on Maxim’s website at www.maxim-ic.com/ucsp. See Figure 15 for the recommended PCB footprint for the MAX9877A. MAX9877AERP 45±5µm 250µm Figure 15. PCB Footprint Recommendation Diagram ______________________________________________________________________________________ 29 Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier MAX9877AERP Typical Application Circuit VBATT VBATT C2 1µ F VSS A3 C1N A4 C1 1µ F C1P A5 1µ F INPUT A 1µ F 1µ F INPUT B 1µ F OPEN-DRAIN GPIO BIAS 1µ F B3 C3 B2 INB1 C2 INA1 D2 CHARGE PUMP VDD B1 1µ F C3 1µ F PVDD C5 MAX9877A -75dB TO 0dB 0dB A1 HPR INA2 D1 INPUT A 0dB/+9dB/+20dB MIXER AND MUX INPUT B 0dB/+9dB/+20dB -75dB TO 0dB -75dB TO 0dB 0dB A2 HPL INB2 C1 CLASS D MODULATOR +12dB B5 D5 OUT+ OUT- SDA SCL I2C CONTROL BYPASS 9.1Ω RxIN+ B4 BASEBAND RECEIVER AMPLIFIER 9.1Ω RxIN- D4 D3 C4 GND PGND Chip Information PROCESS: BiCMOS 30 ______________________________________________________________________________________ Low RF Susceptibility, Mono Audio Subsystem with DirectDrive Headphone Amplifier Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. MAX9877AERP PACKAGE TYPE 20 MaxFilm PACKAGE CODE R202A2+1 DOCUMENT NO. 21-0229 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. ARRAY UCSP.EPS