MAX9967AGCCQ

19-3195; Rev 1; 2/05 Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load General Description The MAX9967 dual, low-power, high-speed, pin electronics driver/comparator/load (DCL) IC includes, for each channel, a three-level pin driver, a dual comparator, variable clamps, and an active load. The driver features a wide voltage range and high-speed operation, includes high-impedance and active-termination (3rd-level drive) modes, and is highly linear even at low-voltage swings. The dual comparator provides low dispersion (timing variation) over a wide variety of input conditions. The clamps provide damping of high-speed device-undertest (DUT) waveforms when the device is configured as a high-impedance receiver. The programmable load supplies up to 35mA of source and sink current. The load facilitates contact/continuity testing, at-speed parametric testing of IOH and IOL, and pullup of high-output-impedance devices. The MAX9967A provides tight matching of gain and offset for the drivers, and offset for the comparators and active load, allowing reference levels to be shared across multiple channels in cost-sensitive systems. Use the MAX9967B for system designs that incorporate independent reference levels for each channel. The MAX9967 provides high-speed, differential control inputs with optional internal termination resistors that are compatible with ECL, LVPECL, LVDS, and GTL. ECL/LVPECL or flexible open-collector outputs with optional internal pullup resistors are available for the comparators. These features significantly reduce the discrete component count on the circuit board. A 3-wire, low-voltage, CMOS-compatible serial interface programs the low-leakage, slew-rate limit, and tristate/terminate operational configurations of the MAX9967. The MAX9967’s operating range is -1.5V to +6.5V with power dissipation of only 1.15W per channel. The device is available in a 100-pin, 14mm x 14mm body, and 0.5mm pitch TQFP. An exposed 8mm x 8mm die pad on the top of the package facilitates efficient heat removal. The device is specified to operate with an internal die temperature of +70°C to +100°C, and features a die temperature monitor output. ♦ High Speed: 500Mbps at 3VP-P ♦ Programmable 35mA Active-Load Current ♦ Low Timing Dispersion ♦ Wide -1.5V to +6.5V Operating Range ♦ Active Termination (3rd-Level Drive) ♦ Low Leakage Mode: 60nA ♦ Integrated Clamps ♦ Interfaces Easily with Most Logic Families ♦ Integrated PMU Connection ♦ Digitally Programmable Slew Rate ♦ Internal Termination Resistors ♦ Low Gain and Offset Error Features ♦ Low Power Dissipation: 1.15W/Channel (typ) MAX9967 Ordering Information PART MAX9967ADCCQ* MAX9967AGCCQ* MAX9967ALCCQ MAX9967AMCCQ* MAX9967AQCCQ* MAX9967ARCCQ* MAX9967BDCCQ MAX9967BGCCQ MAX9967BLCCQ MAX9967BMCCQ MAX9967BQCCQ* MAX9967BRCCQ TEMP RANGE 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C PIN-PACKAGE 100 TQFP-EPR** 100 TQFP-EPR** 100 TQFP-EPR** 100 TQFP-EPR** 100 TQFP-EPR** 100 TQFP-EPR** 100 TQFP-EPR** 100 TQFP-EPR** 100 TQFP-EPR** 100 TQFP-EPR** 100 TQFP-EPR** 100 TQFP-EPR** *Future product—contact factory for availability. **EPR = Exposed pad reversed (TOP). Pin Configuration and Typical Application Circuits appear at end of data sheet. Selector Guide appears at end of data sheet. Applications Low-Cost Mixed-Signal/System-on-Chip ATE Commodity Memory ATE PCI or VXI Programmable Digital Instruments ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 ABSOLUTE MAXIMUM RATINGS VCC to GND .........................................................-0.3V to +11.5V DHV_ to DTV_........................................................…………±10V VEE to GND............................................................-7.0V to +0.3V DLV_ to DTV_ ........................................................…………±10V VCC - VEE ................................................................-0.3V to +18V CHV_ or CLV_ to DUT_..........................................…………±10V GS to GND ...........................................................……………±1V CH_, NCH_, CL_, NCL_ to GND (open collector) ....-2.5V to +5V DUT_, LDH_, LDL_ to GND ...................................-2.5V to +7.5V CH_, NCH_, CL_, NCL_ to GND (open emitter) ..(VCCO_ + 1.0V) All Other Pins to GND ......................(VEE - 0.3V) to (VCC + 0.3V) DATA_, NDATA_, RCV_, NRCV_, Current Out of CH_, NCH_, CL_, NCL_ (open emitter) ....+50mA LDEN_, NLDEN_ to GND ...............................…-2.5V to +5.0V DHV_, DLV_, DTV_, CHV_, CLV_, DATA_ to NDATA_, RCV_ to NRCV_, CPHV_, CPLV_ Current.....................................……….±10mA LDEN_ to NLDEN_............................................…………±1.5V TEMP Current...................................................-0.5mA to +20mA VCCO_ to GND ..........................................................-0.3V to +5V SCLK, DIN, CS, RST, TDATA_, DUT_ Short Circuit to -1.5V to +6.5V..........................Continuous TRCV_, TLDEN_ to GND ..................................…-1.0V to +5V Power Dissipation (TA = +70°C) MAX9967_ _CCQ (derate 167mW/°C above +70°C) ....13.3W* DHV_, DLV_, DTV_, CHV_, CLV_, COM_, Storage Temperature Range .............................-65°C to +150°C FORCE_, SENSE_ to GND.................................-2.5V to +7.5V Junction Temperature ......................................................+125°C CPHV_ to GND ......................................................-2.5V to +8.5V Lead Temperature (soldering, 10s) ....................………..+300°C CPLV_ to GND.......................................................-3.5V to +7.5V DHV_ to DLV_........................................................…………±10V *Dissipation wattage values are based on still air with no heat sink. Actual maximum allowable power dissipation is a function of heat extraction technique and may be substantially higher. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER POWER SUPPLIES Positive Supply Negative Supply Positive Supply Current (Note 2) VCC VEE VLDH_ = VLDL _ = 0 ICC VLDH_ = VLDL _ = 3.5V, load enabled, driver = high impedance VLDH_ = VLDL _ = 0 IEE PD VDUT IDUT VLDH_ = VLDL _ = 3.5V, load enabled, driver = high impedance (Notes 2, 3) (Note 4) LLEAK = 0; 0 ≤ VDUT_ ≤ 3V LLEAK = 0; VDUT_ = -1.5V, +6.5V LLEAK = 1; 0 ≤ VDUT_ ≤ 3V, TJ < +90°C LLEAK = 1; VDUT_ = -1.5V, +6.5V; TJ < +90°C Leakage Current in Low-Leakage Mode LLEAK = 1; 0 < VDUT_ < 3V, VLDL _= VLDH_ = 3.5V; TJ < +90°C LLEAK = 1; VDUT_ = -1.5V, +6.5V; VLDL _ = VLDH_ = 3.5V; TJ < +90°C -1.5 9.5 -6.5 9.75 -5.25 120 220 -220 -320 2.3 10.5 -4.5 155 255 -265 -365 2.9 +6.5 ±1.5 ±3 ±60 ±110 ±80 ±160 nA mA W V µA mA V V SYMBOL CONDITIONS MIN TYP MAX UNITS Negative Supply Current (Note 2) Power Dissipation DUT_ CHARACTERISTICS Operating Voltage Range Leakage Current in HighImpedance Mode 2 _______________________________________________________________________________________ Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER Combined Capacitance Low-Leakage Enable Time Low-Leakage Disable Time Low-Leakage Recovery SYMBOL CDUT CONDITIONS Driver in term mode (DUT_ = DTV_) Driver in high-impedance mode (Notes 5, 6) (Notes 6, 7) Time to return to the specified maximum leakage after a 3V, 4V/ns step at DUT_ IBIAS To 0.1% of full-scale change (Note 7) VIH VIL VDIFF MAX9967_DCCQ, MAX9967_MCCQ VTDATA_, VTRCV_, VTLDEN_ MAX9967_GCCQ, MAX9967_LCCQ, and MAX9967_QCCQ MAX9967_GCCQ, MAX9967_LCCQ, and MAX9967_QCCQ, between signal and corresponding termination voltage input VTHRINT RO VTHR VIH VIL IB fSCLK tCH tCL tCSS0 tCSS1 8 8 3.5 3.5 0.43 VTHR + 0.2 -0.1 -2.1 -1.6 -2.0 ±0.15 1 +3.5 +3.1 ±1.0 ±25 +3.5 MIN TYP 4.0 8.0 20 20 4 MAX UNITS pF µs µs µs MAX9967 LEVEL PROGRAMMING INPUTS (DHV_, DLV_, DTV_, CHV_, CLV_, CPHV_, CPLV_, COM_, LDH_, LDL_) Input Bias Current Settling time Input High Voltage Input Low Voltage Differential Input Voltage Input Bias Current Input Termination Voltage ±25 µA µs V V V µA V DIFFERENTIAL CONTROL INPUTS (DATA_, NDATA_, RCV_, NRCV_, LDEN_, NLDEN_) Input Termination Resistor 48 52 Ω SINGLE-ENDED CONTROL INPUTS (CS, SCLK, DIN, RST) Internal Threshold Reference Internal Reference Output Resistance External Threshold Reference Input High Voltage Input Low Voltage Input Bias Current SERIAL INTERFACE TIMING (Figure 6) SCLK Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Low to SCLK High Setup CS High to SCLK High Setup 50 MHz ns ns ns ns 1.05 1.25 20 1.73 3.5 VTHR 0.2 ±25 1.45 V kΩ V V V µA _______________________________________________________________________________________ 3 Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER SCLK High to CS High Hold DIN to SCLK High Setup DIN to SCLK High Hold CS Pulse Width High TEMPERATURE MONITOR (TEMP) Nominal Voltage Temperature Coefficient Output Resistance DRIVERS (Note 8) DC OUTPUT CHARACTERISTICS (RL ≥ 10MΩ) DHV_, DLV_, DTV_, Output Offset Voltage DHV_, DLV_, DTV_, Output Offset Temperature Coefficient DHV_, DLV_, DTV_, Gain DHV_, DLV_, DTV_, Gain Temperature Coefficient Linearity Error DHV_ to DLV_ Crosstalk DLV_ to DHV_ Crosstalk DTV_ to DLV_ and DHV_ Crosstalk DHV_ to DTV_ Crosstalk DLV_ to DTV_ Crosstalk DHV_, DTV_, DLV_ DC PowerSupply Rejection Ratio Maximum DC Drive Current DC Output Resistance DC Output Resistance Variation PSRR IDUT_ RDUT_ ∆RDUT_ IDUT_ = ±30mA (Note 13) IDUT_ = ±1mA to ±8mA IDUT_ = ±1mA to ±40mA VDUT = 1.5V, 3V (Note 10) Full range (Notes 10, 11) VDLV_ = 0; VDHV_ = 200mV, 6.5V VDHV_ = 5V; VDLV_ = -1.5V, +4.8V VDHV_ = 3V; VDLV_ = 0; VDTV_ = -1.5V, +6.5V VDTV_ = 1.5V; VDLV_ = 0; VDHV_ = 1.6V, 3V VDTV_ = 1.5V; VDHV_ = 3V; VDLV_ = 0, 1.4V (Note 12) 40 ±60 49 50 0.5 1 2.5 ±120 51 AV Measured with VDHV_, VDLV_, and VDTV_ at 0 and 4.5V MAX9967A (Note 9) MAX9967B 0.999 0.96 -35 ±5 ±15 ±2 ±2 ±2 ±3 ±3 VOS At DUT_ with VDHV_, VDTV_, VDLV_ independently tested at +1.5V MAX9967A MAX9967B ±65 1.00 1.001 1.001 ppm/°C mV mV mV mV mV mV dB mA Ω Ω ±15 ±100 mV µV/°C TJ = +70°C, RL ≥ 10MΩ 3.43 +10 15 V mV/°C kΩ SYMBOL tCSH1 tDS tDH tCSWH CONDITIONS MIN 3.5 3.5 3.5 20 TYP MAX UNITS ns ns ns ns V/V 4 _______________________________________________________________________________________ Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER Sense Resistance Force Resistance Force Capacitance SYMBOL RSENSE RFORCE CFORCE VDLV_ = 0, VDHV_ = 0.1V Drive-Mode Overshoot Term-Mode Overshoot Settling Time to Within 25mV Settling Time to Within 5mV Prop Delay, Data to Output Prop Delay Match, tLH vs. tHL Prop Delay Match, Drivers Within Package Prop Delay Temperature Coefficient Prop Delay Change vs. Pulse Width Prop Delay Change vs. CommonMode Voltage Prop Delay, Drive to High Impedance Prop Delay, High Impedance to Drive Prop Delay, Drive to Term Prop Delay, Term to Drive tPDDZ tPDZD tPDDT tPDTD 3VP-P, 40MHz, 2.5ns to 22.5ns pulse width, relative to 12.5ns pulse width VDHV_ - VDLV_ = 1V, VDHV_ = 0 to 6V VDHV_ = 1.0V, VDLV_ = -1.0V, VDTV_ = 0 VDHV_ = 1.0V, VDLV_ = -1.0V, VDTV_ = 0 VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V 0.2VP-P, 20% to 80% Rise and Fall Time tR , t F 1VP-P, 10% to 90% 3VP-P, 10% to 90% 5VP-P, 10% to 90% Rise and Fall Time Match SC1 = 0, SC0 = 1 Slew Rate SC1 = 1, SC0 = 0 Slew Rate SC1 = 1, SC0 = 1 Slew Rate tR vs. tF 3VP-P, 10% to 90% Percent of full speed (SC0 = SC1 = 0), 3VP-P, 20% to 80% Percent of full speed (SC0 = SC1 = 0), 3VP-P, 20% to 80% Percent of full speed (SC0 = SC1 = 0), 3VP-P, 20% to 80% 1.0 tPDD 3VP-P (Note 17) VDLV_ = 0, VDHV_ = 1V VDLV_ = 0, VDHV_ = 3V (Note 14) 3V step (Note 15) 3V step (Note 15) CONDITIONS MIN 7.50 320 TYP 10 400 2 30 40 50 0 10 20 2.2 ±50 40 +3 ±60 85 3.2 3.3 2.5 2.2 370 630 1.3 2.0 ±0.03 75 50 25 1.5 mV ns ns ns ps ps ps/°C ps ps ns ns ns ns mV MAX 13.75 500 UNITS kΩ Ω pF MAX9967 DYNAMIC OUTPUT CHARACTERISTICS (ZL = 50Ω) TIMING CHARACTERISTICS (ZL = 50Ω) (Note 16) DYNAMIC PERFORMANCE (ZL = 50Ω) ps ns ns % % % _______________________________________________________________________________________ 5 Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER Minimum Pulse Width (Note 18) SYMBOL 0.2VP-P 1VP-P 3VP-P 5VP-P 0.2VP-P Data Rate (Note 19) 1VP-P 3VP-P 5VP-P Dynamic Crosstalk Rise and Fall Time, Drive to Term Rise and Fall Time, Term to Drive COMPARATORS (Note 8) DC CHARACTERISTICS Input Voltage Range Differential Input Voltage Hysteresis Input Offset Voltage Input Offset Voltage Temperature Coefficient Common-Mode Rejection Ratio (Note 22) VDUT_ = 0, 3V CMRR VDUT_ = 0, 6.5V VDUT_ = -1.5V, +6.5V VDUT_ = 1.5V, 3V Linearity Error (Note 10) VCC Power-Supply Rejection Ratio (Note 12) VEE Power-Supply Rejection Ratio (Note 12) AC CHARACTERISTICS (Note 23) Minimum Pulse Width (Note 24) Prop Delay Prop Delay Temperature Coefficient tPW(MIN) tPDL MAX9967_DCCQ, MAX9967_GCCQ, MAX9967_LCCQ, MAX9967_RCCQ MAX9967_MCCQ, MAX9967_QCCQ 0.7 0.85 2.2 +6 ns ps/°C ns VDUT_ = 6.5V VDUT_ = -1.5V PSRR PSRR VDUT_ = -1.5V, +6.5V VDUT_ = 0, 6.5V VDUT_ = -1.5V 57 44 33 80 64 60 47 54 44 VIN VDIFF VHYST VOS VDUT_ = 1.5V MAX9967A MAX9967B ±50 78 78 61 ±3 ±5 ±25 dB dB mV dB (Note 4) -1.5 ±8 0 ±20 ±100 +6.5 V V mV mV µV/°C tDTR, tDTF tTDR, tTDF (Note 20) VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V, 10% to 90%, Figure 1a (Note 21) VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V, 10% to 90%, Figure 1b (Note 21) CONDITIONS MIN TYP 650 1.0 2.0 2.9 1700 1000 500 350 10 1.6 0.7 mVP-P ns ns Mbps ns MAX UNITS ps 6 _______________________________________________________________________________________ Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER Prop Delay Match, High/Low vs. Low/High Prop Delay Match, Comparators Within Package Prop Delay Dispersion vs. Common-Mode Input (Note 25) Prop Delay Dispersion vs. Overdrive Prop Delay Dispersion vs. Pulse Width Prop Delay Dispersion vs. Slew Rate Waveform Tracking 10% to 90% (Note 17) VCHV_ = VCLV_= 0, 6.4V VCHV_ = VCLV_ = -1.4V 100mV to 1V 2.5ns to 22.5ns pulse width, relative to 12.5ns pulse width 0.5V/ns to 2V/ns slew rate VDUT_ = 1.0VP-P, tR = tF = 1.0ns, 10% to 90% relative to timing at 50% point Term mode High-Z mode SYMBOL CONDITIONS MIN TYP ±25 35 ±75 ±175 220 ±40 100 250 ps 500 MAX UNITS ps ps ps ps ps ps MAX9967 OPEN-COLLECTOR LOGIC OUTPUTS (CH_, NCH_, CL_, NCL_: MAX9967_DCCQ, MAX9967_GCCQ, MAX9967_LCCQ, and MAX9967_RCCQ) VCCO_ Voltage Range Output Low-Voltage Compliance Output High Current Output Low Current Output High Voltage Output Low Voltage Output Voltage Swing VVCCO_ IOH IOL VOH VOL Set by IOL, RTERM, and VCCO_ MAX9967_DCCQ, MAX9967_GCCQ MAX9967_DCCQ, MAX9967_GCCQ ICH_ = INCH_ = ICL _ = INCL _ = 0, MAX9967_LCCQ, MAX9967_RCCQ ICH_ = INCH_ = ICL _ = INCL _ = 0, MAX9967_LCCQ, MAX9967_RCCQ ICH_ = INCH_ = ICL _ = INCL _ = 0, MAX9967_LCCQ, MAX9967_RCCQ RTERM Single-ended measurement from VCCO_ to CH_, NCH_, CL_, NCL_, MAX9967_LCCQ, MAX9967_RCCQ 20% to 80% 20% to 80% MAX9967_DCCQ, MAX9967_GCCQ, RTERM = 50Ω at end of line MAX9967_LCCQ, MAX9967_RCCQ MAX9967_DCCQ, MAX9967_GCCQ, RTERM = 50Ω at end of line MAX9967_LCCQ, MAX9967_RCCQ -0.1 All outputs 50Ω to (VVCCO_ - 2V) 165 +3.5 V mA 360 0 -0.05 7.6 VCCO_ - 0.05 -0.5 0 8 VCCO_ - 0.005 VCCO_ - 0.4 390 440 3.5 +0.10 8.4 V V mA mA V V mV Output Termination Resistor 48 52 Ω Differential Rise Time tR 280 ps Differential Fall Time tF 280 ps OPEN-EMITTER LOGIC OUTPUTS (CH_, NCH_, CL_, NCL_: MAX9967_MCCQ and MAX9967_QCCQ) VCCO_ Voltage Range VCCO_ Supply Current VVCCO_ IVCCO_ _______________________________________________________________________________________ 7 Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER Output High Voltage Output Low Voltage Output Voltage Swing Differential Rise Time Differential Fall Time CLAMPS High Clamp Input Voltage Range Low Clamp Input Voltage Range Clamp Offset Voltage Offset Voltage Temperature Coefficient Clamp Power-Supply Rejection Ratio (Note 12) Voltage Gain Voltage Gain Temperature Coefficient IDUT_ = 1mA, VCPLV_ = -1.5V, VCPHV_ = -0.3V to +6.5V IDUT _= -1mA, VCPHV_ = 6.5V, VCPLV_ = -1.5V to +5.3V Short-Circuit Output Current Clamp DC Impedance ISCDUT_ ROUT VCPHV_ = 0, VCPLV_ = -1.5V, VDUT_ = 6.5V VCPHV_ = 6.5V, VCPLV_ = 5V, VDUT_ = -1.5V VCPHV_ = 3V, VCPLV_ = 0, IDUT_ = ±5mA and ±15mA 50 -95 50 PSRR AV IDUT_ = 1mA, VCPHV_ = 0 IDUT_ = -1mA, VCPLV_ = 0 0.96 -100 ±10 mV ±10 95 -50 55 mA mA Ω VCPH_ VCPL_ VOS At DUT_ with IDUT_ = 1mA, VCPHV_ = 0 At DUT_ with IDUT_ = -1mA, VCPLV_ = 0 ±0.5 54 54 1.00 -0.3 -2.5 +7.5 +5.3 ±100 ±100 V V mV mV/°C dB V/V ppm/°C tR tF SYMBOL VOH VOL CONDITIONS 50Ω to (VVCCO_ - 2V) 50Ω to (VVCCO_ - 2V) 50Ω_to (V VCCO_ - 2V) 20% to 80% 20% to 80% 800 MIN VCCO_ - 1.0 TYP VCCO_ - 0.85 VCCO_ - 1.7 850 370 370 VCCO_ - 1.6 900 MAX UNITS V V mV ps ps Clamp Linearity ACTIVE LOAD (VCOM_ = +1.5V, RL > 1MΩ, driver in high-impedance mode, unless otherwise noted) COM_ Voltage Range Differential Voltage Range COM_ Offset Voltage Offset Voltage Temperature Coefficient COM_ Voltage Gain Voltage Gain Temperature Coefficient AV VCOM_ = 0, 4.5V, ISOURCE = ISINK = 20mA 0.98 ±25 Vos VCOM_ VDUT_ - VCOM_ ISOURCE = ISINK = 20mA MAX9967A MAX9967B 50 1.00 -1.5 -7.2 +5.7 +8.0 ±15 ±100 V V mV µV/°C V/V ppm/°C 8 _______________________________________________________________________________________ Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER COM_ Linearity Error COM_ Output-Voltage PowerSupply Rejection Ratio PSRR SYMBOL CONDITIONS VCOM_ = -1.5V, +5.7V; ISOURCE = ISINK = 20mA (Note 10) VCOM_ = 2.5V, ISOURCE = ISINK = 20mA ISOURCE = ISINK = 35mA; VDUT_ = 3V, 6.5V with VCOM_ = -1.5V and VDUT_ = -1.5V, +2V with VCOM_ = 5.7V ISOURCE = ISINK = 1mA; VDUT_ = 3V, 6.5V with VCOM_ = -1.5V and VDUT_ = -1.5V, +2V with VCOM_ = 5.7V IDUT_ = ±10mA, ISOURCE = ISINK = 35mA, VCOM_ = 2.5V VCOM_ = 2.5V, 95% ISOURCE to 95% ISINK VLDL _ = 3.8V ATC IOS VLDL _ = 0.3V, 3V; VLDH = 0.1V VLDL_ = 20mV ISOURCE = 35mA PSRR ISOURCE = 25mA ISOURCE = 35mA VLDL _ = 100mV, 1V, 2.5V VLDL _ = 3.5V VLDH_ = 3.8V ATC IOS VLDH_ = 0.3V, 3V; VLDL_ = 0.1V VLDH_ = 20mV ISINK = 35mA PSRR ISINK = 25mA ISINK = 35mA MAX9967A (Note 9) MAX9967B -40 -10.1 -50 -200 +6 ±70 ±84 -10 MAX9967A (Note 9) MAX9967B 36 9.9 10 0 -6 ±70 ±84 ±60 ±130 -36 -9.9 -10 0 10 40 MIN TYP ±3 MAX ±15 UNITS mV dB MAX9967 25 kΩ Output Resistance, Sink or Source Ro 500 kΩ Ω 700 40 10.1 50 200 mV mA mA/V µA µA/oC µA/V µA Output Resistance, Linear Region Deadband SOURCE CURRENT (VDUT_ = 4.5V) Maximum Source Current Source Programming Gain Source Current Offset (Combined Offset of LDL_ and GS) Source Current Temperature Coefficient Source Current Power-Supply Rejection Ratio Source Current Linearity (Note 26) SINK CURRENT (VDUT_ = -1.5V) Maximum Sink Current Sink Programming Gain Sink Current Offset (Combined Offset of LDH_ and GS) Sink Current Temperature Coefficient Sink Current Power-Supply Rejection Ratio Ro 6 400 mA mA/V µA µA/°C µA /V _______________________________________________________________________________________ 9 Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER Sink Current Linearity (Note 26) GROUND SENSE GS Voltage Range VGS Verified by GS common-mode error test VDUT_ = -1.5V, VGS = ±250mV, VLDH_- VGS = 0.1V VDUT_ = +4.5V, VGS = ±250mV, VLDL_ VGS = 0.1V VGS = 0 ISOURCE = 20mA, VCOM_ = -1.5V ISINK = 20mA, VCOM_ = +1.5V ISOURCE = 20mA, VCOM_ = -1.5V ISINK = 20mA, VCOM_ = +1.5V ISOURCE = ISINK = 1mA and 35mA (Notes 7, 28) To 10% To 1.5% ±250 ±25 µA ±25 ±25 µA mV SYMBOL VLDH_ = 3.5V CONDITIONS VLDH_ = 100mV, 1V, 2.5V MIN TYP MAX ±60 ±130 UNITS µA GS Common-Mode Error GS Input Bias Current AC CHARACTERISTICS (ZL = 50Ω to GND) Enable Time (Note 27) Disable Time (Note 27) Current Settling Time on Commutation Spike During Enable/Disable Transition tEN tDIS 2.2 1.9 10 50 100 ns ns ns mV ISOURCE = ISINK = 35mA, VCOM_ = 0 Note 1: All minimum and maximum limits are 100% production tested. Tests are performed at nominal supply voltages unless otherwise noted. Note 2: Total for dual device at worst-case setting. RL > 10MΩ. The supply currents are measured with typical supply voltages. Note 3: Does not include internal dissipation of the comparator outputs. With output loads of 50Ω to (VVCCO - 2V), this adds 120mW (typ) to the total device power (MAX9967_MCCQ and MAX9967_QCCQ). For MAX9967_LCCQ, additional power dissipation is typically (32mA x VVCCO). Note 4: Externally forced voltages may exceed this range provided that the Absolute Maximum Ratings are not exceeded. Note 5: Transition time from LLEAK being asserted to leakage current dropping below specified limits. Note 6: Based on simulation results only. Note 7: Transition time from LLEAK being deasserted to output returning to normal operating mode. Note 8: With the exception of Offset and Gain/CMRR tests, reference input values are calibrated for offset and gain. Note 9: Measured at VCC = +9.75, VEE = -5.25V, and TJ = +85°C. Note 10: Relative to straight line between 0 and 4.5V. Note 11: Specifications measured at the end points of the full range. Full ranges are -1.3V ≤ VDHV_ ≤ 6.5V, -1.5V ≤ VDLV_ ≤ 6.3V, -1.5V ≤ VDTV_ ≤ 6.5V. Note 12: Change in offset voltage with power supplies independently set to their minimum and maximum values. Note 13: Nominal target value is 50Ω. Contact factory for alternate trim selections within the 45Ω to 51Ω range. Note 14: VDTV_ = +1.5V, RS = 50Ω. External signal driven into T-line is a 0 to +3V edge with 1.2ns rise time (10% to 90%). Measurement is made using the comparator. Note 15: Measured from the crossing point of DATA_ inputs to the settling of the driver output. Note 16: Prop delays are measured from the crossing point of the differential input signals to the 50% point of the expected output swing. Rise time of differential inputs DATA_ and RCV_ is 250ps (10% to 90%). Note 17: Rising edge to rising edge or falling edge to falling edge. Note 18: Specified amplitude is programmed. At this pulse width, the output reaches at least 95% of its nominal (DC) amplitude. The pulse width is measured at DATA_. 10 ______________________________________________________________________________________ Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ = +85°C, unless otherwise noted. All temperature coefficients are measured at TJ = +70°C to +100°C, unless otherwise noted.) (Note 1) Note 19: Specified amplitude is programmed. Maximum data rate is specified in transitions per second. A square wave that reaches at least 95% of its programmed amplitude may be generated at one-half this frequency. Note 20: Crosstalk from either driver to the other. Aggressor channel is driving 3VP-P into a 50Ω load. Victim channel is in term mode with VDTV_ = +1.5V. Note 21: Indicative of switching speed from DHV_ or DLV_ to DTV_ and DTV_ to DHV_ or DLV_ when VDLV_ < VDTV_ < VDHV_. If VDTV_ < VDLV_ or VDTV_ > VDHV_, switching speed is degraded by approximately a factor of 3. Note 22: Change in offset voltage over the input range. Note 23: Unless otherwise noted, all propagation delays are measured at 40MHz, VDUT_ = 0 to +2V, VCHV_ = VCLV_ = +1V, slew rate = 2V/ns, ZS = 50Ω, driver in term mode with VDTV_ = 0. Comparator outputs are terminated with 50Ω to GND at scope input with VCCO_ = 2V. Open-collector outputs are also terminated (internally or externally) with RTERM = 50Ω to VCCO_. Measured from VDUT_ crossing calibrated CHV_/CLV_ threshold to crossing point of differential outputs. Note 24: VDUT_ = 0 to +1V, VCHV_ = VCLV _ = +0.5V. At this pulse width, the output reaches at least 90% of its DC voltage swing. The pulse width is measured at the crossing points of the differential outputs. Note 25: Relative to propagation delay at VCHV_ = VCLV_ = +1.5V. VDUT_ = 200mVP-P. Overdrive = 100mV. Note 26: Relative to segmented interpolations between 20mV, 200mV, 2V, and 3V. Note 27: Measured from the crossing point of LDEN_ inputs to the 10% point of the output voltage change. Note 28: VCOM_ = 1.5V, Rs = 50Ω, driving voltage = +4V to -1V transition and -1V to +4V transition. Settling time is measured from VDUT_ = 1.5V to ISINK/ISOURCE settling within specified tolerance. tDTF DHV_ 90% 10% DTV_ DTV_ tTDR DHV_ 90% 10% 90% 10% DLV_ tDTR tTDF MAX9967 90% 10% DLV_ Figure 1a. Drive to Term Rise and Fall Time Figure 1b. Term to Drive Rise and Fall Time Typical Operating Characteristics DRIVER SMALL-SIGNAL RESPONSE MAX9967 toc01 DRIVER LARGE-SIGNAL RESPONSE MAX9967 toc02 DRIVER TRAILING EDGE TIMING ERROR vs. PULSE WIDTH MAX9967 toc03 DLV_ = 0 RL = 50Ω DHV_ = 500mV DLV_ = 0 RL = 50Ω 40 20 LOW PULSE TIMING ERROR (ps) 0 -20 -40 HIGH PULSE -60 -80 -100 NORMALIZED TO PW = 12.5ns PERIOD = 25ns DHV_ = +3V DLV_ = 0 0 5 10 15 20 DHV_ = 5V VDUT_ (500mV/div) VDUT_ (50mV/div) DHV_ = 3V DHV_ = 200mV DHV_ = 1V DHV_ = 100mV 0 t (2.50ns/div) 0 t (2.50ns/div) 25 PULSE WIDTH (ns) ______________________________________________________________________________________ 11 Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 Typical Operating Characteristics (continued) DRIVER TIME DELAY vs. COMMON-MODE VOLTAGE MAX9967 toc04 DRIVE-TO-TERM TRANSITION MAX9967 toc05 HIGH IMPEDANCE TO DRIVE TRANSITION HIGH IMPEDANCE TO DHV_ MAX9967 toc06 MAX9967 toc12 MAX9967 toc09 65 55 45 TIME DELAY (ps) 35 25 15 5 -5 -15 -25 -35 0 1 2 NORMALIZED TO VCM = 1.5V RISING EDGE FALLING EDGE VDUT_ (250mV/div) DLV_ TO DTV_ 0 3 4 5 6 t (2.5ns/div) RL = 50Ω HIGH IMPEDANCE TO DLV_ RL = 50Ω t (2.5ns/div) COMMON-MODE VOLTAGE (V) VDUT_ (250mV/div) DHV_ TO DTV_ 0 DRIVER LINEARITY ERROR vs. OUTPUT VOLTAGE MAX9967 toc07 DRIVER LINEARITY ERROR vs. OUTPUT VOLTAGE MAX9967 toc08 DRIVER LINEARITY ERROR vs. OUTPUT VOLTAGE 6 5 LINEARITY ERROR (mV) 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 VDUT_ (V) DUT_ = DTV_ 6 5 LINEARITY ERROR (mV) 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -1.5 -0.5 0.5 1.5 2.5 3.5 DUT_ = DHV_ 6 5 LINEARITY ERROR (mV) 4 3 2 1 0 -1 -2 -3 -4 -5 -6 DUT_ = DLV_ 4.5 5.5 6.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 VDUT_ (V) VDUT_ (V) CROSSTALK TO DUT_ FROM DLV_ WITH DUT_ = DHV_ MAX9967 toc10 CROSSTALK TO DUT_ FROM DHV_ WITH DUT_ = DLV_ 1.6 1.2 DUT_ ERROR (mV) 0.8 0.4 0 -0.4 -0.8 -1.2 DLV_ = 0 DTV_ = 1.5V MAX9967 toc11 CROSSTALK TO DUT_ FROM DTV_ WITH DUT_ = DHV_ 0.5 0.4 0.3 DUT_ ERROR (mV) 0.2 0.1 0 -0.1 -0.2 -0.3 DHV_ = 3V DLV_ = 0 2.0 1.6 1.2 DUT_ ERROR (mV) 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 -2.0 DHV_ = 5V DTV_ = 1.5V 2.0 NORMALIZED AT DLV_ = 0 -1.5 0 1.5 3.0 4.5 6.0 -1.6 -2.0 -0.5 0.5 1.5 NORMALIZED AT DHV_ = 5V 2.5 3.5 4.5 5.5 6.5 -0.4 -0.5 -1.5 -0.5 0.5 NORMALIZED AT DTV_ = 1.5V 1.5 2.5 3.5 4.5 5.5 6.5 DLV_ VOLTAGE (V) DHV_ VOLTAGE (V) DTV_ VOLTAGE (V) 12 ______________________________________________________________________________________ Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 Typical Operating Characteristics (continued) CROSSTALK TO DUT_ FROM DTV_ WITH DUT_ = DLV_ MAX9967 toc13 CROSSTALK TO DUT_ FROM DLV_ WITH DUT_ = DTV_ MAX9967 toc14 CROSSTALK TO DUT_ FROM DHV_ WITH DUT_ = DTV_ 1.5 1.0 DUT_ ERROR (mV) 0.5 0 -0.5 -1.0 -1.5 -2.0 DTV_ = 1.5V DLV_ = -1.5V MAX9967 toc15 0.5 0.4 0.3 DUT_ ERROR (mV) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 DLV_ = 0 DHV_ = 6.5V 3.0 2.5 2.0 DUT_ ERROR (mV) 1.5 1.0 0.5 0 -0.5 -1.0 DTV_ = 1.5V DHV_ = 6.5V 2.0 NORMALIZED AT DTV_ = 1.5V -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 -1.5 -2.0 -1.5 -0.5 0.5 1.5 NORMALIZED AT DLV_ = 0 2.5 3.5 4.5 5.5 6.5 -2.5 -3.0 -1.5 -0.5 0.5 1.5 NORMALIZED AT DHV_ = 3V 2.5 3.5 4.5 5.5 6.5 DTV_ VOLTAGE (V) DLV_ VOLTAGE (V) DHV_ VOLTAGE (V) DRIVER GAIN vs. TEMPERATURE MAX9967 toc16 DRIVER OFFSET vs. TEMPERATURE MAX9967 toc17 COMPARATOR OFFSET vs. COMMON-MODE VOLTAGE 1.5 1.0 OFFSET (mV) 0.5 0 -0.5 -1.0 VEE = -5.5V VEE = -4.5V MAX9967 toc18 1.0008 1.0006 1.0004 0.6 0.4 0.2 0 OFFSET (mV) -0.2 -0.4 -0.6 -0.8 -1.0 2.0 VEE = -6.5V GAIN (V/V) 1.0002 1.0000 0.9998 0.9996 0.9994 60 NORMALIZED AT TJ = +85°C 65 70 75 80 85 90 95 100 TEMPERATURE (°C) -1.2 -1.4 60 65 70 75 NORMALIZED AT TJ = +85°C 80 85 90 95 100 TEMPERATURE (°C) -1.5 -2.0 -1.5 -0.5 0.5 NORMALIZED AT VCM = 1.5V AND VEE = -5.5V 1.5 2.5 3.5 4.5 5.5 6.5 COMMON-MODE VOLTAGE (V) COMPARATOR RISING-EDGE TIMING VARIATION vs. COMMON-MODE VOLTAGE MAX9967 toc19 COMPARATOR FALLING-EDGE TIMING VARIATION vs. COMMON-MODE VOLTAGE MAX9967 toc20 COMPARATOR TIMING VARIATION vs. OVERDRIVE 250 200 DELAY (ps) 150 100 50 FALLING EDGE MAX9967 toc21 150 100 TIMING VARIATION (ps) 50 0 -50 -100 -150 -1.5 -0.5 0.5 VEE = -4.5V VEE = -5.5V VEE = -6.5V 150 100 TIMING VARIATION (ps) 50 0 -50 -100 -150 VEE = -4.5V VEE = -5.5V 300 VEE = -6.5V NORMALIZED AT VCM = 1.5V AND VEE = -5.25V -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 0 -50 -100 0 RISING EDGE NORMALIZED AT VCM = 1.5V AND VEE = -5.25V 1.5 2.5 3.5 4.5 5.5 6.5 NORMALIZED TO OVERDRIVE = 0.5V 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 OVERDRIVE (V) COMMON-MODE VOLTAGE (V) COMMON-MODE VOLTAGE (V) ______________________________________________________________________________________ 13 Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 Typical Operating Characteristics (continued) COMPARATOR TRAILING TIMING ERROR vs. PULSE WIDTH, MAX9967_LCCQ MAX9967 toc22 COMPARATOR TRAILING-EDGE TIMING ERROR vs. PULSE WIDTH, MAX9967_MCCQ MAX9967 toc23 COMPARATOR TIMING VARIATION vs. INPUT SLEW RATE, DUT_ RISING 20 PROPAGATION DELAY (ps) 10 0 -10 -20 -30 -40 -50 -60 -70 NORMALIZED TO SR = 1.2V/ns 0.5 1.0 1.5 SLEW RATE (V/ns) 2.0 2.5 MAX9967 toc24 20 0 TIMING ERROR (ps) -20 LOW PULSE -40 -60 -80 -100 0 5 NORMALIZED TO PW = 12.5ns PERIOD = 25ns 10 15 20 HIGH PULSE 30 20 10 TIMING ERROR (ps) 0 -10 -20 -30 -40 -50 -60 NORMALIZED TO PW = 12.5ns, PERIOD = 25ns 0 5 10 15 20 HIGH PULSE LOW PULSE 30 25 25 PULSE WIDTH (ns) PULSE WIDTH (ns) COMPARATOR TIMING VARIATION vs. INPUT SLEW RATE, DUT_ FALLING 20 PROPAGATION DELAY (ps) 10 0 -10 -20 -30 -40 -50 -60 -70 0.5 1.0 1.5 SLEW RATE (V/ns) 2.0 2.5 NORMALIZED TO SR = 1.2V/ns MAX9967 toc25 COMPARATOR DIFFERENTIAL OUTPUT RESPONSE (MAX9967_LCCQ) MAX9967 toc26 COMPARATOR DIFFERENTIAL OUTPUT RESPONSE (MAX9967_MCCQ) MAX9967 toc27 30 VOUT_ (50mV/div) 0 VOUT_ (200mV/div) t (2.50ns/div) VDUT_ = 0 TO 3V PULSE, CHV_ = CLV_ = +1.5V, EXTERNAL LOAD = 50Ω 0 t (2.50ns/div) VDUT = 0 TO 3V PULSE, CHV_ = CLV_ = 1.5V, EXTERNAL LOAD = 50Ω 14 ______________________________________________________________________________________ Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 Typical Operating Characteristics (continued) COMPARATOR RESPONSE HIGH SLEW-RATE OVERDRIVE MAX9967 toc28 COMPARATOR OFFSET vs. TEMPERATURE 0.6 0.4 OFFSET (mV) MAX9967 toc29 CLAMP RESPONSE MAX9967 toc30 HIGH-IMPEDANCE MODE 0.8 RISING EDGE V (500mV/div) V (500mV/div) DIGITIZED OUTPUT 0.2 0 -0.2 -0.4 INPUT FALLING EDGE 0 0 INPUT SLEW RATE = 6V/ns t (2.50ns/div) -0.6 -0.8 60 NORMALIZED TO TJ = +85°C 65 70 75 80 85 90 95 100 TEMPERATURE (°C) t (5.0ns/div) DUT_ = 0 TO 3V SQUARE WAVE RS = 25Ω CPLV_ = -0.1V CPHV_ = +3.1V ACTIVE-LOAD VOLTAGE vs. CURRENT MAX9967 toc31 ACTIVE-LOAD LINEARITY ERROR IDUT_ vs. LDH_ MAX9967 toc32 ACTIVE-LOAD LINEARITY ERROR IDUT_ vs. LDL_ 80 60 LINEARITY ERROR (µA) 40 20 0 -20 -40 -60 -80 COM_ = 1.5V LDH_ = 0 DUT_ = 4.5V MAX9967 toc33 40 30 20 IDUT_ (mA) 10 0 -10 -20 -30 -40 COM_ = 2.5V LDH_ = 3.5V LDL_ = 3.5V 100 COM_ = 1.5V LDL_ = 0 DUT_ = -1.5V 100 LINEARITY ERROR (µA) 50 0 -50 -100 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 VDUT_ (V) 0.01 0.1 1 10 LDH_ VOLTAGE (V) CALIBRATION POINTS AT LDH_ = 20mV, 200mV, 2V, 3V -100 0.01 0.1 1 10 LDL_ VOLTAGE (V) CALIBRATION POINTS AT LDL_ = 20mV, 200mV, 2V, 3V ______________________________________________________________________________________ 15 Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 Typical Operating Characteristics (continued) HIGH-IMPEDANCE LEAKAGE CURRENT vs. DUT_ VOLTAGE MAX9967 toc34 LOW-LEAKAGE CURRENT vs. DUT_ VOLTAGE MAX9967 toc35 CLAMP CURRENT vs. DIFFERENCE VOLTAGE 900 800 700 DUT_ = 3V CPLV_ = 0 MAX9967 toc36 1.0 0.8 0.6 0.4 IDUT_ (µA) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 LDH_ = LDL_ = 0 LDH_ = LDL_ = 3.5V 100 80 60 40 IDUT_ (nA) 20 0 -20 -40 -60 -80 -100 LDH_ = LDL_ = 3.5V LDH_ = LDL_ = 0 1000 IDUT_ (µA) 3.5 4.5 5.5 6.5 600 500 400 300 200 100 0 6.5 -1.5 -0.5 0.5 1.5 2.5 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 CPHV_ VOLTAGE (V) VDUT_ (V) VDUT_ (V) CLAMP CURRENT vs. DIFFERENCE VOLTAGE MAX9967 toc37 HIGH-IMPEDANCE TO LOW-LEAKAGE TRANSITION MAX9967 toc38 DRIVER REFERENCE CURRENT vs. DRIVER REFERENCE VOLTAGE 2.25 2.00 INPUT CURRENT (µA) 1.75 1.50 1.25 1.00 0.75 0.50 DTV_ DHV_ DLV_ MAX9967 toc39 100 0 -100 -200 IDUT_ (µA) -300 -400 -500 -600 -700 -800 -900 -1000 -1.50 -1.25 -1.00 -0.75 -0.50 -0.25 0 DUT_ = 0 CPHV_ = 3V RL = 100kΩ CL = 20pF 2.50 IDUT_ (250nA/div) LOW LEAKAGE TO HIGH IMPEDANCE HIGH IMPEDANCE TO LOW LEAKAGE 0 0 t (5µs/div) t = 0 IS THE RISING EDGE OF CS 0.25 0 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 INPUT VOLTAGE (V) CPLV_ VOLTAGE (V) COMPARATOR REFERENCE INPUT CURRENT vs. INPUT VOLTAGE MAX9967 toc40 INPUT CURRENT vs. INPUT VOLTAGE, CPHV_ MAX9967 toc41 INPUT CURRENT vs. INPUT VOLTAGE, CPLV_ CPHV_ = 7.2V MAX9967 toc42 4.0 3.5 INPUT CURRENT (nA) 3.0 2.5 2.0 1.5 1.0 0.5 0 DUT_ = 6.5V 500 450 CPHV_ CURRENT (nA) 400 350 300 250 200 150 100 CPLV_ = -2.2V -600 -650 CPLV_ CURRENT (nA) -700 -750 -800 -850 -900 CHV_ / CLV_ -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 INPUT VOLTAGE (V) CPHV_ VOLTAGE (V) CPLV_ VOLTAGE (V) 16 ______________________________________________________________________________________ Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 Typical Operating Characteristics (continued) LOAD REFERENCES INPUT CURRENTS vs. INPUT VOLTAGE MAX9967 toc43 INPUT CURRENTS vs. INPUT VOLTAGE, COM_ MAX9967 toc44 SUPPLY CURRENT, ICC vs. VCC 225 200 175 ICC (mA) 150 125 100 75 50 25 0 RL = 10kΩ, CL = 0.5pF, VEE = - 5.25V 9.5 9.6 9.7 9.8 9.9 10.0 10.1 10.2 10.3 10.4 10.5 VCC ( V) A: DUT_ = DTV_ = 1.5V, DHV_ = 3V, DLV_ = 0, CHV_ = CLV_ = 0, CPHV_ = 7.2V, CPLV_ = -2.2V, LDH_ = LDL_ = 0 ISOURCE = ISINK = 0 B: SAME AS A EXCEPT DRIVER DISABLED HIGH-Z AND LOAD ENABLED C: SAME AS B EXCEPT ISOURCE = ISINK = 35mA D: SAME AS C EXCEPT LOW-LEAKAGE MODE ASSERTED A B D C MAX9967 toc45 -400 -450 INPUT CURRENT (nA) -500 -550 -600 -650 -700 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 LDL LDH 1.000 0.975 COM_ CURRENT (µA) 0.950 0.925 0.900 0.875 0.850 0.825 0.800 -1.5 0 1.5 3.0 4.5 250 4.0 6.0 INPUT VOLTAGE (V) COM_ VOLTAGE (V) SUPPLY CURRENT, IEE vs. VEE MAX9967 toc46 ICC vs. TEMPERATURE MAX9967 toc47 IEE vs. TEMPERATURE -212 -214 SUPPLY CURRENT (mA) -216 -218 -220 -222 -224 -226 -228 -230 DUT_ = DTV_ = 1.5V, DHV_ = 3V, DLV_ = 0 CHV_ = CLV_ = 0, CPHV_ = 7.2V CPLV_ = -2.2V, LDH_ = LDL_ = 0 VCC = 9.75V, VEE = -5.25V MAX9967 toc48 -150 -170 -190 -210 IEE (mA) -230 -250 -270 -290 -310 -330 -350 RL = 10kΩ, CL = 0.5pF, VCC = 9.75V 125 124 123 SUPPLY CURRENT (mA) 122 121 120 119 118 117 116 115 B A D DUT_ = DTV_ = 1.5V, DHV_ = 3V, DLV_ = 0 CHV_ = CLV_ = 0, CPHV_ = 7.2V CPLV_ = -2.2V, LDH_ = LDL_ = 0 VCC = 9.75V, VEE = -5.25V -210 C -6.50 -6.25 -6.00 -5.75 -5.50 -5.25 -5.00 -4.75 -4.50 VEE ( V) A: DUT_ = DTV_ = 1.5V, DHV_ = 3V, DLV_ = 0, CHV_ = CLV_ = 0, CPHV_ = 7.2V, CPLV_ = -2.2V, LDH_ = LDL_ = 0 ISOURCE = ISINK = 0 B: SAME AS A EXCEPT DRIVER DISABLED HIGH-Z AND LOAD ENABLED C: SAME AS B EXCEPT ISOURCE = ISINK = 35mA D: SAME AS C EXCEPT LOW-LEAKAGE MODE ASSERTED 60 65 70 75 80 85 90 95 100 105 110 TEMPERATURE (°C) 60 65 70 75 80 85 90 95 100 105 110 TEMPERATURE (°C) ______________________________________________________________________________________ 17 Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 Pin Description PIN 1 2, 9, 12, 14, 17, 24, 35, 45, 46, 60, 80, 81, 91 3, 5, 10, 16, 21, 23, 25, 34, 43, 44, 82, 83, 92 4, 11, 15, 22, 33, 41, 42, 66, 84, 85, 93 6 7 8 13 18 19 20 26 27 28 29 30 31 32 36 37 NAME TEMP VEE Temperature Monitor Output Negative Power-Supply Input FUNCTION GND Ground Connection VCC Positive Power-Supply Input FORCE1 Channel 1 Force Input from External PMU DUT1 SENSE1 GS SENSE2 DUT2 CLV2 CHV2 DLV2 DTV2 DHV2 CPLV2 CPHV2 NCH2 CH2 Channel 1 Device-Under-Test Input/Output. Combined I/O for driver, comparator, clamp, and load. Channel 1 Sense Output to External PMU Ground Sense. GS is the ground reference for LDH_ and LDL_. Channel 2 Sense Output to External PMU Channel 2 Device-Under-Test Input/Output. Combined I/O for driver, comparator, clamp, and load. Channel 2 Low Comparator Reference Input Channel 2 High Comparator Reference Input Channel 2 Driver Low Reference Input Channel 2 Driver Termination Reference Input Channel 2 Driver High Reference Input Channel 2 Low-Clamp Reference Input Channel 2 High-Clamp Reference Input Channel 2 Comparator High Output. Differential output of channel 2 high comparator. Channel 2 Collector Voltage Input. Voltage for channel 2 comparator output pullup resistors. For open-collector outputs, this is the pullup voltage for the internal termination resistors. For openemitter outputs, this is the collector voltage of the output transistors. Not internally connected on open-collector versions without internal termination resistors. Channel 2 Comparator Low Output. Differential output of channel 2 low comparator. Channel 2 Active-Load Commutation Voltage Reference Input Channel 2 Active-Load Source Current Reference Input Channel 2 Active-Load Sink Current Reference Input No Connect. Make no connection. Channel 2 Data Termination Voltage Input. Termination voltage input for the DATA2 and NDATA2 differential inputs. Not internally connected on versions without internal termination resistors. FORCE2 Channel 2 Force Input from External PMU 38 VCCO2 39 40 47 48 49 50, 76 51 52 53 NCL2 CL2 COM2 LDL2 LDH2 N.C. TDATA2 NDATA2 Channel 2 Multiplexer Control Inputs. Differential controls DATA2 and NDATA2 select driver 2’s input from DHV2 or DLV2. Drive DATA2 above NDATA2 to select DHV2. Drive NDATA2 above DATA2 DATA2 to select DLV2. 18 ______________________________________________________________________________________ Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 Pin Description (continued) PIN 54 55 56 57 58 59 61 62 63 64 65 67 68 69 70 71 72 73 74 75 77 78 79 86 87 NAME TRCV2 NRCV2 RCV2 TLDEN2 FUNCTION Channel 2 RCV Termination Voltage Input. Termination voltage input for the RCV2 and NRCV2 differential inputs. Not internally connected on versions without internal termination resistors. Channel 2 Multiplexer Control Inputs. Differential controls RCV2 and NRCV2 place channel 2 into receive mode. Drive RCV2 above NRCV2 to place channel 2 into receive mode. Drive NRCV2 above RCV2 to place channel 2 into drive mode. Channel 2 Load Enable Termination Voltage Input. Termination voltage input for the LDEN2 and NLDEN2 differential inputs. Not internally connected on versions without internal termination resistors. NLDEN2 Channel 2 Multiplexer Control Inputs. Differential controls LDEN2 and NLDEN2 enable/disable the active load. Drive LDEN2 above NLDEN2 to enable the channel 2 active load. Drive NLDEN2 above LDEN2 LDEN2 to disable the channel 2 active load. RST CS THR SCLK DIN Reset Input. Asynchronous reset input for the serial register. RST is active low and asserts low-leakage mode. At power-up, hold RST low until VCC and VEE have stabilized. Chip-Select Input. Serial port activation input. CS is active low. Single-Ended Logic Threshold. Leave THR unconnected to set the threshold to +1.25V or force THR to a desired threshold voltage. Serial-Clock Input. Clock for serial port. Data Input. Serial port data input. Channel 1 Multiplexer Control Inputs. Differential controls LDEN1 and NLDEN1 enable/disable the LDEN1 active load. Drive LDEN1 above NLDEN1 to enable the channel 1 active load. Drive NLDEN1 above NLDEN1 LDEN1 to disable the channel 1 active load. TLDEN1 RCV1 NRCV1 TRCV1 DATA1 Channel 1 Load Enable Termination Voltage Input. Termination voltage input for the LDEN1 and NLDEN1 differential inputs. Not internally connected on versions without internal termination resistors. Channel 1 Multiplexer Control Inputs. Differential controls RCV1 and NRCV1 place channel 1 into receive mode. Drive RCV1 above NRCV1 to place channel 1 into receive mode. Drive NRCV1 above RCV1 to place channel 1 into drive mode. Channel 1 RCV Termination Voltage Input. Termination voltage input for the RCV1 and NRCV1 differential inputs. Not internally connected on versions without internal termination resistors. Channel 1 Multiplexer Control Inputs. Differential controls DATA1 and NDATA1 select driver 1’s input from DHV1 or DLV1. Drive DATA1 above NDATA1 to select DHV1. Drive NDATA1 above NDATA1 DATA1 to select DLV1. TDATA1 LDH1 LDL1 COM1 CL1 NCL1 Channel 1 Data Termination Voltage Input. Termination voltage input for the DATA1 and NDATA1 differential inputs. Not internally connected on versions without internal termination resistors. Channel 1 Active-Load Sink Current Reference Input Channel 1 Active-Load Source Current Reference Input Channel 1 Active Load Commutation Voltage Reference Input Channel 1 Low Comparator Output. Differential output of channel 1 low comparator. ______________________________________________________________________________________ 19 Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 Pin Description (continued) PIN NAME FUNCTION Channel 1 Collector Voltage Input. Voltage for channel 1 comparator output pullup resistors. For open-collector outputs, this is the pullup voltage for the internal termination resistors. For openemitter outputs, this is the collector voltage of the output transistors. Not internally connected on open-collector versions without internal termination resistors. Channel 1 High Comparator High Output. Differential output of channel 1 high-side comparator. Channel 1 High-Clamp Reference Input Channel 1 Low-Clamp Reference Input Channel 1 Driver High Reference Input Channel 1 Driver Termination Reference Input Channel 1 Driver Low Reference Input Channel 1 High-Comparator Reference Input Channel 1 Low-Comparator Reference Input 88 VCCO1 CH1 NCH1 CPHV1 CPLV1 DHV1 DTV1 DLV1 CHV1 CLV1 89 90 94 95 96 97 98 99 100 Detailed Description The MAX9967 dual, low-power, high-speed, pin electronics DCL IC includes, for each channel, a three-level pin driver, a dual comparator, variable clamps, and an active load. The driver features a -1.5V to +6.5V operating range and high-speed operation, includes highimpedance and active-termination (3rd-level drive) modes, and is highly linear even at low voltage swings. The dual comparator provides low dispersion (timing variation) over a wide variety of input conditions. The clamps provide damping of high-speed DUT_ waveforms when the device is configured as a high-impedance receiver. The programmable load supplies up to 35mA of source and sink current. The load facilitates contact/continuity testing, at-speed parametric testing of IOH and IOL, and pullup of high output-impedance devices. The MAX9967A provides tight matching of gain and offset for the drivers and offset for the comparators and active load, allowing reference levels to be shared across multiple channels in cost-sensitive systems. Use the MAX9967B for system designs that incorporate independent reference levels for each channel. Optional internal resistors at the high-speed inputs provide compatibility with ECL, LVPECL, LVDS, and GTL interfaces. Connect the termination voltage inputs (TDATA_, TRCV_, TLDEN_) to the appropriate voltage for terminating ECL, LVPECL, GTL, or other logic. Leave the inputs unconnected for 100 Ω differential LVDS termination. In addition, ECL/LVPECL or flexible open-collector outputs with optional internal pullup resistors are available for the comparators. These features significantly reduce the discrete component count on the circuit board. A 3-wire, low-voltage, CMOS-compatible serial interface programs the low-leakage, load-disable, slew-rate, and tri-state/terminate operational configurations of the MAX9967. Output Driver The driver input is a high-speed multiplexer that selects one of three voltage inputs: DHV_, DLV_, or DTV_. This switching is controlled by high-speed inputs DATA_ and RCV_ and mode control bit TMSEL (Table 1). A slew-rate circuit controls the slew rate of the buffer input. Select one of four possible slew rates according to Table 2. The speed of the internal multiplexer sets the100% driver slew rate (see the Driver Large-Signal Response graph in the Typical Operating Characteristics). 20 ______________________________________________________________________________________ Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 Functional Diagram TEMP CS SCLK DIN RST THR CH_ MODE BITS LLEAK SC0 SC1 TMSEL LDDIS LDCAL VCC VEE SERIAL INTERFACE IS COMMON TO BOTH CHANNELS. MODE BITS INDEPENDENTLY LATCHED FOR EACH CHANNEL. 400Ω DLV_ DHV_ DTV_ OPTIONAL RDATA_ = 5OΩ TDATA_ MULTIPLEXER SLEWRATE CONTROL BUFFER 50Ω DUT_ 10kΩ FORCE_ SENSE_ GND SERIAL INTERFACE SC0 SC1 LLEAK DATA_ NDATA_ RCV_ NRCV_ TMSEL TRCV_ OPTIONAL RRCV_ = 5OΩ OPTIONAL HIGH-Z CPHV_ CLAMPS CPLV_ CHV_ CH_ NCH_ 4 x 50Ω OPTIONAL COMPARATORS VCCO_ CL_ NCL_ CLV_ LDH_ GS VCC SINK (HIGH) CURRENT LLEAK LDCAL LDDIS LDEN_ NLDEN_ RLDEN_ 50Ω OPTIONAL TLDEN_ COM_ LDL_ GS ONE OF TWO IDENTICAL CHANNELS SHOWN ACTIVELOAD CONTROL ACTIVE LOAD SOURCE (LOW) CURRENT VEE ______________________________________________________________________________________ 21 Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load DUT_ can be toggled at high speed between the buffer output and high-impedance mode, or it can be placed into low-leakage mode (Figure 2, Table 1). In highimpedance mode, the clamps are connected. Highspeed input RCV_ and mode control bits TMSEL and LLEAK control the switching. In high-impedance mode, the bias current at DUT_ is less than 1.5µA over the 0 to 3V range, while the node maintains its ability to track high-speed signals. In low-leakage mode, the bias current at DUT_ is further reduced to less than 50nA, and signal tracking slows. See the L ow-Leakage Mode, LLEAK section for more details. The nominal driver output resistance is 50Ω. Contact the factory for different resistance values within the 45Ω to 51Ω range. MAX9967 DUT_ voltage range. The optimal clamp voltages are application specific and must be empirically determined. If clamping is not desired, set the clamp voltages at least 0.7V outside the expected DUT_ voltage range; overvoltage protection remains active without loading DUT_. Comparators The MAX9967 provides two independent high-speed comparators for each channel. Each comparator has one input connected internally to DUT_ and the other input connected to either CHV_ or CLV_ (see the Functional Diagram). Comparator outputs are a logical result of the input conditions, as indicated in Table 3. Three configurations are available for the comparator differential outputs to ease interfacing with a wide variety of logic families. An open-collector configuration switches an 8mA current source between the two outputs. This configuration is available with and without internal termination resistors connected to V CCO_ (Figure 3). For open-collector versions without internal termination, leave V CCO_ unconnected and add the required external resistors. These resistors are typically 50Ω to the pullup voltage at the receiving end of the output trace. Alternate configurations may be used, provided that the Absolute Maximum Ratings are not exceeded. For open-collector versions with internal termination, connect VCCO_ to the desired VOH voltage. Clamps Configure the voltage clamps (high and low) to limit the voltage at DUT_ and to suppress reflections when the channel is configured as a high-impedance receiver. The clamps behave as diodes connected to the outputs of high-current buffers. Internal circuitry compensates for the diode drop at 1mA clamp current. Set the clamp voltages using the external connections CPHV_ and CPLV_. The clamps are enabled only when the driver is in the high-impedance mode (Figure 2). For transient suppression, set the clamp voltages to approximately the minimum and maximum expected HIGHSPEED INPUTS REFERENCE INPUTS 0 0 DHV_ DTV_ 1 1 SLEW RATE BUFFER 0 0 1 50Ω DUT_ DLV_ DATA_ RCV_ HIGH-Z CPHV_ CLAMPS CPLV_ TMSEL LLEAK SC0 SC1 COMPARATORS ACTIVE LOAD MODE 4 Figure 2. Simplified Driver Channel 22 ______________________________________________________________________________________ Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load Table 1. Driver Logic EXTERNAL CONNECTIONS DATA_ 1 0 X X X RCV_ 0 0 1 1 X INTERNAL CONTROL REGISTER TMSEL X X 1 0 X LLEAK 0 0 0 0 1 Drive to DHV_ Drive to DLV_ Drive to DTV_ (term mode) High-impedance (high-z) mode Low-leakage mode DRIVER OUTPUT Table 2. Slew-Rate Logic SC1 0 0 1 1 SC0 0 1 0 1 DRIVER SLEW RATE (%) 100 75 50 25 all of the DAC levels are typically offset by V GS, the operation of the MAX9967’s ground-sense input nullifies this offset with respect to the active-load currents. Connect GS to the ground reference used by the DAC. (VLDL_ - VGS) sets the source current by +10mA/V. (VLDH_ - VGS) sets the sink current by -10mA/V. The high-speed differential input LDEN_ and 3 bits of the control word (LDCAL, LDDIS, and LLEAK) control the load (Table 4). When the load is enabled, the internal source and sink current sources connect to the diode bridge. When the load is disabled, the internal current sources shunt to ground and the top and bottom of the bridge float (see the Functional Diagram). LLEAK places the load in low-leakage mode. LLEAK overrides LDEN_, LDDIS, and LDCAL. See the LowLeakage Mode, LLEAK section for more detailed information. LDDIS and LDCAL In some tester configurations, the load enable is driven with the complement of the driver high-impedance signal (RCV_), so disabling the driver enables the load and vice versa. The LDDIS and LDCAL signals disable and enable the load independently of the state of LDEN_. This allows the load and driver to be simultaneously enabled and disabled for diagnostic purposes (Table 4). MAX9967 Each output provides a nominal 400mVP-P swing and 50Ω source termination. An open-emitter configuration is also available (Figure 4). Connect an external collector voltage to VCCO_ and add external pulldown resistors. These resistors are typically 50Ω to VCCO_ - 2V at the receiving end of the output trace. Alternate configurations may be used provided that the Absolute Maximum Ratings are not exceeded. Low-Leakage Mode, LLEAK Asserting LLEAK through the serial port or with RST places the MAX9967 into a very low-leakage state (see the Electrical Characteristics). The comparators function at full speed, but the driver, clamps, and active load are disabled. This mode is convenient for making IDDQ and PMU measurements without the need for an output disconnect relay. LLEAK is programmed independently for each channel. When DUT_ is driven with a high-speed signal while LLEAK is asserted, the leakage current momentarily increases beyond the limits specified for normal operation. The low-leakage recovery specification in the Electrical Characteristics table indicates device behavior under this condition. Active Load The active load consists of linearly programmable source and sink current sources, a commutation buffer, and a diode bridge (see Functional Diagram). Analog reference inputs LDH_ and LDL_ program the sink and source currents, respectively, within the 0 to 35mA range. Analog reference input COM_ sets the commutation buffer output voltage. The source and sink naming convention is referenced to the device under test. Current out of the MAX9967 constitutes sink current and current into the MAX9967 constitutes source current. The programmed source (low) current loads the device under test when VDUT_ > VCOM_. The programmed sink (high) current loads the device under test when VDUT_ < VCOM_. The GS input allows a single level-setting DAC, such as the MAX5631 or MAX5734, to program the MAX9967’s active load, driver, comparator, and clamps. Although Table 3. Comparator Logic DUT_ > CHV_ 0 0 1 1 DUT_ > CLV_ 0 1 0 1 CH_ 0 0 1 1 CL_ 0 1 0 1 ______________________________________________________________________________________ 23 Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 DUT_ 8mA CH_ CHV_ VEE NCH_ 4 x 50Ω OPTIONAL VCCO_ CL_ 8mA CLV_ VEE NCL_ Figure 3. Open-Collector Comparator Outputs CH_ 106Ω DUT_ CHV_ 106Ω NCH_ VCCO_ CL_ 106Ω CLV_ 106Ω NCL_ Figure 4. Open-Emitter Comparator Outputs 24 ______________________________________________________________________________________ Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 Table 4. Active Load Programming EXTERNAL CONNECTIONS LDEN_ 0 1 X X X INTERNAL CONTROL REGISTER LDCAL 0 0 1 X X LDDIS 0 0 0 1 X LLEAK 0 0 0 0 1 Normal operating mode, load disabled Normal operating mode, load enabled Load enabled for diagnostics Load disabled Low-leakage mode MODE SCLK SHIFT REGISTER 0 1 2 3 4 5 6 7 DIN ENABLE CS F/F 5 7 D ENABLE Q 5 6 D F/F Q ENABLE SET RST SET F/F 0-4 7 D ENABLE Q 0-4 6 5 1 D F/F Q ENABLE 5 1 20kΩ THR VTHRINT = 1.25V LDDIS, LDCAL, TMSEL, SC0, SC1 MODE BITS LLEAK LDDIS, LDCAL, TMSEL, LLEAK SC0, SC1 MODE BITS CHANNEL 2 CHANNEL 1 Figure 5. Serial Interface ______________________________________________________________________________________ 25 Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 tCH SCLK tCSS0 tCL tCSH1 tCSS1 CS tCSWH tOH tDS DIN D7 D6 D5 D4 D3 D2 D1 D0 Figure 6. Serial-Interface Timing Serial Interface and Device Control A CMOS-compatible serial interface controls the MAX9967 modes (Figure 5). Control data flow into an 8bit shift register (MSB first) and are latched when CS is taken high, as shown in Figure 6. Latches contain 6 control bits for each channel of the dual pin driver. Data from the shift register are loaded to either or both of the latches as determined by bits D6 and D7, and indicated in Figure 5 and Table 5. The control bits, in conjunction with external inputs DATA_ and RCV_, manage the fea- tures of each channel, as shown in Tables 1 and 2. RST sets LLEAK = 1 for both channels, forcing them into lowleakage mode. All other bits are unaffected. At powerup, hold RST low until VCC and VEE have stabilized. Analog control input THR sets the threshold for the input logic, allowing operation with CMOS logic as low as 0.9V. Leaving THR unconnected results in a nominal threshold of 1.25V from an internal reference, providing compatibility with 2.5 to 3.3V logic. Table 5. Shift-Register Functions BIT D7 D6 D5 D4 D3 D2 D1 D0 NAME CH1 CH2 LLEAK TMSEL SC1 SC0 LDDIS LDCAL DESCRIPTION Channel 1 Write Enable. Set to 1 to update the control byte for channel 1. Set to 0 to make no changes to channel 1. Channel 2 Write Enable. Set to 1 to update the control byte for channel 2. Set to 0 to make no changes to channel 2. Low-Leakage Select. Set to 1 to put driver, load, and clamps into low-leakage mode. Comparators remain active in low-leakage mode. Set to 0 for normal operation. Driver Termination Select. Set to 1 to force the driver output to the DTV_ voltage when RCV_ = 1 (term). Set to 0 to place the driver into high-impedance mode when RCV_ = 1 (high-Z). See Table 1. Driver Slew-Rate Select. SC1 and SC0 set the driver slew rate. See Table 2. Load Disable. Set LDDIS to 1 to disable the load. Set to 0 for normal operation. See Table 4. Load Calibrate. Overrides LDEN to enable load. Set LDCAL to 1 to enable load. Set LDCAL to 0 for normal operation. See Table 4. 26 ______________________________________________________________________________________ Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load Temperature Monitor The MAX9967 supplies a temperature output signal, TEMP, that asserts a nominal output voltage of 3.43V at a die temperature of +70°C (343K). The output voltage increases proportionately with temperature. through the sink (high) current source and the outside of the diode bridge to the DUT. The programmed source current flows from VCC through the commutation buffer, the inside of the diode bridge, and the source (low) current source to VEE. Theta J-C of the exposed-pad package is very low, approximately 3°C/W to 4°C/W. Die temperature is thus highly dependent upon the heat-removal techniques used in the application. Maximum total power dissipation occurs under the following conditions: • VCC = +10.5V • VEE = -6.5V • ISOURCE = ISINK = 35mA for both channels • Load enabled • VDUT_ = +6.5V • VCOM_ < +5.5V Under these extreme conditions, the total power dissipation is approximately 6W. If the die temperature cannot be maintained at an acceptable level under these conditions, use software clamping to limit the load output currents to lower values and/or reduce the supply voltages. MAX9967 Heat Removal Under normal circumstances, the MAX9967 requires heat removal through the exposed pad by use of an external heat sink. The exposed pad is electrically at VEE potential, and must be either connected to VEE or isolated. Power dissipation is highly dependent upon the application. The Electrical Characteristics Table indicates power dissipation under the condition that the source and sink currents are programmed to 0mA. Maximum dissipation occurs when the source and sink currents are both at 35mA, the VDUT_ is at an extreme of the voltage range (-1.5V or +6.5V), and the diode bridge is fully commutated. Under these conditions, the additional power dissipated (per channel) is: If the DUT is sourcing current, ∆PD = (VDUT_ - VEE) x ISOURCE + (VCC - VEE) x ISINK. If the DUT is sinking current, ∆PD = (VCC - VDUT_) x ISINK + (VCC - VEE) x ISOURCE. The DUT sources the programmed (low) current when VDUT_ > VCOM_. The path of the current is from the DUT through the outside of the diode bridge and the source (low) current source to VEE. The programmed sink current flows from VCC through the sink (high) current source, the inside of the diode bridge, and the commutation buffer to VEE. The DUT sinks the programmed (high) current when VDUT_ < VCOM_. The path of the current is from VCC Chip Information TRANSISTOR COUNT: 5656 PROCESS: Bipolar ______________________________________________________________________________________ 27 Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 Typical Application Circuits (Simplified) RB-RE RCOM REFERENCE INPUT IN RXA RXD FORCE FORCE 400Ω DHV SENSE MAIN AMP 10kΩ CURRENTSENSE AMP PMU DTV DLV ~45Ω DUT DCL TO ADC MSR MAX9949F MAX9950F MAX9967 DRIVER IN LOW-LEAKAGE MODE SENSE INTERFACING TO PMU WITHOUT EXTERNAL RELAYS. PMU SOURCING 2mA OR LESS. REFERENCE INPUTS RB-RE RCOM REFERENCE INPUT IN RXA RXD FORCE FORCE 400Ω DHV DTV DLV PMU SENSE MAIN AMP 10kΩ ~45Ω DUT DCL CURRENTSENSE AMP MSR TO ADC MAX9949F MAX9950F MAX9967 DRIVER = DTV SENSE INTERFACING TO PMU WITHOUT EXTERNAL RELAYS. DCL SOURCING UP TO 60mA. REFERENCE INPUTS 28 ______________________________________________________________________________________ Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load Selector Guide PART MAX9967ADCCQ MAX9967AGCCQ MAX9967ALCCQ MAX9967AMCCQ MAX9967AQCCQ MAX967ARCCQ MAX9967BDCCQ MAX9967BGCCQ MAX9967BLCCQ MAX9967BMCCQ MAX9967BQCCQ MAX9967BRCCQ ACCURACY GRADE A A A A A A B B B B B B COMPARATOR OUTPUT TYPE Open collector Open collector Open collector Open emitter Open emitter Open collector Open collector Open collector Open collector Open emitter Open emitter Open collector COMPARATOR OUTPUT TERMINATION None None 50Ω to VCCO_ ECL/LVPECL ECL/LVPECL 50Ω to VCCO_ None None 50Ω to VCCO_ ECL/LVPECL ECL/LVPECL 50Ω to VCCO_ HIGH-SPEED DIGITAL INPUT TERMINATION RCV_ None 100 100 None 100 None None 100 100 None 100 None DATA_ None 100 100 None 100 100 None 100 100 None 100 100 LDEN_ None 100 100 None 100 100 None 100 100 None 100 100 Top Top Top Top Top Top Top Top Top Top Top Top HEAT EXTRACTION MAX9967 ______________________________________________________________________________________ 29 Dual, Low-Power, 500Mbps ATE Driver/Comparator with 35mA Load MAX9967 Pin Configuration CPLV1 CPHV1 VCCO1 CHV1 DHV1 COM1 NCH1 NCL1 DTV1 CLV1 DLV1 LDL1 GND LDH1 77 GND GND CL1 VEE 100 99 TEMP VEE GND VCC GND FORCE1 DUT1 SENSE1 VEE 1 2 3 4 5 6 7 8 9 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 76 75 TDATA1 74 NDATA1 73 DATA1 72 TRCV1 71 NRCV1 70 RCV1 69 TLDEN1 68 NLDEN1 67 LDEN1 66 VCC 65 DIN 64 SCLK 63 THR GND 10 VCC 11 VEE 12 GS 13 VEE 14 VCC 15 GND 16 VEE 17 SENSE2 18 DUT2 19 FORCE2 20 GND 21 VCC 22 GND 23 VEE 24 GND 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MAX9967 N.C. 62 CS 61 RST 60 VEE 59 LDEN2 58 NLDEN2 57 TLDEN2 56 RCV2 55 NRCV2 54 TRCV2 53 DATA2 52 NDATA2 51 TDATA2 CH1 VCC VCC VCC VEE VEE CPHV2 CPLV2 Package Information For the latest package outline information, go to www.maxim-ic.com/packages. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. COM2 NCH2 DHV2 NCL2 CHV2 VCCO2 LDH2 DTV2 LDL2 CH2 DLV2 GND GND GND CLV2 N.C. CL2 VEE VEE VCC VCC VCC VEE