MAX9974GCCB

19-0690; Rev 0; 1/07 Dual Driver/Comparator/Load with Internal DACs General Description The MAX9973/MAX9974 fully integrated, high-performance, dual-channel pin electronics driver/comparator/load (DCL) with built-in level-setting digital-to-analog converters (DACs) are ideally suited for memory and SOC automatic test equipment (ATE) applications. Each channel includes a three-level pin driver, a window comparator, dynamic clamps, a 1kΩ load, and seven independent level-setting DACs. The driver features a wide voltage range and high-speed operation, includes high-impedance and active-termination (3rd-level drive) modes, and is highly linear even at low voltage swings. Additionally, the driver provides highspeed differential multiplexer control inputs, with internal termination resistors that are compatible with ECL, LVPECL, LVDS, and GTL. The window comparators provide extremely low timing variation over changes in slew rate, pulse width, or overdrive voltage, and have open-collector outputs. When high-impedance mode is selected, the dynamic clamps provide damping of high-speed deviceunder-test (DUT) waveforms. The load facilitates fast contact testing when used in conjunction with the comparators, and functions as a pullup for open-drain/collector DUT_ outputs. The MAX9973/ MAX9974 are configured through a serial interface. The MAX9973/MAX9974 differ in two aspects: the position of the exposed heat slug and the pin arrangement. The MAX9973G/MAX9974G comparator outputs sink 8mA (typ), while the MAX9973H/MAX9974H comparator outputs sink 16mA (typ). The devices are available in a 64-pin (10mm x 10mm x 1.00mm) TQFP-EP package with an exposed paddle on top (MAX9973) or bottom (MAX9974) for heat removal. Power dissipation is only 700mW per channel. The full operating voltage range is -1.5V to +6.5V. Operation is specified at an internal die temperature of +40°C to +100°C, and features a temperature monitor output. o 600Mbps at 3V High Speed o 700mW per Channel Extremely Low Power Dissipation o -1.5V to +6.5V Wide Voltage Range o 200mV to 8V Wide Voltage Swing Range o 10nA (max) Low-Leakage Mode o Integrated Termination On-the-Fly (3rd-Level Drive) o Integrated Voltage Clamps o Passive Load or Pullup o Very Low Timing Dispersion o Minimal External Component Count o SPITM-Compatible Serial Control Interface Features MAX9973/MAX9974 Ordering Information PART PIN-PACKAGE PKG CODE OUTPUT SINK CURRENT MAX9973GCCB 64 TQFP-EP-IDP** (10mm x 10mm x C64E-13R 1.00mm) 64 TQFP-EP-IDP** (10mm x 10mm x C64E-13R 1.00mm) 64 TQFP-EP† (10mm x 10mm x 1.00mm) 64 TQFP-EP† (10mm x 10mm x 1.00mm) 8mA MAX9973HCCB* 16mA MAX9974GCCB* — 8mA Applications Memory Testers SOC Testers MAX9974HCCB* — 16mA Note: Devices are available in both leaded and lead-free packages. Specify lead free by adding a + symbol at the end of the part number when ordering. *Future product—contact factory for availability. **EP-IDP = Exposed paddle (inverted die paddle). †EP = Exposed paddle. SPI is a trademark of Motorola Inc. Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 ABSOLUTE MAXIMUM RATINGS VCC to GND ............................................................-0.3V to +11V VEE to GND...............................................................-6V to +0.3V VCC - VEE ................................................................-0.3V to +17V VDD to GND ..............................................................-0.3V to +5V VT0, VT1 to GND .......................................................-0.3V to +5V DGS to GND .......................................................................±0.7V DUT_ to GND.........................................................-2.5V to +7.5V DATA_, NDATA_, RCV_, NRCV_ to GND .................-2.5V to +5V DATA_ to NDATA_, RCV_ to NRCV_ .....................................±1V DATA_, NDATA_, RCV_, NRCV_ to VTERM_......................±1.5V SCLK, DIN, CS, RST, LOAD to GND .........-0.3V to (VDD + 0.3V) TEMP to GND ...........................................................-0.2V to +5V All Other Pins to GND ......................(VEE - 0.3V) to (VCC + 0.3V) DUT_ Short Circuit to -1.5V to +6.5V..........................Continuous Power Dissipation (TA = +70°C) MAX997_GCCB (derate 125mW/°C above +70°C)......10.0W* Storage Temperature Range .............................-65°C to +150°C Junction Temperature .....................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C *Dissipation wattage values are based on still air with no heat sink. Actual maximum power dissipation is a function of heat extraction technique and may be substantially higher. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +9.75V, VEE = -4.75V, VDD = 3.3V, VDHV_ = +3V, VDLV_ = 0, VDTV_ = +1.5V, SC1 = SC0 = 0, VCHV_ = +2.0V, VCLV_ = +1.0V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VVTERM = VT_ = +1.8V, RT = 50Ω || 1pF, TJ = +70°C, unless otherwise noted. All temperature coefficients are measured at TJ = +40°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER DRIVER DC CHARACTERISTICS (RL ≥ 10MΩ, unless otherwise noted; includes DAC error) VDHV_ Output Voltage Range VDLV_ VDTV_ VDHV_ Output Offset Voltage Output-Voltage Temperature Coefficient (Notes 2, 3) VDHV_ Gain VDLV_ VDTV_ VDLV_ VDTV_ VDLV_ = -1.5V, VDTV_ = +1.5V VDHV_ = +6.5V, VDTV_ = +1.5V VDHV_ = +6.5V, VDLV_ = -1.5V VDHV_ = +3V, VDLV_ = -1.5V, VDTV_ = +1.5V VDLV_ = 0V, VDHV_ = +6.5V, VDTV_ = +1.5V VDTV_ = +1.5V, VDHV_ = +6.5V, VDLV_ = -1.5V DHV_, DLV_, DTV_ VDLV_ = -1.5V, VDTV_ = +1.5V, VDHV_ = 0 and +4.5V VDHV_ = +6.5V, VDTV_ = +1.5V, VDLV_ = 0 and +4.5V VDHV_ = +6.5V, VDLV_ = -1.5V, VDTV_ = 0 and +4.5V 0.998 0.998 0.998 ±75 1 1 1 -1.45 -1.50 -1.50 +6.50 +6.45 +6.50 ±50 ±50 ±50 ±400 1.002 1.002 1.002 V/V µV/°C mV V SYMBOL CONDITIONS MIN TYP MAX UNITS 2 _______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -4.75V, VDD = 3.3V, VDHV_ = +3V, VDLV_ = 0, VDTV_ = +1.5V, SC1 = SC0 = 0, VCHV_ = +2.0V, VCLV_ = +1.0V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VVTERM = VT_ = +1.8V, RT = 50Ω || 1pF, TJ = +70°C, unless otherwise noted. All temperature coefficients are measured at TJ = +40°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS VDLV_ = -1.5V, VDTV_ = +1.5V, VDHV_ = 0, +0.75V, +1.5V, +2.25V, +3V VDHV_ = +6.5V, VDTV_ = +1.5V, VDLV_ = 0, +0.75V, +1.5V, +2.25V, +3V VDLV_ = -1.5V, VDHV_ = +6.5V, VDTV_ = 0, +0.75V, +1.5V, +2.25V, +3V VDLV_ = -1.5V, VDTV_ = +1.5V, VDHV_ = -1.25V and +6.5V VDHV_ = +6.5V, VDTV_ = +1.5V, VDLV_ = -1.5V and +6.25V VDLV_ = -1.5V, VDHV_ = +6.5V, VDTV_ = -1.5V and +6.5V MIN TYP MAX ±5 UNITS MAX9973/MAX9974 0 to 3V relative to calibration points at 0 and 3V Linearity Error ±5 ±5 mV Full range relative to calibration points at 0 and 3V ±5 ±5 ±5 ±2 ±2 ±2 ±3 ±3 ±2 40 40 40 -120 +60 -120 +60 48 50 -60 +120 -60 +120 52 Ω mA dB mV mV VDHV_ to VDLV, VDLV_ = 0, VDTV_ = 1.5V, VDHV_ = 0.2V and 6.5V VDLV_ to VDHV, VDHV_ = +5V, VDTV_ = +1.5V, VDLV_ = -1.5V and +4.8V Crosstalk VDTV_ to VDLV_ and VDHV, VDHV_ = +3V, VDLV_ = 0, VDTV_ = -1.5V and +6.5V VDHV_ to VDTV, VDTV_ = +1.5V, VDLV_ = 0, VDHV_ = +1.6V and +3.0V VDLV_ to VDTV, VDTV_ = +1.5V, VDHV_ = +3V, VDLV_ = 0 and +1.4V Term Voltage Dependence on DATA_ VDTV_ = +1.5V, VDHV_ = +3V, VDLV_ = 0, DATA_ = 0 and 1 VDHV_, VDHV_ = 3V, VCC and VEE independently varied over full range DC Power-Supply Rejection VDLV_, VDLV_ = 0, VCC and VEE independently varied over full range VDTV_, VDTV_ = 1.5V, VCC and VEE independently varied over full range VDLV_/VDUT_ = -1.5V/+6.5V, DATA_ = 0 DC Drive Current Limit VDHV_/VDUT_ = +6.5V/-1.5V, DATA_ = 1 VDTV_/VDUT_ = -1.5V/+6.5V, RCV_ = 1 VDTV_/VDUT_ = +6.5V/-1.5V, RCV_ = 1 DC Output Resistance (Note 4) _______________________________________________________________________________________ 3 Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -4.75V, VDD = 3.3V, VDHV_ = +3V, VDLV_ = 0, VDTV_ = +1.5V, SC1 = SC0 = 0, VCHV_ = +2.0V, VCLV_ = +1.0V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VVTERM = VT_ = +1.8V, RT = 50Ω || 1pF, TJ = +70°C, unless otherwise noted. All temperature coefficients are measured at TJ = +40°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS DATA_ = 1, VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V, IDUT_ = 1mA to 40mA DATA_ = 0, VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V, IDUT_ = -1mA to -40mA (Note 6) VDLV_ = 0, VDHV_ = 0.1V Drive-Mode Overshoot VDLV_ = 0, VDHV_ = 1V (Note 2) VDLV_ = 0, VDHV_ = 3V (Note 2) VDLV_ = 0, VDHV_ = 5V (Note 2) Termination-Mode Overshoot Settling Time (Note 8) TIMING CHARACTERISTICS (Notes 5, 9) Data to output; VDHV_ = 3V, VDLV_ = 0 Prop Delay (Note 2) Drive to high impedance, high impedance to drive (Note 10); VDHV_ = +1V, VDLV_ = -1V Drive to term Term to drive Prop Delay Match (Note 2) Prop-Delay Temperature Coefficient tLH vs. tHL Drivers within package; same edge (Note 2) VDHV_ = 1V, VDLV_ = 0, 2ns to 23ns pulse width Prop Delay Change vs. Pulse Width (Note 2) VDHV_ = 3V, VDLV_ = 0, 3ns to 22ns pulse width VDHV_ = 5V, VDLV_ = 0, 4ns to 21ns pulse width Prop Delay Change vs. Common Mode VDHV_ - VDLV_ = 1V, VDHV_ = 0 to 6V, (using a DC block) Drive to high impedance vs. high impedance to drive; VDHV_ = 1V, VDLV_ = -1V (Note 11) Delay Match High impedance vs. data (Note 2) Drive to term vs. term to drive; VDHV_ = 3V, VDL V_ = 0, VDT V_ = 1.5V ( Note 12) Terminate vs. data 2 1.7 2.7 1.7 50 40 1 10 10 20 25 0.2 0.4 1 0.7 ns 3 4 4 4 100 100 5 100 100 100 ps ps ps ps/°C ns (Note 7) To within 100mV, VDHV_ = 5V, VDLV_ = 0 To within 50mV, VDHV_ = 3V, VDLV_ = 0 To within 25mV, VDHV_ = 0.5V, VDLV_ = 0 MIN TYP 1 1 MAX 2 Ω 2 UNITS DC Output Resistance Variation AC CHARACTERISTICS (RDUT_ = 50Ω to ground) (Note 5) Dynamic Drive Current 60 30 40 50 50 0 0.25 0.25 0.25 ns 75 175 275 mV mV mA 4 _______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -4.75V, VDD = 3.3V, VDHV_ = +3V, VDLV_ = 0, VDTV_ = +1.5V, SC1 = SC0 = 0, VCHV_ = +2.0V, VCLV_ = +1.0V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VVTERM = VT_ = +1.8V, RT = 50Ω || 1pF, TJ = +70°C, unless otherwise noted. All temperature coefficients are measured at TJ = +40°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS 0.2VP-P programmed, VDHV_ = 0.2V, VDLV_ = 0, 20% to 80% 1VP-P programmed, VDHV_ = 1V, VDLV_ = 0, 10% to 90% 3VP-P programmed, VDHV_ = 3V, VDLV_ = 0, 10% to 90%, trim condition 5VP-P programmed VDHV_ = 5V, VDLV_ = 0, 10% to 90% 0.2VP-P programmed, VDHV_ = 0.2V, VDLV_ = 0, 20% to 80% 1VP-P programmed, VDHV_ = 1V, VDLV_ = 0, 10% to 90% 3VP-P programmed, VDHV_ = 3V, VDLV_ = 0, 10% to 90 5VP-P programmed, VDHV_ = 5V, VDLV_ = 0, 10% to 90% (Note 2) SC1 = 0, SC0 = 1, VDHV_ = 3V, VDLV_ = 0, 20% to 80% Slew Rate Relative to SC1 = SC0 = 0 SC1 = 1, SC0 = 0, VDHV_ = 3V, VDLV_ = 0, 20% to 80% SC1 = 1, SC0 = 1, VDHV_ = 3V, VDLV_ = 0, 20% to 80% 0.2VP-P programmed, VDHV_ = 0.2V, VDLV_ = 0 Positive or negative 1VP-P programmed VDHV_ = 1V, VDLV_ = 0 (Note 2) 3VP-P programmed VDHV_ = 3V, VDLV_ = 0 (Note 2) 5VP-P programmed VDHV_ = 5V, VDLV_ = 0 (Note 2) 0.2VP-P programmed, VDHV_ = 0.2V, VDLV_ = 0 Data Rate (Note 14) 1VP-P programmed, VDHV_ = 1V, VDLV_ = 0 3VP-P programmed, VDHV_ = 3V, VDLV_ = 0 5VP-P programmed, VDHV_ = 5V, VDLV_ = 0 Rise and Fall Time, Drive to Term Rise and Fall Time, Term to Drive VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V, measured 10% to 90% of waveform VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V, measured 10% to 90% of waveform 75 50 25 0.4 0.7 1.5 2.4 2900 1300 600 400 1.6 0.7 ns ns Mbps 2 ns 2.5 3.5 % 0.35 1.0 MIN TYP 0.20 0.50 1.2 2.0 40 150 ps 200 250 0.75 ns 1.5 MAX UNITS Rise and Fall Time Rise and Fall Time Matching Minimum Pulse Width (Note 13) _______________________________________________________________________________________ 5 Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -4.75V, VDD = 3.3V, VDHV_ = +3V, VDLV_ = 0, VDTV_ = +1.5V, SC1 = SC0 = 0, VCHV_ = +2.0V, VCLV_ = +1.0V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VVTERM = VT_ = +1.8V, RT = 50Ω || 1pF, TJ = +70°C, unless otherwise noted. All temperature coefficients are measured at TJ = +40°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER COMPARATOR DC CHARACTERISTICS Input Voltage Range Differential Input Voltage Minimum Hysteresis Maximum Hysteresis Input Offset Voltage Input-Voltage Temperature Coefficient Common-Mode Rejection Ratio Linearity Error, 0 to 3V Linearity Error, Full Range Power-Supply Rejection Ratio Minimum Pulse Width Prop Delay Prop-Delay Temperature Coefficient Prop Delay Match Prop Delay Dispersion vs. Common-Mode Input Prop Delay Dispersion vs. Pulse Width (Note 2) Prop Delay Dispersion vs. Slew Rate (Note 2) High/low vs. low/high; absolute value of delta for each comparator (Note 2) Common-mode input -1.4V to +6.4V (Note 22) 3ns to 22ns pulse width, 500ps tRISE, positive and negative pulses 2ns to 23ns pulse width Slew rate = 0.5V/ns to 2V/ns 100mV < VC_V_ < 900mV, driver in term mode, peak-to-peak within this window Waveform Tracking (Note 23) 50mV < VC_V__ < 950mV, driver in term mode, peak-to-peak within this window 100mV < VC_V_ < 900mV, driver in high impedance, peak-to-peak within this window LOGIC OUTPUTS (CH_, NCH_, CL_, NCL_) Termination Voltage Output Voltage Compliance Differential Rise Time Differential Fall Time V T_ Set by IOUT, RTERM, and VT_ 20% to 80% (Note 2) 20% to 80% (Note 2) 0 -0.5 200 200 3.5 VT_ 400 400 V V ps ps PSRR AC CHARACTERISTICS (Notes 17–20) (Note 21) 0.85 1.2 2.6 40 20 10 10 10 40 60 100 ps 60 100 ps 2 5 100 ns ns ps/°C ps ps CMRR RHYST_ = open RRHYST_ = 2.5kΩ VDUT_ = 1.5V (Notes 2, 15) VDUT_ = -1.5V, +6.5V VDUT_ = 0, 1.5V, 3V (Note 16) VDUT_ = -1.5V, 0, +1.5V, +3V, +6.5V (Note 16) VDUT_ = -1.5V and +6.5V 50 50 ±75 70 ±1 ±1 75 ±5 ±10 0 10 ±50 ±400 -1.5 +6.5 ±8 V V mV mV mV µV/°C dB mV mV dB SYMBOL CONDITIONS MIN TYP MAX UNITS ps 6 _______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -4.75V, VDD = 3.3V, VDHV_ = +3V, VDLV_ = 0, VDTV_ = +1.5V, SC1 = SC0 = 0, VCHV_ = +2.0V, VCLV_ = +1.0V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VVTERM = VT_ = +1.8V, RT = 50Ω || 1pF, TJ = +70°C, unless otherwise noted. All temperature coefficients are measured at TJ = +40°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER Termination Resistor Value Output High Voltage Output Low Voltage Output Voltage Swing DYNAMIC CLAMPS CPHV_; IDUT_ = -1mA, CPHV_ = -0.4V and +6.6V, CPLV_ = -1.5V CPLV_; IDUT_ = 1mA, CPLV_ = -1.6V and +5.4V, CPHV_ = +6.5V IDUT_ = 0mA (Note 24) IDUT_ = 0mA (Note 24) IDUT_ = -1mA, CPHV_ = +1.5V, CPLV_ = -1.5V IDUT_ = +1mA, CPLV_ = +1.5V, CPHV_ = +6.5V 0.5 IDUT_ = -1mA, CPHV_ = +1.5V, CPLV_ = -1.5V IDUT_ = +1mA, CPLV_ = +1.5V, CPHV_ = +6.5V CPHV_ = 0, +6.5V, CPLV_ = -1.5V CPLV_ = -1.5V, +5.3V, CPHV_ = +6.5V 40 40 0.99 0.99 1.01 1.01 1 100 IDUT_ = -1mA, CPHV_ = 0, +1.5V, +3.25V, +5V, +6.5V IDUT_ = +1mA, CPLV_ = -1.5V, +0.5V, +2.25V, +4V, +5.3V CPHV_ = 0, CPLV_ = -1.5V, RL = 0Ω to +6.5V CPLV_ = +5V, CPHV_ = +6.5V, RL = 0Ω to -1.5V High clamp, VCPHV_ = 2.5V, IDUT_ = -5mA and -15mA Low clamp, VCPLV_ = 2.5V, IDUT_ = 5mA and 15mA High clamp, IDUT_ = -20mA and -30mA, CPHV_ = +2.5V, CPLV_ = -1.5V Low clamp, IDUT_ = 20mA and 30mA, CPLV_ = 2.5V, CPHV_ = 6.5V -120 60 48 48 ±5 Ω ±5 ±30 mV ±30 -60 120 55 Ω 55 mA -0.3 -1.5 7.2 7.5 -2.5 -2.2 ±50 ±50 +6.5 V +5.3 V V mV mV/°C dB V/V V/V % ppm/°C SYMBOL CONDITIONS VT_ to CH_, NCH_, CL_, NCL_ VT_ = 0, 3.5V VT_ = 0, 3.5V VT_ = 0, 3.5V MIN 48 VT_ - 0.1 VT_ - 0.55 350 VT_ - 0.02 VT_ - 0.4 400 TYP MAX 52 VT_ VT_ - 0.35 450 UNITS Ω V V mV Functional Clamp Range Maximum Programmable CPHV_ Minimum Programmable CPLV_ Offset Voltage Offset-Voltage Temperature Coefficient Power-Supply Rejection High-Clamp Voltage Gain Low-Clamp Voltage Gain Voltage Gain Matching Voltage-Gain Temperature Coefficient Linearity Static Output Current DC Impedance DC Impedance Variation (Note 25) _______________________________________________________________________________________ 7 Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -4.75V, VDD = 3.3V, VDHV_ = +3V, VDLV_ = 0, VDTV_ = +1.5V, SC1 = SC0 = 0, VCHV_ = +2.0V, VCLV_ = +1.0V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VVTERM = VT_ = +1.8V, RT = 50Ω || 1pF, TJ = +70°C, unless otherwise noted. All temperature coefficients are measured at TJ = +40°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER Overshoot and Undershoot LEVEL-SETTING DACs Resolution Differential Nonlinearity Voltage Settling Time GROUND SENSE (DGS) Input Range Gain Input Resistance Reference Input 1k TRI-STATE LOAD (PULLUP/PULLDOWN) Source Impedance When Enabled Maximum Source Current Maximum Sink Current Turn-On Time Turn-Off Time Offset Voltage Linearity Error TEMPERATURE MONITOR Nominal Voltage Temperature Coefficient Output Resistance DIFFERENTIAL CONTROL INPUTS (DATA_, NDATA_, RCV_, NRCV_) Input High Voltage Input Low Voltage Differential Input Voltage Termination Resistor VTERM_ Voltage Range 50Ω to VTERM_ Verified by functional test -1.6 -2.0 ±0.15 48 -2.0 2/3 (VDD) -0.1 +3.5 +3.1 ±1.00 52 +3.5 V V V Ω V TJ = +70°C, RL ≥ 10MΩ 3.43 10 15 V mV/°C kΩ Output with no load, VDTV_ = 0 and 3V No load, VDTV_ = -1.5V to +6.5V (Note 27) Tested at -5mA, 0, +5mA using a 0.5mA step VDUT_ = +6.1V, VDTV_ = -1.1V VDUT_ = -1.1V, VDTV_ = +6.1V 1 2.5 VGS Relative to AGND_, verified by functional test -250 1 +250 mV V/V MΩ V N DNL Full-scale change to ±2.5mV 20 DHV_, DLV_, DTV_, CHV_, CLV_ CPLV_, CPHV_ 16 12 ±1 Bits mV µs SYMBOL (Note 26) CONDITIONS MIN TYP 650 MAX UNITS mV 950 6.9 6.9 7.2 7.2 60 60 1050 Ω mA mA ns ns ±50 ±25 mV mV SERIAL PORT INPUTS (CS, SCLK, DIN, RST, LOAD, VDD = 3.3V) Input High Input Low VDD 1/3 (VDD) V V 8 _______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -4.75V, VDD = 3.3V, VDHV_ = +3V, VDLV_ = 0, VDTV_ = +1.5V, SC1 = SC0 = 0, VCHV_ = +2.0V, VCLV_ = +1.0V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VVTERM = VT_ = +1.8V, RT = 50Ω || 1pF, TJ = +70°C, unless otherwise noted. All temperature coefficients are measured at TJ = +40°C to +100°C, unless otherwise noted.) (Note 1) PARAMETER SERIAL PORT TIMING (Note 28) SCLK Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Low to SCLK High Setup SCLK High to CS Low Hold CS High to SCLK High Setup SCLK High to CS High Hold DIN to SCLK High Setup DIN to SCLK High Hold CS High Pulse Width LOAD Low Pulse Width RST Low Pulse Width CS High to LOAD Low Hold Time COMMON FUNCTIONS Operating Voltage Range DUT_ High-Impedance Leakage (Note 29) 0 < VDUT_ < 3V VCLV_ = VCHV_ = +6.5V, VDUT_ = -1.5V VCLV_ = VCHV_ = -1.5V, VDUT_ = +6.5V LEAK = 1, 0 < VDUT_ < 3V, TJ < +90°C DUT_ Low-Leakage Mode Leakage LEAK = 1, VCLV_ = VCHV_ = +6.5V, VDUT_ = -1.5V, TJ < +90°C LEAK = 1, VCLV_ = VCHV_ = -1.5V, VDUT_ = +6.5V, TJ < +90°C DUT_ Combined Capacitance POWER SUPPLY Positive Supply Voltage Negative Supply Voltage Logic Supply Voltage Positive Supply Current Negative Supply Current Logic Supply Current Power Dissipation Power Dissipation per Channel VCC VEE VDD ICC IEE IDD (Note 30) (Note 30) (Note 30) (Notes 30, 31) (Notes 30, 31) 9.5 -5.2 2.7 9.75 -4.75 3.3 70 150 1.2 1.4 700 10.5 -4.5 5.0 85 180 2 1.7 V V V mA mA mA W mW Driver in terminate mode Driver in high impedance -10 -10 -10 2 4 -1.5 +6.5 ±2 ±5 ±5 +10 +10 +10 pF nA µA V t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 8 8 3.5 3.5 3.5 3.5 3.5 3.5 20 20 20 20 50 MHz ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS MAX9973/MAX9974 Note 1: Note 2: All minimum and maximum specifications are 100% production tested, unless otherwise noted. All other test limits are guaranteed by design. Tests are performed at nominal supply voltages, unless otherwise noted. Tested with TJ = +70°C with accuracy of ±15°C. Guaranteed by design and characterization. _______________________________________________________________________________________ 9 Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 ELECTRICAL CHARACTERISTICS (continued) (VCC = +9.75V, VEE = -4.75V, VDD = 3.3V, VDHV_ = +3V, VDLV_ = 0, VDTV_ = +1.5V, SC1 = SC0 = 0, VCHV_ = +2.0V, VCLV_ = +1.0V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VVTERM = VT_ = +1.8V, RT = 50Ω || 1pF, TJ = +70°C, unless otherwise noted. All temperature coefficients are measured at TJ = +40°C to +100°C, unless otherwise noted.) (Note 1) Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: Note 17: Note 18: Note 19: Note 20: Note 21: Note 22: Note 23: Note 24: Note 25: Note 26: Note 27: Note 28: Note 29: Change in any voltage over operating range. Includes both gain and offset temperature effects. Simulated over entire operating range. Verified at worst-case points, which are the endpoints. VDHV_ - VDLV_ > 250mV. DATA_ = 1, VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V, IOUT = ±30mA. Different values within the range of 48Ω to 52Ω are available by custom trimming (contact factory). Rise time of the differential inputs DATA_ and RCV_ is 250ps (10% to 90%). SC1 = SC0 = 0, 40MHz, unless otherwise specified. 0 to 6V step, current supplied for a minimum of 10ns. VDTV_ = 1.5V, RS = 50Ω external signal driven into a transmission line to produce a 0/3V edge at the comparator input with ≤ 1.0ns rise time (10% to 90%). Measurement point is at comparator input. Measured from the 90% point of the driver output (relative to its final value) to the waveform settling to within the specified limit. Propagation delays are measured from the crossing point of the differential input signals to the 50% point of expected output swing. Measured from crossing point of RCV_/NRCV_ to 50% point of the output waveform. Four measurements are made: DHV_ to high impedance, DLV_ to high impedance, high impedance to DHV_, high impedance to DLV_. The worst difference is specified. Four measurements are made: DHV_ to DTV_, DLV_ to DTV_, DTV_ to DHV_, DTV_ to DLV_. The worst difference is specified. At this pulse width, the output reaches at least 95% of its nominal (DC) amplitude. The pulse width is measured at DATA_ and NDATA_. Maximum data rate in transitions/second. A waveform that reaches at least 95% of its programmed amplitude may be generated at one-half of this frequency. Change in offset at any voltage over operating range. Includes both gain (CMRR) and offset temperature effects. Relative to straight line between 0 and 3V. All propagation delays measured from VDUT_ crossing calibrated CHV_/CLV_ threshold to crossing point of differential outputs. Load is a 500ps transmission line terminated with 1pF and 50Ω. All AC specifications are measured with DUT_ (comparator input) as the reference. 40MHz, 0 to 2V input to comparator, reference = 1V, 50% duty cycle, 1ns rise/fall time, ZS = 50Ω, driver in term mode with VDTV_ = 0, unless otherwise noted. At this pulse width, the output reaches at least 90% of its nominal peak-to-peak swing. The pulse width is measured at the crossing points of the differential outputs. 500ps rise and fall time. Timing specs are not guaranteed. VDUT_ = 200mVP-P, rise/fall time = 150ps, overdrive = 100mV, VDTV_ = VCM. Valid for common-mode ranges where the signal does not exceed the operating range. Specification is worst case (slowest to fastest) over the specified range. Input to comparator is 40MHz at 0 to 1V, 50% duty cycle, 1ns rise time. This specification is implicitly tested, by meeting the high-impedance leakage specification. Resistance measurements are made using small-signal voltage changes in the loading instrument. Absolute value of the difference in measured resistance over the specified range, tested separately for each current polarity. Ripple in the DUT_ signal after one round-trip delay. Stimulus is 0 to 3V, 2.5V/ns square wave from far end of 3ns transmission line with RS = 25Ω, clamps set to 0 and 3V. Any deviation from 2.5V affects offset and gain of all levels. Serial port timing specifications are measured at a logic supply voltage (VDD) of +3.3V, ensuring operation of the serial port at rated speed for VDD from +3.3V to +5.5V. The maximum usable output operating voltage is limited to -1.5V to +6.5V. Externally forced voltages may exceed this range without damage to the device, provided that they are limited per the Absolute Maximum Ratings. External clamps must be provided to limit voltages in this range, or damage to the device is likely. Total for dual device. RL ≥ 10MΩ. Worst case of the following conditions: driver enabled, LLEAK = 0; driver disabled, LLEAK = 0; driver enabled, RCV_ = 1; driver disabled, LLEAK = 1. Excludes dissipation of comparator output supply. A typical output configuration and V+ = 1.8V adds 30mW (typ) per channel to device power. Note 30: Note 31: 10 ______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs Typical Operating Characteristics (TJ = +70°C, unless otherwise noted.) DRIVER SMALLSIGNAL RESPONSE MAX9973 toc01 MAX9973/MAX9974 DRIVER LARGESIGNAL RESPONSE VDLV_ = 0 RL = 50Ω VDHV_ = 5V VDUT_ = 500mV/div MAX9973 toc02 DRIVER 3V TRAILING-EDGE TIMING ERROR vs. PULSE WIDTH MAX9973 toc03 VDLV_ = 0 R L = 5 0Ω VDHV_ = 500mV VDUT_ = 50mV/div 80 60 TIMING ERROR (ps) 40 NEGATIVE PULSE 20 0 -20 -40 -60 POSITIVE PULSE NORMALIZED AT PW = 12.5ns PERIOD = 25ns, VDHV_ = +3V, VDLV_ = 0 0 5 10 15 20 VDHV_ = 3V VDHV_ = 200mV VDHV_ = 1V 0 VDHV_ = 100mV 0 t = 2.0ns/div t = 2.0ns/div 25 PULSE WIDTH (ns) DRIVER 1V TRAILING-EDGE TIMING ERROR vs. PULSE WIDTH MAX9973 toc04 DRIVER TIME DELAY vs. COMMON-MODE VOLTAGE NORMALIZED AT VCM = +1.5V MAX9973 toc05 DRIVE TO TERM TRANSITION DHV_ TO DTV_ MAX9973 toc06 50 40 30 TIMING ERROR (ps) 20 10 0 -10 -20 -30 -40 -50 0 NORMALIZED AT PW = 12.5ns PERIOD = 25ns, VDHV_ = +1V, VDLV_ = 0 5 10 15 20 POSITIVE PULSE NEGATIVE PULSE 50 40 30 20 10 0 -10 -20 FALLING EDGE VDUT_ = 250mV/div TIME DELAY (ps) DLV_ TO DTV_ RISING EDGE 0 2 3 4 5 6 t = 2.0ns/div RL = 5 0 Ω VDHV_ = 3.0V VDTV_ = 1.5V VDLV_ = 0 25 -1 0 1 PULSE WIDTH (ns) COMMON-MODE VOLTAGE (V) DRIVE TO HIGH IMPEDANCE TRANSITION MAX9973 toc07 DRIVER LINEARITY ERROR vs. OUTPUT VOLTAGE MAX9973 toc08 DRIVER LINEARITY ERROR vs. OUTPUT VOLTAGE 1.5 LINEARITY ERROR (mV) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 DUT_ = DLV_ VDHV_ = +6.5V VDTV_ = 0 MAX9973 toc09 2.0 1.5 LINEARITY ERROR (mV) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 DHV_ TO HIGH IMPEDANCE DUT_ = DHV_ VDLV_ = -1.5V VDTV_ = 0 2.0 VDUT_ = 200mV/div 0 RL = 50Ω VDHV_ = +1V VDLV_ = -1V DLV_ TO HIGH IMPEDANCE t = 2.0ns/div -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 VDUT_ (V) VDUT_ (V) ______________________________________________________________________________________ 11 Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 Typical Operating Characteristics (continued) (TJ = +70°C, unless otherwise noted.) DRIVER LINEARITY ERROR vs. OUTPUT VOLTAGE MAX9973 toc10 DRIVER GAIN vs. TEMPERATURE MAX9973 toc11 DRIVER OFFSET vs. TEMPERATURE NORMALIZED AT TJ = +70°C 2.0 1.5 OFFSET (mV) 1.0 0.5 0 -0.5 -1.0 -1.5 MAX9973 toc12 2.0 1.5 LINEARITY ERROR (mV) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 DUT_ = DTV_ VDHV_ = +6.5V VDLV_ = -1.5V 1.0008 1.0006 1.0004 GAIN (V/V) 1.0002 1.0000 1.9998 0.9996 0.9994 0.9992 NORMALIZED AT TJ = +70°C 40 50 60 70 80 90 2.5 -2.0 100 40 50 60 70 80 90 100 TEMPERATURE (°C) -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 VDUT_ (V) TEMPERATURE (°C) COMPARATOR OFFSET vs. COMMON-MODE VOLTAGE MAX9973 toc13 COMPARATOR TIMING VARIATION vs. COMMON-MODE VOLTAGE NORMALIZED AT VCM = 1.5V MAX9973 toc14 COMPARATOR WAVEFORM TRACKING FALLING EDGE 0 TIMING VARIATION (ps) -50 -100 -150 -200 -250 RISING EDGE MAX9973 toc15 MAX9973 toc18 2.0 1.6 1.2 0.8 OFFSET (mV) 0.4 0 -0.4 -0.8 -1.2 -1.6 -2.0 OTHER COMPARATOR REFERENCE = 2.5V NORMALIZED AT VCM = 1.5V 20 15 TIMING VARIATION (ps) 10 50 FALLING EDGE 5 0 -5 -10 -15 RISING EDGE NORMALIZED AT 50% REFERENCE LEVEL VDUT_ = 1 TO 1V PULSE 0 20 40 60 80 100 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 COMMON-MODE VOLTAGE (V) COMMON-MODE VOLTAGE (V) REFERENCE LEVEL (%) COMPARATOR TRAILING-EDGE TIMING VARIATION vs. PULSE WIDTH MAX9973 toc16 COMPARATOR TIMING VARIATION vs. INPUT SLEW RATE 40 TIMING VARIATION (ps) 30 20 10 0 -10 -20 VDUT_ RISING NORMALIZED AT SR = 4V/ns 0 1 2 3 4 5 6 VDUT_ FALLING VDUT_ = 100mV/div MAX9973 toc17 COMPARATOR DIFFERENTIAL OUTPUT RESPONSE 80 60 TIMING VARIATION (ps) 40 HIGH PULSE 20 0 -20 -40 0 LOW PULSE NORMALIZED AT PW = 12.5ns 5 10 15 20 50 0 DOUBLE TERMINATED SIGNAL VDUT_ = 0 TO 3V PULSE VCHV_ = VCLV_ = 1.5V t = 2.0ns/div -30 25 PULSE WIDTH (ns) SLEW RATE (V/ns) 12 ______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs Typical Operating Characteristics (continued) (TJ = +70°C, unless otherwise noted.) COMPARATOR RESPONSE TO HIGH SLEW-RATE OVERDRIVE MAX9973 toc19 MAX9973/MAX9974 COMPARATOR OFFSET vs. TEMPERATURE NORMALIZED AT TJ = +70°C 1.0 0.5 OFFSET (mV) MAX9973 toc20 CLAMP RESPONSE AT SOURCE MAX9973 toc21 INPUT 1.5 VDUT_ = 150mV/div OUTPUT 0 -0.5 -1.0 600mV/div 0 INPUT SLEW RATE = 4V/ns HIGH IMPEDANCE t = 2.0ns/div -1.5 -2.0 40 50 60 70 80 90 100 0 VSOURCE_ = 0 TO 3V SQUARE WAVE RS = 25Ω VCPLV_ = 0 VCPHV_ = +3V t = 10ns/div TEMPERATURE (°C) HIGH-IMPEDANCE LEAKAGE CURRENT vs. DUT_ VOLTAGE MAX9973 toc22 LOW LEAKAGE CURRENT vs. DUT_ VOLTAGE MAX9973 toc23 CLAMP CURRENT vs. DIFFERENCE VOLTAGE VDUT_ = 3V VCPLV_ = 0 MAX9973 toc24 100 80 60 LEAKAGE (nA) 30 20 10 1200 1000 800 IDUT_ (μA) 600 400 200 0 -200 40 20 0 -20 -40 -60 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 VDUT_ (V) LEAKAGE (pA) 0 -10 -20 -30 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 VDUT_ (V) 3.0 3.2 3.4 3.6 3.8 4.0 VCPHV_ (V) CLAMP CURRENT vs. DIFFERENCE VOLTAGE MAX9973 toc25 DRIVE 1V TO LOW LEAKAGE TRANSITION MAX9973 toc26 LOW LEAKAGE TO DRIVE 1V TRANSITION MAX9973 toc27 200 0 -200 IDUT_ (mA) -400 -600 -800 -1000 -1200 -1.0 -0.8 -0.6 -0.4 -0.2 0 VCPLV_ (V) VDUT_ = 0 VCPHV_ = 3V C1 FALL 10.12ns C1 HIGH 504mV C1 LOW 4mV C1 RISE 815ns C1 HIGH 500mV C1 LOW 4mV ______________________________________________________________________________________ 13 Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 Typical Operating Characteristics (continued) (TJ = +70°C, unless otherwise noted.) POSITIVE SUPPLY CURRENT vs. POSITIVE SUPPLY VOLTAGE MAX9973 toc28 NEGATIVE SUPPLY CURRENT vs. NEGATIVE SUPPLY VOLTAGE 137.0 136.5 VDHV_ = +3.0V, VDLV_ = 0, VDTV_ = +1.5V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, HIGH IMPEDANCE, VCC = +9.75V MAX9973 toc29 POSITIVE SUPPLY CURRENT vs. TEMPERATURE VDUT_ = VDTV_ = +1.5V, VDHV_ = +3V, VDLV_ = 0, VCHV_ = VCLV_ = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VCC = +9.75V, VEE = -5.25V MAX9973 toc30 MAX9973 toc33 60.5 60.4 60.3 ICC (mA) 60.2 60.1 60.0 59.9 9.5 VDHV_ = +3.0V, VDLV_ = 0, VDTV_ = +1.5V, VCPHV_ = +7.2V, VCPLV_ = -2.2V, HIGH IMPEDANCE, VEE = -5.25V 137.5 62.0 61.5 61.0 ICC (mA) 60.5 60.0 59.5 59.0 IEE (mA) 9.7 9.9 10.1 10.3 10.5 136.0 135.5 135.0 134.5 134.0 133.5 -5.2 -5.1 -5.0 -4.9 -4.8 -4.7 -4.6 -4.5 40 50 60 70 80 90 100 VCC (V) VEE (V) TEMPERATURE (°C) NEGATIVE SUPPLY CURRENT vs. TEMPERATURE MAX9973 toc31 DRIVER LARGE-SIGNAL RESPONSE INTO 500Ω VDLV_ = 0 RL = 500Ω CL = 0.1pF VDUT_ = 1V/div MAX9973 toc32 DRIVER 1V 600Mbps SIGNAL RESPONSE VDLV_ = 0 VDHV_ = +1V RL = 5 0 Ω VDUT_ = 100mV/div 0 137.0 136.5 136.0 IEE (mA) 135.5 135.0 134.5 134.0 133.5 133.0 40 VDUT_ = VDTV_ = +1.5V, VDHV_ = +3V, VDLV_ = 0 VCHV_ = VCLV_ = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VCC = +9.75V, VEE = -5.25V VDHV_ = 5V VDHV_ = 3V VDHV_ = 1V 0 50 60 70 80 90 100 t = 2.0ns/div t = 0.5ns/div TEMPERATURE (°C) DRIVER 1V 1200Mbps SIGNAL RESPONSE MAX9973 toc34 DRIVER 3V 600Mbps SIGNAL RESPONSE VDLV_ = 0 VDHV_ = +3V RL = 5 0 Ω VDUT_ = 250mV/div MAX9973 toc35 VDLV_ = 0 VDHV_ = +1V RL = 50Ω VDUT_ = 100mV/div 0 t = 0.5ns/div 0 t = 0.5ns/div 14 ______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs Typical Operating Characteristics (continued) (TJ = +70°C, unless otherwise noted.) DRIVER 3V 800Mbps SIGNAL RESPONSE VDLV_ = 0 VDHV_ = +3V RL = 50Ω VDUT_ = 250mV/div MAX9973 toc36 MAX9973/MAX9974 DRIVER DYNAMIC CURRENT-LIMIT RESPONSE MAX9973 toc37 DRIVER SOURCING IDUT_ = 50mA/div 0 DRIVER SINKING 0 t = 0.5ns/div t = 50ns/div Pin Description PIN (MAX9973) 1, 16, 18, 33, 36, 39, 42, 45, 48, 63 2, 15, 24, 35, 37, 44, 46, 57 3, 14 4 5 6 7, 17, 32, 40, 41, 49, 64 8 9 10 11 12 13 19 20 21 NAME VEE VCC AGND REF DGS TEMP GND CS SCLK DIN VDD LOAD RST NDATA1 DATA1 VTERM1 Negative Power-Supply Input Positive Power-Supply Input Analog Ground Connection DAC Reference Input. Set to 2.5V with respect to DGS. DUT Ground Sense. DGS is the ground reference for the DACs. Connect DGS to ground of the device-under-test. Temperature Monitor Output Ground Chip-Select Input. Serial port activation input. Serial-Clock Input. Clock for serial port. Data Input. Serial port data input. Digital Interface Power-Supply Input Load Input. Latches serial register data into DACs. Reset Input. Asynchronous reset input for the serial register. Channel 1 Multiplexer Control Input N Channel 1 Multiplexer Control Input Differential controls DATA1 and NDATA1 select driver 1’s input from DHV1 or DLV1. Drive DATA1 above NDATA1 to select DHV1. Drive NDATA1 above DATA1 to select DLV1. FUNCTION Channel 1 RCV/NRCV and DATA/NDATA Termination Voltage Input. Termination voltage input for the RCV1, NRCV1, DATA1, and NDATA1 differential inputs. ______________________________________________________________________________________ 15 Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 Pin Description (continued) PIN (MAX9973) 22 NAME NRCV1 Channel 1 Multiplexer Control Input N FUNCTION Differential controls RCV1 and NRCV1 place channel 1 in receive mode. Drive RCV1 above NRCV1 to place channel 1 into receive mode. Drive NRCV1 above RCV1 to place channel 1 into drive mode. 23 25, 34, 47, 56 26 27 28 29 30 31 38 43 50 51 52 53 54 55 58 RCV1 N.C. NCL1 CL1 VT1 NCH1 CH1 RHYST1 DUT1 DUT0 RHYST0 CH0 NCH0 VT0 CL0 NCL0 RCV0 Channel 1 Multiplexer Control Input No Connection. Make no connection. Channel 1 Low Comparator Output N Channel 1 Low Comparator Output Differential outputs of channel 1 low comparator. Comparator Termination Voltage Input. Termination voltage for the comparator output pullup resistors for channel 1. Channel 1 High Comparator Output N Channel 1 High Comparator Output Differential outputs of channel 1 high comparator. Comparator Hysteresis Programming Input for Channel 1 Channel 1 Device-Under-Test Input/Output. Combined I/O for driver, comparator, clamp, and load. Channel 0 Device-Under-Test Input/Output. Combined I/O for driver, comparator, clamp, and load. Comparator Hysteresis Programming Input for Channel 0 Channel 0 High Comparator Output Channel 0 High Comparator Output N Differential outputs of channel 0 high comparator. Comparator Termination Voltage Input. Termination voltage for the comparator output pullup resistors for channel 0. Channel 0 Low Comparator Output Channel 0 Low Comparator Output N Channel 0 Multiplexer Control Input Differential outputs of channel 0 low comparator. Differential controls RCV0 and NRCV0 place channel 0 in receive mode. Drive RCV0 above NRCV0 to place channel 0 into receive mode. Drive NRCV0 above RCV0 to place channel 0 into drive mode. 59 60 61 62 — NRCV0 VTERM0 DATA0 NDATA0 EP Channel 0 Multiplexer Control Input N Channel 0 RCV/NRCV and DATA/NDATA Termination Voltage Input. Termination voltage input for the RCV0, NRCV0, DATA0, and NDATA0 differential inputs. Channel 0 Multiplexer Control Input Channel 0 Multiplexer Control Input N Differential controls DATA0 and NDATA0 select driver 0’s input from DHV0 or DLV0. Drive DATA0 above NDATA0 to select DHV0. Drive NDATA0 above DATA0 to select DLV0. Exposed Heat Removal Paddle. The paddle is electrically isolated from the die. Make no electrical connection to EP. 16 ______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 VCC CS SCLK DIN RST LOAD REF SERIAL INTERFACE COMMON TO BOTH CHANNELS LDEN_ TMSEL_ LLEAK_ S1_ S0_ LOAD DLV_ DTV_ DHV_ BUFFER MULTIPLEXER SLEW-RATE CONTROL 0 50Ω 0 DUT_ LDEN_ 1 SERIAL INTERFACE TO DCL AND DACs 24 VEE VDD TEMP GND AGND DGS DHV_ DAC DTV_ DAC DLV_ DAC DCL_ MODE CONTROL 1000Ω 1 DATA_ NDATA_ RCV_ NRCV_ HIGH IMPEDANCE TMSEL_ VTERM_ 4 x 50Ω CPHV_ DAC CLAMPS CPLV_ DAC CH_ NCH_ + S0_ S1_ LLEAK_ MAX9973 MAX9974 CHV_ DAC VT_ 4 x 50Ω COMPARATORS CL_ NCL_ ONE OF TWO IDENTICAL CHANNELS SHOWN + CLV_ DAC Figure 1. Functional Diagram ______________________________________________________________________________________ 17 Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 Detailed Description The MAX9973/MAX9974 are fully integrated, high-performance, dual-channel pin electronics driver/comparator/load (DCL) with built-in level-setting DACs. Each channel includes a three-level pin driver with three levelsetting DACs, a window comparator with two level-setting DACs, two dynamic clamps with two level-setting DACs, and a 1kΩ load driven by the driver’s DTV_ DAC. Figure 1 shows a functional diagram of the MAX9973/MAX9974. The three-level pin driver features a wide -1.5V to +6.5V voltage range and includes high-impedance and activetermination (3rd-level drive) modes. High-speed differential multiplexer control inputs DATA and RCV with internal termination resistors switch the driver between the three input levels. Figure 2 shows a block diagram of the simplified driver channel. The window comparators provide extremely low timing variation. The MAX9973G/MAX9974G comparator opencollector outputs sink 8mA (typ), while the MAX9973H/ MAX9974H comparator outputs sink 16mA (typ). Figure 3 shows the comparator function. The dynamic clamps provide damping of high-speed DUT waveforms when high-impedance receive mode is selected. The loads facilitate fast contact testing when used in conjunction with the comparators. Loads also function as pullups for a device-under-test that has open-drain/collector outputs. A serial interface configures the device and its functions. The MAX9973/MAX9974 are available in a 64-pin (10mm x 10mm x 1.00mm) TQFP-EP package with an exposed paddle on top (MAX9973) or bottom (MAX9974) for heat removal. Power dissipation is only 700mW per channel. The full operating voltage range is -1.5V to +6.5V. Operation is specified with an internal die temperature of +40°C to +100°C. The devices feature a temperature monitor output. Output Driver The driver input is a high-speed multiplexer that selects one of three DAC voltages: DHV_, DLV_, or DTV_. The high-speed differential inputs DATA_/NDATA_ and RCV_/NRVC_, and mode-control bit TMSEL_ control the DLV_ DAC DHV_ DAC HIGH-SPEED INPUTS DATA_ NDATA_ DTV_ DAC + - 0 0 1 1 1 SLEW RATE BUFFER 0 0 MAX9973 MAX9974 50Ω DUT_ VTERM_ 4 x 50Ω RCV_ NRCV_ CPHV_ DAC + - CLAMPS CPLV_ DAC COMPARATORS AND LOAD TMSEL_ HIGH IMPEDANCE DCL MODE CONTROL BITS 4 Figure 2. Simplified Driver Channel 18 ______________________________________________________________________________________ LLEAK_ SC0_ SC1_ Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 MAX9973G MAX9974G CHV_ DAC DUT_ + CH_ NCH_ 8mA 4 x 50Ω 8mA VEE + CLV_ DAC CL_ NCL_ VT_ Figure 3. Comparator Functional Diagram Table 1. Driver Channel Logic HIGH-SPEED INPUTS DATA_/NDATA_ DATA_ > NDATA_ DATA_ < NDATA_ X X X RCV_/NRCV_ RCV_ < NRCV_ RCV_ < NRCV_ RCV_ > NRCV_ RCV_ > NRCV_ X MODE CONTROL BITS TMSEL_ (D3) X X 1 0 X LLEAK_ (D2) 0 0 0 0 1 DUT_ DHV_ DLV_ DTV_ High impedance (clamps engaged) Low leakage X = Don’t care. Table 2. Driver Slew-Rate Logic MODE CONTROL BITS S1_ (D1) 0 0 1 1 S0_ (D0) 0 1 0 1 DRIVER SLEW RATE (%) 100 (fastest) 75 50 25 (slowest) Table 3. Comparator Logic COMPARATOR INPUTS COMPARATOR OUTPUTS HIGH LOW DUT_ > CHV_ DUT_ > CLV_ COMPARATOR COMPARATOR CH_ 0 0 1 1 0 1 0 1 0 0 1 1 NCH_ 1 1 0 0 CL_ 0 1 0 1 NCL_ 1 0 1 0 switching between the DAC voltages (Table 1). A slewrate circuit controls the slew rate of the buffer input with one of four possible slew rates selectable (Table 2). The 100% slew rate is a function of the inherent speed of the multiplexer (see the Driver Large-Signal Response graph in the Typical Operating Characteristics). DUT_ can be toggled at high speed between driver and high-impedance modes, or can be placed into low-leakage mode 19 ______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 using mode control bit LLEAK_ (Figure 2, Table 1). In high-impedance mode, the bias current at DUT_ is less than 5µA over the -1.5V to +6.5V range, while the node maintains its ability to track high-speed signals. In lowleakage mode, the bias current at DUT_ is further reduced to less than ±10nA, and signal tracking slows. See the Low-Leakage Mode section for more details. The nominal driver output resistance is 50Ω. Contact the factory for different resistance values within the 48Ω to 52Ω range. impedance mode (Figure 2). For transient suppression, set the clamp voltages to approximately the minimum and maximum expected DUT_ voltage range. The optimal clamp voltages are application-specific and must be empirically determined. If clamping is not desired, set the clamp voltages at least 0.7V outside the expected DUT_ voltage range; overvoltage protection remains active without loading DUT_. Comparators The MAX9973/MAX9974 provide two independent highspeed comparators for each channel. Each comparator has one input connected internally to DUT_ and the other input connected to either DAC CHV_ or DAC CLV_ (see Figures 1 and 3). Comparator outputs are a logical result of the input conditions, as indicated in Table 3. The comparator differential outputs are opencollector to ease interfacing with a wide variety of logic families. The MAX9973G/MAX9974G switch an 8mA current sink between the two outputs, while the Clamps The voltage clamps (high and low) limit the voltage at DUT_ and suppress reflections when the channel is configured as a high-impedance receiver. The clamps behave as diodes with series 50Ω resistors connected to the outputs of high-current buffers. Internal circuitry compensates for the diode drop at 1mA clamp current. Set the clamp voltages using DACs CPHV_ and CPLV_. The clamps are enabled only when the driver is in high- REGISTER ADDRESS WRITE ENABLE CH0 UNUSED SCLK DIN RST CS ENABLE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 1 4 5 LATCH WRITE ENABLE_ ADDRESS DATA CS DCL_ 5 DATA 5 MODE CONTROL BITS LOAD 1 4 16 LATCH WRITE ENABLE_ ADDRESS DATA CS LOAD DHV_ DAC 16 DATA DHV_ LOAD 1 4 16 LATCH WRITE ENABLE_ ADDRESS DATA CS LOAD CLV_ DAC 16 DATA CLV_ Figure 4. Serial Interface Block Diagram 20 ______________________________________________________________________________________ UNUSED MAX9973 MAX9974 WRITE ENABLE CH1 REGISTER DATA Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 Table 4. Load Logic HIGH-SPEED INPUT RCV_/NRCV_ RCV_ < NRCV_ X RCV_ > NRCV_ RCV_ > NRCV_ X MODE CONTROL BITS LOAD LLEAK_ (D2) 0 0 0 0 1 TMSEL_ (D3) X X 0 1 X LDEN_ (D4) X 0 1 1 X Off Off On Off Off Table 6. Register Addresses REGISTER ADDRESS BITS A3 0 0 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 1 1 X A1 0 0 1 1 0 0 1 1 X A0 0 1 0 1 0 1 0 1 X REGISTER FUNCTION DCL mode DHV_ level DLV_ level DTV_ level CHV_ level CLV_ level CPHV_ level CPLV_ level Not used X = Don’t care. Table 5. Serial Interface Data Bit Definitions DIN BIT A7 A6 A5 A4 A3 A2 A1 A0 D15–D0 Register data Register address (Table 6) BIT FUNCTION Not used Not used Write enable channel 1 Write enable channel 0 Table 7. DCL Mode Control Bits BIT D4 D3 D2 D1 D0 NAME LDEN TMSEL LLEAK S1 S0 FUNCTION Load enable Terminate select Low-leakage enable Slew-rate control (Table 2) POWER-UP STATE 0 0 1 0 0 Low-Leakage Mode Asserting LLEAK_ through the serial interface or with the digital input RST places the MAX9973/MAX9974 in a very low-leakage state (see the Electrical Characteristics table). With LLEAK_ asserted, the comparators, driver, clamps, and active load are disabled. This mode is convenient for making IDDQ and PMU measurements without the need for an output disconnect relay. LLEAK_ is programmed independently for each channel, while RST acts on both channels simultaneously. MAX9973H/MAX9974H switch 16mA. The 50Ω output termination resistors connect to voltage input VT_. Each output provides a nominal 400mVP-P swing and 50Ω source termination. 1kΩ Load The 1kΩ load is a resistor connected to DUT_ from the output of an internal buffer. The buffer’s input is DAC DTV_ (Figure 1). The buffer sinks and sources at least 6.9mA. A switch separates the resistor from the buffer. Operate the switch with serial control bits LDEN_, LLEAK_, and TMSEL_, and through high-speed differential input RCV_/NRCV_. Table 4 shows the truth table for the load-switch operation. Serial Interface and Device Control A CMOS-compatible serial interface controls the MAX9973/MAX9974 modes (Figure 4, Table 5). Control data flow into a 24-bit shift register and is latched when CS is taken high, as shown in Figure 5. The first eight bits, A7–A0, determine which of the two channels is being commanded, and which DAC or DCL the following 16 bits program. The 16 bits, D15–D0, set the DAC voltage or control the setup of the MAX9973/MAX9974 through the mode control bits, as shown in Tables 5, 6, 7, and Figure 6. DUT Ground-Sense Input The DUT ground-sense input (DGS) senses the ground potential of the device-under-test and allows the output and DAC levels of the MAX9973/MAX9974 to be set relative to that ground potential. Connect DGS to the ground of the device-under-test. ______________________________________________________________________________________ 21 Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 t1 SCLK t4 t3 CS t9 t8 DIN A7 A0 D15 D0 t12 t2 t6 t5 t7 LOAD t10 RST t11 Figure 5. Serial-Interface Timing High-speed differential inputs RCV_/NRCV_ and DATA_/NDATA_, in conjunction with control bits TMSEL_, LLEAK_, and LDEN_, manage the features of each channel. RST sets LLEAK = 1 for both channels, forcing both channels into low-leakage mode; all other bits are unaffected. At power-up, hold RST low until VCC and VEE have stabilized. Serial Communication Figure 5 and the serial port timing section of the Electrical Characteristics table show the serial interface timing requirements. Note that the first rising clock edge, after CS goes low, shifts in bit A7, and the last rising clock edge latches in bit D0. Forcing LOAD low then transfers the data from the serial input register to the DACs and DCLs. 22 ______________________________________________________________________________________ Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 DCL DHV DTV DLV CHV CLV CPHV CPLV D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RESERVED SET TO ZEROS DAC SETTING DAC SETTING DAC SETTING DAC SETTING DAC SETTING DAC SETTING DAC SETTING UNUSED UNUSED MODE BITS SEE TABLES 1, 2 AND 4 FOR MODE SETTINGS DHV LEVEL = (DAC SETTING x 152.59μV) - 2.5V DTV LEVEL = (DAC SETTING x 152.59μV) - 2.5V DLV LEVEL = (DAC SETTING x 152.59μV) - 2.5V CHV LEVEL = (DAC SETTING x 152.59μV) - 2.5V CLV LEVEL = (DAC SETTING x 152.59μV) - 2.5V CPHV LEVEL = (DAC SETTING x 2.4414mV) - 2.5V CPLV LEVEL = (DAC SETTING x 2.4414mV) - 2.5V Figure 6. Register Data for DCL and DAC Programming DACs as Driver Channel Inputs Digital-to-analog converters, programmed through the serial interface, provide input voltages to the three input multiplexers (DHV_, DTV_, and DLV_), the clamps (CPHV_ and CPLV_), the comparators (CHV_ and CLV_), and the load (DTV_ doubles as the load input voltage source). Set the DAC output voltages as detailed in Figure 6. Heat Removal Under normal circumstances, the MAX9973 requires heat removal through the exposed paddle through the use of an external heat sink. The exposed paddle is electrically isolated from the die. Make no electrical connection to the exposed paddle. Power-Supply Considerations Bypass all VCC and VEE power pins each with a 0.01µF capacitor, and use bulk bypassing of at least 10µF on each supply. Temperature Monitor The MAX9973 supplies a temperature output signal, TEMP, that asserts a nominal output voltage of 3.43V at a die temperature of +70°C (343K). The output voltage changes proportionally with temperature at 10mV/°C, but is not calibrated. ______________________________________________________________________________________ 23 Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 Pin Configuration VTERM0 NDATA0 RHYST0 NRCV0 DATA0 NCH0 RCV0 NCL0 GND GND 48 VEE 47 N.C. 46 VCC 45 VEE 44 VCC 43 DUT0 42 VEE 41 GND 40 GND 39 VEE 38 DUT1 37 VCC 36 VEE 35 VCC 34 N.C. 33 VEE 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VTERM1 NDATA1 RHYST1 DATA1 NRCV1 N.C. RCV1 NCL1 NCH1 CL1 GND CH1 GND VEE VCC VT1 N.C. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VEE 1 VCC 2 AGND 3 REF 4 DGS 5 TEMP 6 GND 7 CS 8 SCLK 9 DIN 10 VDD 11 LOAD 12 RST 13 AGND 14 VCC 15 VEE 16 MAX9973 TQFP-EP-IDP Chip Information PROCESS: BiCMOS 24 ______________________________________________________________________________________ CH0 CL0 VCC VEE VT0 Dual Driver/Comparator/Load with Internal DACs Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX9973/MAX9974 PACKAGE OUTLINE, 64L TQFP, 10x10x1.00mm EXPOSED PAD OPTION, INVERTED DIE PAD 21-0162 A 1 2 ______________________________________________________________________________________ 25 64L TQFP.EPS Dual Driver/Comparator/Load with Internal DACs MAX9973/MAX9974 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) PACKAGE OUTLINE, 64L TQFP, 10x10x1.00mm EXPOSED PAD OPTION, INVERTED DIE PAD 21-0162 A 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 26 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.