MAXQ2000_08

Rev 10; 7/08 KIT ATION EVALU BLE AVAILA Low-Power LCD Microcontroller General Description Features ♦ High-Performance, Low-Power, 16-Bit RISC Core DC to 20MHz Operation, Approaching 1MIPS per MHz Dual 1.8V Core/3V I/O Enables Low Power/Flexible Interfacing 33 Instructions, Most Single Cycle Three Independent Data Pointers Accelerate Data Movement with Automatic Increment/Decrement 16-Level Hardware Stack 16-Bit Instruction Word, 16-Bit Data Bus 16 x 16-Bit, General-Purpose Working Registers Optimized for C-Compiler (High-Speed/Density Code) ♦ Program and Data Memory 32kWords Flash Memory, Mask ROM for HighVolume Applications 10,000 Flash Write/Erase Cycles 1kWord of Internal Data RAM JTAG/Serial Boot Loader for Programming ♦ Peripheral Features Up to 50 General-Purpose I/O Pins 100/132 Segment LCD Driver Up to 4 COM and 36 Segments Static, 1/2, and 1/3 LCD Bias Supported No External Resistors Required SPITM and 1-Wire® (-RAX/-RAX+/-RFX/-RFX+ Only) Hardware I/O Ports One or Two Serial UARTs One-Cycle, 16 x 16 Hardware Multiply/Accumulate with 48-Bit Accumulator Three 16-Bit Programmable Timers/Counters 8-Bit, Subsecond, System Timer/Alarm 32-Bit, Binary Real-Time Clock with Time-of-Day Alarm Programmable Watchdog Timer ♦ Flexible Programming Interface Bootloader Simplifies Programming In-System Programming Through JTAG Supports In-Application Programming of Flash Memory ♦ Ultra-Low-Power Consumption 190µA typ at 8MHz Flash Operation, PMM1 at 2.2V 700nA typ in Lowest Power Stop Mode Low-Power 32kHz Mode and Divide-by-256 Mode MAXQ2000 The MAXQ2000 microcontroller is a low-power, 16-bit device that incorporates a liquid-crystal display (LCD) interface that can drive up to 100 (-RBX/-RBX+) or 132 (-RAX/-RAX+/-RFX/-RFX+) segments. The MAXQ2000 is uniquely suited for the blood-glucose monitoring market, but can be used in any application that requires high performance and low-power operation. The device can operate at a maximum of either 14MHz (VDD > 1.8V) or 20MHz (VDD > 2.25V). The MAXQ2000 has 32kWords of flash memory, 1kWord of RAM, three 16bit timers, and one or two universal synchronous/asynchronous receiver/transmitters (UARTs). Flash memory aids prototyping and low-volume production. The microcontroller core is powered by a 1.8V supply, with a separate I/O supply for optimum flexibility. An ultralow-power sleep mode makes these parts ideal for battery-powered, portable equipment. Applications Medical Instrumentation Battery-Powered and Portable Devices Electrochemical and Optical Sensors Industrial Control Data-Acquisition Systems and Data Loggers Home Appliances Consumer Electronics Thermostats/Humidity Sensors Security Sensors Gas and Chemical Sensors HVAC Smart Transmitters Typical Operating Circuit, Pin Configurations, and Ordering Information appear at end of data sheet. MAXQ is a registered trademark of Maxim Integrated Products, Inc. SPI is a trademark of Motorola, Inc. 1-Wire is a registered trademark of Dallas Semiconductor Corp., a wholly owned subsidiary of Maxim Integrated Products, Inc. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. ______________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Low-Power LCD Microcontroller MAXQ2000 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground Except VDD .................................-0.5V to (VDDIO + 0.5)V Voltage Range on VDD Relative to Ground .........-0.5V to +2.75V Voltage Range on VDDIO Relative to Ground........-0.5V to +3.6V Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Soldering Temperature ..........................Refer to the IPC/JEDEC J-STD-020 Specification. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = VDD(MIN) to VDD(MAX), VDDIO = 2.7V to 3.6V, TA = -40°C to +85°C.) (Note 1) PARAMETER Core Supply Voltage I/O Supply Voltage VDD Slew Rate IDD1 IDD2 Active Current, fHFIN = 14MHz (Note 3) IDD3 IDD4 IDD5 IDD6 IDD1 IDD2 Active Current, fHFIN = 20MHz (Note 3) IDD3 IDD4 IDD5 IDD6 SYMBOL VDD VDDIO VDD rising (Note 2) /1 mode /2 mode /4 mode /8 mode PMM1 mode PMM2 mode; 32KIN = 32.768kHz /1 mode /2 mode /4 mode /8 mode PMM1 mode PMM2 mode; 32KIN = 32.768kHz Rev A2 Rev A3 Rev A2 Rev A3 CONDITIONS 32k x 16 flash Flash programming MIN 1.8 2.25 VDD 225 6.0 5.6 3.4 1.9 0.5 4.8 0.1 6.5 5.9 3.8 2.2 0.6 4.8 0.1 5.1 0.85 0.19 0.30 0.14 0.7 20 1 55 550 50 μA μA mA 9.2 8.6 5.1 2.9 0.7 7.6 0.95 10.4 9.6 6.2 3.8 1.4 7.6 0.95 mA mA TYP 2.5 2.5 MAX 2.75 2.75 3.6 UNITS V V mV/ms Execution from flash memory, 20MHz, VDD = 2.2V, TA = + 25°C Execution from flash memory, 8MHz, /8 mode, VDD = 2.2V, TA = + 25°C Active Current Execution from flash memory, 8MHz, PMM1 mode, VDD = 2 .2V, TA = + 25°C Execution from RAM, 8MHz, /8 mode, VDD = 2.2V, TA = + 25°C Execution from RAM, 1MHz, /1 mode, VDD = 2.2V, TA = + 25°C Stop-Mode Current D igital I/O Supply Current I STOP(VDD) IDDIO -40°C < TA < +25°C TA = +85°C RTC enabled; HFIN 14MHz; all I/O disconnected 2 _____________________________________________________________________ Low-Power LCD Microcontroller ELECTRICAL CHARACTERISTICS (continued) (VDD = VDD(MIN) to VDD(MAX), VDDIO = 2.7V to 3.6V, TA = -40°C to +85°C.) (Note 1) PARAMETER Input High Voltage: HFIN and 32KIN Input High Voltage: P6.4–P6.5 and P7.0–P7.1 Input High Voltage: All Other Pins Input Low Voltage: HFIN and 32KIN Input Low Voltage: All Other Pins Output High Voltage: P6.4–P6.5 and P7.0–P7.1 Output High Voltage: All Other Pins Output Low Voltage for All Other Pins Output Low Voltage for P6.4–P6.5 and P7.0–P7.1 Input Leakage Current Input Pullup Current LCD INTERFACE LCD Reference Voltage LCD Bias Voltage 1 LCD Bias Voltage 2 LCD Adjustment Voltage LCD Bias Resistor LCD Adjustment Resistor VLCD VLCD1 VLCD2 VADJ RLCD RLADJ L RA4:LRA0 = 11111b When segment is driven at VLCD level; VLCD = 3V; I SEGxx = -3μA; guaranteed by design When segment is driven at VLCD1 level; VLCD1 = 2V; I SEGxx = -3μA; guaranteed by design LCD Segment Voltage VSEGxx When segment is driven at VLCD2 level; VLCD2 = 1V; I SEGxx = -3μA; guaranteed by design When segment is driven at VADJ level; VADJ = 0V; I SEGxx = 3μA; guaranteed by design VLCD2 0.02 VLCD2 VLCD 0.02 1/3 bias 1/3 bias Guaranteed by design 2.7 3.3 3.6 V V V V k k VLCD VADJ + 2/3 (VLCD - VADJ) VADJ + 1/3 (VLCD - VADJ) 0 100 200 0.4 x VLCD SYMBOL VIH1 VIH2 VIH3 VIL1 VIL2 VOH1 VOH2 VOL1 VOL2 IL I IP SVS on; I OH(MAX) = 0.75mA; VLCD = 2.7V I OH(MAX) = 0.75mA; VDDIO = 1.8V I OL = 1.0mA; VDDIO = 1.8V I OL = 1.4mA; VDDIO = 2.7V Internal pullup disabled Internal pullup enabled SVS on, VLCD = 3.3V CONDITIONS MIN 0.8 x VDDIO 0.8 x VLCD 0.8 x VDDIO 0 0 VLCD 0.2 VDDIO 0.2 GND GND -100 -20 0.2 0.2 +100 -5 TYP MAX VDDIO VLCD VDDIO 0.2 x VDDIO 0.2 x VDDIO UNITS V V V V V V V V V nA μA MAXQ2000 VLCD1 0.02 VLCD1 V VADJ 0.1 _____________________________________________________________________ 3 Low-Power LCD Microcontroller MAXQ2000 ELECTRICAL CHARACTERISTICS (continued) (VDD = VDD(MIN) to VDD(MAX), VDDIO = 2.7V to 3.6V, TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS External oscillator, VDD External-Clock Frequency 2.25V MIN 0 0 3 3 2 2 50 0 0 50 32kHz watch crystal Mass erase Page erase TA = + 25°C TA = +25°C 200 20 2.5 10,000 100 5.0 32.768 20 14 TYP MAX 20 14 20 14 20 14 ns MHz ns kHz MHz UNITS EXTERNAL CLOCK SOURCE External oscillator, VDD < 2 .25V fHFIN External crystal, VDD 2.25V External crystal, VDD < 2.25V F lash programming, VDD External-Clock Period System-Clock Frequency System-Clock Period R EAL-TIME CLOCK RTC Input Frequency JTAG/FLASH PROGRAMMING F lash Erase Time F lash Programming Time Write/Erase Cycles Data Retention S PI TIMING SPI Master Operating Frequency SPI Slave Operating Frequency SCLK Output Pulse-Width High/Low SCLK Input Pulse-Width High/Low MOSI Output Hold Time after SCLK Sample Edge MOSI Output Valid to Sample Edge MISO Input Valid to SCLK Sample Edge Rise/Fall Setup MISO Input to SCLK Sample Edge Rise/Fall Hold 1/tMCK 1/t SCK tMCH, tMCL t SCH, t SCL tMOH tMOV CL = 5 0pF tMCK / 2 - 25 tMCK / 2 - 25 30 tMCK / 2 - 25 t SCK / 2 fCK / 2 fCK / 8 MHz MHz ns ns ns ns ms ms cycles years f32KIN tCLCL fCK tCK 2.25V Flash programming, VDD < 2.25V 48% minimum duty cycle 2.25V 1.8V VDD VDD 2.75V 2.75V tMIS ns tMIH 0 ns 4 _____________________________________________________________________ Low-Power LCD Microcontroller ELECTRICAL CHARACTERISTICS (continued) (VDD = VDD(MIN) to VDD(MAX), VDDIO = 2.7V to 3.6V, TA = -40°C to +85°C.) (Note 1) PARAMETER SCLK Inactive to MOSI Inactive MOSI Input to SCLK Sample Edge Rise/Fall Setup MOSI Input from SCLK Sample Edge Transition Hold MISO Output Valid after SCLK Shift Edge Transition SS Inactive SCLK Inactive to SS Rising MISO Output Disabled after CS Edge Rise SS Active to First Shift Edge SYMBOL tMLH CONDITIONS MIN tMCK / 2 - 25 30 TYP MAX UNITS ns MAXQ2000 t SIS ns t SIH tCK + 25 ns t SOV t SSH t SD t SLH t SSE 4tCK tCK + 25 tCK + 25 3tCK + 25 ns ns ns 2tCK + 50 ns ns Note 1: Specifications to -40°C are guaranteed by design and not production tested. Note 2: Guaranteed by design. Note 3: Measured on the VDD pin with VDD = 2.75V and not in reset. _____________________________________________________________________ 5 Low-Power LCD Microcontroller MAXQ2000 SPI Master Timing SHIFT SS SAMPLE SHIFT SAMPLE SCLK CKPOL/CKPHA 0/1 or 1/0 tMCK SCLK CKPOL/CKPHA 0/0 or 1/1 tMCH tMCL tMOH tMLH MOSI MSB MSB-1 tMOV tMIS MISO MSB MSB-1 tMIH LSB LSB SPI Slave Timing SHIFT tSSE SS SAMPLE SHIFT SAMPLE tSSH SCLK CKPOL/CKPHA 0/1 or 1/0 tSCK tSD SCLK CKPOL/CKPHA 0/0 or 1/1 tSCH tSCL tSIS MOSI MSB tSIH MSB-1 LSB tSOV MISO MSB MSB-1 LSB tSLH 6 _____________________________________________________________________ Low-Power LCD Microcontroller Typical Operating Characteristics DIGITAL SUPPLY CURRENT vs. CLOCK FREQUENCY 7 6 IDD1 (mA) 5 4 3 2 1 VDD = 2.75V 0 0 5 10 fHFIN (MHz) 15 20 TA = +25°C TA = +85°C TA = -40°C TA = 0°C MAXQ2000 toc01 MAXQ2000 8 Pin Description PIN TQFN-EP 40 22 23, 35 45 QFN-EP 49 27 28, 42 54 LQFP 70 36, 62 39, 63 83 NAME VDD VDDIO GND VLCD Digital Supply Voltage I/O Supply Voltage Ground LCD Bias-Control Voltage. Highest LCD drive voltage used with static bias. Connected to an external source. LCD Bias, Voltage 1. LCD drive voltage used with 1/2 and 1/3 LCD bias. An internal resistor- divider sets the voltage. External resistors and capacitors can be used to change the LCD voltage or drive capability at this pin. LCD Bias, Voltage 2. LCD drive voltage used with 1/3 LCD bias. An internal resistor-divider sets the voltage. External resistors and capacitors can be used to change LCD voltage or drive capability at this pin. LCD Adjustment Voltage. Connect to an external resistor to provide external control of the LCD contrast. Leave disconnected for internal contrast adjustment. Digital, Active-Low, Reset Input/Output. The CPU is held in reset when this is low and begins executing from the reset vector when released. The pin includes pullup current source and should be driven by an open-drain, external source capable of sinking in excess of 2mA. This pin is driven low as an output when an internal reset condition occurs. High-Frequency Crystal Input. Connect an external crystal or resonator between HFXIN and HFXOUT as the high-frequency system clock. Alternatively, HFXIN is the input for an external, high-frequency clock source when HFXOUT is floating. FUNCTION 46 55 84 VLCD1 47 56 85 VLCD2 48 57 86 VADJ 28 33 50 RESET 42 51 76 HFXIN 41 50 71 High-Frequency Crystal Output/Input. Connect an external crystal or resonator between HFXIN and HFXOUT as the high-frequency system clock. Alternatively, HFXOUT float HFXOUT when an external, high-frequency clock source is connected to the HFXIN pin. _____________________________________________________________________ 7 Low-Power LCD Microcontroller MAXQ2000 Pin Description (continued) PIN NAME TQFN-EP QFN-EP LQFP 32kHz Crystal Input. Connect an external, 32kHz watch crystal between 32KIN and 32KOUT as the low-frequency system clock. Alternatively, 32KIN is the input for an external, 32kHz clock source when 32KOUT is floating. FUNCTION 29 34 52 32KIN 30 35 53 32kHz Crystal Output/Input. Connect an external, 32kHz watch crystal between 32KOUT 32KIN and 32KOUT as the low-frequency system clock. Alternatively, float 32KOUT when an external, 32kHz clock source is connected to the 32KIN pin. General-Purpose, 8-Bit, Digital, I/O, Type-C Port; LCD Segment-Driver Output. These port pins function as both bidirectional I/O pins and LCD segment-drive outputs. All port pins are defaulted as input with weak pullup after a reset. Enabling a pin’s LCD function disables the general-purpose I/O on the pin. Setting the PCF1 bit enables the LCD for all pins on this port and disables the general-purpose I/O function on all pins. 56-PIN 68-PIN 100-PIN PORT ALTERNATE FUNCTION 1 2 3 4 5 6 7 8 66 67 68 1 2 3 4 5 97 98 3 4 5 6 7 8 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 1 –8 66, 67, 68; 1–5 97, 98, 3–8 P1.0– P1.7; SEG8– SEG15 9 –12 6–13 9, 10, 11, 14– 18 P2.0– P2.7; SEG16– SEG23 General-Purpose, 8-Bit, Digital, I/O, Type-C Port; LCD Segment-Driver Output. These port pins function as both bidirectional I/O pins and LCD segment-drive outputs. All port pins are defaulted as input with weak pullup after a reset. Enabling a pin’s LCD function disables the general-purpose I/O on the pin. Setting the PCF2 bit enables the LCD for all pins on this port and disables the general-purpose I/O function on all pins. ALTERNATE FUNCTIONS 56-PIN 68-PIN 100-PIN PORT 56-PIN 68-PIN — — — — 9 10 11 12 6 7 8 9 10 11 12 13 9 10 11 14 15 16 17 18 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 — — — — SEG16 SEG17 SEG18 SEG19 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 8 _____________________________________________________________________ Low-Power LCD Microcontroller Pin Description (continued) PIN TQFN-EP QFN-EP LQFP NAME FUNCTION General-Purpose, Digital, I/O, Type-D Port; LCD Segment-Driver Output; External Edge-Selectable Interrupt. This port functions as both bidirectional I/O pins and LCD segment-drive outputs. All port pins are defaulted as inputs with weak pullups after a reset. The port pads can be configured as an external interrupt for pins 7 to 4. If the external interrupt is enabled, the LCD function on the associated pin is disabled. Setting the PCF3 bit enables the LCD for all pins on this port and disables the generalpurpose I/O function on all pins. It is possible to mix the LCD and interrupt functions on the same port. To do this, the interrupt enable must be established prior to setting the PCF0 bit. Care must be taken not to enable the external interrupt while the LCD is in normal operational mode, as this could result in potentially harmful contention between the LCD controller output and the external source connected to the interrupt input. ALTERNATE FUNCTIONS 56-PIN 68-PIN 100-PIN PORT 56-PIN 68-PIN — — — — 13 14 15 16 14 15 16 17 18 19 20 21 19 20 21 22 23 27 28 29 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 — — — — SEG20/INT4 SEG21/INT5 SEG22/INT6 SEG23/INT7 SEG24 SEG25 SEG26 SEG27 SEG28/INT4 SEG29/INT5 SEG30/INT6 SEG31/INT7 MAXQ2000 13–16 14–21 19–23, 27, 28, 29 P3.0– P3.7; SEGx; INT4– INT7 LCD Segment-Driver Output; LCD Common-Drive Output. The selection of a pin function as either segment or its alternative common-mode signal is controlled by the choice of duty cycle (DUTY1:0). SEGx; COM3– COM0 56-PIN 17 18 19 20 21 68-PIN 22 23 24 25 26 100-PIN 30 31 32 33 34 FUNCTION 56-PIN SEG24 SEG25 SEG26 SEG27 — 68-PIN SEG32 SEG33 SEG34 SEG35 COM0 100-PIN SEG32 COM3 COM2 COM1 COM0 ALTERNATE FUNCTIONS — COM3 COM2 COM1 — 17–21 22–26 30–34 24–27 29–32 40–43 General-Purpose, Digital, I/O, Type-D Port; Debug Port Signal; External EdgeSelectable Interrupt. Pins default to JTAG on POR; other functions must be enabled P4.0– from software. P4.3; TCK/TDI/ 56-PIN 68-PIN 100-PIN PORT ALTERNATE FUNCTIONS TMS/ 24 29 40 P4.0 TCK INT8 TDO; 25 30 41 P4.1 TDI INT9 INT8, INT9 26 31 42 P4.2 TMS — 27 32 43 P4.3 TDO — _____________________________________________________________________ 9 Low-Power LCD Microcontroller MAXQ2000 Pin Description (continued) PIN NAME TQFN-EP — — 31 QFN-EP 36 37 38 LQFP 54 56 57 P5.2/RX1/ General-Purpose, Digital, I/O, Type-D Port; Serial Port 1 Receive; External EdgeINT10 Selectable Interrupt 10 P5.3/TX1/ General-Purpose, Digital, I/O, Type-D Port; Serial Port 1 Transmit; External EdgeINT11 Selectable Interrupt 11 P5.4/SS P5.5; MOSI P5.6; SCLK P5.7/ MISO General-Purpose, Digital, I/O, Type-C Port; Active-Low, SPI, Slave-Select Input. Becomes the slave-select input in SPI mode. General-Purpose, Digital, I/O, Type-C Port; SPI, Master-Out Slave-In Output. Data is clocked out of the microcontroller on SCLK’s falling edge and into the slave device on SCLK’s rising edge. Becomes MOSI input in SPI mode. General-Purpose, Digital, I/O, Type-C Port; SPI, Clock Output. Becomes SCLK input in slave mode but limited to SYSCLK / 8. General-Purpose, Digital, I/O, Type-C Port; SPI, Master-In Slave-Out Input. Data is clocked out of the slave on SCLK’s falling edge and into the microcontroller on SCLK’s rising edge. Becomes MISO output in slave mode. FUNCTION 32 39 58 33 40 59 34 41 60 36 37 — — 38 39 43 44 43 44 45 46 47 48 52 53 64 65 66 67 68 69 81 82 P6.0/T1B/ General-Purpose, Digital, I/O, Type-D Port; Timer 1 Alternative Output (PWM); INT12 External Edge-Selectable Interrupt 12 P6.1/T1/ INT13 General-Purpose, Digital, I/O Type-D Port; Timer 1 Output (PWM); External EdgeSelectable Interrupt 13 P6.2/T2B/ General-Purpose, Digital, I/O, Type-D Port; Timer 2 Alternative Output (PWM); OW_OUT 1-Wire Data Output P6.3/T2/ OW_IN General-Purpose, Digital, I/O, Type-D Port; Timer 2 Output (PWM); 1-Wire Data Input P6.4/T0B/ General-Purpose, Digital, I/O, Type-C Port; Timer 0 Alternative Output (PWM); WKOUT0 Wakeup Output 0 P6.5/T0/ General-Purpose, Digital, I/O, Type-C Port; Timer 0 Output (PWM); Wakeup WKOUT1 Output 1 P7.0/TX0/ General-Purpose, Digital, I/O, Type-D Port; Serial Port 0 Transmit; External, EdgeINT14 Selectable Interrupt 14 P7.1/RX0/ General-Purpose, Digital, I/O, Type-D Port; Serial Port 0 Receive; External EdgeINT15 Selectable Interrupt 15 10 ____________________________________________________________________ Low-Power LCD Microcontroller Pin Description (continued) PIN TQFN-EP QFN-EP LQFP NAME FUNCTION General-Purpose, Digital, I/O, Type-D Port; LCD Segment-Driver Output; External Edge-Selectable Interrupt. This port functions as both bidirectional I/O pins and LCD segment-drive outputs. All port pins are defaulted as input with weak pullup after a reset. The port pads can be configured as an external interrupt for pins 7 to 4. If the external interrupt is enabled, the LCD function on the associated pin is disabled. Setting the PCF0 bit enables the LCD for all pins on this port and disables the general-purpose I/O function on all pins. It is possible to mix the LCD and interrupt functions on the same port. To do this, the interrupt enable must be established prior to setting the PCF0 bit. Care must be taken not to enable the external interrupt while the LCD is in normal operational mode, as this could result in potentially harmful contention between the LCD controller output and the external source connected to the interrupt input. 56-PIN 49 50 51 52 53 54 55 56 1, 2, 12, 13, 24, 25, 26, 35, 37, 38, 44– 49, 51, 55, 61, 72–75, 77–80, 87, 88, 99, 100 — 68-PIN 58 59 60 61 62 63 64 65 100-PIN 89 90 91 92 93 94 95 96 PORT P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 ALTERNATE FUNCTIONS SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 — — — — INT0 INT1 INT2 INT3 MAXQ2000 49–56 58–65 89–96 P0.0– P0.7; SEG0– SEG7; INT0– INT3 — — N.C. No Connection. These pins should not be connected. — — EP Exposed Paddle. E xposed paddle is on the under side of the package. It should be left unconnected. ____________________________________________________________________ 11 Low-Power LCD Microcontroller MAXQ2000 Block Diagram VLCD SS SCLK 3/4-WIRE (SPI) INTERFACE MOSI MISO WKUP WK_OUT VDDIO P5.4/SS P5.5/MOSI P5.6/SCLK P5.7/MISO 3WINT MAXQ2000 1WINT INTERRUPT CONTROLLER T0INT T0CLK T1INT WDCLK WATCHDOG TIMER SYS_AL DAY_AL WDINT T1CLK T2INT T2CLK IOINT U1INT TIMER0 TIMER1 TIMER2 WKOUT_EN 1-WIRE INTERFACE OWOUT OWIN T0 T0B T1 T1B T2 T2B PAD DRIVERS P6.4/T0/WKOUT P6.5/T0B/WKOUT P6.1/T1/INT13 P6.0/T1B/INT12 P6.3/T2/OWIN P6.2/T2B/OWOUT TXD0 SERIAL UART1 SERIAL UART2 REGISTER FILE DPTR0 DPTR1 DPTR2 RXD0 TXD1 RXD1 P7.0/TX0/INT14 P7.1/RX0/INT15 P5.3/TX1/INT11 P5.2/RX1/INT10 SEG[28:31]/P3[4:7]/INT[4:7] U2INT VDD SEG[0]:SEG32 SEG[24:27]/P3[0:3] SEG[16:23]/P2[0:7] SEG[8:15]/P1[0:7] SEG[0:3]/P0[0:3] P4.0/TCK/INT8 P4.1/TDI/INT9 P4.2/TMS P4.3/TDO EMULATION/ DOWNLOAD 16-BIT RISC CPU 32k x 16 (64kByte) FLASH ROM OR MASK ROM 2k x 8 RAM 16 x 16 HW MULTIPLY 17 x 8 LCD DISPLAY RAM LCD CONTROLLER/ DRIVER SEG[4:7]/P0[4:7]/INT[0:3] VDDIO LCD BIAS CONTROL VLCD GND RESET GND HFXIN HFXOUT 32KIN 32KOUT 32k OSC 32KCLK HF OSC HFCLK SCLKDIV 2:1 MUX SYSCLK WDDIV WDCLK TCLKDIV 3 2:1 MUXES T0CLK T1CLK T2CLK RTC AND ALARMS VLCD1 SYS_AL DAY_AL VLCD2 32KHz HF OSC / 128 LCD CLK SELECT VADJ GNDIO SEG[32]/INT16 COM[0] COM[3:1]/SEG[33:35] 12 ____________________________________________________________________ Low-Power LCD Microcontroller Detailed Description The following is an introduction to the primary features of the microcontroller. More detailed descriptions of the device features can be found in the data sheets, errata sheets, and user’s guides described later in the Additional Documentation section. format field, this can either be an immediate value or a source register. If this field represents a register, the lower four bits contain the module specifier and the upper four bits contain the register index in that module. Bits 8 to 14 represent the destination for the transfer. This value always represents a destination register, with the lower four bits containing the module specifier and the upper three bits containing the register subindex within that module. Any time that it is necessary to directly select one of the upper 24 registers as a destination, the prefix register, PFX, is needed to supply the extra destination bits. This prefix register write is inserted automatically by the assembler and requires only one additional execution cycle. MAXQ2000 MAXQ Core Architecture The MAXQ2000 is a low-cost, high-performance, CMOS, fully static, 16-bit RISC microcontroller with flash memory and an integrated 100- or 132-segment LCD controller. It is structured on a highly advanced, accumulator-based, 16-bit RISC architecture. Fetch and execution operations are completed in one cycle without pipelining, because the instruction contains both the op code and data. The result is a streamlined 20 million instructions-per-second (MIPS) microcontroller. The highly efficient core is supported by a 16-level hardware stack, enabling fast subroutine calling and task switching. Data can be quickly and efficiently manipulated with three internal data pointers. Multiple data pointers allow more than one function to access data memory without having to save and restore data pointers each time. The data pointers can automatically increment or decrement following an operation, eliminating the need for software intervention. As a result, application speed is greatly increased. Memory Organization The device incorporates several memory areas: • 4kB utility ROM, • 32kWords of flash memory for program storage, • 1kWord of SRAM for storage of temporary variables, and • 16-level stack memory for storage of program return addresses and general-purpose use. The memory is arranged by default in a Harvard architecture, with separate address spaces for program and data memory. A special mode allows data memory to be mapped into program space, permitting code execution from data memory. In addition, another mode allows program memory to be mapped into data space, permitting code constants to be accessed as data memory. The incorporation of flash memory allows the devices to be reprogrammed, eliminating the expense of throwing away one-time programmable devices during development and field upgrades. Flash memory can be password protected with a 16-word key, denying access to program memory by unauthorized individuals. A pseudo-Von Neumann memory map can also be enabled. This places the utility ROM, code, and data memory into a single contiguous memory map. This is useful for applications that require dynamic program modification or unique memory configurations. Instruction Set The instruction set is composed of fixed-length, 16-bit instructions that operate on registers and memory locations. The instruction set is highly orthogonal, allowing arithmetic and logical operations to use any register along with the accumulator. Special-function registers control the peripherals and are subdivided into register modules. The family architecture is modular, so that new devices and modules can reuse code developed for existing products. The architecture is transport-triggered. This means that writes or reads from certain register locations can also cause side effects to occur. These side effects form the basis for the higher-level op codes defined by the assembler, such as ADDC, OR, JUMP, etc. The op codes are actually implemented as MOVE instructions between certain register locations, while the assembler handles the encoding, which need not be a concern to the programmer. The 16-bit instruction word is designed for efficient execution. Bit 15 indicates the format for the source field of the instruction. Bits 0 to 7 of the instruction represent the source for the transfer. Depending on the value of the Stack Memory A 16-bit-wide internal stack provides storage for program return addresses and general-purpose use. The stack is used automatically by the processor when the CALL, RET, and RETI instructions are executed and interrupts serviced. The stack can also be used explicitly to store and retrieve data by using the PUSH, POP, and POPI instructions. ____________________________________________________________________ 13 Low-Power LCD Microcontroller MAXQ2000 PROGRAM MEMORY FFFFh FFFFh DATA MEMORY 0Fh 16 x 16 STACK 00h 87FFh 2k x 16 UTILITY ROM FFh 7FFFh REGISTERS 1Fh 0Fh SPRs 32k x 16 FLASH MEMORY 07h 06h SFRs 03FFh 1k x 16 SRAM 00h 0000h 0000h Figure 1. Memory Map 14 ____________________________________________________________________ Low-Power LCD Microcontroller On reset, the stack pointer, SP, initializes to the top of the stack (0Fh). The CALL, PUSH, and interrupt-vectoring operations increment SP, then store a value at the location pointed to by SP. The RET, RETI, POP, and POPI operations retrieve the value @SP and then decrement SP. methods afford great flexibility in system design as well as reduce the life-cycle cost of the embedded system. These features can be password protected to prevent unauthorized access to code memory. MAXQ2000 Utility ROM The utility ROM is a 4kB block of internal ROM memory that defaults to a starting address of 8000h. The utility ROM consists of subroutines that can be called from application software. These include: • In-system programming (bootstrap loader) over JTAG or UART interfaces • In-circuit debug routines • Test routines (internal memory tests, memory loader, etc.) • User-callable routines for in-application flash programming and fast table lookup Following any reset, execution begins in the utility ROM. The ROM software determines whether the program execution should immediately jump to location 0000h, the start of user-application code, or to one of the special routines mentioned. Routines within the utility ROM are user-accessible and can be called as subroutines by the application software. More information on the utility ROM contents is contained in the MAXQ Family User’s Guide: MAXQ2000 Supplement. Some applications require protection against unauthorized viewing of program code memory. For these applications, access to in-system programming, inapplication programming, or in-circuit debugging functions is prohibited until a password has been supplied. The password is defined as the 16 words of physical program memory at addresses x0010h to x001Fh. A single password lock (PWL) bit is implemented in the SC register. When the PWL is set to one (power-on reset default), the password is required to access the utility ROM, including in-circuit debug and in-system programming routines that allow reading or writing of internal memory. When PWL is cleared to zero, these utilities are fully accessible without password. The password is automatically set to all ones following a mass erase. In-System Programming An internal bootstrap loader allows the device to be reloaded over a simple JTAG interface. As a result, software can be upgraded in-system, eliminating the need for a costly hardware retrofit when updates are required. Remote software uploads are possible that enable physically inaccessible applications to be frequently updated. The interface hardware can be a JTAG connection to another microcontroller, or a connection to a PC serial port using a serial-to-JTAG converter such as the MAXQJTAG-001, available from Maxim Integrated Products. If in-system programmability is not required, a commercial gang programmer can be used for mass programming. Activating the JTAG interface and loading the test access port (TAP) with the system programming instruction invokes the bootstrap loader. Setting the SPE bit to 1 during reset through the JTAG interface executes the bootstrap-loader-mode program that resides in the utility ROM. When programming is complete, the bootstrap loader can clear the SPE bit and reset the device, allowing the device to bypass the utility ROM and begin execution of the application software. The following bootstrap loader functions are supported: • Load • Dump • CRC • Verify • Erase Optionally, the bootstrap loader can be invoked by the application code. In this mode, the application software would configure the SPE and PSS bits for UART communication, then jump to the start of the utility ROM. In this way, the bootstrap loader can be accessed through another UART-enabled peripheral, or a PC serial port through an RS-232 transceiver such as the MAX232. Because the bootstrap loader defaults to the JTAG configuration on reset, the UART versus JTAG selection must be made from the application code. As a result, bootstrap loader access through the UART is not possible in an unprogrammed device. Programming The flash memory of the microcontroller can be programmed by two different methods: in-system programming and in-application programming. Both ____________________________________________________________________ 15 Low-Power LCD Microcontroller In-Application Programming The in-application programming feature allows the microcontroller to modify its own flash program memory while simultaneously executing its application software. This allows on-the-fly software updates in missioncritical applications that cannot afford downtime. Alternatively, it allows the application to develop custom loader software that can operate under the control of the application software. The utility ROM contains user-accessible flash programming functions that erase and program flash memory. These functions are described in detail in the user’s guide supplement for this device. MAXQ2000 Register Set Most functions of the device are controlled by sets of registers. These registers provide a working space for memory operations as well as configuring and addressing peripheral registers on the device. Registers are divided into two major types: system registers and peripheral registers. The common register set, also known as the system registers, includes the ALU, accumulator registers, data pointers, interrupt vectors and control, and stack pointer. The peripheral registers define additional functionality that may be included by different products based on the MAXQ architecture. This functionality is broken up into discrete modules so that only the features required for a given product need to be included. Tables 1 and 4 show the MAXQ2000 register set. Table 1. System Register Map REGISTER INDEX 0xh 1xh 2xh 3xh 4xh 5xh 6xh 7xh 8xh 9xh Axh Bxh Cxh Dxh Exh Fxh MODULE NAME (BASE SPECIFIER) AP (8h) AP APC — — PSF IC IMR — SC — — IIR — — CKCN WDCN A (9h) A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] A[14] A[15] PFX (Bh) PFX — — — — — — — — — — — — — — — IP (Ch) IP — — — — — — — — — — — — — — — SP (Dh) — SP IV — — — LC0 LC1 — — — — — — — — DPC (Eh) — — — Offs DPC GR GRL BP GRS GRH GRXL FP — — — — DP (Fh) — — — DP0 — — — DP1 — — — — — — — — Note: Names that appear in italics indicate that all bits of a register are read-only. Names that appear in bold indicate that a register is 16 bits wide. Registers in module AP are bit addressable. 16 ____________________________________________________________________ Table 2. System Register Bit Functions REGISTER BIT 13 — CLR Z — IMS TAP IIS — POR A[n] (16 bits) PFX (16 bits) IP (16 bits) — IV (16 bits) LC[0] (16 bits) LC[1] (16 bits) Offs (8 bits) — GR.13 GR.7 BP (16 bits) GR.5 GR.15 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 FP (16 bits) DP[0] (16 bits) DP[1] (16 bits) GR.4 GR.3 GR.2 GR.1 GR.0 GR.15 GR.14 GR.14 GR.6 GR.13 GR.13 GR.5 GR.12 GR.12 GR.4 GR.11 GR.11 GR.3 GR.10 GR.10 GR.2 GR.9 GR.9 GR.1 GR.8 GR.8 GR.0 GR.6 GR.12 GR.11 GR.10 GR.9 GR.8 GR.7 GR.6 — — — — — — — — GR.5 GR.5 WBS2 GR.4 GR.4 WBS1 GR.3 GR.3 WBS0 GR.2 GR.2 SDPS1 GR.1 GR.1 SDPS0 GR.0 GR.0 — — — — — — — — — SP (4 bits) EWDI WD1 WD0 WDIF WTRF RGSL RGMD STOP SWB PMME CD1 EWT — — II4 II3 II2 II1 — — CDA0 — ROD PWL — II0 CD0 RWT — — IM4 IM3 IM2 IM1 IM0 — CGDS — — — INS IGE S — GPF1 GPF0 OV C E IDS — — — MOD2 MOD1 MOD0 — — — AP (4 bits) 12 11 10 9 8 7 6 5 4 3 2 1 0 REGISTER 15 14 AP APC PSF IC IMR SC IIR CKCN WDCN A[n] (0..15) PFX IP SP — — IV LC[0] LC[1] Offs DPC — — GR GR.15 GR.14 GRL BP GRS GR.7 GR.6 GRH GRXL GR.7 GR.7 FP DP[0] MAXQ2000 ____________________________________________________________________ DP[1] Low-Power LCD Microcontroller 17 Low-Power LCD Microcontroller MAXQ2000 Table 3. System Register Bit Reset Values REGISTER AP APC PSF IC IMR SC IIR CKCN WDCN A[n] (0..15) PFX IP SP IV LC[0] LC[1] Offs DPC GR GRL BP GRS GRH GRXL FP DP0 DP1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGISTER BIT 15 14 13 12 11 10 9 8 7 0 0 1 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 s s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 s 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18 ____________________________________________________________________ Low-Power LCD Microcontroller Table 4. Peripheral Register Map REGISTER INDEX 0xh 1xh 2xh 3xh 4xh 5xh 6xh 7xh 8xh 9xh Axh Bxh Cxh Dxh Exh Fxh 10xh 11xh 12xh 13xh 14xh 15xh 16xh 17xh 18xh 19xh 1Axh 1Bxh 1Cxh 1Dxh 1Exh 1Fxh MODULE NAME (BASE SPECIFIER) M0 (x0h) PO0 PO1 PO2 PO3 — — EIF0 EIE0 PI0 PI1 PI2 PI3 EIES0 — — — PD0 PD1 PD2 PD3 — — — — — RCNT RTSS RTSH RTSL RSSA RASH RASL M1 (x1h) PO4 PO5 PO6 PO7 — — EIF1 EIE1 PI4 PI5 PI6 PI7 EIES1 — — — PD4 PD5 PD6 PD7 — — — — — — — — — — SVS WKO M2 (x2h) MCNT MA MB MC2 MC1 MC0 SCON0 SBUF0 SMD0 PR0 — MC1R MC0R LCRA LCFG LCD16 LCD0 LCD1 LCD2 LCD3 LCD4 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 LCD11 LCD12 LCD13 LCD14 LCD15 M3 (x3h) T2CNA0 T2H0 T2RH0 T2CH0 — SPIB SCON1 SBUF1 SMD1 PR1 — — T2CNB0 T2V0 T2R0 T2C0 T2CFG0 — — OWA OWD SPICN SPICF SPICK ICDT0 ICDT1 ICDC ICDF ICDB ICDA ICDD TM M4 (x4h) T2CNA1 T2H1 T2RH1 T2CH1 T2CNA2 T2H2 T2RH2 T2CH2 T2CNB1 T2V1 T2R1 T2C1 T2CNB2 T2V2 T2R2 T2C2 T2CFG1 T2CFG2 — — — — — — — — — — — — — — M5 (x5h) — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — MAXQ2000 19 Note: Names that appear in italics indicate that all bits of a register are read-only. Names that appear in bold indicate that a register is 16 bits wide. ____________________________________________________________________ MAXQ2000 REGISTER BIT 13 PO0 (8 bits) PO1 (8 bits) PO2 (8 bits) PO3 (8 bits) IE7 EX7 PI0 (8 bits) PI1 (8 bits) PI2 (8 bits) PI3 (8 bits) IT7 PD0 (8 bits) PD1 (8 bits) PD2 (8 bits) PD3 (8 bits) ACS RTSH (16 bits) RTSL (16 bits) RSSA (8 bits) RASH (8 bits) RASL (16 bits) — — — PO5 (8 bits) PO6 (8 bits) — IE15 EX15 — — IE14 EX14 — — IE13 EX13 — PI5 (8 bits) PI6 (8 bits) — IT15 — — IT14 — — IT13 — PD5 (8 bits) PD6 (8 bits) — IT12 — IT11 — IT10 PD4 (5 bits) PI7 (2 bits) IT9 IT8 — IE12 EX12 — IE11 EX11 — IE10 EX10 PI4 (5 bits) PO7 (2 bits) IE9 EX9 IE8 EX8 PO4 (5 bits) — — — — — ALSF ALDF RDYE RDY BUSY ASE ADE RTCE RTSS (8 bits) IT6 IT5 IT4 IT3 IT2 IT1 IT0 EX6 EX5 EX4 EX3 EX2 EX1 IE6 IE5 IE4 IE3 IE2 IE1 IE0 EX0 12 11 10 9 8 7 6 5 4 3 2 1 0 Low-Power LCD Microcontroller 20 Table 5. Peripheral Register Bit Functions REGISTER 15 14 PO0 PO1 PO2 PO3 EIF0 EIE0 PI0 PI1 PI2 PI3 EIES0 PD0 PD1 PD2 PD3 RCNT WE X32D RTSS RTSH RTSL RSSA RASH RASL PO4 ____________________________________________________________________ PO5 PO6 PO7 EIF1 EIE1 PI4 PI5 PI6 PI7 EIES1 PD4 PD5 PD6 Table 5. Peripheral Register Bit Functions (continued) REGISTER BIT 13 — SV67 — OF MA (16 bits) MB (16 bits) MC2 (16 bits) MC1 (16 bits) MC0 (16 bits) SM0/FE SBUF0 (8 bits) — PR0 (16 bits) MC1R (16 bits) MC0R (16 bits) — PCF3 ET2 T2OE0 T2POL0 PCF2 PCF1 DUTY1 DUTY0 FRM3 FRM2 FRM1 FRM0 LCCS LRIG LRA4 PCF0 TR2L LRA3 — LCD[0..15] (8 bits) TR2 CPRL2 SS2 T2V0.9 T2R0.9 T2C0.9 SM1 — ET2L T2V0.8 T2R0.8 T2V0.7 T2R0.7 T2C0.7 T2CI — STBY T2R0.9 T2OE1 T2V0.6 T2R0.6 T2C0.6 DIV2 — SPIC SM2 — T2POL1 T2V0.5 T2R0.5 T2C0.5 DIV1 — ROVR REN — TR2L T2V0.4 T2R0.4 T2C0.4 DIV0 — WCOL TB8 SBUF1 (8 bits) — PR1 (16 bits) TF2 T2V0.3 T2R0.3 T2C0.3 T2MD — OWD (8 bits) MODF MODFE MSTM SPIEN TF2L T2V0.2 T2R0.2 T2C0.2 CCF1 A2 TCC2 T2V0.1 T2R0.1 T2C0.1 CCF0 A1 TC2L T2V0.0 T2R0.0 T2C0.0 C/T2 A0 — ESI1 SMOD1 FEDE1 RB8 TI G2EN T2V0.8 T2R0.8 T2C0.8 RI T2V0.15 T2V0.14 T2V0.13 T2V0.12 T2V0.11 T2V0.10 T2R0.15 T2R0.14 T2R0.13 T2R0.12 T2R0.11 T2R0.10 T2C0.15 T2C0.14 T2C0.13 T2C0.12 T2C0.11 T2C0.10 SPIB (16 bits) SM0/FE LRA2 — LRA1 OPM LRA0 DPE — — — — ESI0 SMOD0 FEDE0 SM1 SM2 REN TB8 RB8 TI RI MCW CLD SQU OPCS MSUB MMAC SUS — — — — WKL WKE1 WKE0 SV66 SV65 SV64 — — SV71 SV70 — — — — — PD7 (2 bits) 12 11 10 9 8 7 6 5 4 3 2 1 0 REGISTER 15 14 PD7 SVS WKO MCNT MA MB MC2 MC1 MC0 SCON0 SBUF0 SMD0 PR0 MC1R MC0R LCRA — — LCFG LCD[0..15] T2CNA0 T2H0 T2RH0 T2CH0 SPIB SCON1 SBUF1 SMD1 PR1 T2CNB0 T2V0 T2V0.15 T2V0.14 T2V0.13 T2V0.12 T2V0.11 T2V0.10 T2V0.9 T2R0 T2R0.15 T2R0.14 T2R0.13 T2R0.12 T2R0.11 T2R0.10 T2C0 T2C0.15 T2C0.14 T2C0.13 T2C0.12 T2C0.11 T2C0.10 T2C0.9 T2C0.8 T2CFG0 OWA OWD MAXQ2000 ____________________________________________________________________ SPICN Low-Power LCD Microcontroller 21 MAXQ2000 REGISTER BIT 13 ESPI1 CKR7 DME — ICDB (8 bits) ICDA (16 bits) ICDD (16 bits) ET2 T2V1.15 T2V1.14 T2V1.13 T2V1.12 T2V1.11 T2V1.10 T2R1.15 T2R1.14 T2R1.13 T2R1.12 T2R1.11 T2R1.10 T2C1.15 T2C1.14 T2C1.13 T2C1.12 T2C1.11 T2C1.10 ET2 T2OE0 T2POL0 TR2L TR2 CPRL2 T2V2.15 T2V2.14 T2V2.13 T2V2.12 T2V2.11 T2V2.10 T2R2.15 T2R2.14 T2R2.13 T2R2.12 T2R2.11 T2R2.10 T2C2.15 T2C2.14 T2C2.13 T2C2.12 T2C2.11 T2C2.10 ET2L T2V1.8 T2R1.8 T2C1.7 ET2L T2V2.8 T2R2.8 T2C2.7 T2CI T2CI T2R2.7 T2V2.7 T2V2.6 T2R2.6 T2C2.6 DIV2 DIV2 T2R2.9 T2OE1 T2C1.6 T2R1.7 T2R1.6 T2R1.5 T2C1.5 T2POL1 T2V2.5 T2R2.5 T2C2.5 DIV1 DIV1 T2V1.7 T2V1.6 T2V1.5 T2R1.9 T2OE1 T2POL1 TR2L T2V1.4 T2R1.4 T2C1.4 TR2L T2V2.4 T2R2.4 T2C2.4 DIV0 DIV0 TF2 T2V1.3 T2R1.3 T2C1.3 TF2 T2V2.3 T2R2.3 T2C2.3 T2MD T2MD TF2L T2V1.2 T2R1.2 T2C1.2 TF2L T2V2.2 T2R2.2 T2C2.2 CCF1 CCF1 T2OE0 T2POL0 TR2L TR2 CPRL2 SS2 T2V1.9 T2R1.9 T2C1.9 SS2 T2V2.9 T2R2.9 T2C2.9 TCC2 T2V1.1 T2R1.1 T2C1.1 TCC2 T2V2.1 T2R2.1 T2C2.1 CCF0 CCF0 G2EN T2V1.8 T2R1.8 T2C1.8 G2EN T2V2.8 T2R2.8 T2C2.8 TC2L T2V1.0 T2R1.0 T2C1.0 TC2L T2V2.0 T2R2.0 T2C2.0 C/T2 C/T2 — — — PSS1 PSS0 SPE TXC — REGE — CMD3 CMD2 CMD1 CMD0 CKR6 CKR5 CKR4 CKR3 CKR2 CKR1 CKR0 — — — — CHR CKPHA CKPOL 12 11 10 9 8 7 6 5 4 3 2 1 0 Low-Power LCD Microcontroller 22 Table 5. Peripheral Register Bit Functions (continued) REGISTER 15 14 SPICF SPICK ICDC ICDF ICDB ICDA ICDD T2CNA1 T2H1 T2RH1 T2CH1 T2CNA2 T2H2 T2RH2 T2CH2 T2CNB1 T2V1 T2V1.15 T2V1.14 T2V1.13 T2V1.12 T2V1.11 T2V1.10 T2V1.9 T2R1 T2R1.15 T2R1.14 T2R1.13 T2R1.12 T2R1.11 T2R1.10 T2C1 T2C1.15 T2C1.14 T2C1.13 T2C1.12 T2C1.11 T2C1.10 T2C1.9 T2C1.8 T2CNB2 T2V2 T2V2.15 T2V2.14 T2V2.13 T2V2.12 T2V2.11 T2V2.10 T2V2.9 T2R2 T2R2.15 T2R2.14 T2R2.13 T2R2.12 T2R2.11 T2R2.10 T2C2 T2C2.15 T2C2.14 T2C2.13 T2C2.12 T2C2.11 T2C2.10 T2C2.9 T2C2.8 ____________________________________________________________________ T2CFG1 T2CFG2 Low-Power LCD Microcontroller Table 6. Peripheral Register Reset Values REGISTER PO0 PO1 PO2 PO3 EIF0 EIE0 PI0 PI1 PI2 PI3 EIES0 PD0 PD1 PD2 PD3 RCNT RTSS RTSH RTSL RSSA RASH RASL PO4 PO5 PO6 PO7 EIF1 EIE1 PI4 PI5 PI6 PI7 EIES1 PD4 PD5 PD6 PD7 SVS WKO 0 0 0 0 0 0 0 0 s s s s s s s s s s s s s s s s 0 s s 0 0 0 0 0 REGISTER BIT 15 14 13 12 11 10 9 8 7 1 1 1 1 0 0 s s s s 0 0 0 0 0 s s s s 0 0 0 0 1 1 0 0 0 0 s s 0 0 0 0 0 0 0 0 6 1 1 1 1 0 0 s s s s 0 0 0 0 0 s s s s 0 0 0 0 1 1 0 0 0 0 s s 0 0 0 0 0 0 0 0 5 1 1 1 1 0 0 s s s s 0 0 0 0 0 0 s s s 0 0 0 0 1 1 0 0 0 0 s s 0 0 0 0 0 0 0 0 4 1 1 1 1 0 0 s s s s 0 0 0 0 0 0 s s s 0 0 0 1 1 1 0 0 0 s s s 0 0 0 0 0 0 0 0 3 1 1 1 1 0 0 s s s s 0 0 0 0 0 1 s s s 0 0 0 1 1 1 0 0 0 s s s 0 0 0 0 0 0 0 0 2 1 1 1 1 0 0 s s s s 0 0 0 0 0 s s s s 0 0 0 1 1 1 0 0 0 s s s 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 s s s s 0 0 0 0 0 s s s s 0 0 0 1 1 1 1 0 0 s s s s 0 0 0 0 0 0 0 0 1 1 1 1 0 0 s s s s 0 0 0 0 0 s s s s 0 0 0 1 1 1 1 0 0 s s s s 0 0 0 0 0 0 0 MAXQ2000 23 ____________________________________________________________________ Low-Power LCD Microcontroller MAXQ2000 Table 6. Peripheral Register Reset Values (continued) REGISTER MCNT MA MB MC2 MC1 MC0 SCON0 SBUF0 SMD0 PR0 MC1R MC0R LCRA LCFG LCD[0..15] T2CNA0 T2H0 T2RH0 T2CH0 SPIB SCON1 SBUF1 SMD1 PR1 T2CNB0 T2V0 T2R0 T2C0 T2CFG0 OWA OWD SPICN SPICF SPICK ICDC ICDF ICDB ICDA ICDD T2CNA1 s s s s s s s s s s s s s s s s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGISTER BIT 15 14 13 12 11 10 9 8 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 s s s s s 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 s s s s s 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 s s s s s 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 s s s s s 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 s s s s s 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 s s s s s 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 s s s s s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 s s s s s 0 24 ____________________________________________________________________ Low-Power LCD Microcontroller Table 6. Peripheral Register Reset Values (continued) REGISTER T2H1 T2RH1 T2CH1 T2CNA2 T2H2 T2RH2 T2CH2 T2CNB1 T2V1 T2R1 T2C1 T2CNB2 T2V2 T2R2 T2C2 T2CFG1 T2CFG2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGISTER BIT 15 14 13 12 11 10 9 8 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAXQ2000 ____________________________________________________________________ 25 Low-Power LCD Microcontroller MAXQ2000 System Timing For maximum versatility, the MAXQ2000 generates its internal system clock from one of five possible sources: • Internal ring oscillator • External high-frequency crystal or ceramic resonator, using an internal oscillator • External high-frequency clock source • External 32kHz crystal or ceramic resonator, using an internal oscillator • External 32kHz clock source A crystal warmup counter enhances operational reliability. Each time the external crystal oscillation must restart, such as after exiting Stop mode, the device initiates a crystal warmup period of 65,536 oscillations. This allows time for the crystal amplitude and frequency to stabilize before using it as a clock source. While in the warmup mode, the device can begin operation from the internal ring oscillator and automatically switch back to the crystal as soon as it is ready. POWER-ON RESET STOP RWT RESET XDOG STARTUP TIMER CLK INPUT CRYSTAL KLL HF CRYSTAL XDOG COUNT RESET DOG WATCHDOG TIMER XDOG DONE RESET WATCHDOG RESET WATCHDOG INTERRUPT MAXQ2000 STOP GLITCH-FREE MUX POWER-ON RESET GLITCH-FREE MUX CLOCK DIVIDER ENABLE CLOCK GENERATION SYSTEM CLOCK RING ENABLE DIV 1 DIV 2 DIV 4 DIV 8 32kHz PWM 32kHz CRYSTAL WAKE-UP ALARM TIMERS SELECTOR DEFAULT RING SELECT SWB INTERRUPT/SERIAL PORT RESET STOP INPUT CRYSTAL MONITOR ENABLE RGMD POWER-ON RESET XDOG DONE RGSL Figure 2. Clock Sources 26 ____________________________________________________________________ Low-Power LCD Microcontroller Power Management Advanced power-management features minimize power consumption by dynamically matching the processing speed of the device to the required performance level. This means device operation can be slowed and power consumption minimized during periods of reduced activity. When more processing power is required, the microcontroller can increase its operating frequency. Software-selectable clock-divide operations allow flexibility, selecting whether a system clock cycle is 1, 2, 4, or 8 oscillator cycles. By performing this function in software, a lower power state can be entered without the cost of additional hardware. For extremely power-sensitive applications, three additional low-power modes are available: • PMM1: divide-by-256 power-management mode (PMME = 1, CD1:0 = 00b) • PMM2: 32kHz power-management mode (PMME = 1, CD1:0 = 11b) • Stop mode (STOP = 1) In PMM1, one system clock is 256 oscillator cycles, significantly reducing power consumption while the microcontroller functions at reduced speed. In PMM2, the device can run even slower by using the 32kHz oscillator as the clock source. The optional switchback feature allows enabled interrupt sources including external interrupts, UARTs, and the SPI module to quickly exit the power-management modes and return to a faster internal clock rate. Power consumption reaches its minimum in Stop mode. In this mode, the external oscillator, system clock, and all processing activity is halted. Stop mode is exited when an enabled external interrupt pin is triggered, an external reset signal is applied to the RESET pin, or the RTC timeof-day alarm is activated. Upon exiting Stop mode, the microcontroller can choose to wait for the external highfrequency crystal to complete its warmup period, or it can start execution immediately from its internal ring oscillator while the warmup period completes. to avoid repeated interrupts from the same source. Application software must ensure a delay between the write to the flag and the RETI instruction to allow time for the interrupt hardware to remove the internal interrupt condition. Asynchronous interrupt flags require a one-instruction delay and synchronous interrupt flags require a two-instruction delay. When an enabled interrupt is detected, software jumps to a user-programmable interrupt vector location. The IV register defaults to 0000h on reset or power-up, so if it is not changed to a different address, the user program must determine whether a jump to 0000h came from a reset or interrupt source. Once software control has been transferred to the ISR, the interrupt identification register (IIR) can be used to determine if a system register or peripheral register was the source of the interrupt. The specified module can then be interrogated for the specific interrupt source and software can take appropriate action. Because the interrupts are evaluated by user software, the user can define a unique interrupt priority scheme for each application. The following interrupt sources are available. Sources marked with an asterisk are not available on the 56-pin version. • Watchdog Interrupt • External Interrupts 0 to 15 (INT10*, INT11*) • RTC Time-of-Day and Subsecond Alarms • Serial Port 0 Receive and Transmit Interrupts • Serial Port 1 Receive and Transmit Interrupts* • SPI Mode Fault, Write Collision, Receive Overrun, and Transfer Complete Interrupts • Timer 0 Low Compare, Low Overflow, Capture/Compare, and Overflow Interrupts • Timer 1 Low Compare, Low Overflow, Capture/Compare, and Overflow Interrupts • Timer 2 Low Compare, Low Overflow, Capture/Compare, and Overflow Interrupts • 1-Wire Presence Detect, Transmit Buffer Empty, Transmit Shift Register Empty, Receive Buffer Full, and Shift Register Full, Short, and Low Interrupts* MAXQ2000 Interrupts Multiple interrupt sources are available for quick response to internal and external events. The MAXQ architecture uses a single interrupt vector (IV), single interrupt-service routine (ISR) design. For maximum flexibility, interrupts can be enabled globally, individually, or by module. When an interrupt condition occurs, its individual flag is set, even if the interrupt source is disabled at the local, module, or global level. Interrupt flags must be cleared within the user-interrupt routine Reset Sources Several reset sources are provided for microcontroller control. Although code execution is halted in the reset state, the high-frequency oscillator and the ring oscillator continue to oscillate. Internal resets such as the poweron and watchdog resets assert the RESET pin low. ____________________________________________________________________ 27 Low-Power LCD Microcontroller MAXQ2000 Power-On Reset An internal power-on reset circuit enhances system reliability. This circuit forces the device to perform a power-on reset whenever a rising voltage on VDDIO climbs above approximately 1.8V. At this point the following events occur: • All registers and circuits enter their reset state • The POR flag (WDCN.7) is set to indicate the source of the reset • The ring oscillator becomes the clock source and • Code execution begins at location 8000h I/O Ports The microcontroller uses the type C and type D bidirectional I/O ports described in the MAXQ Family User’s Guide. The use of two port types allows for maximum flexibility when interfacing to external peripherals. Each port has eight independent, general-purpose I/O pins and three configure/control registers. Many pins support alternate functions such as timers or interrupts, which are enabled, controlled, and monitored by dedicated peripheral registers. Using the alternate function automatically converts the pin to that function. Type-C port pins have Schmitt Trigger receivers and full CMOS output drivers, and can support alternate functions. The pin is either tri-stated or weak pullup when defined as an input, dependent on the state of the corresponding bit in the output register. Type-D port pins have Schmitt Trigger receivers and full CMOS output drivers, and can support alternate functions. The pin is either tri-stated or weak pullup when defined as an input, dependent on the state of the corresponding bit in the output register. All type-D pins also have interrupt capability. Watchdog Timer Reset The watchdog timer functions are described in the MAXQ Family User’s Guide. Execution resumes at location 8000h following a watchdog timer reset. External System Reset Asserting the external RESET pin low causes the device to enter the reset state. The external reset functions as described in the MAXQ Family User’s Guide. Execution resumes at location 8000h after the R ESET pin is released. VDDIO WEAK PD.x SF DIRECTION MUX VDDIO SF ENABLE PO.x SF OUTPUT MUX MAXQ2000 I/O PAD PIN.x PI.x OR SF INPUT FLAG INTERRUPT FLAG DETECT CIRCUIT EIES.x TYPE-D PORT ONLY Figure 3. Type-C/D Port Pin Schematic 28 ____________________________________________________________________ Low-Power LCD Microcontroller High-Speed Hardware Multiplier The hardware multiplier module performs high-speed multiply, square, and accumulate operations, and can complete a 16-bit x 16-bit multiply-and-accumulate operation in a single cycle. The hardware multiplier consists of two 16-bit parallel-load operand registers (MA, MB), an accumulator that is formed by up to three 16-bit parallel registers (MC2, MC1, and MC0), and a status/control register (MCNT). Loading the registers can automatically initiate the operation, saving time on repetitive calculations. The accumulate function of the hardware multiplier is an essential element of digital filtering, signal processing, and PID control systems. The hardware multiplier module supports the following operations: • Multiply unsigned (16 bit x 16 bit) • Multiply signed (16 bit x 16 bit) • Multiply-Accumulate unsigned (16 bit x 16 bit) • • • • Multiply-Accumulate signed (16 bit x 16 bit) Square unsigned (16 bit) Square signed (16 bit) Square-Accumulate unsigned (16 bit) An internal crystal oscillator clocks the RTC using integrated 6pF load capacitors, and give the best performance when mated with a 32.768kHz crystal rated for a 6pF load. No external load capacitors are required. Higher accuracy can be obtained by supplying an external clock source to the RTC. The frequency accuracy of a crystal-based oscillator circuit is dependent upon crystal accuracy, the match between the crystal and the oscillator capacitor load, ambient temperature, etc. An error of 20ppm is equivalent to approximately 1 minute per month. MAXQ2000 Programmable Timers The microcontroller incorporates three 16-bit programmable instances of the Timer 2 peripheral, denoted TR2A, TR2B, and TR2C. These timers can be used in counter/timer/capture/compare/PWM functions, allowing precise control of internal and external events. Timer 2 supports optional single-shot, external gating, and polarity control options. Timer 2 The Timer 2 peripheral includes the following: • 16-bit autoreload timer/counter • 16-bit capture • 16-bit counter • 8-bit capture and 8-bit timer • 8-bit counter and 8-bit timer • Square-Accumulate signed (16 bit) Real-Time Clock A binary real-time clock keeps the time of day in absolute seconds with 1/256-second resolution. The 32-bit second counter can count up to approximately 136 years and be translated to calendar format by the application software. A time-of-day alarm and independent subsecond alarm can cause an interrupt, or wake the device from Stop mode. The independent subsecond alarm runs from the same RTC, and allows the application to perform periodic interrupts up to ones with a granularity of approximately 3.9ms. This creates an additional timer that can be used to measure long periods without performance degradations. Traditionally, long time periods have been measured using multiple interrupts from shorter programmable timers. Each timer interrupt required servicing, with each accompanying interruption slowing system operation. By using the RTC subsecond timer as a long-period timer, only one interrupt is needed, eliminating the performance hit associated with using a shorter timer. Watchdog Timer An internal watchdog timer greatly increases system reliability. The timer resets the device if software execution is disturbed. The watchdog timer is a free-running counter designed to be periodically reset by the application software. If software is operating correctly, the counter will be periodically reset and never reach its maximum count. However, if software operation is interrupted, the timer does not reset, triggering a system reset and optionally a watchdog timer interrupt. This protects the system against electrical noise or electrostatic discharge (ESD) upsets that could cause uncontrolled processor operation. The internal watchdog timer is an upgrade to older designs with external watchdog devices, reducing system cost and simultaneously increasing reliability. ____________________________________________________________________ 29 Low-Power LCD Microcontroller The watchdog timer is controlled through bits in the WDCN register. Its timeout period can be set to one of four programmable intervals ranging from 212 to 221 system clocks in its default mode, allowing flexibility to support different types of applications. The interrupt occurs 512 system clocks before the reset, allowing the system to execute an interrupt and place the system in a known, safe state before the device performs a total system reset. At 16MHz, watchdog timeout periods can be programmed from 256µs to 33.5s, depending on the system clock mode. MAXQ2000 1-Wire Bus Master The MAXQ2000-RAX/-RAX+/-RFX/-RFX+ include a Dallas Semiconductor 1-Wire bus master, which communicates to other 1-Wire peripherals, including iButton® products, through a simple bidirectional signaling scheme over a single electrical connection. The bus master provides complete control of the 1-Wire bus and transmit and receive activities, and generates all timing and control sequences of the 1-Wire bus. Communication between the CPU and the bus master is achieved through read/write access of the 1-Wire master address (OWA) and 1-Wire master data (OWD) peripheral registers. Detailed operation of the 1-Wire bus is described in the B ook of i Button Standards (www.maxim-ic.com/iButtonbook). Serial Peripherals The microcontroller incorporates several common serial-peripheral interfaces for interconnection with popular external devices. Multiple formats provide maximum flexibility and lower cost when designing a system. Serial-Peripheral Interface (SPI) Module The SPI port is a common, high-speed, synchronous peripheral interface that shifts a bit stream of variable length and data rate between the microcontroller and other peripheral devices. The SPI can be used to communicate with other microcontrollers, serial shift registers, or display drivers. Multiple master and slave modes permit communication with multiple devices in the same system. Programmable clock frequency, character lengths, polarity, and error handling enhance the usefulness of the peripheral. The maximum baud rate of the SPI interface is 1/2 the system clock for master mode operation and 1/8 the system clock for slave mode operation. UARTs Serial interfacing is provided through one (-RBX/-RBX+) or two (-RAX/-RAX+/-RFX/-RFX+) 8051-style universal synchronous/asynchronous receiver/transmitters. The UART allows the device to conveniently communicate with other RS-232 interface-enabled devices, as well as PCs and serial modems when paired with an external RS-232 line driver/receiver. The dual independent UARTs can communicate simultaneously at different baud rates with two separate peripherals. The UART can detect framing errors and indicate the condition through a user-accessible software bit. The time base of the serial ports is derived from either a division of the system clock or the dedicated baud clock generator. The following table summarizes the operating characteristics as well as the maximum baud rate of each mode: MODE Mode 0 Mode 1 Mode 2 Mode 3 TYPE Synchronous Asynchronous Asynchronous Asynchronous START BITS N/A 1 1 1 DATA BITS 8 8 8+1 8+1 STOP BIT N/A 1 1 1 MAX BAUD RATE AT 16MHz 4Mbps 500kbps 500kbps 500kbps iButton is a registered trademark of Dallas Semiconductor Corp., a wholly owned subsidiary of Maxim Integrated Products, Inc. 30 ____________________________________________________________________ Low-Power LCD Microcontroller In-Circuit Debug Embedded debugging capability is available through the JTAG-compatible Test Access Port. Embedded debug hardware and embedded ROM firmware provide in-circuit debugging capability to the user application, eliminating the need for an expensive in-circuit emulator. Figure 4 shows a block diagram of the in-circuit debugger. The in-circuit debug features include: • a hardware debug engine, • a set of registers able to set breakpoints on register, code, or data accesses, and • a set of debug service routines stored in the utility ROM. The embedded hardware debug engine is an independent hardware block in the microcontroller. The debug engine can monitor internal activities and interact with selected internal registers while the CPU is executing user code. Collectively, the hardware and software features allow two basic modes of in-circuit debugging: • Background mode allows the host to configure and set up the in-circuit debugger while the CPU continues to execute the application software at full speed. Debug mode can be invoked from background mode. • Debug mode allows the debug engine to take control of the CPU, providing read/write access to internal registers and memory, and single-step trace operation. LCD Controller The MAXQ2000 microcontroller incorporates an LCD controller that interfaces to common low-voltage displays. By incorporating the LCD controller into the microcontroller, the design requires only an LCD glass rather than a considerably more expensive LCD module. Every character in an LCD glass is composed of one or more segments, each of which is activated by selecting the appropriate segment and common signal. The microcontroller can multiplex combinations of up to 33 segment (SEG0–SEG32) outputs and four common signal outputs (COM0–COM3). Unused segment outputs can be used as general-purpose port pins. The segments are easily addressed by writing to dedicated display memory. Once the LCD controller settings and display memory have been initialized, the 17-byte display memory is periodically scanned, and the segment and common signals are generated automatically at the selected display frequency. No additional processor overhead is required while the LCD controller is running. Unused display memory can be used for general-purpose storage. The design is further simplified and cost-reduced by the inclusion of software-adjustable internal voltage dividers to control display contrast, using either VDDIO or an external voltage. If desired, contrast can also be controlled with an external resistance. The features of the LCD controller include the following: • Automatic LCD segment and common-drive signal generation • Four display modes supported: Static (COM0) 1/2 duty multiplexed with 1/2 bias voltages (COM0, COM1) 1/3 duty multiplexed with 1/3 bias voltages (COM0, COM1, COM2) 1/4 duty multiplexed with 1/3 bias voltages (COM0, COM1, COM2, COM3) • Up to 36 segment outputs and four common-signal outputs • 17 bytes (136 bits) of display memory • Flexible LCD clock source, selectable from 32kHz or HFClk / 128 • Adjustable frame frequency • Internal voltage-divider resistors eliminate requirement for external components • Internal adjustable resistor allows contrast adjustment without external components MAXQ2000 MAXQ2000 DEBUG SERVICE ROUTINES (UTILITY ROM) CPU DEBUG ENGINE TMS TCK TDI TDO TAP CONTROLLER CONTROL BREAKPOINT ADDRESS DATA Figure 4. In-Circuit Debugger ____________________________________________________________________ 31 Low-Power LCD Microcontroller MAXQ2000 • Flexibility to use external resistors to adjust drive voltages and current capacity A simple LCD-segmented glass interface example demonstrates the minimal hardware required to interface to a MAXQ2000 microcontroller. A two-character LCD is controlled, with each character containing seven segments plus decimal point. The LCD controller is configured for 1/2 duty cycle operation, meaning the active segment is controlled using a combination of segment signals, and COM0 or COM1 signals are used to select the active display. reduces component count and board space, critical factors in the design of portable systems. The MAXQ2000 is ideally suited for applications such as medical instrumentation, portable blood glucose equipment, and data collection devices. For blood glucose measurement, the microcontroller integrates an SPI interface that directly connects with analog front ends for measuring test strips. Additional Documentation Designers must have four documents to fully use all the features of this device. This data sheet contains pin descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations from published specifications. The user’s guides offer detailed information about device features and operation. The following documents can be downloaded from www.maxim-ic.com/microcontrollers. • The MAXQ2000 errata sheet, available at www.maxim-ic.com/errata. • The M AXQ Family User’s Guide , which contains detailed information on core features and operation, including programming. • The M AXQ Family User’s Guide: MAXQ2000 Supplement, which contains detailed information on features specific to the MAXQ2000. Applications The low-power, high-performance RISC architecture of the MAXQ2000 makes it an excellent fit for many portable or battery-powered applications that require cost-effective computing. The high-throughput core is complemented by a 16-bit hardware multiplier-accumulator, allowing the implementation of sophisticated computational algorithms. Applications benefit from a wide range of peripheral interfaces, allowing the microcontroller to communicate with many external devices. With integrated LCD support of up to 100 or 132 segments, applications can support complex user interfaces. Displays are driven directly with no additional external hardware required. Contrast can be adjusted using a built-in, adjustable resistor. The simplified architecture MAXQ2000 SEG0:7 SEG0 SEG4 SEG1 SEG5 SEG2 SEG3 COM0 COM1 CONNECTED TO DARK GREY SEGMENTS CONNECTED TO LIGHT GREY SEGMENTS SEG6 SEG7 Figure 5. Two-Character, 1/2 Duty, LCD Interface Example 32 ____________________________________________________________________ Low-Power LCD Microcontroller Development and Technical Support A variety of highly versatile, affordably priced development tools for this microcontroller are available from Maxim and third-party suppliers, including: • Compilers • In-circuit emulators • Integrated development environments (IDEs) • JTAG-to-serial converters for programming and debugging A partial list of development tool vendors can be found on our website at www.maxim-ic.com/MAXQ_tools. For technical support, go to www.maxim-ic.com/support. MAXQ2000 Pin Configurations 65 SEG7/P0.7/INT3 64 SEG6/P0.6/INT2 63 SEG5/P0.5/INT1 62 SEG4/P0.4/INT0 53 P7.1/RX0/INT15 68 SEG10/P1.2 TOP VIEW 60 SEG2/P0.2 SEG11/P1.3 SEG12/P1.4 SEG13/P1.5 SEG14/P1.6 SEG15/P1.7 SEG16/P2.0 SEG17/P2.1 SEG18/P2.2 SEG19/P2.3 SEG20/P2.4 SEG21/P2.5 SEG22/P2.6 SEG23/P2.7 SEG24/P3.0 SEG25/P3.1 SEG26/P3.2 SEG27/P3.3 54 VLCD 52 P7.0/TX0/INT14 51 50 49 48 47 46 45 44 67 SEG9/P1.1 66 SEG8/P1.0 61 SEG3/P0.3 59 SEG1/P0.1 58 SEG0/P0.0 56 VLCD2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 55 VLCD1 57 VADJ HFXIN HFXOUT VDD P6.5/T0/WKOUT1 P6.4/T0B/WKOUT0 P6.3/T2/OW_IN P6.2/T2B/OW_OUT P6.1/T1/INT13 P6.0/T1B/INT12 GND P5.7/MISO P5.6/SCLK P5.5/MOSI P5.4/SS P5.3/TX1/INT11 P5.2/RX1/INT10 32KOUT MAXQ2000 43 42 41 40 39 38 37 36 *EP 23 18 19 21 22 20 (132-SEGMENT LCD) 24 25 26 27 28 29 31 30 32 33 34 32KIN 35 SEG28/P3.4/INT4 SEG29/P3.5/INT5 SEG30/P3.6/INT6 SEG31/P3.7/INT7 P4.0/TCK/INT8 P4.1/TDI/INT9 SEG32 SEG33/COM3 SEG34/COM2 SEG35/COM1 VDDIO GND QFN *EP = EXPOSED PAD. ____________________________________________________________________ P4.2/TMS P4.3/TDO RESET COM0 33 Low-Power LCD Microcontroller MAXQ2000 Pin Configurations (continued) 44 P7.1/RXO/INT15 TOP VIEW 48 VADJ 43 P7.0/TXO/INT14 42 41 40 39 38 37 36 56 SEG7/P0.7/INT3 55 SEG6/P0.6/INT2 54 SEG5/P0.5/INT1 53 SEG4/P0.4/INT0 52 SEG3/P0.3 51 SEG2/P0.2 50 SEG1/P0.1 49 SEG0/P0.0 47 VLCD2 46 VLCD1 SEG8/P1.0 SEG9/P1.1 SEG10/P1.2 SEG11/P1.3 SEG12/P1.4 SEG13/P1.5 SEG14/P1.6 SEG15/P1.7 SEG16/P2.4 SEG17/P2.5 SEG18/P2.6 SEG19/P2.7 SEG20/P3.4/INT4 SEG21/P3.5/INT5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 45 VLCD HFXIN HFXOUT VDD P6.5/T0/WKOUT1 P6.4/T0B/WKOUT0 P6.1/T1/INT13 P6.0/T1B/INT12 GND P5.7/MISO P5.6/SCLK P5.5/MOSI P5.4/SS 32KOUT 32KIN MAXQ2000 35 34 33 32 31 30 *EP 16 18 19 17 (100-SEGMENT LCD) 20 21 22 23 24 25 26 27 28 RESET 29 SEG22/P3.6/INT6 SEG23/P3.7/INT7 P4.0/TCK/INT8 P4.1/TDI/INT9 P4.2/TMS SEG25/COM3 SEG26/COM2 SEG27/COM1 TQFN *EP = EXPOSED PAD. 34 ____________________________________________________________________ P4.3/TDO SEG24 COM0 VDDIO GND Low-Power LCD Microcontroller Pin Configurations (continued) P1.0/SEG8 P0.7/SEG7/INT3 P0.6/SEG6/INT2 P0.5/SEG5/INT1 P0.4/SEG4/INT0 P0.3/SEG3 P0.2/SEG2 P0.1/SEG1 P7.1/RX0/INT15 P7.0/TX0/INT14 N.C. N.C. N.C. N.C. MAXQ2000 N.C. P1.1/SEG9 P0.0/SEG0 N.C. N.C. VADJ TOP VIEW 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VLCD2 VLCD1 VLCD HFXIN N.C. N.C. N.C. P1.2/SEG10 P1.3/SEG11 P1.4/SEG12 P1.5/SEG13 P1.6/SEG14 P1.7/SEG15 P2.0 P2.1 P2.2 N.C. N.C. P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 N.C. N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 N.C. N.C. N.C. N.C. HFXOUT VDD P6.5/T0/WKOUT1 P6.4/T0B/WKOUT0 P6.3/T2/OW_IN P6.2/T2B/OW_OUT P6.1/T1/INT13 P6.0/T1B/INT12 GND VDDIO N.C. P5.7/MISO P5.6/SCLK P5.5/MOSI P5.4/SS P5.3/TX1/INT11 N.C. P5.2/RX1/INT10 32KOUT 32KIN N.C. MAXQ2000 62 61 60 59 58 57 56 55 54 53 52 51 (132-SEGMENT LCD) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P4.1/TDI/INT9 VDDIO N.C. N.C. GND P4.0/TCK/INT8 P4.2/TMS P3.5 P3.6 IP3.7 SEG32 COM3 COM2 COM0 N.C. N.C. LQFP ____________________________________________________________________ P4.3/TDO N.C. N.C. N.C. N.C. N.C. RESET N.C. COM1 35 Low-Power LCD Microcontroller MAXQ2000 Typical Operating Circuit VSS GLUCOSE MICROCONTROLLER RS-232 SERIAL PORT PC_RX +3.3V TX +3.3V RS-232 RX PC_TX CHIP INTERFACE CABLE SERIAL DATA DOWNLOAD CONNECTOR VLCD (+3.3V) P7.1RX0/INT15 P7.0TX0/INT14 VSS GND 1-WIRE INTERFACE GND VLCD (+3.3V) TDO JTAG DOWNLOAD/ DEBUG CONNECTOR TMS TDI TCK P4.3/TDO P4.2/TMS P4.1/TDI/INT9 P4.0/TCK/INT8 GNDIO VDDIO P6.1/T1/INT13 PIEZO BUZZER P6.0/T1B/INT12 GNDIO VDDIO VDDIO 200kΩ 200kΩ STRIP INSERTED SEG31/P3.7/INT7 SEG29/P3.5/INT5 GNDIO VLCD (+3.3V) VLCD OR GND GNDIO VSS P6.5/T0/WKOUT TIMER 0 32KCLK VDDIO VDD DIFFERENTIALLY DRIVEN AT ±6.6V AND -2kHz TO 10kHz MAX 1678 VBATT AVDD 2 AAA OR 1 LITHIUM COIN CELL (+1.8V TO +3.6V) DVDD JTAG 4-WIRE SPI INTERFACE VDDIO P5.5/MOSI P5.7/MISO P5.6/SCLK P5.4/SS GNDIO DIN DOUT SCLK CSI UPIO2 UPIO3 UPIO4 UART1 VDDIO P6.2/T2B/OW_OUT P6.3/T2/OW_IN CPOUT 1-WIRE EEPROM GND DATA CAL PORT CONNECTOR 1-WIRE EPROM DATA METER CAL PARAMETERS AND PATIENT DATA STORAGE GND VSS TEST STRIP CAL PARAMETERS MAXQ2000 5kΩ MAX1358 MAX1359 MAX1360 OUTA SWA FBA TEST STRIP PORT CONNECTOR DACA OUTB TEST STRIP AGND DGND UPI01 ON VSS WAKEUP SWB FBB REGULATED +3.3V CPOUT ADC DACB SNO1 VSS VLCD1 VSS CF+ CHARGEPUMP DOUBLER SCM1 SNC1 OUT1 INM1 LINEAR REG INP1 BG REF 116 SEGMENT LCD GLASS SEG[28:5] SEG[0:3] SEG[32] COM[3:1]/SEG[35:33] COM[0] VLCD2 LCD DRIVERS CFREG STRIP INSERTED VADJ VSS DVDD NOTE THAT UP TO 132 LCD SEGMENTS CAN BE DRIVEN IF OTHER MUXED PIN FUNCTIONS ARE NOT USED 32/64kB FLASH/ MASK RTC AND SYSTEM TIMERS/ ALARMS SNO2 GNDIO VSS 32KIN 32.768kHz WATCH XTAL 32K OSC 1-5MHz FLL AIN1 AIN2 SCM2 SNC2 VSS REMOTE TEMPERATURE MEASUREMENT DIODE 32KOUT 32K OSC 32KIN HFXIN VDDIO 16-BIT RISC MICRO INT INT INT GNDIO 200kΩ 200kΩ 200kΩ HF OSC HFXOUT RESET 32KOUT 32kHz MICRO CLOCK (OPTIONAL) CLK32K HIGH-FREQUENCY MICRO CLOCK VDD RESET MONITOR MAX1358/9/60 INTERRUPT RESET CLK VSS SEG30/ MEM P3.6/INT6 P5.3/ UP TX1/INT11 P5.2/ DOWN RX1/INT10 VSS SEG4/P0.4/INTO INT WATCHDOG TIMER GLUCOSE METER CIRCUIT BOARD 36 ____________________________________________________________________ Low-Power LCD Microcontroller Ordering Information PART MAXQ2000-RAX MAXQ2000-RAX+ MAXQ2000-RBX MAXQ2000-RBX+ MAXQ2000-RFX MAXQ2000-RFX+ PROGRAM MEMORY 32kWord Flash 32kWord Flash 32kWord Flash 32kWord Flash 32kWord Flash 32kWord Flash DATA MEMORY 1kWord SRAM 1kWord SRAM 1kWord SRAM 1kWord SRAM 1kWord SRAM 1kWord SRAM LCD SEGMENTS 132 132 100 100 132 132 EXTERNAL INTERRUPTS 16 16 14 14 16 16 UARTS 2 2 1 1 2 2 PINPACKAGE 68 QFN 68 QFN 56 TQFN 56 TQFN 100 LQFP 100 LQFP PKG CODE G6800-4 G6800+4 T5688+2 T5688-2 — — MAXQ2000 Note: All devices are specified over the -40°C to +85°C operating temperature range. +Denotes a Pb-free/RoHS-compliant package. Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 68 QFN 56 TQFN 100 LQFP PACKAGE CODE G6800-4 T5688-2 — DOCUMENT NO. 21-0122 21-0135 21-0297 ____________________________________________________________________ 37 Low-Power LCD Microcontroller MAXQ2000 Revision History REVISION NUMBER 0 1 REVISION DATE 10/04 10/04 DESCRIPTION Initial release for QFN package variant. New product release for TQFN package variant. In the F eatures section under Peripheral Features, corrected accumulator to show 48 bits (not 40 bits). 2 12/04 In the E lectrical Characteristics t able, added Active Current line for 2.2V, 20MHz flash operation; VIH2(MIN) changed from 0.8 x VDDIO t o 0.75 x VDDIO; updated VIH, VIL, VOH, and VOL data to match GBD/FTEC data. Replaced the package drawing for 56-pin package. Added lead-free part numbers to the Ordering Information t able. 3 6/05 In the E lectrical Characteristics t able under LCD Segment Voltage, clarified wording on VADJ spec to VADJ(MIN) = VADJ and VADJ(MAX) = 0 .1V; changed ISEGxx to 3μA. Clarified that flash memory write/erase cycles and data retention specifications are at +25°C. Clarified VIH1/VIH3 specifications, matching presented values to test program values (0.8 x VDDIO); clarified VIH2 specification, matching presented values to test program values (0.8 x VLCD); clarified VIL2 specification, matching presented values to test program values (0.2 x VDDIO). These changes do not affect the testing or operation of the device. Corrected typo on pin 38 (Pin Configuration) from P4/SS to P5.4/SS. 6 7 3/06 6/06 Corrected Pb-free package number denotations. Should be MAXQ2000-RAX+ and MAXQ2000-RBX+. Added Revision A3 typ and max conditions to IDD6 in the E lectrical Characteristics table. Added 100-pin LQFP package. Added EP lines and note to QFN and TQFN pin configurations. 8 12/06 Changed 4kWords Utility ROM (Memory Organization section) to 4kB. Changed 4k x 16 Utility ROM (Figure 1) to 2k x 16 Utility ROM, changed 8FFFh to 87FFh. Changed 4kWord to 4kB (Utility ROM section). Added VDD slew rate specification to E lectrical Characteristics t able. Corrected references of SSEL to SS. 9 3/08 In the Typical Operating Circuit , added the reset monitor to ensure the VDD slew rate specification is met. Added QFN and TQFN package codes to the Ordering Information table; removed package drawings and replaced with Package Information table. PAGES CHANGED — 1 1 2, 3 38 1 3 4 10/05 4 2, 3 5 1/06 33 1, 30, 34 2 1, 7–11, 30, 35, 42 33, 34 13 14 15 2 5, 6 36 37 38 ____________________________________________________________________ Low-Power LCD Microcontroller Revision History (continued) REVISION NUMBER REVISION DATE DESCRIPTION In the E lectrical Characteristics t able, changed the conditions for RLADJ from LRA4:LRA0 = 0 to LRA4:LRA0 = 11111b; added the tSSE parameter to the SPI Timing section. Adjusted the location of “tMOV ” in the SPI Master Timing f igure. PAGES CHANGED 3, 5 6 MAXQ2000 10 7/08 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 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