MAXQ7666

19-4257; Rev 0; 8/08 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System General Description The MAXQ7666 smart systems-on-a-chip (SoC) is a data-acquisition system based on a microcontroller (µC). As a member of the MAXQ® family of 16-bit reduced instruction set computing (RISC) µCs, the MAXQ7666 is ideal for low-cost, low-power, embedded applications such as automotive, industrial controls, and building automation. The flexible, modular architecture design used in this µC allows targeted product development for specific applications with minimal effort. The MAXQ7666 incorporates a high-performance 16-bit RISC core, a 12-bit 500ksps SAR ADC with a programmable-gain amplifier (PGA), a 12-bit DAC with a buffered voltage output, and a full CAN 2.0B controller, supporting transfer rates up to 1Mbps. The device includes an internal crystal oscillator that drives an external crystal of 8MHz for the system clock. An internal 7.6MHz RC oscillator provides an alternate system clock. The MAXQ7666 includes an internal temperature sensor to measure die temperature and an external temperature-sensor driver. The analog functions and digital I/O operate from a +5V supply, while the internal digital core operates from a +3.3V supply. An internal linear regulator can provide +3.3V to the digital supply if an external +3.3V supply is not available. The MAXQ7666 also includes two powersupply supervisors and a JTAG interface for in-system programming and debugging. The device includes 16KB (8K x 16) of program flash memory, up to 512 bytes (256 x 16) of data flash, and 512 bytes (256 x 16) of RAM. The MAXQ7666 is available in a 48-pin TQFN (7mm x 7mm) package and is specified to operate from -40°C to +125°C. o Program and Data Memory 16KB (8K x 16) Program Flash Up to 512 Bytes (256 x 16) Data Flash 512 Bytes (256 x 16) RAM Low-Power, Eight Differential-Channel, 12-Bit, 500ksps ADC PGA, Software-Selectable Gain: 1V/V, 2V/V, 4V/V, 8V/V, 16V/V, 32V/V 12-Bit DAC with Buffered Voltage Output External References for ADC and DAC Internal (Die) and External Diode Temperature Sensing Full CAN 2.0B Controller 15 Message Centers (256-Byte Dual Port Memory) Programmable Bit Rates from 10kbps to 1Mbps Standard 11-Bit or Extended 29-Bit Identification Modes Two Data Masks and Associated IDs for DeviceNET™, SDS, and Other Higher Layer CAN Protocols External Transmit Disable for Autobaud SIESTA Low-Power Mode Wake-Up on CANRXD Edge Transition UART (LIN) with User-Programmable Baud Rate 16 x 16 Hardware Multiplier with 48-Bit Accumulator, Single Clock-Cycle Operation Three 16-Bit (or Six 8-Bit) Programmable Timer/Counter/PWM Eight General-Purpose, Digital I/Os, with External Interrupt Capability Wake-Up Capable Interrupts Internal Oscillator for Use with External Crystal Internal RC Oscillator Eliminates External Crystal External Clock-Source Operation Programmable Watchdog Timer Power-On Reset (POR) Power-Supply Supervisor/Brownout Detection for Digital I/O and Digital Core Supplies On-Chip +3.3V, 50mA Linear Regulator Extensive Debug and Emulation Support In-System Test Capability Flash-Memory-Program Download Software Bootstrap Loader for Flash Programming MAXQ7666 o Smart Analog Peripherals o Timer/Digital I/O Peripherals o Crystal/Clock Module Applications Automotive Steering Sensors CAN- and LIN-Based Automotive Sensors Industrial Control o Power-Management Module o JTAG Interface Features o High-Performance, Low-Power, 16-Bit RISC Core 8MHz Operation, Approaching 1MIPS per MHz Low Power (< 3mA/MIPS, DVDD = +3.3V) 16-Bit Instruction Word, 16-Bit Data Bus 33 Instructions (Most Require Only One Clock Cycle) 16-Level Hardware Stack Three Independent Data Pointers with Automatic Increment/Decrement o Low-Power Consumption Low-Power Stop Mode (CPU Shutdown) Ordering Information and Pin Configuration appear at end of data sheet. MAXQ is a registered trademark of Maxim Integrated Products, Inc. DeviceNet is a trademark of Open DeviceNet Vendor Association, Inc. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 ABSOLUTE MAXIMUM RATINGS DVDD to DGND, AGND, or GNDIO ..........................-0.3V to +4V DGND to GNDIO or AGND....................................-0.3V to +0.3V DVDDIO to DGND, AGND, or GNDIO .......................-0.3V to +6V AVDD to DGND, AGND, or GNDIO...........................-0.3V to +6V Digital Inputs/Outputs to DGND, AGND, or GNDIO ..............................................................-0.3V to (DVDDIO + 0.3V) Analog Inputs/Outputs to DGND, AGND, or GNDIO .................................................................-0.3V to (AVDD + 0.3V) RESET, XIN, XOUT to DGND, AGND, or GNDIO .................................................................-0.3V to (DVDD + 0.3V) Continuous Current into Any Pin.......................................±50mA Continuous Power Dissipation (TA = +70°C) 48-Pin TQFN (derate 40mW/°C above +70°C) ..........3200mW Operating Temperature Range .........................-40°C to +125°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER POWER REQUIREMENTS DVDD Supply Voltage Range AVDD DVDDIO AVDD Supply Current IAVDD Shutdown (Note 2) All analog functions enabled ADC enabled, fADC = 1ksps, fSYSCLK = 8MHz ADC enabled, fADC = 500ksps, fSYSCLK = 8MHz Analog Module Subfunction Incremental Supply Current DAC enabled (zero scale) Internal temperature sensor enabled Additional current when one or more of the ADC, DAC, and/or temperature sensor is enabled (only counted once) PGA enabled CPU in stop mode, all peripherals disabled DVDD Supply Current IDVDD High-speed mode (Note 3) Flash erase or write mode DVDD Module Subfunction Incremental Supply Current DVDDIO Supply Current IDVDDIO DVDD supervisor and brownout monitor High-frequency crystal oscillator Internal RC oscillator All digital I/Os static at GND or DVDDIO (Note 4) 25 2 700 200 10 1000 µA µA Safe mode (RC/2 = 3.8MHz) Normal mode 2.7 3.0 4.75 4.75 3.3 3.3 5.0 5.0 0.1 6.7 4.2 1890 305 502 151 4.5 160 225 28 35 mA µA mA µA 3.6 3.6 5.25 5.25 10 8 µA mA V SYMBOL CONDITIONS MIN TYP MAX UNITS 2 ________________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER MEMORY SECTION Program Flash Total Size Program Flash Page Size Program Flash Erase Size Page erase Erase all Using utility ROM function programFlashWritePage: must erase full two pages and rewrite entire page to change any values on that page Using JTAG boot loader protocol command to load code (family 90h and D0h): must erase full two pages and rewrite two pages Program Flash Erase/ Programming Cell Endurance Program Flash DVDD Supply Voltage Program Flash Erase Timing Program Flash Programming Timing Program Flash Data Retention Data Flash Total Size Data Flash Page Size Erasing, programming, or fetching instructions Page erase Entire flash Page program Full program flash program TA = +85°C Data flash is accessed as 16-bit words (Note 5) 15 512 2 10,000 3.0 3.3 24 240 2.2 575 3.6 30 300 2.75 704 Program flash is accessed as 16-bit words 16 64 4 256 KB Bytes Pages SYMBOL CONDITIONS MIN TYP MAX UNITS MAXQ7666 1 Pages 2 Program Flash Programming Size Cycles V ms ms Years Bytes Bytes _______________________________________________________________________________________ 3 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS Page erase using utility ROM function dataFlashPageErase Data Flash Erase Size Page erase using utility ROM function dataFlashPageEraseEven Erase all Using utility ROM function dataFlashWritePage: must erase full two pages and rewrite entire page to change any values on that page Using utility ROM function dataFlashWritePageEven: must erase one even page and rewrite entire page to change any values on that page 10,000 Erasing, writing, or reading Page erase Entire flash Page write (1 x 16) Data Flash Programming Timing Data Flash Data Retention RAM Data Retention Voltage Data RAM Memory Size Utility ROM Size Full data flash write TA = +85°C 64 x 16 256 x 16 15 2 512 8192 3.0 3.3 24 240 73 4.7 18.7 3.6 30 300 90 5.8 23 MIN TYP 2 1 256 Pages MAX UNITS 1 Pages 1 Data Flash Programming Size Data Flash Erase/Write Cell Endurance Data Flash DVDD Supply Voltage Data Flash Erase Timing Cycles V ms µs ms Years V Bytes Bytes 4 ________________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER ANALOG SENSE PATH Resolution NADC No missing codes Gain = 1, bipolar mode, VIN = ±2500mV, 500ksps Gain = 8, unipolar mode, VIN = +400mV, 142ksps Integral Nonlinearity INLADC Gain = 16, bipolar mode, VIN = ±156mV, 142ksps Gain = 32, bipolar mode, VIN = ±50mV, 142ksps Gain = 1, bipolar, VIN = ±2500mV, 500ksps Differential Nonlinearity Offset Error Offset-Error Temperature Coefficient Zero-Code Error Gain Error Gain-Error Temperature Coefficient Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious-Free Dynamic Range Noise ADC Convert Start Pulse Width Conversion Clock Frequency Sample Rate fADCCLK fSAMPLE SINAD THD SFDR PGA gain = 1V/V PGA gain = 1V/V PGA gain = 1V/V Input referred, gain = 1 Input referred, gain = 32 Minimum pulse width on P0.4/ADCCNV or a timer port when triggering the ADC fSYSCLK = 8MHz PGA gain = 1V/V, RSOURCE ≤ 1kΩ Any PGA gain setting > 1V/V, RSOURCE ≤ 5kΩ 0.5 Bipolar, differential measurement of error for ideal ADC output of 0x000 Exclude offset and reference error -1.0 ±8.5 -71 -85 -91 0.2 3.6 1 8.0 500 142 ksps DNLADC Gain = 16, bipolar, VIN = ±156mV, 142ksps All other gain settings Input referred ±0.6 ±3.2 ±8 ±3.2 +1.0 ±5 mV µV/°C mV % ppm/°C dB dB dB LSBRMS ADC CLK MHz 12 ±0.5 ±2.0 LSB ±2.0 ±2.0 ±1.0 ±1.0 LSB ±4.0 ±4.0 Bits SYMBOL CONDITIONS MIN TYP MAX UNITS MAXQ7666 _______________________________________________________________________________________ 5 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Conversion Time Channel/Gain Select Plus Conversion Time Track-and-Hold Acquisition Time Turn-On Time Aperture Delay Aperture Jitter PGA gain = 1V/V PGA gain = 2V/V Unipolar mode PGA gain = 4V/V PGA gain = 8V/V PGA gain = 16V/V PGA gain = 32V/V PGA gain = 1V/V Input Voltage Range PGA gain = 2V/V PGA gain = 4V/V Bipolar mode PGA gain = 8V/V PGA gain = 16V/V PGA gain = 32V/V Absolute Input Voltage Range Input Leakage Current AIN15–AIN0 PGA gain = 1V/V PGA gain = 2V/V Small-Signal Bandwidth (-3dB) VIN x gain = 100mVP-P PGA gain = 4V/V PGA gain = 8V/V PGA gain = 16V/V PGA gain = 32V/V 0 0 0 0 0 0 -VREFADC /2 -VREFADC /4 -VREFADC /8 -VREFADC /16 -VREFADC /32 -VREFADC /64 AGND ±20 180 140 120 100 82 80 MHz tACQ tRECOV SYMBOL tCONV CONDITIONS tACQ plus 13 ADCCLK cycles at 8MHz PGA gain = 1V/V, RSOURCE ≤ 1kΩ Any PGA gain setting > 1V/V, RSOURCE ≤ 5kΩ PGA gain = 1V/V, RSOURCE ≤ 1kΩ Any PGA gain setting > 1V/V, RSOURCE ≤ 5kΩ 5 30 50 AVDD 1.6 0.8 0.4 0.2 0.1 +VREFADC /2 +VREFADC /4 +VREFADC /8 +VREFADC /16 +VREFADC /32 +VREFADC /64 AVDD V nA V MIN TYP MAX tACQ + 1.625 2 7 375 5 UNITS µs µs ns µs µs ns psP-P 6 ________________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS PGA gain = 1V/V PGA gain = 2V/V Large-Signal Bandwidth (-3dB) VIN x gain = 3.2VP-P PGA gain = 4V/V PGA gain = 8V/V PGA gain = 16V/V PGA gain = 32V/V PGA gain = 1V/V PGA gain = 2V/V Input Capacitance Differential to AGND, any input of AIN0–AIN15 PGA gain = 4V/V PGA gain = 8V/V PGA gain = 16V/V PGA gain = 32V/V Crosstalk Between Channels Input Common-Mode Rejection Ratio Power-Supply Rejection Ratio Resolution Differential Nonlinearity Integral Nonlinearity Offset Error Offset-Error Temperature Coefficient Gain Error Gain-Error Temperature Coefficient DAC Output Range DC Output Impedance Output Slew Rate Output Settling Time Output Short-Circuit Current ZOUT Excludes reference error, tested at E68h Excludes offset and reference drift; calculated from FSR No load Termination resistance to AGND DAC enabled Power-down mode 0 0.5 105 0.6 8 27 -46 15 CMRR PSRR NDAC DNLDAC INLDAC AIN15–AIN0, VIN = 1VP-P, 10kHz, RSOURCE = 5kΩ AIN15–AIN0 (bipolar, differential), VCM = 100mV to 4.5V AVDD = +4.75V to +5.25V Guaranteed monotonic Codes 147h to E68h Codes 147h to E68h Reference to code 040h 70 67 12 ±0.4 ±0.5 ±2.5 ±5 ±3 ±2 VREFDAC ±20 ±1 ±4 ±30 MIN TYP 180 140 120 100 82 80 13.6 2 4 8 16 32 -80 88 72 dB dB dB Bits LSB LSB mV µV/°C LSB ppm of FSR/°C V Ω kΩ V/µs µs mA pF MHz MAX UNITS MAXQ7666 DAC SECTION (DACOUT, RL = 5kΩ and CL = 100pF) 400h to C00h code swing, rising or falling 147h to E68h code swing, settling to ±0.5 LSB (Note 6) Short to AGND Short to AVDD _______________________________________________________________________________________ 7 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER DAC Glitch Impulse DAC Power-On Time Power-Supply Rejection Output Noise EXTERNAL REFERENCE INPUTS REFADC Input Voltage Range REFDAC Input Voltage Range REFDAC Input Impedance REFADC Leakage Current ADC disabled TA = +25°C Internal diode TA = -30°C to +85°C TA = -40°C to +125°C TA = +25°C, TRJ = +25°C Temperature Error TA = -30°C to +85°C, TRJ = +25°C TA = -40°C to +125°C, TRJ = +25°C TA = -30°C to +85°C, TRJ = -30°C to +85°C TA = -40°C to +125°C, TRJ = -40°C to +125°C Internal (Die) or External Temperature Measurement Error vs. VREFADC Variation External Diode Source Current External Diode Drive Current Ratio Conversion Time Temperature Resolution +3.3V LINEAR REGULATOR (CDVDD = 4.7µF) DVDDIO Input Voltage Range DVDD Output Voltage DVDD Input Voltage Range No-Load Quiescent Current Output Short-Circuit Current REGEN = GNDIO REGEN = DVDDIO CPU in sleep mode; all digital peripherals disabled, no external load, REGEN = GNDIO Short to DGND 4.25 3.0 3.0 175 110 5.0 3.4 5.25 3.6 3.6 250 V V V µA mA fADCCLK = fSYSCLK = 8MHz, no interrupts, internal utility ROM tempConv 12-bit ADC High level Low level TEMPERATURE SENSOR (Remote NPN Transistor 2N3904) ±1 ±2 ±5 ±2 ±3 ±3 ±3 ±5 1.0 0 200 1 AVDD AVDD V V kΩ µA SYMBOL CONDITIONS From 7FFh to 800h Excluding reference, settling to ±0.5 LSB AVDD step from +4.75V to +5.25V, code = E66h CL = 200pF MIN TYP 12 14 62 200 MAX UNITS nV·s µs µV/V µVRMS External diode, differential configuration (Note 7) °C 0.095 74.7 4 18.7:1 70 0.125 °C/mV µA µs °C/LSB 8 ________________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER DVDD Voltage-Supervisor Reset Rising Threshold SYMBOL CONDITIONS Power-on default, DVDD voltage rising (Note 8) DVDD voltage falling, firmware selectable, measured with CPU active at 8MHz (Note 9) DVDD voltage falling, firmware selectable, measured with CPU active at 8MHz (Note 10) DVDDIO voltage falling, firmware selectable, measured with CPU active at 8MHz (Note 11) DVDD, DVDDIO Voltage difference between VVDBI and VVDBR, time allowing software clean-up before RESET asserted, VDBI = 11b and VDBR = 10b DVDD Ensure DVDD rises faster than this rate between +2.7V and +3.0V when using either an external DVDD supply or the internal linear regulator After DVDD rises above the VVDBR voltage trip threshold CANCLK = 8MHz 50ppm external crystal error, 8MHz crystal 50ppm external crystal error, 8MHz crystal, clock divided and measured over 500µs interval, mean plus peak cycle jitter Using external crystal External clock source 7.6 7.6 60 < 0.5 VDBR = 00b (default) VDBR = 01b VDBR = 10b VDBR = 11b VDBI = 00b (default) VDBI = 01b VDBI = 10b VDBI = 11b VIOBI = 00b (default) VIOBI = 01b VIOBI = 10b VIOBI = 11b MIN TYP MAX UNITS MAXQ7666 SUPPLY VOLTAGE SUPERVISORS AND BROWNOUT DETECTION 2.70 2.70 2.77 2.84 2.91 2.77 2.84 2.91 2.99 4.25 4.30 4.35 4.40 1 2.99 2.99 3.06 3.13 3.20 2.99 3.13 3.20 3.27 4.74 4.79 4.84 4.89 % V V V V DVDD Voltage-Supervisor Brownout Reset Falling Threshold VVDBR Software-Selectable DVDD Voltage-Supervisor Brownout Interrupt Falling Threshold VVDBI DVDDIO Voltage-Supervisor Brownout Interrupt Threshold VVIOBI Voltage-Supervisor Hysteresis DVDD Brownout-Interrupt to Brownout Reset Falling Threshold Voltage Monitor Supply Voltage Range 155 mV 1.0 3.6 V DVDD Ramp-Up Rate 35 mV/ms RESET Hold Time CAN INTERFACE CAN Baud Rate CANCLK Mean Frequency Error CANCLK Total Frequency Error HIGH-FREQUENCY CRYSTAL OSCILLATOR Clock Frequency 10 ms 1 Mbps ppm % 8.12 8.12 MHz _______________________________________________________________________________________ 9 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Crystal Oscillator Startup Time External Clock Input Duty Cycle Crystal Oscillator Stability SYMBOL 8MHz crystal Ratio high-to-low or low-to-high Excluding crystal HFIC = 00b (default) XIN Input Load Capacitance HFIC = 01b HFIC = 10b HFIC = 11b HFIC = 00b (default) XOUT Output Load Capacitance HFIC = 01b HFIC = 10b HFIC = 11b HFOC = 00b (default), ESR = 240Ω Crystal Oscillator Drive Strength HFOC = 01b, ESR = 240Ω HFOC = 10b, ESR = 240Ω HFOC = 11b, ESR = 240Ω XIN Input Low Voltage XIN Input High Voltage INTERNAL RC OSCILLATOR Oscillator Frequency Oscillator Startup Time Oscillator Jitter UART (LIN) INTERFACE (UTX, URX) UART Baud Rate Minimum LIN Mode Operation Maximum LIN Mode Operation Crystal clock source UART Baud Rates Error RESET (RESET) RESET Internal Pullup Resistance RESET Output Voltage Pullup to DVDD High, RESET deasserted, no load Low, RESET asserted, no load RESET Input High Voltage RESET Input Low Voltage 0.7 x DVDD 0.3 x DVDD 0.9 x DVDD 0.4 V V 305 kΩ V Using internal RC oscillator before autobaud Using internal RC oscillator after autobaud 20 -0.5 -14.0 -0.5 +0.5 +14.0 +0.5 % 2 1 Mbps kbps kbps 7.0 7.6 10 2.7 8.0 MHz µs ns Driven with external clock source Driven with external clock source 0.7 x DVDD 45 3 7 18 27 34 7 18 27 34 62 95 13 23 0.3 x DVDD V V µW pF pF CONDITIONS MIN TYP 10 55 MAX UNITS ms % ppm/V 10 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 0.3 x DVDDIO 0.7 x DVDDIO 500 VIN = GNDIO or DVDDIO, pullup disabled Pullup to DVDDIO VIN = GNDIO or DVDDIO ISINK = 1.6mA ISOURCE = 1.6mA I/Os three-stated I/Os three-stated Short to DVDDIO = +5.25V Short to GNDIO DVDDIO - 0.5 -1 ±0.01 15 -29 28 +1 -1 ±0.01 400 15 0.4 +1 UNITS DIGITAL INPUTS (P0._, CANRXD, URX, REGEN) Input Low Voltage Input High Voltage Input Hysteresis Input Leakage Current Input Pullup Resistance Input Capacitance DIGITAL OUTPUTS (P0._, CANTXD, UTX) Output Low Voltage Output High Voltage Output Leakage Current Output Capacitance Output Short-Circuit Current V V µA pF mA V V mV µA kΩ pF MAXQ7666 Note 1: All devices are 100% production tested at TA = +25°C. Note 2: All analog functions disabled and all digital inputs connected to DVDDIO or GNDIO. Note 3: High-speed mode: CPU and three timers running at 8MHz from an external crystal oscillator, CAN enabled and communicating at 500kbps, all other peripherals disabled, all digital I/Os static at DVDDIO or GNDIO. Note 4: CAN transmitting at 500kbps, one timer output at 500kHz, all active I/Os are loaded with 20pF capacitor, all remaining digital I/Os are at DVDDIO or GNDIO. Note 5: Utility ROM software supports a range of data flash sizes up to 256 x 16 (512 bytes). Refer to the MAXQ7665/MAXQ7666 User’s Guide for details. Note 6: Guaranteed by design and characterization. Note 7: Based on diode ideality factor of 1.008. Note 8: DVDD must rise above VVDBR for RESET to become deasserted. Caution: Operation is not guaranteed for DVDD below +2.7V (utility ROM) or +3.0V (flash). Note 9: RESET is asserted if DVDD falls below VVDBR. Caution: Operation is not guaranteed for DVDD below +2.7V (utility ROM) or +3.0V (flash). Note 10: An interrupt is generated if DVDD falls below VVDBI. Caution: Operation is not guaranteed for DVDD below +2.7V (utility ROM) or +3.0V (flash). Note 11: An interrupt is generated if DVDDIO falls below VVIOBI. Caution: Operation is not guaranteed if DVDDIO or AVDD is below 4.75V, except for the DVDDIO brownout monitor and +3.3V linear regulator, that still operate down to 0V and +4.25V, respectively. ______________________________________________________________________________________ 11 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 Typical Operating Characteristics (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.) PO._ OUTPUT HIGH VOLTAGE vs. SOURCE CURRENT MAXQ7666 toc01 PO._ OUTPUT LOW VOLTAGE vs. SINK CURRENT MAXQ7666 toc02 DAC INL vs. INPUT CODE (VREFDAC = +5V) 0.4 0.3 0.2 INL (LSB) MAXQ7666 toc03 6 5 4 VOH (V) 3 2 1 0 0 2 4 IOH (mA) 6 8 TA = +85°C TA = +125°C TA = -40°C TA = +25°C 3.0 2.5 2.0 VOL (V) 1.5 1.0 0.5 0 TA = +25°C TA = -40°C TA = +125°C TA = +85°C 0.5 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 10 0 2 4 IOL (mA) 6 8 10 0 1000 2000 3000 4000 DIGITAL INPUT CODE DAC DNL vs. INPUT CODE (VREFDAC = +5V) 0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 1000 2000 3000 4000 DIGITAL INPUT CODE 0 MAXQ7666 toc04 DAC OFFSET VOLTAGE vs. TEMPERATURE MAXQ7666 toc05 DAC GAIN ERROR vs. TEMPERATURE MAXQ7666 toc06 0.5 2.5 4.0 2.0 OFFSET VOLTAGE (mV) 3.5 GAIN ERROR (LSB) -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 1.5 3.0 1.0 0.5 2.5 2.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) DAC OFFSET ERROR vs. AVDD SUPPLY VOLTAGE MAXQ7666 toc07 DAC GAIN ERROR vs. AVDD SUPPLY VOLTAGE MAXQ7666 toc08 DACOUT OUTPUT HIGH VOLTAGE vs. SOURCE CURRENT 5.5 5.4 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 0 VREFDAC = +5V OUTPUT CODE = FFFh MAXQ7666 toc09 1.8 4.0 VREFDAC = +4.75V DAC GAIN ERROR (LSB) 3.5 DAC OFFSET ERROR (mV) 1.7 1.6 3.0 VREFDAC = AVDD 2.5 1.5 VREFDAC = AVDD VREFDAC = +4.75V 1.4 4.75 4.85 4.95 5.05 5.15 5.25 AVDD SUPPLY VOLTAGE (V) 2.0 4.75 4.85 4.95 5.05 5.15 5.25 AVDD SUPPLY VOLTAGE (V) VOH (V) 1 2 IOH (mA) 3 4 5 12 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Typical Operating Characteristics (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.) DACOUT OUTPUT LOW VOLTAGE vs. SINK CURRENT MAXQ7666 toc10 MAXQ7666 DACOUT LARGE-SIGNAL STEP RESPONSE (CODE 000h TO FFFh) MAXQ7666 toc11 ADC INL vs. OUTPUT CODE (VREFADC = +5V, 142ksps, PGA GAIN = 16V/V) BIPOLAR MODE VIN = -156mV TO +156mV MAXQ7666 toc12 0.5 VREFDAC = +5V OUTPUT CODE = 000h 1.5 1.0 VREFDAC = +5V 0.4 VOL (V) 0.3 ADC INL (LSB) 4µs/div DACOUT (1V/div) 0.5 0 -0.5 0.2 0.1 -1.0 -1.5 -2048 0 0 1 2 IOL (mA) 3 4 5 -1024 0 1024 2048 DIGITAL OUTPUT CODE ADC DNL vs. OUTPUT CODE (VREFADC = +5V, 142ksps, PGA GAIN = 16V/V) MAXQ7666 toc13 ADC/PGA OFFSET ERROR (GAIN = 16V/V) vs. TEMPERATURE MAXQ7666 toc14 ADC/PGA GAIN ERROR (GAIN = 16V/V) vs. TEMPERATURE 0.8 0.6 GAIN ERROR (% FSR) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 MAXQ7666 toc15 1.0 0.8 0.6 0.4 ADC DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 BIPOLAR MODE VIN = -156mV TO +156mV 1.8 1.6 1.4 OFFSET ERROR (mV) 1.2 1.0 0.8 0.6 0.4 0.2 0 1.0 -1.0 -2048 -1024 0 1024 2048 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) DIGITAL OUTPUT CODE ADC BIPOLAR ZERO-CODE ERROR vs. TEMPERATURE MAXQ7666 toc15b ADC/PGA OFFSET ERROR (GAIN = 16V/V) vs. AVDD SUPPLY VOLTAGE MAXQ7666 toc16 ADC/PGA GAIN ERROR (GAIN = 16V/V) vs. AVDD SUPPLY VOLTAGE -0.1 -0.2 GAIN ERROR (% FSR) -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 VREFADC = AVDD VREFDAC = +4.75V MAXQ7666 toc17 0.6 0.5 ZERO-CODE ERROR (mV) 0.4 0.3 0.2 0.1 0 5.0 4.5 4.0 OFFSET ERROR (mV) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 VREFDAC = +4.75V VREFADC = AVDD 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 4.75 4.85 4.95 5.05 5.15 5.25 4.75 4.85 4.95 5.05 5.15 5.25 AVDD (V) AVDD (V) ______________________________________________________________________________________ 13 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 Typical Operating Characteristics (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.) ADC/PGA ZERO-CODE ERROR (GAIN = 16V/V) vs. AVDD SUPPLY VOLTAGE BIPOLAR MODE 1.75 ZERO-CODE ERROR (mV) 1.50 1.25 1.00 0.75 0.50 0.25 0 4.75 4.85 4.95 5.05 5.15 5.25 AVDD (V) VREFADC = +4.75V VREFADC = AVDD MAXQ7666 toc17b INTERNAL DIODE TEMPERATURE-SENSOR ERROR vs. TEMPERATURE MAXQ7666 toc18 EXTERNAL DIODE TEMPERATURE-SENSOR ERROR vs. TEMPERATURE 4 ERROR (ACTUAL - REPORTED °C) 3 2 1 0 -1 -2 -3 -4 -5 MAXQ7666 toc19 2.00 5 4 ERROR (ACTUAL - REPORTED °C) 3 2 1 0 -1 -2 -3 -4 -5 5 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) EXTERNAL TEMPERATURE-SENSOR ERROR DUE TO CAPACITIVE LOADING MAXQ7666 toc20 DVDD, RESET POWER-UP CHARACTERISTICS MAXQ7666 toc21 DVDD, RESET POWER-DOWN CHARACTERISTICS MAXQ7666 toc22 16 TEMPERATURE-SENSOR ERROR (°C) 14 12 10 8 6 4 2 0 0 5 10 15 20 DVBR[1:0] = 00 DVDD (1V/div) DVDD (1V/div) DVBR[1:0] = 00 RESET (2V/div) RESET (2V/div) 25 10ms/div 10ms/div CAPACITIVE LOAD BETWEEN AIN0 AND AIN1 (nF) MAXIMUM DVDD TRANSIENT DURATION vs. BOR THRESHOLD OVERDRIVE MAXQ7666 toc23 MAXIMUM DVDD TRANSIENT DURATION vs. BOI THRESHOLD OVERDRIVE MAXQ7666 toc24 MAXIMUM DVDDIO TRANSIENT DURATION vs. BOI THRESHOLD OVERDRIVE MAXIMUM TRANSIENT DURATION (μs) 900 800 700 600 500 400 300 200 100 0 1 10 100 1000 BROWNOUT INTERRUPT ASSERTED ABOVE THIS LINE MAXQ7666 toc25 1000 MAXIMUM TRANSIENT DURATION (µs) 900 800 700 600 500 400 300 200 100 0 1 10 100 BOR ASSERTED ABOVE THIS LINE 1000 MAXIMUM TRANSIENT DURATION (µs) 900 800 700 600 500 400 300 200 100 0 1 10 100 BROWNOUT INTERRUPT (BOI) ASSERTED ABOVE THIS LINE 1000 1000 1000 DVDD BOR THRESHOLD OVERDRIVE (mV) DVDD BOI THRESHOLD OVERDRIVE (mV) DVDDIO BOI THRESHOLD OVERDRIVE (mV) 14 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Typical Operating Characteristics (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.) DVDD BOR THRESHOLD VOLTAGE vs. TEMPERATURE MAXQ7666 toc26 MAXQ7666 DVDD BOI THRESHOLD VOLTAGE vs. TEMPERATURE MAXQ7666 toc27 DVDDIO BOI THRESHOLD VOLTAGE vs. TEMPERATURE 4.44 4.43 VDVDDIO-BOI (V) 4.42 4.41 4.40 4.39 4.38 4.37 4.36 4.35 VIOBI[1:0] = 00 MAXQ7666 toc28 2.90 2.89 2.88 2.87 VDVDD-BOR (V) 2.86 2.85 2.84 2.83 2.82 2.81 2.80 DVBR[1:0] = 00 REGEN = DVDDIO 2.95 2.94 2.93 2.92 VDVDD-BOI (V) 2.91 2.90 2.89 2.88 2.87 2.86 2.85 4.45 DVBI[1:0] = 00 REGEN = DVDDIO -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) DVDD LINEAR REGULATOR OUTPUT VOLTAGE vs. DVDDIO SUPPLY VOLTAGE MAXQ7666 toc29 DVDD LINEAR REGULATOR OUTPUT VOLTAGE vs. TEMPERATURE MAXQ7666 toc30 DVDD LINEAR REGULATOR OUTPUT VOLTAGE vs. LOAD CURRENT STOP MODE REGEN = GNDIO MAXQ7666 toc31 4.0 3.5 3.0 DVDD (V) 3.50 3.48 ILOAD = +25mA REGEN = GNDIO CPU IN STOP MODE 3.60 3.55 TA = +125°C DVDD (V) 3.50 TA = +85°C 2.5 2.0 ILOAD = 25mA ILOAD = 50mA DVDD (V) ILOAD = 0mA 3.46 3.44 3.45 TA = +25°C TA = -40°C 3.40 -40 -7 26 59 92 125 TEMPERATURE (°C) 3.40 0 10 20 30 40 50 LOAD CURRENT (mA) 1.5 1.0 3.0 3.5 4.0 REGEN = GNDIO CPU IN STOP MODE 4.5 5.0 5.5 3.42 DVDDIO SUPPLY VOLTAGE (V) DVDD LINEAR REGULATOR OUTPUT VOLTAGE LINE-TRANSIENT RESPONSE (DVDDIO = +4.75V TO +5.25V STEP) MAXQ7666 toc32 DVDD LINEAR REGULATOR OUTPUT VOLTAGE LOAD-TRANSIENT RESPONSE (IDVDD = 0 TO 50mA STEP) MAXQ7666 toc33 DVDD LINEAR REGULATOR DROPOUT VOLTAGE vs. LOAD CURRENT REGEN = GNDIO TA = +85°C TA = +125°C 500 VDROPOUT (mV) 400 TA = +25°C 300 200 100 0 0 10 TA = -40°C VDROPOUT = DVDDIO - DVDD, WHEN DVDDIO IS REDUCED BELOW +5V UNTIL DVDD DROPS BY 100mV. 20 30 40 50 MAXQ7666 toc34 REGEN = GNDIO ILOAD = 25mA DVDD (10mV/div) AC-COUPLED 700 REGEN = GNDIO DVDD (100mV/div) AC-COUPLED 600 DVDDIO (200mV/div) +4.75V OFFSET ILOAD (50mA/div) 100µs/div 200µs/div LOAD CURRENT (mA) ______________________________________________________________________________________ 15 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 Typical Operating Characteristics (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.) RC OSCILLATOR OUTPUT FREQUENCY vs. TEMPERATURE MAXQ7666 toc35 RC OSCILLATOR OUTPUT FREQUENCY vs. DVDD SUPPLY VOLTAGE MAXQ7666 toc36 DVDD ACTIVE SUPPLY CURRENT vs. DVDD SUPPLY VOLTAGE SEE NOTE 3 AFTER ELECTRICAL CHARACTERISTICS TABLE. FLASH ERASE/PROGRAM 20 IDVDD (mA) 15 10 5 0 HIGH-SPEED MODE MAXQ7666 toc37 7.70 7.65 FREQUENCY (MHz) 7.60 7.55 7.50 7.45 7.40 DVDD = +3.3V REGEN = DVDDIO 7.70 7.65 FREQUENCY (MHz) 7.60 7.55 7.50 7.45 7.40 30 25 REGEN = DVDDIO -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 2.7 3.0 DVDD (V) 3.3 3.6 2.7 3.0 DVDD (V) 3.3 3.6 DVDD ACTIVE SUPPLY CURRENT vs. TEMPERATURE SEE NOTE 3 AFTER ELECTRICAL CHARACTERISTICS TABLE. MAXQ7666 toc38 DVDD STOP-MODE SUPPLY CURRENT vs. DVDD SUPPLY VOLTAGE MAXQ7666 toc39 DVDD STOP-MODE SUPPLY CURRENT vs. TEMPERATURE 190 180 IDVDD (µA) 170 BOR ENABLED 160 150 140 BOR DISABLED REGEN = DVDDIO CPU IN STOP MODE ALL PERIPHERALS DISABLED MAXQ7666 toc40 30 25 20 IDVDD (mA) 15 10 5 0 160 REGEN = DVDDIO CPU IN STOP MODE ALL PERIPHERALS DISABLED 200 158 FLASH ERASE/PROGRAM IDVDD (µA) 156 BOR ENABLED BOR DISABLED 152 HIGH-SPEED MODE 154 130 150 -40 -7 26 59 92 125 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 DVDD SUPPLY VOLTAGE (V) TEMPERATURE (°C) 120 -40 -7 26 59 92 125 TEMPERATURE (°C) AVDD ACTIVE SUPPLY CURRENT vs. AVDD SUPPLY VOLTAGE MAXQ7666 toc41 AVDD ACTIVE SUPPLY CURRENT vs. TEMPERATURE MAXQ7666 toc42 AVDD SHUTDOWN SUPPLY CURRENT vs. AVDD SUPPLY VOLTAGE ALL ANALOG FUNCTIONS DISABLED MAXQ7666 toc43 6.0 ALL ANALOG FUNCTIONS ENABLED CONTINUOUS CONVERSION 6.0 ALL ANALOG FUNCTIONS ENABLED CONTINUOUS CONVERSION 1.0 5.8 5.8 0.8 IAVDD (mA) IAVDD (mA) IAVDD (nA) 5.6 5.6 0.6 5.4 5.4 0.4 5.2 5.2 0.2 5.0 4.75 4.85 4.95 5.05 5.15 5.25 AVDD SUPPLY VOLTAGE (V) 5.0 -40 -7 26 59 92 125 TEMPERATURE (°C) 0 4.75 4.85 4.95 5.05 5.15 5.25 AVDD SUPPLY VOLTAGE (V) 16 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Typical Operating Characteristics (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.) AVDD SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE MAXQ7666 toc44 MAXQ7666 DVDDIO DYNAMIC SUPPLY CURRENT vs. DVDDIO SUPPLY VOLTAGE MAXQ7666 toc45 DVDDIO DYNAMIC SUPPLY CURRENT vs. TEMPERATURE CAN COMMUNICATING AT 500kbps ONE TIMER OUTPUT AT 500kHz ALL ACTIVE I/O LOADED WITH 20pF CAPACITORS MAXQ7666 toc46 1000 ALL ANALOG FUNCTIONS DISABLED 200 CAN COMMUNICATING AT 500kbps ONE TIMER OUTPUT AT 500kHz ALL ACTIVE I/O LOADED WITH 20pF CAPACITORS 200 100 175 IDVDDIO (µA) 175 IDVDDIO (µA) IAVDD (nA) 10 150 150 1 0.1 125 125 0.01 -40 -7 26 59 92 125 TEMPERATURE (°C) 100 4.750 100 4.875 5.000 5.125 5.250 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) DVDDIO SUPPLY VOLTAGE (V) DVDDIO STATIC SUPPLY CURRENT vs. DVDDIO SUPPLY VOLTAGE MAXQ7666 toc47 DVDDIO STATIC SUPPLY CURRENT vs. TEMPERATURE MAXQ7666 toc48 AVDD SUPPLY CURRENT vs. ADC SAMPLING RATE MAXQ7666 toc49 300 250 200 150 100 50 0 4.750 ALL DIGITAL I/O STATIC REGEN = DVDDIO 300 250 200 ALL DIGITAL I/O STATIC REGEN = DVDDIO 2.5 2.0 PGA DISABLED AUTOMATIC SHUTDOWN OFF IDVDDIO (nA) IDVDDIO (nA) IAVDD (mA) 1.5 150 100 50 0 1.0 0.5 PGA DISABLED AUTOMATIC SHUTDOWN ON 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 1 10 fADC (ksps) AUTOMATIC SHUTDOWN MAX SAMPLING RATE 100 1000 4.875 5.000 DVDDIO (V) 5.125 5.250 AVDD SUPPLY CURRENT vs. ADC SAMPLING RATE (PGA ENABLED) MAXQ7666 toc50 SAMPLING ERROR vs. INPUT SOURCE IMPEDANCE PGA GAIN = 32V/V MAXQ7666 toc51 6 5 4 IAVDD (mA) 3 2 1 0 1 10 fADC (ksps) 100 PGA ENABLED AUTOMATIC SHUTDOWN ON PGA ENABLED AUTOMATIC SHUTDOWN OFF 1 0 SAMPLING ERROR (LSB) -1 -2 -3 -4 -5 1000 1 10 SOURCE IMPEDANCE (kΩ) 100 ______________________________________________________________________________________ 17 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 Pin Description PIN 1 2 3 4 5, 8 6 7 9 10 11 12 13 14 15 16 17 18, 19, 31 20 21 22 23 24 NAME AIN11 AIN10 AIN9 AIN8 AGND REFADC REFDAC AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 DACOUT DGND CANRXD CANTXD UTX URX P0.6/T0 FUNCTION Analog Input Channel 11. AIN11 is multiplexed to the PGA as a differential input with AIN10. Analog Input Channel 10. AIN10 is multiplexed to the PGA as a differential input with AIN11. Analog Input Channel 9. AIN9 is multiplexed to the PGA as a differential input with AIN8. Analog Input Channel 8. AIN8 is multiplexed to the PGA as a differential input with AIN9. Analog Ground. Connect all AGND nodes together. Connect to DGND at a single point. ADC External Reference Input. Connect an external reference voltage between 1V and AVDD to REFADC. DAC External Reference Input. Connect an external reference voltage between 0V and AVDD to REFDAC. Analog Input Channel 7. AIN7 is multiplexed to the PGA as a differential input with AIN6. Analog Input Channel 6. AIN6 is multiplexed to the PGA as a differential input with AIN7. Analog Input Channel 5. AIN5 is multiplexed to the PGA as a differential input with AIN4. Analog Input Channel 4. AIN4 is multiplexed to the PGA as a differential input with AIN5. Analog Input Channel 3. AIN3 is multiplexed to the PGA as a differential input with AIN2. AIN3–AIN0 have external temperature sensor capability. Analog Input Channel 2. AIN2 is multiplexed to the PGA as a differential input with AIN3. AIN3–AIN0 have external temperature sensor capability. Analog Input Channel 1. AIN1 is multiplexed to the PGA as a differential input with AIN0. AIN3–AIN0 have external temperature sensor capability. Analog Input Channel 0. AIN0 is multiplexed to the PGA as a differential input with AIN1. AIN3–AIN0 have external temperature sensor capability. DAC Buffer Output. DACOUT is the DAC voltage buffer output. Digital Ground for the Digital Core and Flash. Connect all DGND nodes together. Connect to AGND at a single point. CAN Bus Receiver Input. Control area network receiver input. CAN Bus Transmitter Output. Control area network transmitter output. UART or LIN Transmitter Output UART or LIN Receiver Input Port 0 Bit 6/Timer 0. P0.6 is a general-purpose digital I/O with interrupt/wake-up input capability. T0 is a primary timer/PWM input or output. Refer to the MAXQ7665/MAXQ7666 User’s Guide sections 7 and 8. Port 0 Bit 7/Timer 1. P0.7 is a general-purpose digital I/O with interrupt/wake-up input capability. T1 is a primary timer/PWM input or output. Refer to the MAXQ7665/MAXQ7666 User’s Guide sections 7 and 8. Digital I/O Supply Voltage. Supplies all digital I/O except for XIN, XOUT, and RESET. Bypass DVDDIO to GNDIO with a 0.1µF capacitor placed as close as possible to the device. DVDDIO also connects to the input of the linear regulator. Digital I/O Ground. Connect all grounds together at a single point. Internal Connection. Connect I.C. to GNDIO or DVDDIO. Internal Connection. Leave unconnected or connect to DVDDIO. 25 P0.7/T1 26, 39 27 28, 29 30 DVDDIO GNDIO I.C. I.C. 18 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Pin Description (continued) PIN 32 NAME P0.0/TDO FUNCTION Port 0 Data 0/JTAG Serial Test Data Output. P0.0 is a general-purpose digital I/O with interrupt/wake-up capability. TDO is the JTAG serial test, data output. Refer to the MAXQ7665/MAXQ7666 User’s Guide sections 8 and 10. Port 0 Data 1/JTAG Test Mode Select. P0.1 is a general-purpose digital I/O with interrupt/wakeup capability. TMS is the JTAG test mode select input. Refer to the MAXQ7665/MAXQ7666 User’s Guide sections 8 and 10. Port 0 Data 2/JTAG Serial Test Data Input. P0.2 is a general-purpose digital I/O with interrupt/wake-up capability. TDI is the JTAG serial test, data input. Refer to the MAXQ7665/MAXQ7666 User’s Guide sections 8 and 10. Port 0 Data 3/JTAG Serial Test Clock Input. P0.3 is a general-purpose digital I/O with interrupt/wake-up capability. TCK is the JTAG serial test, clock input. Refer to the MAXQ7665/MAXQ7666 User’s Guide sections 8 and 10. Port 0 Data 4/ADC Start Conversion Control. P0.4 is a general-purpose digital I/O with interrupt/wakeup capability. ADCCNV is firmware configurable for a rising or falling edge start/convert to trigger ADC conversions. Refer to the MAXQ7665/MAXQ7666 User’s Guide sections 3 and 8. MAXQ7666 33 P0.1/TMS 34 P0.2/TDI 35 P0.3/TCK 36 P0.4/ADCCNV 37 Port 0 Data 5/DAC Data Register Load/Update Input. P0.5 is a general-purpose digital I/O with P0.5/DACLOAD interrupt/wake-up capability. DACLOAD is firmware configurable for a rising or falling edge to update the DACOUT register. Refer to the MAXQ7665/MAXQ7666 User’s Guide sections 3 and 8. REGEN Active-Low Linear Regulator Enable Input. Connect REGEN to GNDIO to enable the linear regulator. Connect REGEN to DVDDIO to disable the linear regulator. Digital Supply Voltage. DVDD supplies the internal digital core and flash memory. DVDD is internally connected to the output of the internal 3.3V linear regulator. Disable the internal regulator to connect DVDD to an external supply. When using the on-chip linear regulator, bypass DVDD to DGND with a 4.7µF ±20% capacitor with a maximum ESR of 0.5Ω. In addition, bypass DVDD with a 0.1µF capacitor. Place both bypass capacitors as close as possible to the device. Reset Input and Output. Active-low open-drain input/output with internal 305kΩ (typ) pullup to DVDD. Drive low to reset the µC. RESET is low during power-up reset and during DVDD brownout conditions. High-Frequency Crystal Output. Connect an external crystal to XIN and XOUT for normal operation. Leave XOUT unconnected if XIN is driven with an external clock source. XOUT is not driven when using the internal RC oscillator. High-Frequency Crystal Input. Connect an external crystal or resonator to XIN and XOUT for normal operation, or drive XIN with an external clock source. XIN is not driven when using the internal RC oscillator. Analog Supply Voltage Input. Connect AVDD to a +5V supply. Bypass AVDD to AGND with a 0.1µF capacitor placed as close as possible to the device. Analog Input Channel 15. AIN15 is multiplexed to the PGA as a differential input with AIN14. Analog Input Channel 14. AIN14 is multiplexed to the PGA as a differential input with AIN15. Analog Input Channel 13. AIN13 is multiplexed to the PGA as a differential input with AIN12. Analog Input Channel 12. AIN12 is multiplexed to the PGA as a differential input with AIN13. Exposed Pad. EP is internally connected to AGND. Connect EP to AGND externally. 38 40 DVDD 41 RESET 42 XOUT 43 XIN 44 45 46 47 48 — AVDD AIN15 AIN14 AIN13 AIN12 EP ______________________________________________________________________________________ 19 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 Block Diagram IINT EXTERNAL TEMP-SENSE DIODE CURRENT DRIVE 1:2 CURRENT DEMUX AIN0 AIN1 AIN2 AIN3 TEMPERATURE SENSORS INTERNAL TSE ADCMX0 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 AIN1 AIN3 AIN5 AIN7 AIN9 AIN11 AIN13 AIN15 +3.3V LINEAR REGULATOR DVDD EWT AGND T0I HFFINT EIFO UARTI 9:1 MUX SOFTWAREINTERRUPT CONTROLLER T1I T2I CANSTI CANERI VIOBI 17:1 MUX PGAE PGA GAIN = x1, x2, x4, x8, x16, x32 ADCE ADCREF ADCCLK 12-BIT ADC DACREF 12-BIT DAC + DACE ADCOV ADCRY DACE R R REFADC REFDAC ADCMX3 MAXQ7666 DACOUT VIBE DVDDIO BROWNOUT MONITOR DVDDIO GNDIO ADCMX[3.0] DVBI AVDD DVDDIO REGEN RESET DVDD DGND HFRCCLK WATCHDOG TIMER WTR WDI DVDD T0CLK T0I T1CLK T1I T2CLK T2I TIMER0/PWM0 (2 x 8 BITS OR 1 x 16 BITS) TIMER1/PWM1 (2 x 8 BITS OR 1 x 16 BITS) TIMER2/PWM2 (2 x 8 BITS OR 1 x 16 BITS) P0.6/T0 P0.7/T1 DVDD POWER-ONRESET/ BROWNOUT MONITOR VDPE VDBE DVBI 8KB UTILITY ROM 8K x 16 PROGRAM FLASH 256 x 16 DATA FLASH 512 BYTES DATA RAM JTAG INTERFACE PORT 0 I/O REGISTERS CAN CLOCK PRESCALER ADC CLOCK PRESCALER M U X CANCLK P0.4/ADCCNV 16-BIT MAXQ20 RISC CPU P0.5/DACLOAD PD0 PO0 PI0 PORT 0 I/O REGISTERS I/O BUFFERS DVDDIO P0.3/TCK P0.2/TDI P0.1/TMS P0.0/TDO EIF0 I/O BUFFERS DVDD GNDIO DGND 16 x 16 HW MULTIPLY UARTI UART INTERFACE GNDIO UTX URX XIN XOUT HF XTAL OSC. HFFINT XHFRY XHFE HFCLK ADCCLK HF CLOCK PRESCALER DGND INT HF R-C OSC HFRCCLK RCE TIMER CLOCK PRESCALERS 2:1 M U X DVDDIO SYSCLK CANSTI CAN 2.0B INTERFACE DGND GNDIO I/O BUFFERS CANTXD CANRXD SYSCLK AGND T0CLK T1CLK T2CLK CANERI CANCLK GNDIO 20 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Detailed Description The 16-bit RISC core (MAXQ20) of the MAXQ7666 controls the analog and digital peripheral functions. The 16-bit RISC ALU addresses 16KB (8K x 16) program flash, up to 512 bytes (256 x 16) data flash and 512 bytes (256 x 16) of RAM memory with Harvard memory architecture. The MAXQ7666 peripheral components include a precision 12-bit 500ksps ADC with an 8-channel differential mux and PGA, a 12-bit precision DAC, an internal temperature sensor, an external temperature-sensor driver, a hardware multiplier, eight digital I/Os, a controller area network (CAN 2.0B) bus, a JTAG interface, and three type-2 timers. An internal 7.6MHz RC oscillator or a crystal oscillator driving an external crystal of 8MHz provide the system clock. The device also includes a +3.3V linear regulator, watchdog timer, and two power-supply supervisors. The MAXQ20 offers a low < 3mA/MIPS ratio. The integrated 16-bit x 16-bit hardware multiplier with accumulator performs single-cycle computations. Refer to the MAXQ7665/MAXQ7666 User’s Guide for more detailed information on configuring and programming the MAXQ7666. MAXQ7666 Analog Input Peripheral The integrated 12-bit ADC employs an ultra-low-power, high-precision, SAR-based conversion method and operates up to 500ksps (142ksps with PGA ≥ 2). The ADC measures eight fully differential multiplexed analog inputs with software-selectable input ranges through a PGA. See Figure 1. TIMERS 0, 1, 2 P0.4/ADCCNV ADCBY ADCS AIN0 AIN2 AIN4 AIN6 AIN8 AIN10 AIN12 AIN14 AIN1 AIN3 AIN5 AIN7 AIN9 AIN11 AIN13 AIN15 ADCE ADC CLOCK DIV SYSCLK SOURCE ADCASD 8:1 MUX PGAE ADCDIF PGA 1 TO 32 12-BIT ADC 500ksps 12 DATA BUS 8:1 MUX 2 PGG 1 0 ADCBIP ADCOV ADCRDY CONVERSION CONTROL 2 1 0 ADCDUL 4 REFADC ADCMX 321 0 2 MAXQ7666 1 ADCCD 0 Figure 1. Simplified Analog Input Diagram (Eight Fully Differential Inputs) ______________________________________________________________________________________ 21 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System The MAXQ7666 ADC converts temperature and voltage signals into a 12-bit digital result using a fully differential SAR conversion technique and an on-chip T/H block. An analog input channel mux supports 8 differential channels. The differential analog inputs are selected from the following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, AIN6/AIN7, AIN8/AIN9, AIN10/AIN11, AIN12/AIN13, and AIN14/AIN15. External temperature-sensor configuration in differential mode uses analog input channel pairs AIN2/AIN3 and AIN0/AIN1. Use AIN0 and AIN2 in single-ended external temperature-sensor configuration. Internal temperaturesensor configuration measures internal die temperature and does not use any analog input channel. There are four ways to control the ADC conversion timing: 1) Software register bit control 2) Continuous conversion 3) Internal timers (T0, T1, or T2) 4) External input through pin ADCCNV Refer to the MAXQ7665/MAXQ7666 User’s Guide for more detailed information on the ADC and mux. MAXQ7666 REFDAC DACE DAC INPUT REGISTER DAC OUTPUT REGISTER 12-BIT DAC DACOUT R P0.5/DACLOAD DAC LOAD CONTROL R MAXQ7666 AGND Figure 2. Simplified DAC Diagram 12-Bit Digital-to-Analog Converter (DAC) The MAXQ7666 contains a 12-bit voltage-output DAC with an output buffer. The data path to the DAC is double buffered. Update the DAC output register using the DACLOAD digital input or software. Refer to the MAXQ7665/MAXQ7666 User’s Guide for detailed programming information. The DAC also supports a square-wave-output toggle mode with precise amplitude control for applications that require pulse-amplitude modulation (PAM) and/or pulse-width modulation (PWM) signals. See Figure 2 for a simplified block diagram of the DAC. The DAC output buffer is configured as a voltage follower (gain of 1V/V from REFDAC). Disable the buffer using software. When the buffer is disabled, the output is connected internally to AGND through a 100kΩ resistor. The reference input REFDAC accepts an input voltage of less than or equal to AVDD for a maximum output swing of 0V to AVDD. Temperature Sensor The internal ADC and a ROM-based tempConv subroutine measure temperature. Use the tempConv subroutine to initiate a measurement (refer to the MAXQ7665/ MAXQ7666 User’s Guide for detailed information). The device supports conversions of two external and one internal temperature sensor. The external temperature sensor is typically a diode-connected small-signal transistor, connected between two analog inputs (differential) or one analog input and AGND (single-ended). Figures 3 and 4 illustrate these two configurations. 22 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 AIN15 AIN3 AIN2 AIN1 AIN0 CURRENT SOURCES ADCMX3 MUX 12-BIT ADC 500ksps 2N3904 2N3904 AGND 4 ADCMX 321 0 MAXQ7666 Figure 3. Temperature-Sensor Application Circuit—Single-Ended Configuration AIN15 AIN4 2N3904 AIN2 AIN3 AIN0 AIN1 ADCMX 321 MUX 12-BIT ADC 500ksps CURRENT SOURCES ADCMX3 2N3904 AGND 4 0 MAXQ7666 Figure 4. Temperature-Sensor Application Circuit—Differential Configuration Power-On Reset and Brownout Power supplies DV DD and DV DDIO each include a brownout monitor that alerts the µC through an interrupt when their corresponding supply voltage drops below a selectable threshold. This condition is generally referred to as brownout interrupt (BOI). Set the thresholds using the VDBI and VIOBI bits for DVDD and DV DDIO, respectively. Monitoring the supplies allows for appropriate action to be taken in a brownout condition. The DVDDIO brownout monitor also covers the analog peripherals if AVDD and DVDDIO are directly connected. The DVDD supply (internal core logic) also includes a voltage supervisor that controls the µC reset during power-up (DV DD rising) and brownout reset (DV DD falling) conditions (see Figure 5 for a POR and brownout timing example). ______________________________________________________________________________________ 23 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 NOMINAL DVDD (+3.3V) BROWNOUT INTERRUPT TRIGGER POINT +3.13V +3.06V DVDD BROWNOUT INTERRUPT THRESHOLD RANGE VDBI[1:0] = 01 +2.84V BROWNOUT RESET +2.77V TRIGGER POINT BROWNOUT INTERRUPT BROWNOUT RESET POWER-UP* DELAY (8.6ms) DVDD BROWNOUT RESET THRESHOLD RANGE VDBR[1:0] = 01 INTERNAL RESET RESET OUTPUT BOR STATE DGND DVLVL FLAG (ASR[14]) VDBE BIT SET BY µC DVBI FLAG (ASR[4]) FLAG ARBITRARILY CLEARED BY µC *POWER-UP DELAY IS ONLY PRESENT WHEN DVDD DROPS BELOW ~1.2V Figure 5. DVDD Brownout Interrupt Detection During power-up, RESET is held low once DVDD rises above +1.0V. All internal register bits are set to their default, POR state after DVDD exceeds a threshold of approximately +1.2V. DV DD brownout reset (BOR) threshold defaults to the +2.70V to +2.99V range following POR. Once DVDD rises above this DVDD brownout threshold, the 7.6MHz RC oscillator starts driving the power-up counter, and 8.6ms (typ) later, RESET goes high if nothing external holds it low. Ramp-up DVDD at a rate of at least 35mV/ms between +2.7V and +3.0V to ensure RESET is held low before DVDD reaches a minimum flash operating level of +3.0V. After DVDD reaches a valid level and RESET goes high, software execution begins at the reset vector (8000h in the utility ROM). Perform software clean-up when DVDD BOI is generated before DV DD BOR occurs. The amount of time between BOI and BOR detection depends on the brownout interrupt and reset threshold settings, the size of the DVDD bypass capacitors, and the applicationdependent µC power management and software cleanup tasks. Use the internal +3.3V linear regulator for additional software cleanup time by using the DVDDIO brownout monitor as an early warning that the regulator’s input voltage is falling. RESET is pulled low when DVDD falls below the DVDD BOR threshold set by the VDBR bits. Upon reset, the µC and peripheral activity stops and most registers are 24 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System set to their default state. The VDBR bits retain their value if DV DD falls below the BOR threshold but remains above the POR threshold. The following scenarios apply once DVDD enters BOR: • If DV DD remains below the BOR threshold, the RESET pin remains low, and the µC remains in the reset state. • If DV DD stops falling before reaching the POR threshold, then begins rising above the BOR threshold, the RESET pin is released and the µC jumps to the reset vector (8000h in the utility ROM). This is similar to the DVDD power-up case described in the previous scenario, except there is no power-up counter delay and some of the register bits are set to BOR values rather than POR values. See Tables 3 and 5 for the reset behavior of specific bits. In particular, the retained VDBR setting, if higher than the default value of 00b, allows a potentially more robust brownout recovery closer to or above the minimum flash operating level of +3.0V. • If DVDD falls below the 1.2V POR threshold, all register bits are reset, and any DVDD recovery from that point is identical to the power-up case described above. See Tables 3 and 5 for the reset behavior of specific bits. Refer to the MAXQ7665/MAXQ7666 User’s Guide for detailed programming information, and a more thorough description of POR and brownout behavior. single SYSCLK period. The oscillator module contains all of the primary clock-generation circuitry. Figure 6 shows a block diagram of the system clock module. The MAXQ7666 supports many features for generating a master clock signal timing source: • Internal, fast-starting, 7.6MHz RC oscillator eliminates external crystal • Internal high-frequency oscillator that can drive an external 8MHz crystal • External high-frequency clock input (8MHz) • Selectable internal capacitors for high-frequency crystal oscillator • Power-up timer • Fail-safe modes MAXQ7666 Watchdog Timer The primary function of the watchdog timer is to watch for stalled or stuck software. The watchdog timer performs a controlled system restart when the µP fails to write to the watchdog timer register before a selectable timeout interval expires. In some designs, the watchdog timer is also used to implement a real-time operating system (RTOS) in the µC. When used to implement an RTOS, a watchdog timer typically has four objectives: 1) To detect if a system is operating normally 2) To detect an infinite loop in any of the tasks 3) To detect an arbitration deadlock involving two or more tasks 4) To detect if some lower priority tasks are not running because of higher priority tasks Internal 3.3V Linear Regulator An internal +3.3V/50mA linear regulator provides alternate supply to the MAXQ7666 core logic if an external supply is not used. Connect R EGEN to GNDIO to enable the linear regulator. When using the linear regulator, ensure the DVDDIO supply can support both the I/O and digital supply current requirements. Connect REGEN to DVDDIO when using a +3.3V external supply. Apply DVDDIO before DVDD when using external supply for DVDD. HFE XIN XOUT RCE XT System Clock Generator The MAXQ7666 oscillator module is the master clock generator that supplies the system clock for the µC core and all of the peripheral modules using either a crystal oscillator or an internal RC oscillator. The crystal oscillator operates with an 8MHz crystal. Use the RC oscillator in applications that do not require precise timing. The MAXQ7666 executes most instructions in a HF XTAL OSC EXTHF RC OSC HFRCCLK MUX CLOCK DIVIDE SYSCLK CD0 Figure 6. Crystal and RC Oscillator Block Diagram ______________________________________________________________________________________ 25 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 As illustrated in Figure 7, the internal RC oscillator (HFRCCLK) is the only clock source for the watchdog timer (through a series of dividers). The divider output is programmable and determines the timeout interval. When enabled, the interrupt flag WDIF is set when a timeout is reached. A system reset then occurs after a time delay (based on the divider ratio). The watchdog timer functions as the source of both the watchdog interrupt and the watchdog reset. The interrupt timeout has a default divide ratio of 212 of the HFRCCLK, with the watchdog reset set to timeout 29 clock cycles later. With the nominal RC oscillator value of 7.6MHz, an interrupt timeout occurs every 539µs, followed by a watchdog reset 67.4µs later. The watchdog timer resets to the default divide ratio following any reset. Using the WD0 and WD1 bits in the WDCN register, select other divide ratios for longer watchdog interrupt periods. If the WD[1:0] bits are changed before the watchdog interrupt timeout occurs (i.e. before the watchdog reset counter begins), the watchdog timer count is reset. All watchdog timer reset timeouts follow the programmed interrupt timeout 512 source clock cycles later. For more information on the MAXQ7666 watchdog timer, refer to the MAXQ7665/MAXQ7666 User’s Guide. HFRCCLK (7.6MHz) DIV 212 DIV 23 DIV 23 DIV 23 Timer and PWM The MAXQ7666 includes three 16-bit timers. Each timer is a type 2 timer implemented in the MAXQ family (see Figure 8). Two of the timers are accessible through I/Os or software, and one is accessible only through software. Type 2 timers are auto-reload 16-bit timers/counters offering the following functions: • 8-bit/16-bit timer/counter • Up/down auto-reload • Counter function of external pulse • Capture • Compare WD1 WD0 RWT 212 215 218 221 TIME TIMEOUT WDIF EWDI WTRF RESET EWT RESET INTERRUPT Figure 7. Watchdog Functional Diagram TR2L T2MD T2L COMPARE MATCH T2CL T2CH T2H:T2L COMPARE MATCH OR T2H COMPARE MATCH T2L T2H T2CLK T2RL T2RH C/T2 EDGE DETECTION AND GATING T2L OVERFLOW T2H:T2L OVERFLOW OR T2H OVERFLOW TIMER EVENT CCF[1:0] G2EN TR2 SS2 T2POL[0] Figure 8. Type 2 Timer Functional Diagram 26 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Note: The MAXQ7666 does not have secondary timer I/Os (such as T0B and T1B) that are present in some other MAXQ products. • Unsigned 16-bit multiplication (one cycle) • Unsigned 16-bit multiplication and accumulation (two cycles) • Unsigned 16-bit multiplication and subtraction (two cycles) • Signed 16-bit multiplication (one cycle) • Signed 16-bit multiplication and negate (one cycle) • Signed 16-bit multiplication and accumulation (two cycles) • Signed 16-bit multiplication and subtraction (two cycles) Figure 9 illustrates the simplified hardware multiplier circuitry. MAXQ7666 16-Bit x 16-Bit Hardware Multiplier A hardware multiplier supports high-speed multiplications. The multiplier completes a 16-bit x 16-bit multiplication in a single clock cycle and contains a 48-bit accumulator that requires one more cycle. The multiplier is a peripheral that performs seven different multiplication operations: 15 MA 0 15 MB 0 CAN Interface Bus SUS MMAC MSUB MCNT OPCS SQU CLD MCW MULTIPLIER OVERFLOW 15 0 15 0 15 0 15 0 15 0 MC1R MC0R MC2 MC1 MC0 Figure 9. 16-Bit Hardware Multiplier Functional Diagram The MAXQ7666 CAN controller fully complies with the CAN 2.0B specification. The µC interface to the CAN controller utilizes two groups of registers. To simplify the software associated with the operation of the CAN controllers, most of the global CAN status and controls as well as the individual message center control/status registers are located in the peripheral register map. The remaining registers associated with the data identification, identification masks, format, and data are located in a dual port memory to allow the CAN controller and the processor access to the required functions. The CAN controller directly accesses the dual port memory. A dedicated interface supports dual port memory accessing by the processor through the CAN 0 data pointer (C0DP) and the CAN 0 data buffer (C0DB) special function registers. ______________________________________________________________________________________ 27 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System CAN Functional Description The basic functions covered by the CAN controller include the use of 11-bit standard or 29-bit extended acceptance identifiers, as programmed by the µC for each message center, as shown in Figure 10. The CAN unit stores up to 15 messages, with the standard 8-byte data field in each message. Each of the first 14 message centers is programmable in either transmit or receive mode. Message center 15 is a receive-only message center with a buffer FIFO arrangement to help prevent the inadvertent loss of data when the µC is busy and is not allowed time to retrieve the incoming message prior to the acceptance of a second message into message center 15. Message center 15 also utilizes an independent set of mask registers and identification registers, only applied once an incoming message has not been accepted by any of the first 14 message centers. A second filter test is also supported for all message centers (1–15) to allow the CAN controller to use two separate 8-bit media masks and media arbitration fields to verify the contents of the first 2 bytes of data of each incoming MAXQ7666 CAN 0 CONTROLLER BLOCK DIAGRAM DUAL PORT MEMORY MESSAGE CENTERS 1–15 MESSAGE CENTER 1 ARBITRATION 0–3 DATA 0–7 FORMAT 8-BIT Tx MESSAGE CENTER 2 ARBITRATION 0–3 DATA 0–7 FORMAT CAN PROTOCOL FSM CRC GENERATE BIT STUFF Tx SHIFT CANTXD 8-BIT Rx CRC CHECK CAN PROCESSOR BUS ACTIVITY WAKE-UP BIT DESTUFF Rx SHIFT BIT TIMING CANRXD CAN INTERRUPT SOURCES MESSAGE CENTER 14 ARBITRATION 0–3 DATA 0–7 FORMAT CAN 0 PERIPHERAL REGISTERS MESSAGE CENTER 15 ARBITRATION 0–3 DATA 0–7 FORMAT CAN 0 TRANSMIT ERROR COUNTER CAN 0 RECEIVE ERROR COUNTER CAN 0 CONTROL REGISTER CAN 0 OPERATION CONTROL CONTROL/STATUS/MASK REGISTERS MEDIA ID MASK 0–1 MEDIA ARBITRATION 0–1 BUS TIMING 0–1 STD GLOBAL MASK 0–1 EXT GLOBAL MASK 0–3 MSG15 MASK 0–3 CAN 0 MESSAGE 1–15 CONTROL REGISTERS CAN 0 DATA POINTER CAN 0 DATA BUFFER CAN 0 STATUS REGISTER CAN 0 INTERRUPT REGISTER CAN 0 TRANSMIT MSG ACK CAN 0 RECEIVE MSG ACK MAXQ7666 Figure 10. CAN 0 Controller Block Diagram 28 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 SBUF0 OUTPUT SHIFT REGISTER LOAD CLOCK S0 D7 D6 D5 D4 D3 D2 D1 D0 LATCH URX INPUT SYSCLK DIVIDE BY 12 0 DIVIDE BY 4 1 LDSBUF RDSBUF LOAD SERIAL BUFFER BAUD CLOCK INTS SERIAL I/O CONTROL SHIFT READ SERIAL SBUF0 RD RECEIVE DATA BUFFER WR DATA BUS RECEIVE BUFFER DATA CLOCK CLOCK SI RECEIVE SHIFT REGISTER D7 D6 D5 D4 D3 D2 D1 D0 UTX OUTPUT TI FLAG = SCON0.1 RI FLAG = SCON0.0 SERIAL INTERRUPT Figure 11a. UART Synchronous Mode (Mode 0) message, before accepting an incoming message. This feature allows the CAN unit to directly support the use of higher CAN protocols, which make use of the first and/or second byte of data as a part of the acceptance layer for storing incoming messages. Program each message center independently to perform testing of the incoming data with or without the use of the global masks. Global controls and status registers in the CAN unit allow the µC to evaluate error messages, validate new data and the location of such data, establish the bus timing for the CAN bus, establish the identification mask bits, and verify the source of individual messages. In addition, each message center is individually equipped with the necessary status and controls to establish directions, interrupt generation, identification mode (standard or extended), data field size, data status, automatic remote frame request and acknowledgment, and masked or nonmasked identification acceptance testing. UART Interface Use the 8051-style universal synchronous/asynchronous receiver/transmitter (UART) capable of interfacing with a LIN transceiver for serial interfacing. Figure 11a shows the UART block diagram in synchronous mode and Figure 11b shows asynchronous mode. The UART allows the device to conveniently communicate with other RS-232 interface-enabled devices, as well as PCs and serial modems when paired with an external RS232 line driver/receiver. The UART can detect framing errors and indicate the condition through a user-accessible software bit. The time base of the serial port is derived from either a division of the system clock or the dedicated baud clock generator. The UART is capable of supporting LIN protocol implementation in software when using one of the timers for autobaud detection. Table 1 summarizes the operating characteristics as well as the maximum baud rate of each mode. Refer to the MAXQ7665/MAXQ7666 User’s Guide for detailed UART information. 29 ______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 SBUF0 TRANSMIT SHIFT REGISTER LOAD CLOCK START STOP S0 LATCH UTX OUTPUT D7 D6 D5 D4 D3 D2 D1 D0 SYSCLK 1 0 DIVIDE BY 4 0 SMOD LDSBUF RDSBUF LOAD SERIAL BUFFER BAUD CLOCK RESET INTS SHIFT READ SERIAL BUFFER LOAD RB8 = SCON0.2 RD RECEIVE DATA BUFFER SBUF0 WR 1 DATA BUS BAUD CLOCK GENERATOR DIVIDE BY 16 SERIAL I/O CONTROL START CLOCK TI FLAG = SCON0.1 RI FLAG = SCON0.0 SERIAL INTERRUPT SI RECEIVE SHIFT REGISTER DIVIDE BY 16 BIT DETECTION URX INPUT Figure 11b. UART Asynchronous Mode (Mode 1) JTAG Interface Bus The joint test action group (JTAG) IEEE 1149.1 standard defines a unique method for in-circuit testing and programming. The MAXQ7666 conforms to this standard, implementing an external test access port (TAP) and internal TAP controller for communication with a JTAG bus master, such as an automatic test equipment (ATE) system. For detailed information on the TAP and TAP controller, refer to IEEE Standard 1149.1 on the IEEE website at http://standards.ieee.org. The JTAG on the MAXQ7666 is used for in-circuit emulation and debug support, but does not support boundary scan test capability. Disable the JTAG function after powerup before normal operation. The TAP controller communicates synchronously with the host system (bus master) through four digital I/O pins: test mode select (TMS), test clock (TCK), test data input (TDI), and test data output (TDO). The internal TAP module consists of several shift registers and a TAP controller (see Figure 12). The shift registers serve Table 1. UART Operating Characteristics and Mode Baud Rate MODE Mode 0 Mode 1 Mode 2 Mode 3 TYPE Synchronous Asynchronous Asynchronous Asynchronous BAUD CLOCK 4 or 12 clock Baud generation 32 or 64 clock Baud generation START BITS N/A 1 1 1 DATA BITS 8 8 8+1 8+1 STOP BITS N/A 1 1 1 MAX BAUD RATE AT 8MHz 2Mbps 250kbps 250kbps 250kbps 30 _______________________________________________________________________________________ START D7 D6 D5 D4 D3 D2 D1 D0 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System as transmit-and-receive data buffers for a debugger. From a JTAG perspective, shift registers are userdefined optional data registers. The bypass register and the instruction register, for example, are realized as a set of shift-register-based elements connected in parallel between a common serial input (TDI) and a common serial output (TDO). The instruction register, through the TAP controller, selects one of the registers to form an active serial path. Maintain the maximum TCK clock frequency to below 1/8 of the system clock frequency for proper operation. The following four digital I/Os form the TAP interface: • TDO—Serial output signal for test instruction and data. Data transitions on the falling edge of TCK. TDO idles high when inactive. TDO serially transfers internal data to the external host. Data transfers least significant bit first. • TDI—Serial input signal for test instruction and data. Transition data on the rising edge of TCK. TDI pulls high when unconnected. TDI serially transfers data from the external host to the internal TAP module shift registers. Data transfers least significant bit first. • TCK—Serial clock for the test logic. When TCK stops at 0, storage elements in the test logic must retain their data indefinitely. Force TCK high when inactive. MAXQ7666 READ TO DEBUG ENGINE WRITE SHADOW REGISTER MAXQ7666 7 MUX 6 5 43210 SYSTEM PROGRAMMING REGISTER BYPASS MUX 4 3 2 1 0 S1 S0 DEBUG REGISTER DVDDIO DVDDIO MUX PO.2/TDI DVDDIO 2 INSTRUCTION REGISTER 1 0 MUX PO.0/TDO PO.1/TMS DVDDIO TAP CONTROLLER PO.3/TCK POWER-ON RESET UPDATE-DR UPDATE-DR Figure 12. JTAG Interface Block Diagram ______________________________________________________________________________________ 31 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 • TMS—Test Mode Selection. The rising edge of TCK samples the test signal at TMS. The TAP controller decodes the test signal at TMS to control the test operation. Force TMS high when inactive. the data direction. The port input register (PI) is a readonly register that always reflects the logic state of the I/Os. When an I/O is configured as an input, writing to the PO register enables/disables the pullup resistor. Refer to the MAXQ7665/MAXQ7666 User’s Guide for more detailed information. General-Purpose Digital I/Os The MAXQ7666 provides eight general-purpose digital I/Os (GPIOs). All GPIOs have an additional special function (SF), such as a timer input/output, or TAP signal for JTAG communication. For example, the state of P0.6/T0 can be programmed to depend on timer channel 0 logic. When programmed as a port, each I/O is configurable for high-impedance or weak pullup to DVDDIO. At power-up, each GPIO is configured as an input with pullups to DVDDIO. In addition, each GPIO can cause an externally triggered interrupt on falling or rising edges. Any externally triggered interrupt can wake up the device from stop mode. The data input/output direction in a port is independently controlled by the port direction register (PD). Each I/O within the port is individually set as an output or input. The port output register (PO) contains the current state of the logic output buffers. When an I/O is configured as an output, writing to the PO register controls the output logic state. Reading the PO register shows the current state of the output buffers, independent of Port Characteristics The MAXQ7666 contains one GPIO port (P0). It is a bidirectional 8-bit I/O port, which contains the following features: • Schmitt trigger input circuitry with software-selectable high-impedance or weak pullup to DVDDIO • Software-selectable push-pull CMOS output drivers capable of sinking and sourcing 1.6mA • Software-selectable open-drain output drivers capable of sinking 1.6mA • Falling or rising edge interrupt capability • All I/Os contain an additional special function, such as a logic input/output for a timer channel. Selecting an I/O for a special function alters the port characteristics of that I/O (refer to the MAXQ7665/MAXQ7666 User’s Guide for more details). Figure 13 illustrates the functional blocks of an I/O. DVDDIO MAXQ7666 PD0._ MUX PD DVDDIO 400kΩ I/O PAD SF DIRECTION SF ENABLE PO0._ MUX PO P0._ GNDIO SF OUTPUT PI0._ OR SF INPUT FLAG INTERRUPT FLAG DETECT CIRCUIT EIEO._ EIES._ Figure 13. Digital I/O Circuitry 32 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ Core Architecture The MAXQ7666 is structured on a highly advanced, accumulator-based, 16-bit RISC architecture. Fetch and execution operations complete in one cycle without pipelining, because the instruction contains both the operation code and data. The result is a streamlined 8 million instructions-per-second (MIPS) µC. A 16-level hardware stack supports the highly efficient core, enabling fast subroutine calling and task switching. Manipulate data quickly and efficiently with three internal data pointers. Multiple data pointers allow more than one function to access data memory without having to save and restore data pointers each time. The data pointers automatically increment or decrement following an operation, eliminating the need for software intervention. As a result, application speed is greatly increased. • 256B (128 x 16) data flash memory • 512 bytes (256 x 16) of SRAM for storage of temporary variables • 16-level stack memory for storage of program return addresses and general-purpose use The memory is arranged by default in a Harvard architecture, with separate address spaces for program and data memory (see Figure 14). A special mode allows data memory mapping into program space, permitting code execution from data memory. Another mode allows program memory mapping into data space, permitting access to code constants as data memory. The flash memory allows reprogramming the devices, eliminating the expense of throwing away one-time programmable devices during development and field upgrades (see Figure 15 for the flash memory sector maps). Password protect flash memory with a 16-word key to deny access to program memory by unauthorized individuals. A pseudo-Von Neumann memory map places the utility ROM, code, and data memory into a single contiguous memory map. This is useful for applications that require dynamic program modification or unique memory configurations. MAXQ7666 Instruction Set The instruction set is composed of fixed-length, 16-bit instructions that operate on registers and memory locations. The highly orthogonal instruction set allows arithmetic and logical operations to use any register along with the accumulator. Special-function registers (also called peripheral registers) control the peripherals and are subdivided into register modules. The architecture is transport-triggered. Writes or reads from certain register locations potentially cause side effects. These side effects form the basis for the higher level operation codes defined by the assembler, such as ADDC, OR, JUMP, etc. The operation codes are implemented as MOVE instructions between certain register locations, while the assembler handles the encoding. Stack Memory A 16-bit-wide x 16 deep internal hardware stack provides storage for program return addresses and general-purpose use. The stack is used automatically by the processor when the CALL, RET, and RETI instructions are executed and interrupts serviced. The stack also explicitly stores and retrieves data by using the PUSH, POP, and POPI instructions. On reset, the stack pointer, SP, initializes to the top of the stack (0Fh). The CALL, PUSH, and interrupt-vectoring operations increment SP, then store a value at the location pointed to by SP. The RET, RETI, POP, and POPI operations retrieve the value at SP and then decrement SP. Memory Organization The MAXQ7666 incorporates several memory areas: • 8KB (4K x 16) utility ROM • 16KB (8K x 16) program flash memory for program storage ______________________________________________________________________________________ 33 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 PROGRAM SPACE DATA SPACE (BYTE MODE) DATA SPACE (WORD MODE) A0FFh 256 x 16 DATA SRAM A000h 8FFFh 4K x 16 UTILITY ROM 8000h 8K x 8 UTILITY ROM 9FFFh 4K x 16 UTILITY ROM 8000h 8FFFh 8000h 256 x 16 DATA FLASH EXECUTING FROM 16KB (8K x 16) PROGRAM FLASH OR MASKED ROM 40FFh 4000h 1FFFh 512 x 8 DATA SRAM 0000h 0000h 01FFh 256 x 16 DATA SRAM 0000h 00FFh Figure 14. MAXQ7666 Memory Map Utility ROM The utility ROM is an 8KB (4K x 16) block of internal ROM memory that defaults to a starting address of 8000h. The utility ROM consists of subroutines called from application software. These include: • In-system programming (bootstrap loader) over JTAG • In-circuit debug routines • User-callable routines for in-application flash programming and fast table lookup Following any reset, execution begins in the utility ROM. The ROM software determines whether the program execution should immediately jump to location 0000h, the start of user-application code, or to one of the special routines mentioned. Access routines within the utility ROM as subroutines by the application software. More information on the utility ROM contents is contained in the MAXQ7665/MAXQ7666 User’s Guide. Some applications require protection against unauthorized viewing of program code memory. For these applications, access to in-system programming, inapplication programming, or in-circuit debugging functions is prohibited until a password is supplied. The password is defined as the 16 words of physical program memory at addresses 0010h to 001Fh. A single password lock (PWL) bit is implemented in the SC register. When the PWL is set to one (POR default), the password is required to access the utility ROM, including in-circuit debug and in-system programming routines that allow reading or writing of internal memory. When PWL is cleared to zero, these utilities are fully accessible without the password. The password is automatically set to all ones following a mass erase. When the password is all ones or all zeros, the PWL bit clears to zero. 34 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Programming Program the flash memory of the µC using two different methods: in-system programming and in-application programming. Both methods afford great flexibility in system design as well as reduce the life-cycle cost of the embedded system. Password protect these features to prevent unauthorized access to program memory. Program/Data Flash and Data RAM Memory The MAXQ7666 provides the following memory configurations (see Figure 15): • 16KB (8K x 16) of program flash • Up to 512 bytes (256 x 16) of data flash • 512 bytes (256 x 16) of data RAM The program flash is divided into 256 pages. Each page contains 64 bytes (32 x 16-bit words). Program flash is erased four pages (128 x 16 = 256 bytes) at a time, and must be programmed a full page (32 x 16 = 64 bytes) at a time from the application code (see Figure 17). Both erase and programming operations are performed by calling built-in utility ROM functions programFlashErasePage and programFlashWritePage (see Figure 19). When programmed over JTAG, the built-in boot loader supports commands to program flash two pages (128 bytes) at a time. The data flash is divided into 256 pages. Each page contains 2 bytes (1 x 16-bit word). A typical data flash configuration is erased two pages (2 x 16 = 4 bytes) at a time using the utility ROM function dataFlashPageErase, and is written one page/word (1 x 16-bit word = 2 bytes) at a time using the utility ROM function dataFlashWrite. It is also possible to write and read from only even data flash addresses using the utility ROM functions dataFlashWriteEven and dataFlashReadEven. The even functions make it possible to work around the asymmetric "erase two, write one" page behavior by writing to only even addresses. By putting data into alternate locations, the intrinsic two-page erase function is made to look like a single word erase at the cost of halving the available storage. Figure 16 shows the data flash memory organization for one page and two page write/erase operations. Refer to the MAXQ7665/MAXQ7666 User’s Guide for all possible configurations. Note that the data flash is under application control only through the utility ROM functions discussed in this section and is not available when programmed over JTAG. MAXQ7666 In-System Programming An internal bootstrap loader programs the device over a simple JTAG interface. This allows in-system software upgrading, eliminating the need for costly hardware retrofit when updates are required. Remote software uploading of physically inaccessible applications are possible. After a power-up or reset, the JTAG interface is active and loading the TAP with the system programming instruction invokes the bootstrap loader. Setting the SPE bit to 1 during reset through the JTAG interface executes the bootstrap-loader-mode program that resides in the utility ROM. When programming is complete, the bootstrap loader can clear the SPE bit and reset the device, allowing the device to bypass the utility ROM and begin execution of the application software. The following bootstrap loader functions are supported: • • • • Load Dump CRC Verify • Erase In-Application Programming The in-application programming feature allows the µC to modify its own flash program memory while simultaneously executing its application software. This allows on-the-fly software updates in mission-critical applications that cannot afford downtime. Alternatively, it allows the application to develop custom loader software that can operate under the control of the application software. The utility ROM contains user-accessible flash programming functions that erase and program flash memory. These functions are described in detail in the M AXQ7665/MAXQ7666 User’s Guide for this device. Register Set Most functions of the device are controlled by sets of registers. These registers provide a working space for memory operations as well as configuring and addressing peripheral registers on the device. Registers are divided into two major types: system registers and peripheral registers. The common register set, also known as the system registers, includes the ALU, ______________________________________________________________________________________ 35 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 407Fh 128 x 16 DATA FLASH 4000h 1FFFh 8K x 16 PROGRAM FLASH 00FFh 256 x 16 DATA RAM 0000h 0000h Figure 15. Memory Organization 36 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 DATA FLASH: 128 PAGES (1 PAGE = 1 WORD = 16 BITS) DW127 DW126 . . . DW65 DW64 DW63 DW62 . . . DW3 DW2 DW1 DW0 DATA FLASH 2 PAGE ERASE DW127 DW126 . . . DW65 DW64 DW63 DW62 . . . DW3 DW2 DW1 DW0 DATA FLASH 1 PAGE PROGRAM DW127 DW126 . . . DW65 DW64 DW63 DW62 . . . DW3 DW2 DW1 DW0 WRITE[x] DATA FLASH (2 PAGE ERASE/ 1 PAGE WRITE) 407Fh 128 x 16 DATA FLASH 4000h ERASE[m] ERASE[m] DATA FLASH: 64 EVEN PAGES (1 PAGE = 1 WORD = 16 BITS) DW63 DATA FLASH EVEN (1 PAGE ERASE/ 1 PAGE WRITE) 403Fh 128 x 16 DATA FLASH 4000h . . DW31 DW30 . . . DW2 DW1 DW0 DATA FLASH EVEN 1 PAGE ERASE DW63 . . DW31 DW30 . . . DW2 DW1 DW0 ERASE[m] DATA FLASH EVEN 1 PAGE PROGRAM DW63 . . DW31 DW30 . . . DW2 DW1 DW0 WRITE[x] Figure 16. Two of the Possible Data Flash Organizations PROGRAM FLASH: 256 PAGES (1 PAGE = 32 WORDS = 64 BYTES) PAGE 255 PAGE 254 . . . PAGE 131 PAGE 130 PAGE 129 PAGE 128 . . . PAGE 3 PAGE 2 PAGE 1 PAGE 0 PROGRAM FLASH 4 PAGE ERASE PAGE 255 PAGE 254 . . . PAGE 131 PAGE 130 PAGE 129 PAGE 128 . . . PAGE 3 PAGE 2 PAGE 1 PAGE 0 PROGRAM FLASH 1 PAGE PROGRAM PAGE 255 PAGE 254 . . . PAGE 131 PAGE 130 PAGE 129 PAGE 128 . . . PAGE 3 PAGE 2 PAGE 1 PAGE 0 1FFFh 8K x 16 PROGRAM FLASH 0000h ERASE[n] ERASE[n] ERASE[n] ERASE[n] WRITE[y] Figure 17. Program Flash Organization ______________________________________________________________________________________ 37 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 PROGRAM SPACE FFFFh A100h A0FFh 256 x 16 DATA RAM A000h 8FFFh 4K x 16 UTILITY ROM 8000h 407Fh 128 x 16 DATA FLASH 4000h 1FFFh 0100h 00FFh 256 x 16 DATA RAM 0000h 0000h 4K x 16 UTILITY ROM 8000h 7FFFh 9000h 8FFFh DATA SPACE (WORD MODE) FFFFh EXECUTING FROM 8K x 16 PROGRAM FLASH Figure 18. Memory Map (Executing from Program Flash) PROGRAM SPACE FFFFh A100h A0FFh 256 x 16 DATA RAM A000h 8FFFh EXECUTING FROM 4K x 16 UTILITY ROM 8000h 407Fh 128 x 16 DATA FLASH 4000h 1FFFh DATA SPACE (WORD MODE) FFFFh C080h C07Fh 128 x 16 DATA FLASH C000h 9FFFh 8K x 16 PROGRAM FLASH 8000h 7FFFh 8K x 16 PROGRAM FLASH 0100h 00FFh 256 x 16 DATA RAM 0000h 0000h Figure 19. Memory Map (Executing from Utility ROM) 38 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System accumulator registers, data pointers, interrupt vectors and control, and stack pointer. The peripheral registers define additional functionality that may be included by different products based on the MAXQ architecture. This functionality is broken up into discrete modules so that only the features required for a given product need to be included. Tables 2 and 4 show the MAXQ7666 register set. Tables 3 and 5 show the bit functions and reset values. Power Management Power consumption reaches its minimum in stop mode. In this mode, the external oscillator, internal RC oscillator, system clock, and all processing activity is halted. Stop mode is exited when an enabled external interrupt input is triggered or an external reset signal is applied to RESET. Upon exiting stop mode, the µC waits for the external high-frequency crystal to complete its warmup period, or starts execution immediately from its internal RC oscillator while the warmup period completes. MAXQ7666 Table 2. System Register Map REGISTER INDEX 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh MODULE NAME (BASE SPECIFIER) AP (8h) AP APC — — PSF IC IMR — SC — — IIR — — CKCN WDCN A (9h) A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] A[14] A[15] — — — — — — — PFX (Bh) PFX[0] PFX[1] PFX[2] PFX[3] PFX[4] PFX[5] PFX[6] PFX[7] IP (Ch) IP — — — — — — — — — — — — — — — SP (Dh) — SP IV — — — LC0 LC1 — — — — — — — — DPC (Eh) — — — OFFS DPC GR GRL BP GRS GRH GRXL FP — — — — DP (Fh) — — — DP0 — — — DP1 — — — — — — — — Note: Names that appear in italics indicate that all bits of a register are read-only. Names that appear in bold indicate that a register is 16 bits wide. ______________________________________________________________________________________ 39 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 Interrupts Multiple interrupt sources quickly respond to internal and external events. The MAXQ architecture uses a single interrupt vector (IV), single interrupt-service routine (ISR) design. Enable interrupts globally, individually, or by module. When an interrupt condition occurs, its individual flag is set, even if the interrupt source is disabled at the local, module, or global level. Clear interrupt flags within the user-interrupt routine to avoid repeated false interrupts from the same source. Application software must ensure a delay between the write to the flag and the RETI instruction to allow time for the interrupt hardware to remove the internal interrupt condition. Asynchronous interrupt flags require a one-instruction delay and synchronous interrupt flags require a twoinstruction delay. When an enabled interrupt is detected, software jumps to a user-programmable interrupt vector location. The IV register defaults to 0000h on reset or power-up, so if it is not changed to a different address, the user program must determine whether a jump to 0000h came from a reset or interrupt source. Once software control transfers to the ISR, use the interrupt identification register (IIR) to determine if a system register or peripheral register was the source of the interrupt. The specified module can then be interrogated for the specific interrupt source and software can take appropriate action. The following interrupt sources are available. • Watchdog interrupt • External interrupts 0 to 7 • Serial port 0 receive and transmit interrupts • Timer 0 low compare, low overflow, capture/compare, and overflow interrupts • Timer 1 low compare, low overflow, capture/compare, and overflow interrupts • Timer 2 low compare, low overflow, and overflow interrupts • CAN0 receive and transmit interrupts and a change in CAN0 status register interrupt • ADC data ready and overrun interrupts • Digital and I/O voltage brownout interrupts • Crystal oscillator failure interrupt Reset Sources Several reset sources are provided for µC control. Although code execution is halted in the reset state, the crystal oscillator, and the internal RC oscillator continue to oscillate. The crystal oscillator is turned off by a POR, but not by other reset sources. Internal resets such as the power-on and watchdog resets assert the RESET output low. Power-On Reset (POR) An internal POR circuit enhances system reliability. This circuit forces the device to perform a POR whenever a rising voltage on DVDD climbs above the POR threshold level of 2.7V. At this point the following events occur: • All registers and circuits enter the default state • The POR flag (WDCN.POR) is set to indicate if the source of the reset was a loss of power • The internal RC oscillator becomes the clock source • Code execution begins at location 8000h Watchdog Timer Reset The watchdog timer functions are described in the MAXQ7665/MAXQ7666 User’s Guide. Execution resumes at location 8000h following a watchdog timer reset. 40 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System External System Reset Assert the external RESET input low to enter the reset state. The external reset functions are described in the MAXQ7665/MAXQ7666 User’s Guide . Execution resumes at location 8000h after RESET is released. For typical CO and CLOAD values, the effective resistance can be greater than R1 by a factor of 2. MAXQ7666 Development and Technical Support A variety of highly versatile, affordably priced development tools for this µC are available from Maxim and third-party suppliers. These tools include: • Compilers • Evaluation kits • JTAG-to-serial converters for programming and debugging A list of some development-tool vendors can be found at www.maxim-ic.com/microcontrollers. Technical support is available through email at maxq.support@maxim-ic.com. Crystal Selection The MAXQ7666 requires a crystal with the following specifications: Frequency: 8MHz CLOAD: 6pF (min) Drive level: 5µW (min) Series resonance resistance: 300Ω max Note: Series resonance resistance is the resistance observed when the resonator is in the series resonant condition. This is a parameter often stated by quartz crystal vendors and is called R1. When a resonator is used in the parallel resonant mode with an external load capacitance, as is the case with the MAXQ7666 oscillator circuit, the effective resistance is sometimes stated. This effective resistance at the loaded frequency of oscillation is: R1 x ( 1 + (CO/CLOAD))2 ______________________________________________________________________________________ 41 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 Table 3. System Register Bit Functions and Reset Values REGISTER AP APC PSF IC IMR SC IIR CKCN WDCN A[n] (0..15) PFX[n] (0..15) IP SP IV LC[0] LC[1] OFFS DPC GR GRL BP GRS GRH GRXL FP DP[0] DP[1] GR.7 0 0 0 0 GR.7 0 0 0 0 GR.7 0 0 0 0 GR.7 0 0 0 0 GR.7 0 0 0 0 GR.7 0 0 0 0 GR.7 0 0 0 0 — 0 GR.15 0 — 0 GR.14 0 — 0 GR.13 0 — 0 GR.12 0 — 0 GR.11 0 — 0 GR.10 0 — 0 GR.9 0 0 0 1 — 0 0 0 0 0 0 0 — 0 0 0 0 0 0 0 — 0 0 0 0 0 0 0 — 0 0 0 0 0 0 0 — 0 0 0 0 0 0 0 — 0 0 0 0 0 0 0 — 0 0 0 0 15 14 13 12 11 10 9 REGISTER BIT 8 7 6 — — 0 0 CLR IDS 0 0 Z S 1 0 — — 0 0 IMS — 0 0 TAP — 1 0 IIS — 0 0 XT — s* 0 POR EWDI s* s* A[n] (16 Bits) 0 0 0 PFX[n] (16 Bits) 0 0 0 IP (16 Bits) 0 0 0 — — — 0 0 0 IV (16 Bits) 0 0 0 LC[0] (16 Bits) 0 0 0 LC[1] (16 Bits) 0 0 0 0 0 — — 0 0 GR.7 GR.6 0 0 GR.7 GR.6 0 0 BP (16 Bits) 0 0 0 GR.0 GR.15 GR.14 0 0 0 GR.15 GR.14 0 0 GR.7 GR.7 GR.6 0 0 0 FP (16 Bits) 0 0 0 DP[0] (16 Bits) 0 0 0 DP[1] (16 Bits) 0 0 0 5 — 0 — 0 — 0 CGDS 0 IM5 0 CDA1 0 II5 0 RGMD s* WD1 0 0 0 0 — 0 0 0 0 0 — 0 GR.5 0 GR.5 0 0 GR.13 0 GR.13 0 GR.5 0 0 0 0 4 — 0 — 0 GPF1 0 — 0 IM4 0 CDA0 0 II4 0 STOP 0 WD0 0 0 0 0 — 0 0 0 3 0 — 0 GPF0 0 — 0 IM3 0 UPA 0 II3 0 SWB 0 WDIF 0 0 0 0 1 0 0 2 1 AP (4 Bits) 0 0 MOD2 MOD1 0 0 OV C 0 0 — INS 0 0 IM2 IM1 0 0 ROD PWL 0 s* II2 II1 0 0 — — 0 0 WTRF EWT s* s* 0 0 0 0 0 0 MOD0 0 E 0 IGE 0 IM0 0 — 0 II0 0 CD0 1 RWT 0 0 0 0 1 0 0 0 0 SDPS0 0 GR.0 0 GR.0 0 0 GR.8 0 GR.8 0 GR.0 0 0 0 0 0 0 SP (4 Bits) 1 1 0 0 0 0 WBS0 1 GR.2 0 GR.2 0 0 GR.10 0 GR.10 0 GR.2 0 0 0 0 0 0 0 0 SDPS1 0 GR.1 0 GR.1 0 0 GR.9 0 GR.9 0 GR.1 0 0 0 0 — 0 GR.8 0 0 0 OFFS (8 Bits) 0 0 WBS2 WBS1 1 1 GR.4 GR.3 0 0 GR.4 GR.3 0 0 0 GR.12 0 GR.12 0 GR.4 0 0 0 0 0 GR.11 0 GR.11 0 GR.3 0 0 0 0 0 GR.7 0 0 GR.6 0 0 GR.5 0 0 GR.4 0 0 GR.3 0 0 GR.2 0 0 GR.1 0 *Bits indicated by an "s" are only affected by a POR and not by other forms of reset. These bits are set to 0 after a POR. Refer to the MAXQ7665/MAXQ7666 User’s Guide for more information. 42 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 Table 4. Peripheral Register Map REGISTER INDEX 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh MODULE NAME (BASE SPECIFIER) M0 (0h) PO0 — — EIF0 — — — SBUF0 PI0 — — EIE0 — — — — PD0 — — EIES0 — — — — — — — — — SCON0 SMD0 PR0 M1 (1h) MCNT MA MB MC2 MC1 MC0 — — — — FCNTL FDATA MC1R MC0R — — — — — — — — — — — — — — Reserved — — — M2 (2h) T2CNA0 T2H0 T2RH0 T2CH0 T2CNA1 T2H1 T2RH1 T2CH1 T2BNB0 T2V0 T2R0 T2C0 T2CNB1 T2V1 T2R1 T2C1 T2CFG0 T2CFG1 — — — — — — ICDT0 ICDT1 ICDC ICDF ICDB ICDA ICDD — M3 (3h) T2CNA2 T2H2 T2RH2 T2CH2 — — — — T2CNB2 T2V2 T2R2 T2C2 — — — — T2CFG2 — — — — — — — — — — — — — — — M4 (4h) C0C C0S C0IR C0TE C0RE COR C0DP C0DB C0RMS C0TMA — — — — — — — C0M1C C0M2C C0M3C C0M4C C0M5C C0M6C C0M7C C0M8C C0M9C C0M10C C0M11C C0M12C C0M13C C0M14C C0M15C M5 (5h) VMC APE ACNT DCNT DACI — DACO — ADCD TSO AIE ASR OSCC — — — — — — — — — — — — — — — — — — — Note: Names that appear in bold indicate that the register is read-only. ______________________________________________________________________________________ 43 MAXQ7666 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System 44 13 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 PR0.13 0 — 0 MA.13 0 MB.13 0 MC2.13 0 MC1.13 0 MC0.13 0 — 0 FDATA.13 0 MC1R.13 0 MC0R.13 0 FADDR.13 0 — 0 — 0 12 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 PR0.12 0 — 0 MA.12 0 MB.12 0 MC2.12 0 MC1.12 0 MC0.12 0 — 0 FDATA.12 0 MC1R.12 0 MC0R.12 0 FADDR.12 0 — 0 — 0 11 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 PR0.11 0 — 0 MA.11 0 MB.11 0 MC2.11 0 MC1.11 0 MC0.11 0 — 0 FDATA.11 0 MC1R.11 0 MC0R.11 0 FADDR.11 0 — 0 — 0 10 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 PR0.10 0 — 0 MA.10 0 MB.10 0 MC2.10 0 MC1.10 0 MC0.10 0 — 0 FDATA.10 0 MC1R.10 0 MC0R.10 0 FADDR.10 0 — 0 — 0 9 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 PR0.9 0 — 0 MA.9 0 MB.9 0 MC2.9 0 MC1.9 0 MC0.9 0 — 0 FDATA.9 0 MC1R.9 0 MC0R.9 0 FADDR.9 0 — 0 — 0 REGISTER BIT 8 7 — PO0.7 0 1 — IE7 0 0 — SBUF0.7 0 0 — PI0.7 0 ST — EX7 0 0 — PD0.7 0 0 — IT7 0 0 — SM0/FE 0 0 — — 0 0 PR0.8 PR0.7 0 0 — OF 0 0 MA.8 MA.7 0 0 MB.8 MB.7 0 0 MC2.8 MC2.7 0 0 MC1.8 MC1.7 0 0 MC0.8 MC0.7 0 0 — FBUSY 0 1 FDATA.8 FDATA.7 0 0 MC1R.8 MC1R.7 0 0 MC0R.8 MC0R.7 0 0 FADDR.8 FADDR.7 0 0 — ET2 0 0 — T2H0.7 0 0 6 PO0.6 1 IE6 0 SBUF0.6 0 PI0.6 ST EX6 0 PD0.6 0 IT6 0 SM1 0 — 0 PR0.6 0 MCW 0 MA.6 0 MB.6 0 MC2.6 0 MC1.6 0 MC0.6 0 FERR 0 FDATA.6 0 MC1R.6 0 MC0R.6 0 FADDR.6 0 T2OE0 0 T2H0.6 0 5 PO0.5 1 IE5 0 SBUF0.5 0 PI0.5 ST EX5 0 PD0.5 0 IT5 0 SM2 0 — 0 PR0.5 0 CLD 0 MA.5 0 MB.5 0 MC2.5 0 MC1.5 0 MC0.5 0 FINE 0 FDATA.5 0 MC1R.5 0 MC0R.5 0 FADDR.5 0 T2POL0 0 T2H0.5 0 4 PO0.4 1 IE4 0 SBUF0.4 0 PI0.4 ST EX4 0 PD0.4 0 IT4 0 REN 0 — 0 PR0.4 0 SQU 0 MA.4 0 MB.4 0 MC2.4 0 MC1.4 0 MC0.4 0 FBYP 0 FDATA.4 0 MC1R.4 0 MC0R.4 0 FADDR.4 0 TR2L 0 T2H0.4 0 3 PO0.3 1 IE3 0 SBUF0.3 0 PI0.3 ST EX3 0 PD0.3 0 IT3 0 TB8 0 — 0 PR0.3 0 OPCS 0 MA.3 0 MB.3 0 MC2.3 0 MC1.3 0 MC0.3 0 DQ5 0 FDATA.3 0 MC1R.3 0 MC0R.3 0 FADDR.3 0 TR2 0 T2H0.3 0 2 PO0.2 1 IE2 0 SBUF0.2 0 PI0.2 ST EX2 0 PD0.2 0 IT2 0 RB8 0 ESI 0 PR0.2 0 MSUB 0 MA.2 0 MB.2 0 MC2.2 0 MC1.2 0 MC0.2 0 FC2 0 FDATA.2 0 MC1R.2 0 MC0R.2 0 FADDR.2 0 CPRL2 0 T2H0.2 0 1 PO0.1 1 IE1 0 SBUF0.1 0 PI0.1 ST EX1 0 PD0.1 0 IT1 0 TI 0 SMOD 0 PR0.1 0 MMAC 0 MA.1 0 MB.1 0 MC2.1 0 MC1.1 0 MC0.1 0 FC1 0 FDATA.1 0 MC1R.1 0 MC0R.1 0 FADDR.1 0 SS2 0 T2H0.1 0 0 PO0.0 1 IE0 0 SBUF0.0 0 PI0.0 ST EX0 0 PD0.0 0 IT0 0 RI 0 FEDE 0 PR0.0 0 SUS 0 MA.0 0 MB.0 0 MC2.0 0 MC1.0 0 MC0.0 0 — 0 FDATA.0 0 MC1R.0 0 MC0R.0 0 FADDR.0 0 G2EN 0 T2H0.0 0 Table 5. Peripheral Register Bit Functions and Reset Values REGISTER PO0 (M0, 0h) _______________________________________________________________________________________ EIF0 (M0, 3h) SBUF0 (M0, 7h) PI0 (M0, 8h) EIE0 (M0, Bh) PD0 (M0, 10h) EIES0 (M0, 13h) SCON0 (M0, 1Dh) SMD0 (M0, 1Eh) PR0 (M0, 1Fh) MCNT (M1, 0h) MA (M1, 1h) MB (M1, 2h) MC2 (M1, 3h) MC1 (M1, 4h) MC0 (M1, 5h) FCNTL (M1, Ah) FDATA (M1, Bh) MC1R (M1, Ch) MC0R (M1, Dh) FADDR (M1, 1Ch) T2CNA0 (M2, 0h) T2H0 (M2, 1h) 15 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 PR0.15 0 — 0 MA.15 0 MB.15 0 MC2.15 0 MC1.15 0 MC0.15 0 — 0 FDATA.15 0 MC1R.15 0 MC0R.15 0 FADDR.15 0 — 0 — 0 14 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 PR0.14 0 — 0 MA.14 0 MB.14 0 MC2.14 0 MC1.14 0 MC0.14 0 — 0 FDATA.14 0 MC1R.14 0 MC0R.14 0 FADDR.14 0 — 0 — 0 Table 5. Peripheral Register Bit Functions and Reset Values (continued) REGISTER T2RH0 (M2, 2h) MAXQ7666 ______________________________________________________________________________________ T2CH0 (M2, 3h) T2CNA1 (M2, 4h) T2H1 (M2, 5h) T2RH1 (M2, 6h) T2CH1 (M2, 7h) T2CNB0 (M2, 8h) T2V0 (M2, 9h) T2R0 (M2, Ah) T2C0 (M2, Bh) T2CNB1 (M2, Ch) T2V1 (M2, Dh) T2R1 (M2, Eh) T2C1 (M2, Fh) T2CFG0 (M2, 10h) T2CFG1 (M2, 11b) ICDT0 (M2, 18h) ICDT1 (M2, 19h) ICDC (M2, 1Ah) ICDF (M2, 1Bh) ICDB (M2, 1Ch) ICDA M2, 1Dh) ICDD (M2, 1Eh) T2CNA2 (M3, 0h) T2H2 (M3, 1h) T2RH2 (M3, 2h) T2CH2 (M3, 3h) 15 — 0 — 0 — 0 — 0 — 0 — 0 — 0 T2V0.15 0 T2R0.15 0 T2C0.15 0 — 0 T2V1.15 0 T2R1.15 0 T2C1.15 0 — 0 — 0 ICDT0.15 DB ICDT1.15 DB — 0 — 0 — 0 ICDA.15 0 ICDD.15 0 — 0 — 0 — 0 — 0 14 — 0 — 0 — 0 — 0 — 0 — 0 — 0 T2V0.14 0 T2R0.14 0 T2C0.14 0 — 0 T2V1.14 0 T2R1.14 0 T2C1.14 0 — 0 — 0 ICDT0.14 DB ICDT1.14 DB — 0 — 0 — 0 ICDA.14 0 ICDD.14 0 — 0 — 0 — 0 — 0 13 — 0 — 0 — 0 — 0 — 0 — 0 — 0 T2V0.13 0 T2R0.13 0 T2C0.13 0 — 0 T2V1.13 0 T2R1.13 0 T2C1.13 0 — 0 — 0 ICDT0.13 DB ICDT1.13 DB — 0 — 0 — 0 ICDA.13 0 ICDD.13 0 — 0 — 0 — 0 — 0 12 — 0 — 0 — 0 — 0 — 0 — 0 — 0 T2V0.12 0 T2R0.12 0 T2C0.12 0 — 0 T2V1.12 0 T2R1.12 0 T2C1.12 0 — 0 — 0 ICDT0.12 DB ICDT1.12 DB — 0 — 0 — 0 ICDA.12 0 ICDD.12 0 — 0 — 0 — 0 — 0 11 — 0 — 0 — 0 — 0 — 0 — 0 — 0 T2V0.11 0 T2R0.11 0 T2C0.11 0 — 0 T2V1.11 0 T2R1.11 0 T2C1.11 0 — 0 — 0 ICDT0.11 DB ICDT1.11 DB — 0 — 0 — 0 ICDA.11 0 ICDD.11 0 — 0 — 0 — 0 — 0 10 — 0 — 0 — 0 — 0 — 0 — 0 — 0 T2V0.10 0 T2R0.10 0 T2C0.10 0 — 0 T2V1.10 0 T2R1.10 0 T2C1.10 0 — 0 — 0 ICDT0.10 DB ICDT1.10 DB — 0 — 0 — 0 ICDA.10 0 ICDD.10 0 — 0 — 0 — 0 — 0 9 — 0 — 0 — 0 — 0 — 0 — 0 — 0 T2V0.9 0 T2R0.9 0 T2C0.9 0 — 0 T2V1.9 0 T2R1.9 0 T2C1.9 0 — 0 — 0 ICDT0.9 DB ICDT1.9 DB — 0 — 0 — 0 ICDA.9 0 ICDD.9 0 — 0 — 0 — 0 — 0 REGISTERED BIT 8 7 — T2RH0.7 0 0 — T2CH0.7 0 0 — ET2 0 0 — T2H1.7 0 0 — T2RH1.7 0 0 — T2CH1.7 0 0 — ET2L 0 0 T2V0.8 T2V0.7 0 0 T2R0.8 T2R0.7 0 0 T2C0.8 T2C0.7 0 0 — ET2L 0 0 T2V1.8 T2V1.7 0 0 T2R1.8 T2R1.7 0 0 T2C1.8 T2C1.7 0 0 — — 0 0 — — 0 0 ICDT0.8 ICDT0.7 DB DB ICDT1.8 ICDT1.7 DB DB — DME 0 DW — — 0 0 — ICDB.7 0 0 ICDA.8 ICDA.7 0 0 ICDD.8 ICDD.7 0 0 — ET2 0 0 — T2H2.7 0 0 — T2RH2.7 0 0 — T2CH2.7 0 0 6 T2RH0.6 0 T2CH0.6 0 T2OE0 0 T2H1.6 0 T2RH1.6 0 T2CH1.6 0 — 0 T2V0.6 0 T2R0.6 0 T2C0.6 0 — 0 T2V1.6 0 T2R1.6 0 T2C1.6 0 T2DIV2 0 T2DIV2 0 ICDT0.6 DB ICDT1.6 DB — 0 — 0 ICDB.6 0 ICDA.6 0 ICDD.6 0 T2OE0 0 T2H2.6 0 T2RH2.6 0 T2CH2.6 0 5 T2RH0.5 0 T2CH0.5 0 T2POL0 0 T2H1.5 0 T2RH1.5 0 T2CH1.5 0 — 0 T2V0.5 0 T2R0.5 0 T2C0.5 0 — 0 T2V1.5 0 T2R1.5 0 T2C1.5 0 T2DIV1 0 T2DIV1 0 ICDT0.5 DB ICDT1.5 DB REGE DW — 0 ICDB.5 0 ICDA.5 0 ICDD.5 0 T2POL0 0 T2H2.5 0 T2RH2.5 0 T2CH2.5 0 4 T2RH0.4 0 T2CH0.4 0 TR2L 0 T2H1.4 0 T2RH1.4 0 T2CH1.4 0 — 0 T2V0.4 0 T2R0.4 0 T2C0.4 0 — 0 T2V1.4 0 T2R1.4 0 T2C1.4 0 T2DIV0 0 T2DIV0 0 ICDT0.4 DB ICDT1.4 DB — 0 — 0 ICDB.4 0 ICDA.4 0 ICDD.4 0 TR2L 0 T2H2.4 0 T2RH2.4 0 T2CH2.4 0 3 T2RH0.3 0 T2CH0.3 0 TR2 0 T2H1.3 0 T2RH1.3 0 T2CH1.3 0 TF2 0 T2V0.3 0 T2R0.3 0 T2C0.3 0 TF2 0 T2V1.3 0 T2R1.3 0 T2C1.3 0 T2MD 0 T2MD 0 ICDT0.3 DB ICDT1.3 DB CMD3 DW PSS1 0 ICDB.3 0 ICDA.3 0 ICDD.3 0 TR2 0 T2H2.3 0 T2RH2.3 0 T2CH2.3 0 2 T2RH0.2 0 T2CH0.2 0 CPRL2 0 T2H1.2 0 T2RH1.2 0 T2CH1.2 0 TF2L 0 T2V0.2 0 T2R0.2 0 T2C0.2 0 TF2L 0 T2V1.2 0 T2R1.2 0 T2C1.2 0 CCF1 0 CCF1 0 ICDT0.2 DB ICDT1.2 DB CMD2 DW PSS0 0 ICDB.2 0 ICDA.2 0 ICDD.2 0 CPRL2 0 T2H2.2 0 T2RH2.2 0 T2CH2.2 0 1 T2RH0.1 0 T2CH0.1 0 SS2 0 T2H1.1 0 T2RH1.1 0 T2CH1.1 0 TCC2 0 T2V0.1 0 T2R0.1 0 T2C0.1 0 TCC2 0 T2V1.1 0 T2R1.1 0 T2C1.1 0 CCF0 0 CCF0 0 ICDT0.1 DB ICDT1.1 DB CMD1 DW SPE 0 ICDB.1 0 ICDA.1 0 ICDD.1 0 SS2 0 T2H2.1 0 T2RH2.1 0 T2CH2.1 0 0 T2RH0.0 0 T2CH0.0 0 G2EN 0 T2H1.0 0 T2RH1.0 0 T2CH1.0 0 TC2L 0 T2V0.0 0 T2R0.0 0 T2C0.0 0 TC2L 0 T2V1.0 0 T2R1.0 0 T2C1.0 0 C/T2 0 C/T2 0 ICDT0.0 DB ICDT1.0 DB CMD0 DW TXC 0 ICDB.0 0 ICDA.0 0 ICDD.0 0 G2EN 0 T2H2.0 0 T2RH2.0 0 T2CH2.0 0 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System 45 MAXQ7666 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System 46 11 10 — — 0 0 T2V2.11 T2V2.10 0 0 T2R2.11 T2R2.10 0 0 T2C2.11 T2C2.10 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 C0DP.11 C0DP.10 0 0 C0DB.11 C0DB.10 0 0 C0RMS.12 C0RMS.11 0 0 C0TMA.12 C0TMA.11 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 9 — 0 T2V2.9 0 T2R2.9 0 T2C2.9 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 C0DP.9 0 C0DB.9 0 C0RMS.10 0 C0TMA.10 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 REGISTER BIT 8 7 — ET2L 0 0 T2V2.8 T2V2.7 0 0 T2R2.8 T2R2.7 0 0 T2C2.8 T2C2.7 0 0 — — 0 0 — ERIE 0 0 — BSS 0 0 — INTIN7 0 0 — C0TE.7 0 0 — C0RE.7 0 0 — CAN0BA 0 0 C0DP.8 C0DP.7 0 0 C0DB.8 C0DB.7 0 0 C0RMS.9 C0RMS.8 0 0 C0TMA.9 C0TMA.8 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 6 — 0 T2V2.6 0 T2R2.6 0 T2C2.6 0 T2DIV2 0 STIE 0 EC96/128 0 INTIN6 0 C0TE.6 0 C0RE.6 0 INCDEC 0 C0DP.6 0 C0DB.6 0 C0RMS.7 0 C0TMA.7 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 5 — 0 T2V2.5 0 T2R2.5 0 T2C2.5 0 T2DIV1 0 PDE 0 WKS 0 INTIN5 0 C0TE.5 0 C0RE.5 0 AID 0 C0DP.5 0 C0DB.5 0 C0RMS.6 0 C0TMA.6 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 4 — 0 T2V2.4 0 T2R2.4 0 T2C2.4 0 T2DIV0 0 SIESTA 0 RXS 0 INTIN4 0 C0TE.4 0 C0RE.4 0 C0BPR7 0 C0DP.4 0 C0DB.4 0 C0RMS.5 0 C0TMA.5 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 3 TF2 0 T2V2.3 0 T2R2.3 0 T2C2.3 0 T2MD 0 CRST 1 TXS 0 INTIN3 0 C0TE.3 0 C0RE.3 0 C0BPR6 0 C0DP.3 0 C0DB.3 0 C0RMS.4 0 C0TMA.4 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 2 TF2L 0 T2V2.2 0 T2R2.2 0 T2C2.2 0 CCF1 0 AUTOB 0 ER2 0 INTIN2 0 C0TE.2 0 C0RE.2 0 — 0 C0DP.2 0 C0DB.2 0 C0RMS.3 0 C0TMA.3 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 1 TCC2 0 T2V2.1 0 T2R2.1 0 T2C2.1 0 CCF0 0 ERCS 0 ER1 0 INTIN1 0 C0TE.1 0 C0RE.1 0 C0BIE 0 C0DP.1 0 C0DB.1 0 C0RMS.2 0 C0TMA.2 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 0 TC2L 0 T2V2.0 0 T2R2.0 0 T2C2.0 0 C/T2 0 SWINT 1 ER0 0 INTIN0 0 C0TE.0 0 C0RE.0 0 C0IE 0 C0DP.0 0 C0DB.0 0 C0RMS.1 0 C0TMA.1 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 Table 5. Peripheral Register Bit Functions and Reset Values (continued) REGISTER _______________________________________________________________________________________ T2CNB2 (M3, 8h) T2V2 (M3, 9h) T2R2 (M3, Ah) T2C2 (M3, Dh) T2CFG2 (M3, 10h) C0C (M4, 0h) C0S (M4, 1h) C0IR (M4, 2h) C0TE (M4, 3h) C0RE (M4, 4h) C0R (M4, 5h) C0DP (M4, 6h) C0DB (M4, 7h) C0RMS (M4, 8h) C0TMA (M4, 9h) C0M1C (M4, 11h) C0M2C (M4, 12h) C0M3C (M4, 13h) C0M4C (M4, 14h) C0M5C (M4, 15h) C0M6C (M4, 16h) C0M7C (M4, 17h) C0M8C (M4, 18h) C0M9C (M4, 19h) C0M10C (M4, 1Ah) C0M11C (M4, 1Bh) C0M12C (M4, 1Ch) C0M13C (M4, 1Dh) 15 — 0 T2V2.15 0 T2R2.15 0 T2C2.15 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 C0DP.15 0 C0DB.15 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 14 13 12 — — — 0 0 0 T2V2.14 T2V2.13 T2V2.12 0 0 0 T2R2.14 T2R2.13 T2R2.12 0 0 0 T2C2.14 T2C2.13 T2C2.12 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 C0DP.14 C0DP.13 C0DP.12 0 0 0 C0DB.14 C0DB.13 C0DB.12 0 0 0 C0RMS.15 C0RMS.14 C0RMS.13 0 0 0 C0TMA.15 C0TMA.14 C0TMA.13 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 Table 5. Peripheral Register Bit Functions and Reset Values (continued) REGISTER C0M14C (M4, 1Eh) C0M15C (M4, 1Fh) VMC (M5, 0h) APE (M5, 1h) ACNT (M5, 2h) DCNT (M5, 3h) DACI (M5, 4h) DACO (M5, 6h) ADCD (M5, 8h) TSO (M5, 9h) AIE (M5, Ah) ASR (M5, Bh) OSCC (M5, Ch) 15 — 0 — 0 — 0 — 0 ADCMX4 0 — 0 — 0 — 0 — 0 TSO.15 0 — 0 VIOLVL 0 — 0 14 — 0 — 0 — 0 — 0 ADCMX3 0 — 0 — 0 — 0 — 0 TSO.14 0 — 0 DVLVL 0 — 0 13 — 0 — 0 — 0 — 0 ADCMX2 0 — 0 — 0 — 0 — 0 TSO.13 0 — 0 — 0 — 0 12 — 0 — 0 — 0 VIBE 0 ADCMX1 0 — 0 — 0 — 0 — 0 TSO.12 0 — 0 — 0 — 0 11 — 0 — 0 — 0 VDBE 0 ADCMX0 0 — 0 DACI.11 0 DACO.11 0 ADCD.11 0 TSO.11 0 — 0 XHFRY 0 HFOC1 0 10 — 0 — 0 — 0 VDPE 1 ADCDIF 0 — 0 DACI.10 0 DACO.10 0 ADCD.10 0 TSO.10 0 — 0 — 0 HFOC0 0 9 — 0 — 0 — 0 — 0 ADCBIP 0 — 0 DACI.9 0 DACO.9 0 ADCD.9 0 TSO.9 0 — 0 — 0 HFIC1 0 REGISTER BIT 8 7 — MSRDY 0 0 — MSRDY 0 0 — — 0 0 — PGG2 0 0 — — 0 0 — — 0 0 DACI.8 DACI.7 0 0 DACO.8 DACO.7 0 0 ADCD.8 ADCD.7 0 0 TSO.8 TSO.7 0 0 — — 0 0 — — 0 0 HFIC0 ADCCD2 0 0 6 ETI 0 ETI 0 — 0 PGG1 0 ADCDUL 0 DACLD2 0 DACI.6 0 DACO.6 0 ADCD.6 0 TSO.6 0 HFFIE 0 HFFINT 0 ADCCD1 0 5 ERI 0 ERI 0 VIOBI1 0 PGG0 0 — 0 DACLD1 0 DACI.5 0 DACO.5 0 ADCD.5 0 TSO.5 0 VIOBIE 0 VIOBI 0 ADCCD0 0 4 INTRQ 0 INTRQ 0 VIOBI0 0 TSE 0 ADCASD 0 DACLD0 0 DACI.4 0 DACO.4 0 ADCD.4 0 TSO.4 0 DVBIE 0 DVBI 0 — 0 3 EXTRQ 0 EXTRQ 0 VDBI1 0 PGAE 0 ADCBY 0 — 0 DACI.3 0 DACO.3 0 ADCD.3 0 TSO.3 0 — 0 — 0 — 0 2 MTRQ 0 MTRQ 0 VDBI0 0 — 0 ADCS2 0 — 0 DACI.2 0 DACO.2 0 ADCD.2 0 TSO.2 0 AORIE 0 ADCOV 0 EXTHF 0 1 ROW/TIH 0 ROW/TIH 0 VDBR1 S DACE 0 ADCS1 0 — 0 DACI.1 0 DACO.1 0 ADCD.1 0 TSO.1 0 ADCIE 0 ADCRY 0 RCE 1 0 DTUP 0 DTUP 0 VDBR0 S ADCE 0 ADCS0 0 — 0 DACI.0 0 DACO.0 0 ADCD.0 0 TSO.0 0 — 1 — 0 HFE 0 Bits indicated by "—" are unused. Bits indicated by "ST" reflect the input signal state. Bits indicated by "S" are only affected by a POR and not by other forms of reset. These bits are set to 0 after a POR. Bits indicated by "DB" have read/write access only in background or debug mode. These bits are cleared after a POR. Bits indicated by "DW" are only written to in debug mode. These bits are cleared after a POR. MAXQ7666 ______________________________________________________________________________________ The OSCC register is cleared to 0002h after a POR and is not affected by other forms of reset. 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System 47 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System MAXQ7666 Typical Operating Circuit AIN0 AIN2 AIN4 AIN6 AIN8 AIN10 AIN12 AIN14 2N3904 TEMPERATURE SENSOR MUX DUAL-BRIDGE SENSOR VBRIDGEA OUTA+ dr RR+ dr PGA AIN1 AIN3 AIN5 AIN7 AIN9 AIN11 AIN13 AIN15 12-BIT ADC ~2nF ~2nF MUX OUTAR+ dr P0.7/T1 P0.6/T0 P0.5/DACLOAD P0.4/ADCCNV DIGITAL I/O GNDA VBRIDGEB OUTB+ dr RR+ dr dr GNDB R+ VBRIDGEA OUTA+ dr RR+ dr dr GNDA VBRIDGEB OUTB+ dr RR+ dr R+ R+ dr GNDB REFADC REFDAC +12V IN 10µF EN HOLD OUT (+5V) AV DD Rdr Rdr Rdr Rdr ~2nF 12-BIT DAC OUTB~2nF DACOUT ANALOG OUTPUT OR DVDDIO +12V DUAL-BRIDGE SENSOR UTX AGND ~2nF URX OUTA~2nF RXD TXD TXD LIN TRANSCEIVER LIN RXD LIN BUS MAXQ7666 P0.3/TCK P0.2/TDI P0.1/TMS P0.0/TD0 JTAG ~2nF ~2nF VCC +5V OUTB- UART (LIN 2.0) CAN 2.0B MAXQ20 16-BIT RISC MICRO 16KB PROGRAM FLASH 512B DATA FLASH 512 BYTES DATA RAM CANTXD CANRXD TXD RXD STBY MAX13050 CAN TRANSCEIVER CANH CAN BUS CANL GND DVDD +3.3V MAX5024 LDO SET DVDDIO DGND REGEN GNDIO GND RESET EXTERNAL RESET IS OPTIONAL RESET XIN 8MHz XOUT AGND 48 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Smart Data-Acquisition System Pin Configuration P0.4/ADCCNV MAXQ7666 TOP VIEW P0.1/TMS P0.0/TDO P0.3/TCK P0.2/TDI 36 35 34 P0.5/DACLOAD 37 REGEN 38 DVDDIO 39 DVDD 40 RESET 41 XOUT 42 XIN 43 AVDD 44 AIN15 45 AIN14 46 AIN13 47 AIN12 48 33 32 31 30 29 28 27 26 25 24 P0.6/TO 23 URX 22 UTX 21 CANTXD 20 CANRXD 19 DGND MAXQ7666BATM P0.7/T1 18 DGND 17 DACOUT 16 AIN0 15 AIN1 14 AIN2 13 AIN3 AIN4 *EXPOSED PAD + 1 AIN11 2 AIN10 3 AIN9 4 AIN8 5 AGND 6 REFADC 7 REFDAC 8 AGND 9 AIN7 10 11 12 AIN6 AIN5 TQFN 7mm x 7mm *CONNECT EXPOSED PAD TO AGND. DVDDIO GNDIO DGND I.C. I.C. I.C. Chip Information PROCESS: BiCMOS and CMOS PACKAGE TYPE Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE CODE T4877MK-6 DOCUMENT NO. 21-0199 Ordering Information PART MAXQ7666BATM+ TEMP RANGE -40°C to +125°C PIN-PACKAGE 48 TQFN-EP* 48 TQFN-EP +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 49 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.