MX7847BN

19-0158; Rev 0; 7/93 Complete, Dual, 12-Bit Multiplying DACs _______________General Description The MX7837/MX7847 are dual, 12-bit, multiplying, voltage-output digital-to-analog converters (DACs). Each DAC has an output amplifier and a feedback resistor. The output amplifier is capable of developing ±10V across a 2kΩ load. The amplifier feedback resistor is internally connected to VOUT on the MX7847. No external trims are required to achieve full 12-bit performance over the entire operating temperature range. The MX7847 has a 12-bit parallel data input, whereas the MX7837 operates with a double-buffered 8-bit-bus interface that loads data in two write operations. All logic signals are level triggered and are TTL and CMOS compatible. Fast timing specifications make these DACs compatible with most microprocessors. ____________________________Features o Two 12-Bit Multiplying DACs with Buffered Voltage Output o Specified with ±12V or ±15V Supplies o No External Adjustments Required o Fast Timing Specifications o 24-Pin DIP and SO Packages o 12-Bit Parallel Interface (MX7847) 8-Bit + 4-Bit Interface (MX7837) MX7837/MX7847 ______________Ordering Information PART MX7837JN MX7837KN MX7837JR MX7837KR MX7837C/D TEMP. RANGE 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C PIN-PACKAGE 24 Narrow Plastic DIP 24 Narrow Plastic DIP 24 Wide SO 24 Wide SO Dice* ERROR (LSB) ±1 ±1/2 ±1 ±1/2 ±1 ________________________Applications Small Component-Count Analog Systems Digital Offset/Gain Adjustments Industrial Process Control Function Generators Automatic Test Equipment Automatic Calibration Machine and Motion Control Systems Waveform Reconstruction Synchro Applications Ordering Information continued on last page. * Contact factory for availability and processing to MIL-STD-883. _________Typical Operating Circuits VDD _________________Pin Configurations TOP VIEW CS 1 RFBA 2 VREFA 3 VOUTA 4 AGNDA 5 VDD 6 VSS 7 AGNDB 8 VOUTB 9 VREFB 10 DGND 11 RFBB 12 24 DB0/DB8 23 DB1/DB9 22 DB2/DB10 21 DB3/DB11 VREFA VREFB MSB LSB INPUT INPUT LATCH LATCH 4 8 DAC LATCH A 12 DAC A RFBA VOUTA AGNDA DB0 DB7 DAC B 12 DAC LATCH B 8 4 LSB MSB INPUT INPUT LATCH LATCH RFBB VOUTB MX7837 20 DB4 19 DB5 18 DB6 17 DB7 16 A0 15 A1 14 LDAC 13 WR LDAC CS WR A0 A1 AGNDB CONTROL LOGIC MX7837 DIP/SO DGND VSS MX7847 on last page. MX7847 on last page. 1 ________________________________________________________________ Maxim Integrated Products Call toll free 1-800-998-8800 for free samples or literature. Complete, Dual, 12-Bit Multiplying DACs MX7837/MX7847 ABSOLUTE MAXIMUM RATINGS VDD to DGND, AGNDA, AGNDB ............................-0.3V to +17V VSS to DGND, AGNDA, AGNDB (Note 1) ..............+0.3V to -17V VREFA, VREFB to AGNDA, AGNDB .. (VSS - 0.3V) to (VDD + 0.3V) AGNDA, AGNDB to DGND.........................-0.3V to (VDD + 0.3V) VOUTA, VOUTB to AGNDA, AGNDB .....(VSS - 0.3V) to (VDD + 0.3V) RFBA, RFBB to AGNDA, AGNDB .......(VSS - 0.3V) to (VDD + 0.3V) Digital Inputs to DGND ...............................-0.3V to (VDD + 0.3V) Continuous Power Dissipation (TA = +70°C) Narrow Plastic DIP (derate 13.33mW/°C above +70°C)....1067mW SO (derate 11.76mW/°C above +70°C) .........................941mW Narrow CERDIP (derate 12.50mW/°C above +70°C) ..1000mW Operating Temperature Ranges: MX78_7J_/K_ ........................................................0°C to +70°C MX78_7A_/B_ .................................................. -40°C to +85°C MX78_7SQ/TQ ............................................... -55°C to +125°C Storage Temperature Range ............................ -65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Note 1: If VSS is open-circuited with VDD and either AGND applied, the VSS pin will float positive exceeding the Absolute Maximum Ratings. If this possibility exists, a Schottky diode connected between V and GND ensures the maximum ratings will be observed. SS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA = VREFB = +10V, RL = 2kΩ, CL = 100pF, VOUT connected to RFB (MX7837), TA = TMIN to TMAX, unless otherwise noted.) (Note 2) PARAMETER SYMBOL STATIC PERFORMANCE (Note 3) Resolution Relative Accuracy Differential Nonlinearity N INL DNL MX78_7J/A/S MX78_7K/B/T Guaranteed monotonic TA = +25°C Zero-Code Offset Error Loaded with all 0s, MX78_7J/A tempco = ±5µV/°C typ TA = TMIN to TMAX MX78_7K/B MX78_7S/T Loaded with all 1s, tempco = ±2ppm of FSR/°C typ TA = +25°C TA = TMIN to TMAX MX78_7J/A/S MX78_7K/B/T MX78_7J/A/S MX78_7K/B/T 8 10 ±0.5 CONDITIONS MIN 12 ±1 ±1/2 ±1 ±2 ±4 ±3 ±5 ±5 ±2 ±7 ±4 13 ±3 kΩ % LSB mV TYP MAX UNITS Bits LSB LSB Gain Error REFERENCE INPUTS VREF Input Resistance VREFA, VREFB Resistance Matching DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current Input Capacitance (Note 4) ANALOG OUTPUTS DC Output Impedance Short-Circuit Current 2 VOUT connected to AGND 0.2 15 Ω mA VINH VINL Digital inputs at 0V and VDD 2.4 0.8 ±1 8 V µA pF _______________________________________________________________________________________ Complete, Dual, 12-Bit Multiplying DACs ELECTRICAL CHARACTERISTICS (continued) (VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA = VREFB = +10V, RL = 2kΩ, CL = 100pF, VOUT connected to RFB (MX7837), TA = TMIN to TMAX, unless otherwise noted.) (Note 1) PARAMETER POWER REQUIREMENTS VDD Range VSS Range Positive Supply Current Negative Supply Current VDD VSS IDD ISS Output unloaded Output unloaded 11.4 -11.4 5 4 16.5 -16.5 10 6 ±0.01 ±0.01 ±0.01 ±0.01 % per % V V mA mA SYMBOL CONDITIONS MIN TYP MAX UNITS MX7837/MX7847 ∆Gain/∆VDD VDD = 15V ±5%, VREF = -10V Power-Supply Rejection ∆Gain/∆VSS VSS = -15V ±5%, VREF = 10V ∆Gain/∆VDD VDD = 12V ±5%, VREF = -8.9V ∆Gain/∆VSS VSS = -12V ±5%, VREF = 8.9V AC CHARACTERISTICS Voltage-Output Settling Time Slew Rate Digital-to Analog Glitch Impulse Channel-to-Channel Isolation (VREFA to VOUTB, VREFB to VOUTA) Multiplying Feedthrough Error Unity-Gain Small-Signal Bandwidth Full-Power Bandwidth Total Harmonic Distortion Digital Crosstalk Output Noise Voltage at +25°C (0.1Hz to 10Hz) THD tS Settling time to within ±1/2LSB of final DAC value; DAC latch alternately loaded will all 0s and all 1s DAC latch alternately loaded with 01…11 and 10…00 VREF = 20p-p, 10kHz sine wave, Alternate DAC Latch Loaded with all 0s VREF_ = 20Vp-p, 10kHz sine wave, latches loaded with all 0s VREF = 100mVp-p sine wave, DAC latch loaded with all 1s VREF = 20Vp-p Sine wave, DAC latch loaded with all 1s VREF = 6VRMS, 1kHz, DAC latch loaded with all 1s Code transition from all 0s to all 1s; see Typical Operating Characteristics graphs Amplifier noise and Johnson noise of RFB 4 7 Q 60 -95 -90 1 125 -88 10 2 µs V/µs nV-s dB dB MHz kHz dB nV-s µVRMS Note 2: The analog outputs can swing to within 2.5V of the supply rails. Hence, for good linearity towards full-scale, |V REFA| and |VREFB| must be at least 2.5V lower than VDD and |VSS|. Tests done with supply voltages below ±12.5V are done with VREFA = VREFB = ±8.9V. Note 3: Static performance tested at VDD = +15V, VSS = -15V. Performance over supplies guaranteed by PSRR test. Note 4: Guaranteed by design. _______________________________________________________________________________________ 3 Complete, Dual, 12-Bit Multiplying DACs MX7837/MX7847 TIMING CHARACTERISTICS (VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, TA = TMIN to TMAX, unless otherwise noted.) (Note 5) PARAMETER CS to WR Setup Time CS to WR Hold Time WR Pulse Width Data to WR Setup Time Data to WR Hold Time Address to WR SetupTime Address to WR Hold Time LDAC Pulse Width SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 MX7837 only MX7837 only MX7837 only CONDITIONS MX78_7J/K/A/B MIN MAX 0 0 80 80 10 15 15 80 MX78_7S/T MIN MAX 0 0 80 80 10 15 15 80 UNITS ns ns ns ns ns ns ns ns Note 5: All input signals are specified with tR = tF ≤ 5ns. Logic swing is 0V to 5V. __________________________________________Typical Operating Characteristics (TA = +25°C, VDD = 15V, VSS = -15V, RL = 2kΩ, CL = 100pF, unless otherwise noted) OUTPUT VOLTAGE SWING vs. RESISTIVE LOAD 25 NOISE SPECTRAL DENSITY (nV/ Hz) VREF = 20Vp-p at 1kHz 20 VOUT (Vp-p) 300 VREF = 0V DAC CODE = 11...111 GAIN = -1 GAIN (dB) NOISE SPECTRAL DENSITY 5 0 -5 200 -10 -15 -20 0 -25 10 100 1k FREQUENCY (Hz) 10k 100k SMALL-SIGNAL FREQUENCY RESPONSE 15 VREF = 100mVp-p DAC CODE = 11...111 GAIN = -1 10 100 5 0 10 100 1k 10k LOAD RESISTANCE (Ω) 100 1k 10k 100k 1M 10M FREQUENCY (Hz) MULTIPLYING FEEDTHROUGH ERROR -35 -40 -45 ATTENUATION (dB) -50 -55 -60 -65 -70 -75 -80 -85 1k 10k 100k 1M FREQUENCY (Hz) -106 THD (dB) VREFA = 20Vp-p VREFB = AGNDB DAC CODE = 00...00 -94 -96 -98 TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (BANDWIDTH = 80kHz) -60 VREF = 6VRMS DAC CODE = 111...111 -65 -70 THD (dB) -75 -80 -85 -90 -104 -95 -100 100 1k FREQUENCY (Hz) 10k TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (BANDWIDTH > 500kHz) VREF = 6VRMS DAC CODE = 111...111 -100 -102 100 1k 10k 100k FREQUENCY (Hz) 4 _______________________________________________________________________________________ Complete, Dual, 12-Bit Multiplying DACs ____________________________Typical Operating Characteristics (continued) (TA = +25°C, VDD = 15V, VSS = -15V, RL = 2kΩ, CL = 100pF, unless otherwise noted.) SMALL-SIGNAL PULSE RESPONSE LARGE-SIGNAL PULSE RESPONSE MX7837/MX7847 AGNDA A AGNDA A A = VOUTA, 50mV/div TIMEBASE = 2µs/div VREFA = ±100mV SQUARE WAVE A = VOUTA, 5V/div TIMEBASE = 2µs/div VREFA = ±10V SQUARE WAVE ______________________________________________________________Pin Description PIN MX7837 1 – 2 – 3 4 5 6 7 8 9 10 11 12 – 13 14 – 15 16 17-20 21-24 MX7847 – 1 – 2 3 4 5 6 7 8 9 10 11 – 12 13 – 14-24 – – – – NAME CS CSA RFBA CSB VREFA VOUTA AGNDA VDD VSS AGNDB VOUTB VREFB DGND RFBB DB11 WR LDAC DB10-DB0 A1 A0 DB7-DB4 DB3/DB11DB0/DB8 Chip Select – active-low logic input Chip-Select Input for DAC A – active-low logic input Amplifier Feedback Resistor for DAC A Chip-Select Input for DAC B – active-low logic input Reference Input Voltage for DAC A Analog Output Voltage from DAC A Analog Ground for DAC A Positive Power Supply Negative Power Supply Analog Ground for DAC B Analog Output Voltage from DAC B Reference Input Voltage for DAC B Digital Ground Amplifier Feedback Resistor for DAC B Data Bit 11 (MSB) Write Input – active-low logic input (MX7837); positive-edge-triggered input used with CSA and CSB (MX7847) Asynchronous Load – DAC input, active-low Data Bit 10 to Data Bit 0 (LSB) Address Input – most significant address input for input latches Address Input – least significant address input for input latches Data Bit 7 to Data Bit 4 Data Bit 3 to Data Bit 0 (LSB), or Data Bit 11 (MSB) to Data Bit 8 FUNCTION _______________________________________________________________________________________ 5 Complete, Dual, 12-Bit Multiplying DACs MX7837/MX7847 VREF R R R Interface Logic Information (MX7847) Figure 2 shows the MX7847 input control logic. The device contains two independent DACs, each with its own CS input and a common WR input. CSA and WR control data loading to the DAC A latch, and CSB and WR control data loading to the DAC B latch. The latches are edge triggered so that input data is latched to the respective latch on WR's rising edge. The same data will be latched to both DACs if CSA and CSB are low and WR is taken high. Table 1 shows the device control-logic truth table, and Figure 3 shows the writecycle timing diagram. Table 1. MX7847 Truth Table 2R C 2R B 2R A 2R S9 2R S8 2R S0 2R R/2 VOUT SHOWN FOR ALL 1s ON DAC AGND Figure 1. D/A Simplified Circuit Diagram CSA X 1 0 1 0 1 CSB X 1 1 0 0 1 WR 1 X Function No Data Transfer No Data Transfer Data Latched to DAC A Data Latched to DAC B Data Latched to Both DACs _______________Detailed Description D/A Section Figure 1 shows a simplified circuit diagram for one of the DACs and the output amplifier. Using a segmented scheme, the two MSBs of the 12-bit data word are decoded to drive the three switches (A to C). The remaining 10 bits drive the switches (S0 to S9) in a standard R-2R ladder. Each switch (A to C) directs 1/4 of the total reference current, and the remaining current passes through the R-2R section. The output amplifier and feedback resistor convert current to voltage as follows: VOUT_ = (-D)(VREF_), where D is the fractional representation of the digital word. (D can be set from 0 to 4095/4096.) The output amplifier is capable of developing ±10V across a 2kΩ load. It is internally compensated and settles to 0.01% FSR (1/2LSB) in less than 4µs. VOUT on the MX7837 is not internally connected to RFB. 0 0 0 Data Latched to DAC A Data Latched to DAC B Data Latched to Both DACs X = Don't Care = Rising Edge Triggered Interface Logic Information (MX7837) The MX7837 input loading structure is configured for interfacing with 8-bit-wide data-bus microprocessors. Each DAC has two 12-bit latches: an input latch, and a DAC latch. Each input latch is subdivided into a leastsignificant 8-bit latch and a most-significant 4-bit latch. The data held in the DAC latches determines the outputs. Figure 4 shows the MX7837 input control logic, and Figure 5 shows the write-cycle timing diagram. CSA, CSB CSA WR WR CSB DAC B LATCH DATA t4 VALID DATA t5 DAC A LATCH t1 t3 t2 Figure 2. MX7847 Input Control Logic Figure 3. MX7847 Write-Cycle Timing Diagram 6 _______________________________________________________________________________________ Complete, Dual, 12-Bit Multiplying DACs MX7837/MX7847 LDAC CS WR 4 DAC A MS INPUT LATCH DAC A LATCH 12 4 DAC B LATCH 12 CS t1 8 DAC A LS INPUT LATCH 8 WR t4 DATA DAC B MS INPUT LATCH VALID DATA t8 DAC B LS INPUT LATCH LDAC t5 t3 t2 A0/A1 t6 ADDRESS VALID t7 A0 A1 Figure 5. MX7837 Write-Cycle Timing Diagram 8 DB7 DB0 Figure 4. MX7837 Input Control Logic CS, WR, A0, and A1 control data loading to the input latches. The eight data inputs accept right-justified data, which can be loaded to the input latches in any sequence. If LDAC is held high, loading data to the input latches will not change the analog output. A0 and A1 determine which input latch will receive the data when CS and WR are low. Table 2 shows the control logic truth table. Table 2. MX7837 Truth Table and independent of WR. This is useful in many applications, especially in updating multiple MX7837s simultaneously. However, be careful when exercising LDAC during a write cycle; if an LDAC operation overlaps a CS and WR operation, invalid data may be latched to the output. To avoid this, LDAC must remain low after CS or WR have returned high for a period equal to or greater than t8, the minimum LDAC pulse width. Unipolar Binary Operation Figure 6 shows DAC A (MX7837/MX7847) connected for unipolar binary operation. Similar connections apply for DAC B. When VIN is an AC signal, the circuit performs 2-quadrant multiplication. Table 3 shows the code table for this circuit. On the MX7847, the RFB feedback resistor is internally connected to VOUT. Table 3. Unipolar Code Table DAC Latch Contents MSB LSB 1111 1111 1111 Analog Output, VOUT  4095  −VIN ×    4096   2048  1 −VIN ×   = − VIN 2  4096  1 −VIN ×    4096  0V CS WR 1 X 0 0 0 0 1 X 1 0 0 0 0 1 A1 X X 0 0 1 1 X A0 X X 0 1 0 1 X LDAC 1 1 1 1 1 1 0 Function No Data Transfer No Data Transfer DAC A LS Input Latch Transparent DAC A MS Input Latch Transparent DAC B LS Input Latch Transparent DAC B MS Input Latch Transparent Updated Simultaneously from the Respective Input Latches 1000 0000 0000 X = Don't Care The LDAC input controls 12-bit data transfer from the input latches to the DAC latches. When LDAC is taken low, both DAC latches (thus, both analog outputs) are updated simultaneously. When LDAC is low, the DAC latches are transparent; DAC data is latched on the rising edge of LDAC. The LDAC input is asynchronous 0000 0000 0001 0000 0000 0000 V  Note : 1LSB =  IN   4096  _______________________________________________________________________________________ 7 Complete, Dual, 12-Bit Multiplying DACs MX7837/MX7847 Bipolar Operation (4-Quadrant Multiplication) Figure 7 shows the MX7837/MX7847 connected for binary operation. The offset-binary coding is shown in Table 4. When VIN is an AC signal, the circuit performs 4-quadrant multiplication. R1, R2, and R3 resistors should be 0.01% ratio matched to maintain gain-error specifications. On the MX7847, the R FB feedback resistor is internally connected to VOUT. Table 4. Bipolar Code Table DAC Latch Contents MSB LSB 1111 1111 1111 Analog Output, VOUT  2047  +VIN ×    2048  1 +VIN ×    2048  0V 1 −VIN ×    2048   2048  −VIN ×   = − VIN  2048  __________Applications Information Ground Management The use of an uninterrupted ground plane is strongly recommended. AC or transient voltages between analog and digital grounds (between AGNDA/AGNDB and DGND) can inject noise into the analog circuitry. Connect the MX7837/MX7847 AGNDs and DGND directly to the ground plane or to a star ground to ensure that they are at the same potential. In complex systems with separate analog and digital ground planes, connect two diodes (1N914 or equivalent) in inverse parallel between the AGND and DGND pins. Power-Supply Decoupling To minimize noise, decouple the VDD and VSS lines to DGND using a 10µF capacitor in parallel with a 0.1µF ceramic capacitor. Minimize capacitor lead lengths for best noise rejection. 1000 0000 0001 1000 0000 0000 0111 1111 1111 Operation with Reduced Power-Supply Voltages The MX7837/MX7847 are specified for operation with V DD/V SS = ±11.4V to ±16.5V. However, the output amplifier requires 2.5V of headroom, so the reference input should not come within 2.5V of VDD/VSS in order to maintain accuracy at full scale. 0000 0000 0000 V  Note : 1LSB =  IN   2048  VDD VDD RFBA* VDD VDD VOUT VIN VREFA DAC A R1 20k R3 10k RFBA* VOUTA R2 20k VOUT MAX427 VIN VREFA DAC A VOUTA* DGND AGNDA VSS VSS VSS MX7837 MX7847 * INTERNALLY CONNECTED ON MX7847 DGND AGNDA MX7837 MX7847 VSS VSS * INTERNALLY CONNECTED ON MX7847 Figure 6. Unipolar Binary Operation Figure 7. Bipolar Offset Binary Operation 8 _______________________________________________________________________________________ Complete, Dual, 12-Bit Multiplying DACs ______Pin Configurations (continued) TOP VIEW CSA 1 CSB 2 VREFA 3 VOUTA 4 AGNDA 5 VDD 6 VSS 7 AGNDB 8 VOUTB 9 VREFB 10 DGND 11 DB11 12 24 DB0 23 DB1 22 DB2 21 DB3 ____Ordering Information (continued) PART TEMP. RANGE PIN-PACKAGE 24 Narrow Plastic DIP 24 Narrow Plastic DIP 24 Wide SO 24 Wide SO 24 Narrow CERDIP 24 Narrow CERDIP 24 Narrow CERDIP 24 Narrow CERDIP 24 Narrow Plastic DIP 24 Narrow Plastic DIP 24 Wide SO 24 Wide SO Dice* 24 Narrow Plastic DIP 24 Narrow Plastic DIP 24 Wide SO 24 Wide SO 24 Narrow CERDIP 24 Narrow CERDIP 24 Narrow CERDIP 24 Narrow CERDIP ERROR (LSB) ±1 ±1/2 ±1 ±1/2 ±1 ±1/2 ±1 ±1/2 ±1 ±1/2 ±1 ±1/2 ±1 ±1 ±1/2 ±1 ±1/2 ±1 ±1/2 ±1 ±1/2 MX7837/MX7847 MX7837AN -40°C to +85°C MX7837BN MX7837AR MX7837BR MX7837AQ MX7837BQ MX7837SQ MX7837TQ MX7847JN MX7847KN MX7847JR MX7847KR MX7847C/D MX7847AN MX7847BN MX7847AR MX7847BR MX7847AQ MX7847BQ MX7847SQ MX7847TQ -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C -55°C to +125°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C -55°C to +125°C MX7847 20 DB4 19 DB5 18 DB6 17 DB7 16 DB8 15 DB9 14 DB10 13 WR DIP/SO Typical Operating Circuits (continued) VDD DAC LATCH A VREFA VREFB DAC A VOUTA AGNDA DB0 DB11 DAC B WR CSA CSB CONTROL LOGIC VOUTB DAC LATCH B AGNDB MX7847 DGND VSS _______________________________________________________________________________________ 9 Complete, Dual, 12-Bit Multiplying DACs MX7837/MX7847 __________________________________________________________Chip Topographies MX7837 V REFA R FBA CS DB0/DB8 DB1/DB9 DB2/DB10 V REFA CSB MX7847 CSA DB0 DB1 DB2 V OUTA DB3/ DB11 V OUTA DB3 A GNDA DB4 DB5 A GNDA DB4 DB5 V DD V SS V SS 0.250" (6.35mm) V DD V SS V SS 0.250" (6.35mm) A GNDB DB6 DB7 A GNDB DB6 DB7 V OUTB A0 A1 VREFB DGND RFBB WR LDAC VOUTB DB8 DB9 VREFB DGND DB11 WR DB10 0.140" (3.56mm) 0.140" (3.56mm) TRANSISTOR COUNT: 1240; SUBSTRATE CONNECTED TO V DD. TRANSISTOR COUNT: 1240; SUBSTRATE CONNECTED TO V DD. 10 ______________________________________________________________________________________ Complete, Dual, 12-Bit Multiplying DACs ________________________________________________________Package Information DIM INCHES MAX MIN 0.200 – – 0.015 0.150 0.125 0.080 0.055 0.022 0.016 0.065 0.050 0.012 0.008 1.265 1.235 0.080 0.050 0.325 0.300 0.280 0.240 0.100 BSC 0.300 BSC 0.400 – 0.150 0.115 15˚ 0˚ MILLIMETERS MIN MAX – 5.08 0.38 – 3.18 3.81 1.40 2.03 0.41 0.56 1.27 1.65 0.20 0.30 31.37 32.13 1.27 2.03 7.62 8.26 6.10 7.11 2.54 BSC 7.62 BSC – 10.16 2.92 3.81 0˚ 15˚ 21-337A MX7837/MX7847 D1 E E1 A A2 D A3 A A1 A2 A3 B B1 C D D1 E E1 e eA eB L α A1 L e B B1 α C eA eB 24-PIN PLASTIC DUAL-IN-LINE (NARROW) PACKAGE INCHES MAX MIN 0.104 0.093 0.012 0.004 0.019 0.014 0.013 0.009 0.614 0.598 0.299 0.291 0.050 BSC 0.419 0.394 0.030 0.010 0.050 0.016 8˚ 0˚ MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.35 0.49 0.23 0.32 15.20 15.60 7.40 7.60 1.27 BSC 10.00 10.65 0.25 0.75 0.40 1.27 0˚ 8˚ 21-338A DIM A A1 B C D E e H h L α E H D A 0.127mm 0.004in. h x 45˚ α e B A1 C L 24-PIN PLASTIC SMALL-OUTLINE PACKAGE ______________________________________________________________________________________ 11 Complete, Dual, 12-Bit Multiplying DACs MX7837/MX7847 ___________________________________________Package Information (continued) DIM A B B1 C D E E1 e L L1 Q S S1 α INCHES MAX MIN 0.200 – 0.023 0.014 0.065 0.038 0.015 0.008 1.280 – 0.310 0.220 0.320 0.290 0.100 BSC 0.200 0.125 – 0.150 0.060 0.015 0.098 – – 0.005 15˚ 0˚ MILLIMETERS MIN MAX – 5.08 0.36 0.58 0.97 1.65 0.20 0.38 – 32.51 5.59 7.87 7.37 8.13 2.54 BSC 3.18 5.08 3.81 – 0.38 1.52 – 2.49 0.13 – 0˚ 15˚ 21-340B S1 S E1 A D E Q L e B B1 L1 α C 24-PIN CERAMIC DUAL-IN-LINE (NARROW) PACKAGE Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1993 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.