SSC050-01

SSC050-01 Two-Wire Serial Backplane Controller Data Sheet Revision 4.0 November 10, 2004 Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Contents SSC050-01 Data Sheet Contents Revision History Chapter 1 Introduction....................................................................................... 1-1 Feature Summary ..............................................................................................................1-2 Typical Applications ...........................................................................................................1-3 FC-AL Drive Enclosure Configuration .......................................................................1-3 General Purpose I/O Configuration ...........................................................................1-3 Chapter 2 Functional Description..................................................................... 2-1 Two-wire Serial Interface ...................................................................................................2-1 Control Registers ...............................................................................................................2-2 I/O Logic ............................................................................................................................2-3 Clock Generator ................................................................................................................2-3 Power-On Reset ................................................................................................................2-3 Chapter 3 Pin Description ................................................................................. 3-1 Functional Signal Grouping ...............................................................................................3-1 Pinout Diagram ..................................................................................................................3-2 Pin Description List ............................................................................................................3-3 Chapter 4 Control Registers ............................................................................. 4-1 Register Map .....................................................................................................................4-1 Address Map .....................................................................................................................4-4 Control Register Definition ................................................................................................4-6 00h: General Purpose I/O Port 0 Data (GPD0) .........................................................4-6 01h: General Purpose I/O Port 1 Data (GPD1) .........................................................4-7 02h: General Purpose I/O Port 2 Data (GPD2) .........................................................4-7 03h: General Purpose I/O Port 3 Data (GPD3) .........................................................4-8 04h: General Purpose I/O Port 4 Data (GPD4) .........................................................4-8 10h: I/O Port 0 Data Direction (DDP0) ......................................................................4-9 11h: I/O Port 1 Data Direction (DDP1) ......................................................................4-9 12h: I/O Port 2 Data Direction (DDP2) ....................................................................4-10 13h: I/O Port 3 Data Direction (DDP3) ....................................................................4-10 14h: I/O Port 4 Data Direction (DDP4) ....................................................................4-11 20h: Port Bypass Control 0 (PBC0) .......................................................................4-12 21h: Port Bypass Control 1 (PBC1) .......................................................................4-13 22h: Port Bypass Control 2 (PBC2) .......................................................................4-14 23h: Port Bypass Control 3 (PBC3) .......................................................................4-15 24h: Port Bypass Control 4 (PBC4) .......................................................................4-16 25h: Port Bypass Control 5 (PBC5) .......................................................................4-17 -i Revision 4.0 November 10, 2004 Contents SSC050-01 Data Sheet 26h: Port Bypass Control 6 (PBC6) .......................................................................4-18 27h: Port Bypass Control 7 (PBC7) .......................................................................4-19 30h: Fan Speed Control 0 Register (FSC0) ............................................................4-20 31h: Fan Speed Count Overflow 0 (FSCO0, R/W) .................................................4-22 32h: Fan Speed Current Count 0 (FSCC0) ............................................................4-23 34h: Fan Speed Control 1 (FSC1) ..........................................................................4-24 35h: Fan Speed Count Overflow 1 (FSCO1) ..........................................................4-26 36h: Fan Speed Current Count 1 (FSCC1) ............................................................4-27 38h: Fan Speed Control 2 (FSC2) ..........................................................................4-28 39h: Fan Speed Count Overflow 2 (FSCO2) ..........................................................4-30 3Ah: Fan Speed Current Count 2 (FSCC2) ...........................................................4-31 3Ch: Fan Speed Control 3 (FSC3) .........................................................................4-32 3Dh: Fan Speed Count Overflow 3 (FSCO3) .........................................................4-34 3Eh: Fan Speed Current Count 3 (FSCC3) ...........................................................4-35 80h-87h: Bit Control Port 0 Registers (BCP00-BCP07) .........................................4-36 90h-97h: Bit Control Port 1 Registers (BCP10-BCP17) .........................................4-38 98h-9Bh: Pulse Width Modulation Control Registers (PWMC0-PWMC3) .............4-40 A0h-A7h: Bit Control Port 2 Registers (BCP20-BCP27) ........................................4-42 B0h-B7h: Bit Control Port 3 Registers (BCP30-BCP37) ........................................4-44 C0h-C7h: Bit Control Port 4 Registers (BCP40-BCP47) ........................................4-46 F8h: Backplane Controller Interrupt Status (BCIS) ................................................4-48 FCh: Backplane Controller Test (BCT) ...................................................................4-49 FDh: Backplane Controller Option (BCO) ..............................................................4-50 FFh: Backplane Controller Version (VER) ..............................................................4-51 Chapter 5 Electrical Characteristics................................................................. 5-1 Maximum Ratings ..............................................................................................................5-1 DC Characteristics ............................................................................................................5-1 AC Characteristics .............................................................................................................5-5 External Clock Timing ...............................................................................................5-5 Two-wire Serial Interface Operation ..........................................................................5-7 Oscillator Requirements ............................................................................................5-7 External Reset Circuit ...............................................................................................5-9 Optional External Tach Filter ...................................................................................5-10 Chapter 6 Chapter 7 Mechanical Drawing ......................................................................... 6-1 Ordering Information........................................................................ 7-1 -ii Revision 4.0 November 10, 2004 SSC050-01 Data Sheet REVISION HISTORY Revision 1.01 1.0 4.0 Date 11/4/03 11/10/04 11/10/04 Section All Initial Revision Updated Data Manual migrated to Data Sheet status Change Revision 4.0 November 10, 2004 Introduction SSC050-01 Data Sheet Chapter 1 Introduction The SSC050-01 is a I/O-intensive peripheral device which is intended to be a portion of a cost effective FC-AL, SCSI, SAS or SATA enclosure management solution. The device contains an address programmable two wire serial interface, a block of control and status registers, I/O port control logic, specialized port bypass control logic and a clock generation block. Along with an external crystal, the device can be configured to support up to 40 bits of general purpose I/O or 16 bits of general purpose I/ O, 16 bits of port bypass control (8 pairs supporting 8 drives), 4 fan speed monitoring inputs and 4 pulse width modulated outputs. The SSC050-01 is capable of supporting various combinations of individual PBC/CRU/SDU functions as well as integrated solutions. The control register portion of the device allows the user to individually program each I/O pin as an input, output or open source/drain output. Additional control features include selectable flash rates for direct LED drive, input edge detection for interrupt generation, fan speed monitoring and pulse width modulated outputs. The addressing capability of the SSC050-01 includes three pins, which are used for device addressing, as well as one pin, which can be used to select two device type identifiers. Sixteen devices can be used in a single two-wire serial interface system. 1-1 Revision 4.0 November 10, 2004 Introduction Feature Summary SSC050-01 Data Sheet I/O Ports P0.0 - P0.7 P1.0 - P1.7 P2.0 - P2.7 P3.0 - P3.7 P4.0 - P4.7 Power On Reset Clock Generator and Dividers I/O Control and LED Flashing Fan Speed Sensors and PWM Control Port Bypass Control OSCI OSCO SDA SCL A2-A0 ASEL INT# Two-Wire Serial Slave Interface Interrupt Priority and Control Figure 1-1. Chip Block Diagram FEATURE SUMMARY ● ● ● ● ● ● ● ● ● ● Up to 40 bits of user-definable, bidirectional general purpose I/O Integrated Port Bypass, Clock Recovery and Signal Detect support for up to 8 drives Four programmable fan speed monitoring inputs 5 volt tolerant Interrupt output eliminates polling requirements Selectable direct LED drive flashing capability Pin-programmable addressing for up to 16 devices on a single serial bus 5 volt tolerant slave mode two wire serial interface 20% of package pins are power and ground Four programmable pulse width modulation outputs Enhanced fan speed monitor input filters 1-2 Revision 4.0 November 10, 2004 Introduction Typical Applications SSC050-01 Data Sheet TYPICAL APPLICATIONS FC-AL Drive Enclosure Configuration ● Basic port bypass configuration ● ● Support for up to 128 drives Backplane controller supports up to two sets of CRU/SDU functions and 8 drives ● ● Sixteen Backplane controllers can be simultaneously attached to the serial bus Four drive implementation shown - four channel PBC with two CRU/SDU functions ● General purpose I/O lines used for drive control/status and system control/status Local I/O (x26) Cu or Optics X24C16 EEPROM MAXIM Embedded Controller (VSC120) Flash (512K x 16) PBC_EN VSC7147 PBC_EN1 PBC_EN2 PBC_EN3 PBC_EN4 Drive Bay 1 Drive Bay 2 Drive Bay 3 Drive Bay 4 Two-Wire Serial Interface Temperature Sensor (LM75) MAXIM Backplane Controller (SSC050-01) LEDs (x16) PWM out Power Supplies Tach in Fans (x4) Figure 1-2. Single Loop, Single Controller with Four Drives General Purpose I/O Configuration ● ● Controlled by general purpose Microcontroller with two wire serial interface Support for up to 640 I/O lines ● ● Backplane controller supports up to 40 I/O lines Sixteen backplane controllers can be simultaneously attached to the serial bus Four backplane controller implementation shown with shared open drain interrupt 1-3 Revision 4.0 November 10, 2004 Introduction Typical Applications SSC050-01 Data Sheet MicroController with Two Wire Serial I/F Two Wire Serial I/F Interrupt(optional) I/O (x8) I/O (x8) I/O (x8) I/O (x8) I/O (x8) I/O (x8) I/O (x8) I/O (x8) I/O (x8) I/O (x8) I/O (x8) I/O (x8) I/O (x8) I/O (x8) I/O (x8) I/O (x8) I/O (x8) I/O (x8) I/O (x8) I/O (x8) MAXIM Backplane Controller (SSC050-01) MAXIM Backplane Controller (SCC050-01) MAXIM Backplane Controller (SSC050-01) MAXIM Backplane Controller (SCC050-01) Figure 1-3. Four Backplane Controllers, 160 Bidirectional I/O Lines 1-4 Revision 4.0 November 10, 2004 Functional Description Two-wire Serial Interface SSC050-01 Data Sheet Chapter 2 FUNCTIONAL DESCRIPTION The SSC050-01 is composed of five major functional blocks; a slave mode two-wire serial interface, a block of control registers, general purpose I/O and specialized port bypass control logic, a clock generator and power-on reset control logic. The SSC050-01 fully supports a generic two-wire serial interface and is compatible with other industry standard devices which also support this interface at both 100K and 400K bits per second. TWO-WIRE SERIAL INTERFACE The device supports a single slave mode two-wire serial interface. All inter-chip communication to a microcontroller takes place over this bus. The interface supports a three-bit address bus, which allows the user to select one of eight possible addresses. The address bus is compared to bits three through one of the slave address byte, which is the first byte transmitted to the device after a start condition. The SSC050-01 supports two pin selectable four-bit device type identifier values, 1000b and 1100b. The address bits and the device identifier allow the use of up to 16 devices on a single two-wire serial interface. The serial interface control logic includes the slave state machine, address comparison logic, serial to parallel and parallel to serial conversion, register read/write control and filtering for the clock and data line. A read or write transaction is determined by the least significant bit (R/W) of the first byte transferred. Write accesses require a three-byte transfer. The first byte is the slave address with the R/W bit low, the second byte contains the register address and the third byte is the write data. Read accesses require a four-byte transfer since data transfer direction can not change after receipt of the slave address byte. The first byte is the slave address with the R/W bit low, the second byte contains the register address, the third byte is a repeated slave address with the R/W bit high and the fourth byte is the read data. If the transaction is a write, the data will be latched into the appropriate register during the acknowledge of the third byte. All transactions to or from the device complete during the acknowledge of the third byte allowing the user to immediately initiate another transfer to the device. Sequential read or write transactions are allowed and are extensions of the above protocol with additional data bytes added to the end of the transaction. All sequential transactions will cause the internal address to increment by one regardless of the register address. 2-1 Revision 4.0 November 10, 2004 Functional Description Control Registers SSC050-01 Data Sheet CONTROL REGISTERS The SSC050-01 contains five groups of control registers. Each group supports a specific function within the device as follows; the first group is the port data registers, the second is the data direction registers, the third contains special bit control features, the fourth supports the port bypass control function and the fifth supports fan speed monitoring. Currently the device contains 78 registers to support all required functions. In normal I/O operation, each eight-bit group of I/O pins are controlled by a pair of registers, Port Data and Data Direction. The use of these pairs of registers allows each I/O line to be individually configured as an input with internal pull-up, output or open drain output with internal pull-up. The bit control features are enabled through a separate register for each I/O pin. The Bit Control registers allow the user to independently configure each I/O pin to enable one of the special control features as well as control Port Data and Data Direction (which are shadowed copies of the standard control bits found in the Port Data and Data Direction registers). Each I/O pin which has been configured as an input can also be configured to assert the open drain interrupt pin when a rising edge, a falling edge or either edge is detected on the I/O pin. An Interrupt Status register provides the user with a binary indication of which I/O pin is the source of the current interrupt. Each I/O pin which is configured as an output can automatically generate one of seven selectable flashing rates, which are normally driven in an open drain mode. By providing all I/O control capability in a single register, the user can control the operation of the I/O on a pin-by-pin basis. The Port Bypass registers control the operation of a selected group of I/O lines which can be dedicated to support various combinations of individual PBC/CRU/SDU functions as well as integrated solutions. Enabling port bypass control causes the normal or bit control register settings to be overridden and any further changes to the affected registers will have no effect. Each Port Bypass Control register will automatically configure the I/O lines to support a Force Bypass output and a Signal Detected input. The Fan Speed registers control the operation of four programmable inputs which can be used to monitor signals from fans equipped with tachometer outputs. Enabling fan speed control causes the normal or bit control register settings to be overridden and any further changes to the affected registers will have no effect. Each group of three registers provides the capability to enable the function, establish a user defined RPM overflow value which indicates a failure and determine the current RPM value of the fan. The digital filters on the fan speed inputs can optionally be enabled to increase the normal 100 to 200 nanosecond filter to 400 to 500 nanoseconds. The Pulse Width Modulation Control registers enable internal logic to provide duty cycles of 0% to 100% in 3% increments at default frequencies of 26KHz, 52KHz and 104KHz. Optionally, the PWM outputs can be programmed for three additional frequency ranges of 5.2KHz, 10.4KHz and 20.8KHz or 1.04KHz, 2.08KHz and 4.16KHz or 208Hz, 416Hz and 833Hz. These outputs can vary the speed of up to four fans through the use of external drivers and power MOSFETs or pulse width to voltage converters. They can also be used to support other pulse width modulated requirements within the system. 2-2 Revision 4.0 November 10, 2004 Functional Description I/O Logic SSC050-01 Data Sheet I/O LOGIC Each general purpose I/O pin is controlled by a set of registers in the Control Register Block. The I/O supports a high current drive output buffer, which can be configured as a totem pole or open drain driver. The input section of the I/O supports TTL signaling and includes an internal weak pull-up device. This allows unused I/O pins to be left unconnected without high current drain issues. The port bypass control I/O pins which are shared with Port 3 and Port 4 are generated using the same buffer logic as the other ports. When enabled in port bypass control mode, internal logic overrides the existing configuration, with each I/O pin dedicated to the specific port bypass function. All I/O lines default as inputs with the weak internal pull-up enabled. CLOCK GENERATOR Clock generation for the device is composed of an internal oscillator, divider circuits and a distribution network. The primary clock frequency of 10.0MHz is used for filtering incoming serial interface signals and interrupt sources as well as clocking the slave state machine. Divided clocks provide the source for LED flash rate generators. Logic within the SSC050-01 synchronizes the divided clocks between devices attached to the same two-wire serial bus with no more than 200 nanoseconds of skew. Multiple devices can then be used to drive different LED's at the same frequency, providing a synchronized visible indication. The oscillator provides a stable clock source for the device and requires the use of an off chip crystal and related passive components or external clock source. There are no programmable options related to clock generation except the selection of the seven fixed LED Flashing rates. The SSC050-01 can operate at frequencies other than 10.0MHz and continue to meet both the standard mode (100KHz) and fast mode (400KHz) serial interface timings. Frequencies from 8.0MHz to 12.5MHz are allowable as long as they meet the AC timing requirements listed in section 5.3.1 of this manual. Operation of the LED flashing circuits, fan speed counters and pulse width modulated outputs will be affected by a change in base operating frequency. The user must scale the expected operating parameters by the change in frequency from a nominal 10.0MHz. As and example, operating the SSC050-01 at 8.0MHz will cause the LED flashing circuits, fan speed counters and pulse width modulated outputs to operate 25% slower than normal. POWER-ON RESET Power-On Reset is accomplished by the use of logic internal to the device. No external components are required. After power-on, the serial interface state machine will always return an idle state waiting for a start condition to appear on the SCL and SDA pins. A proper power-on reset sequence will clear the serial interface state machine, the clock generators, the control registers, the I/O control logic and the port bypass control logic. The divided clocks used for LED flash rate generation will also be in a known state. An external reset circuit utilizing the TEST1 and ASEL pins can be developed as an option to the internal Power-On Reset logic. Regardless of the effectiveness of either power-on reset sequence, it is highly recommended that the control registers and I/O control logic be cleared through the Soft Reset Register bit. This can be accomplished by writing a 80h to the BCT Register (FCh) followed immediately by a STOP condition. This bit is self resetting and will not require further attention. 2-3 Revision 4.0 November 10, 2004 Pin Description Functional Signal Grouping SSC050-01 Data Sheet Chapter 3 Pin Description The SSC050-01 is packaged in a 64-pin PQFP. All pins have been placed to optimize their connection to external components. Power and ground distribution has also been optimized for core and high current I/ O connections. All serial interface pins as well as the interrupt output are 5 volt tolerant. VDD and VDD2 should be connected to a 3.3 volt supply with no more than 10% tolerances. FUNCTIONAL SIGNAL GROUPING Serial Interface A2-A0 ASEL SCL SDA OSCI OSCO TEST0 TEST1 TEST2 P0.7-P0.0 P1.7-P1.0 P2.7-P2.0 P3.7-P3.0 P4.7-P4.0 I/O Ports Clock Functional Test INT# Interrupt Figure 3-1. Functional Signal Grouping 3-1 Revision 4.0 November 10, 2004 Pin Description Pinout Diagram SSC050-01 Data Sheet PINOUT DIAGRAM VDD VSS2 VSS TEST0 TEST1 TEST2 A0 A1 A2 OSCO OSCI ASEL SCL SDA INT# P4.7 P4.6 VSS VDD 1 64 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 VDD2 60 52 51 50 10 SSC050-01 40 19 20 30 33 32 VDD VSS P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 VDD VSS Revision 4.0 November 10, 2004 VDD2 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 P3.7 P3.6 P3.5 P3.4 P3.3 VSS2 Figure 3-2. Pinout Diagram 3-2 Pin Description Pin Description List SSC050-01 Data Sheet PIN DESCRIPTION LIST The following pin descriptions are grouped by function. Table 3-1: Serial Interface Pin Names A2-A0 Pin No. 9-7 Type Inputs Address Select Bus This pin group provides the value, which will be compared to bits 3 through 1 of the serial slave address. These pins should be strapped to VDD or VSS to provide the appropriate binary value. ASEL 12 Input Device Type Address Select This pin provides the ability to select between two-device type address values in the serial slave address. When tied to VSS, the device type address is 1000b and when tied to VDD, the device type address is 1100b. SCL 13 Input Two-wire Serial Interface Clock This pin is used by the device to latch the data present on the SDA pin. This pin in conjunction with the SDA pin also determines Start and Stop conditions on the serial bus. SDA 14 Bidirectional Two-wire Serial Interface Data This pin is used to transfer all serial data into and out of the device. This pin in conjunction with the SCL pin also determines Start and Stop conditions on the serial bus. Pin Description Table 3-2: Clock Pin Names OSCI Pin No. 11 Type Input Oscillator Input This pin is connected to one side of an external 10.0MHz crystal to produce the clock required for serial signal filtering, state machine clocking and flash rate generation. An alternate external 3.3 volt 10.0MHz clock source can be connected to this pin. OSCO 10 Output Oscillator Output This pin is connected to the other side of an external 10.0MHz crystal. When an alternate external clock source is used, this pin should be left unconnected. Pin Description Table 3-3: Interrupt Pin Names INT# Pin No. 15 Type Open-Drain Output Interrupt This open-drain output can be used to signal the microcontroller that an event has occurred on an I/O pin which is configured as an input or that a special function event has occurred. This pin can be wire ORed with other open drain outputs to provide a single interrupt input source. Pin Description 3-3 Revision 4.0 November 10, 2004 Pin Description Pin Description List SSC050-01 Data Sheet Table 3-4: I/O Ports Pin Names P0.7-P0.0 Pin No. 57-64 Type Bidirectional I/O Port 0 Port 0 is a dedicated eight-bit bidirectional I/O port. The user can select between an input, totem pole output or open-drain output. Additional capability to detect input edge changes and select various output flashing rates is also available. P1.7-P1.0 46-49, 53-56 Bidirectional I/O Port 1 Port 1 is a dedicated eight-bit bidirectional I/O port. The user can select between an input, totem pole output or open-drain output. Additional capability to detect input edge changes and select various output flashing rates is also available. Bidirectional I/O Port 2 Port 2 is an eight-bit bidirectional I/O port. The user can select between an input, totem pole output or open-drain output. Additional capability to detect input edge changes and select various output flashing rates is also available. Through control register setup, P2.7-P2.4 can be dedicated to monitoring fans equipped with tachometer outputs. Through control register setup, P2.3P2.0 can be dedicated to controlling fan speed utilizing pulse width modulated outputs. 27-31, 35-37 Bidirectional I/O Port 3 Port 3 is a shared eight bit bidirectional I/O port which can be used as a general purpose I/O port or as Port Bypass control. The user can select between an input, totem pole output or open-drain output. Additional capability to detect input edge changes and select various output flashing rates is also available. Through control register setup, four two-bit portions of this port can be dedicated to the control of a combination of PBC/ CRU/SDU functions. Any combination of port bypass control functions can be enabled with the remaining I/O pins used for general purpose functions. Bidirectional I/O Port 4 Port 4 is a shared eight bit bidirectional I/O port which can be used as a general purpose I/O port or as Port Bypass control. The user can select between an input, totem pole output or open-drain output. Additional capability to detect input edge changes and select various output flashing rates is also available. Through control register setup, four two-bit portions of this port can be dedicated to the control of a combination of PBC/ CRU/SDU functions. Any combination of port bypass control functions can be enabled with the remaining I/O pins used for general purpose functions. Pin Description P2.7-P2.0 (Tach Inputs and PWM outputs) 38-45 P3.7-P3.0 (Bypass I/O) P4.7-P4.0 (Bypass I/O) 16, 17, 21-26 Table 3-5: Test Pin Names TEST2TEST0 Pin No. 6-4 Type Input Functional Test These inputs allow the device to be placed in specific test modes for device level testing. These inputs should be connected to VSS for normal operation. Pin Description 3-4 Revision 4.0 November 10, 2004 Pin Description Pin Description List SSC050-01 Data Sheet Table 3-6: Supply Pin Names VDD Pin No. 1, 19, 34, 51 VSS 3, 18, 33, 50 VDD2 20, 52 Power Ground Type Power I/O Power These pins are the power sources for the I/O drivers of all nonanalog output and bidirectional pins. I/O Ground These pins are the ground connections for the I/O drivers of all non-analog output and bidirectional pins. Digital Core Power These pins are the power sources for the digital core logic and receivers of all non-analog input and bidirectional pins. VSS2 2, 32 Ground Digital Core Ground These pins are the ground connections for the digital core logic and receivers of all non-analog input and bidirectional pins. Pin Description 3-5 Revision 4.0 November 10, 2004 Control Registers Register Map SSC050-01 Data Sheet Chapter 4 CONTROL REGISTERS This section contains descriptions for the device-specific control registers. All register locations are fixed within the device and are mapped for easy access as well as future enhancements. The control register section is separated into three sub-sections; a register map, an address map and the bit level description of all registers. The register map lists all registers by operating address. The address map shows the relative layout of all control registers. All registers can be accessed at any time and no register function will interfere with the operation of the serial interface. However, changing register bits will have an immediate effect on the respective I/O lines. REGISTER MAP Table 4-1: Register Map Data Memory Address 00h 01h 02h 03h 04h 10h 11h 12h 13h 14h 20h 21h 22h 23h Read/Write Label Description R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W GPD0 GPD1 GPD2 GPD3 GPD4 DDP0 DDP1 DDP2 DDP3 DDP4 PBC0 PBC1 PBC2 PBC3 General Purpose I/O Port 0 Data Register General Purpose I/O Port 1 Data Register General Purpose I/O Port 2 Data Register General Purpose I/O Port 3 Data Register General Purpose I/O Port 4 Data Register I/O Port 0 Data Direction Register I/O Port 1 Data Direction Register I/O Port 2 Data Direction Register I/O Port 3 Data Direction Register I/O Port 4 Data Direction Register Port Bypass Control 0 Register Port Bypass Control 1 Register Port Bypass Control 2 Register Port Bypass Control 3 Register 4-1 Revision 4.0 November 10, 2004 Control Registers Register Map SSC050-01 Data Sheet Table 4-1: Register Map (continued) Data Memory Address 24h 25h 26h 27h 30h 31h 32h 34h 35h 36h 38h 39h 3Ah 3Ch 3Dh 3Eh 80h 81h 82h 83h 84h 85h 86h 87h 90h 91h 92h 93h 94h 95h 96h 97h Read/Write Label Description R/W R/W R/W R/W R/W R/W R R/W R/W R R/W R/W R R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PBC4 PBC5 PBC6 PBC7 FSC0 FSCO0 FSCC0 FSC1 FSCO1 FSCC1 FSC2 FSCO2 FSCC2 FSC3 FSCO3 FSCC3 BCP00 BCP01 BCP02 BCP03 BCP04 BCP05 BCP06 BCP07 BCP10 BCP11 BCP12 BCP13 BCP14 BCP15 BCP16 BCP17 Port Bypass Control 4 Register Port Bypass Control 5 Register Port Bypass Control 6 Register Port Bypass Control 7 Register Fan Speed Control 0 Register Fan Speed Count Overflow 0 Register Fan Speed Current Count 0 Register Fan Speed Control 1 Register Fan Speed Count Overflow 1 Register Fan Speed Current Count 1 Register Fan Speed Control 2 Register Fan Speed Count Overflow 2 Register Fan Speed Current Count 2 Register Fan Speed Control 3 Register Fan Speed Count Overflow 3 Register Fan Speed Current Count 3 Register Bit Control Port 0 - Bit 0 Register Bit Control Port 0 - Bit 1 Register Bit Control Port 0 - Bit 2 Register Bit Control Port 0 - Bit 3 Register Bit Control Port 0 - Bit 4 Register Bit Control Port 0 - Bit 5 Register Bit Control Port 0 - Bit 6 Register Bit Control Port 0 - Bit 7 Register Bit Control Port 1 - Bit 0 Register Bit Control Port 1 - Bit 1 Register Bit Control Port 1 - Bit 2 Register Bit Control Port 1 - Bit 3 Register Bit Control Port 1 - Bit 4 Register Bit Control Port 1 - Bit 5 Register Bit Control Port 1 - Bit 6 Register Bit Control Port 1 - Bit 7 Register 4-2 Revision 4.0 November 10, 2004 Control Registers Register Map SSC050-01 Data Sheet Table 4-1: Register Map (continued) Data Memory Address 98h 99h 9Ah 9Bh A0h A1h A2h A3h A4h A5h A6h A7h B0h B1h B2h B3h B4h B5h B6h B7h C0h C1h C2h C3h C4h C5h C6h C7h F8h FCh FDh FFh Read/Write Label Description R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R PWMC0 PWMC1 PWMC2 PWMC3 BCP20 BCP21 BCP22 BCP23 BCP24 BCP25 BCP26 BCP27 BCP30 BCP31 BCP32 BCP33 BCP34 BCP35 BCP36 BCP37 BCP40 BCP41 BCP42 BCP43 BCP44 BCP45 BCP46 BCP47 BCIS BCT BCO VER Pulse Width Modulation Control 0 Register Pulse Width Modulation Control 1 Register Pulse Width Modulation Control 2 Register Pulse Width Modulation Control 3 Register Bit Control Port 2 - Bit 0 Register Bit Control Port 2 - Bit 1 Register Bit Control Port 2 - Bit 2 Register Bit Control Port 2 - Bit 3 Register Bit Control Port 2 - Bit 4 Register Bit Control Port 2 - Bit 5 Register Bit Control Port 2 - Bit 6 Register Bit Control Port 2 - Bit 7 Register Bit Control Port 3 - Bit 0 Register Bit Control Port 3 - Bit 1 Register Bit Control Port 3 - Bit 2 Register Bit Control Port 3 - Bit 3 Register Bit Control Port 3 - Bit 4 Register Bit Control Port 3 - Bit 5 Register Bit Control Port 3 - Bit 6 Register Bit Control Port 3 - Bit 7 Register Bit Control Port 4 - Bit 0 Register Bit Control Port 4 - Bit 1 Register Bit Control Port 4 - Bit 2 Register Bit Control Port 4 - Bit 3 Register Bit Control Port 4 - Bit 4 Register Bit Control Port 4 - Bit 5 Register Bit Control Port 4 - Bit 6 Register Bit Control Port 4 - Bit 7 Register Backplane Controller Interrupt Status Register Backplane Controller Test Register Backplane Controller Option Register Backplane Controller Version Register 4-3 Revision 4.0 November 10, 2004 Control Registers Address Map SSC050-01 Data Sheet ADDRESS MAP Table 4-2: Address Map 11b GPD3 reserved reserved reserved DDP3 reserved reserved reserved PBC3 PBC7 reserved reserved reserved reserved reserved reserved reserved BCP03 BCP07 reserved reserved BCP13 BCP17 PWMC3 reserved BCP23 BCP27 reserved reserved BCP33 10b GPD2 reserved reserved reserved DDP2 reserved reserved reserved PBC2 PBC6 reserved reserved FSCC0 FSCC1 FSCC2 FSCC3 reserved BCP02 BCP06 reserved reserved BCP12 BCP16 PWMC2 reserved BCP22 BCP26 reserved reserved BCP32 01b GPD1 reserved reserved reserved DDP1 reserved reserved reserved PBC1 PBC5 reserved reserved FSCO0 FSCO1 FSCO2 FSCO3 reserved BCP01 BCP05 reserved reserved BCP11 BCP15 PWMC1 reserved BCP21 BCP25 reserved reserved BCP31 00b GPD0 GPD4 reserved reserved DDP0 DDP4 reserved reserved PBC0 PBC4 reserved reserved FSC0 FSC1 FSC2 FSC3 reserved BCP00 BCP04 reserved reserved BCP10 BCP14 PWMC0 reserved BCP20 BCP24 reserved reserved BCP30 Address 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h-7Ch 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B0h 4-4 Revision 4.0 November 10, 2004 Control Registers Address Map SSC050-01 Data Sheet Table 4-2: Address Map (continued) 11b BCP37 reserved reserved BCP43 BCP47 reserved reserved VER 10b BCP36 reserved reserved BCP42 BCP46 reserved reserved reserved 01b BCP35 reserved reserved BCP41 BCP45 reserved reserved BCO 00b BCP34 reserved reserved BCP40 BCP44 reserved BCIS BCT Address B4h B8h BCh C0h C4h C8h-F4h F8h FCh 4-5 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet CONTROL REGISTER DEFINITION The register definition provides a bit-level description of all register bits including power-on and default values. The terms "set" and "assert" refer to bits which are programmed to a binary one. The terms "reset", "de-assert" and "clear" refer to bits which are programmed to a binary zero. Reserved bits are represented by "RES" and will always return an unknown value and should be masked. Any bits which are reserved should never be set to a binary one. These bits may be defined in future versions of the device. 00h: General Purpose I/O Port 0 Data (GPD0) Register Name: Address: Reset Value: Description GPD0 00h XXXX_XXXXb General Purpose I/O Port 0 Data 7 6 5 4 3 2 1 0 General Purpose Data Bit(s) 7:0 Bit Label GPD0.7-0 Access R/W Description When the I/O pin has been enabled as an output, writing these bits determines the data value which will be present on the corresponding I/O pin. If the I/O pin has been enabled as an input, reading these register bits will represent the current voltage applied to the pin. At no time will the bits directly represent the value latched into the data register. If a pin is enabled as an input and there is no signal applied, weak internal pull-up resistors will hold the pin at a binary one. After a reset or power-on, the register bits will be set to a binary one, but the value returned from a register read will be the level applied to the pin since by default each pin is an input. GPD Read Data FILTER GPD Write Data D CK Q I/O Port DD Write Data D CK Q DD Read Data I/O Port Block Diagram Figure 4-1. I/O Port Block Diagram 4-6 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 01h: General Purpose I/O Port 1 Data (GPD1) Register Name: Address: Reset Value: Description GPD1 01h XXXX_XXXXb General Purpose I/O Port 1 Data 7 6 5 4 3 2 1 0 General Purpose Data Bit(s) 7:0 Bit Label GPD0.7-0 Access R/W Description When the I/O pin has been enabled as an output, writing these bits determines the data value which will be present on the corresponding I/O pin. If the I/O pin has been enabled as an input, reading these register bits will represent the current voltage applied to the pin. At no time will the bits directly represent the value latched into the data register. If a pin is enabled as an input and there is no signal applied, weak internal pull-up resistors will hold the pin at a binary one. After a reset or power-on, the register bits will be set to a binary one, but the value returned from a register read will be the level applied to the pin since by default each pin is an input. 02h: General Purpose I/O Port 2 Data (GPD2) Register Name: Address: Reset Value: Description GPD2 02h XXXX_XXXXb General Purpose I/O Port 2 Data 7 6 5 4 3 2 1 0 General Purpose Data Bit(s) 7:0 Bit Label GPD0.7-0 Access R/W Description When the I/O pin has been enabled as an output, writing these bits determines the data value which will be present on the corresponding I/O pin. If the I/O pin has been enabled as an input, reading these register bits will represent the current voltage applied to the pin. At no time will the bits directly represent the value latched into the data register. If a pin is enabled as an input and there is no signal applied, weak internal pull-up resistors will hold the pin at a binary one. After a reset or power-on, the register bits will be set to a binary one, but the value returned from a register read will be the level applied to the pin since by default each pin is an input. 4-7 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 03h: General Purpose I/O Port 3 Data (GPD3) Register Name: Address: Reset Value: Description GPD3 03h XXXX_XXXXb General Purpose I/O Port 3 Data 7 6 5 4 3 2 1 0 General Purpose Data Bit(s) 7:0 Bit Label GPD0.7-0 Access R/W Description When the I/O pin has been enabled as an output, writing these bits determines the data value which will be present on the corresponding I/O pin. If the I/O pin has been enabled as an input, reading these register bits will represent the current voltage applied to the pin. At no time will the bits directly represent the value latched into the data register. If a pin is enabled as an input and there is no signal applied, weak internal pull-up resistors will hold the pin at a binary one. After a reset or power-on, the register bits will be set to a binary one, but the value returned from a register read will be the level applied to the pin since by default each pin is an input. 04h: General Purpose I/O Port 4 Data (GPD4) Register Name: Address: Reset Value: Description GPD4 04h XXXX_XXXXb General Purpose I/O Port 4 Data 7 6 5 4 3 2 1 0 General Purpose Data Bit(s) 7:0 Bit Label GPD0.7-0 Access R/W Description When the I/O pin has been enabled as an output, writing these bits determines the data value which will be present on the corresponding I/O pin. If the I/O pin has been enabled as an input, reading these register bits will represent the current voltage applied to the pin. At no time will the bits directly represent the value latched into the data register. If a pin is enabled as an input and there is no signal applied, weak internal pull-up resistors will hold the pin at a binary one. After a reset or power-on, the register bits will be set to a binary one, but the value returned from a register read will be the level applied to the pin since by default each pin is an input. 4-8 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 10h: I/O Port 0 Data Direction (DDP0) Register Name: Address: Reset Value: Description DDP0 10h 1111_1111b I/O Port 0 Data Direction 7 6 5 4 Data Direction 3 2 1 0 Bit(s) 7:0 Bit Label DDP0.7-0 Access R/W Description Data Direction These bits determine the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. Additionally, an open-drain or opensource function can be developed by resetting or setting the appropriate data bit and using the data direction bit as the programmed data value. After a reset or power-on, these bits will be set to a binary one, enabling the I/O as an input with weak pull-up. 11h: I/O Port 1 Data Direction (DDP1) Register Name: Address: Reset Value: Description DDP1 11h 1111_1111b I/O Port 1 Data Direction 7 6 5 4 Data Direction 3 2 1 0 Bit(s) 7:0 Bit Label DDP0.7-0 Access R/W Description Data Direction These bits determine the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. Additionally, an open-drain or opensource function can be developed by resetting or setting the appropriate data bit and using the data direction bit as the programmed data value. After a reset or power-on, these bits will be set to a binary one, enabling the I/O as an input with weak pull-up. 4-9 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 12h: I/O Port 2 Data Direction (DDP2) Register Name: Address: Reset Value: Description DDP2 12h 1111_1111b I/O Port 2 Data Direction 7 6 5 4 Data Direction 3 2 1 0 Bit(s) 7:0 Bit Label DDP0.7-0 Access R/W Description Data Direction These bits determine the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. Additionally, an open-drain or opensource function can be developed by resetting or setting the appropriate data bit and using the data direction bit as the programmed data value. After a reset or power-on, these bits will be set to a binary one, enabling the I/O as an input with weak pull-up. 13h: I/O Port 3 Data Direction (DDP3) Register Name: Address: Reset Value: Description DDP3 13h 1111_1111b I/O Port 3 Data Direction 7 6 5 4 Data Direction 3 2 1 0 Bit(s) 7:0 Bit Label DDP0.7-0 Access R/W Description Data Direction These bits determine the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. Additionally, an open-drain or opensource function can be developed by resetting or setting the appropriate data bit and using the data direction bit as the programmed data value. After a reset or power-on, these bits will be set to a binary one, enabling the I/O as an input with weak pull-up. 4-10 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 14h: I/O Port 4 Data Direction (DDP4) Register Name: Address: Reset Value: Description DDP4 14h 1111_1111b I/O Port 4 Data Direction 7 6 5 4 Data Direction 3 2 1 0 Bit(s) 7:0 Bit Label DDP0.7-0 Access R/W Description Data Direction These bits determine the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. Additionally, an open-drain or opensource function can be developed by resetting or setting the appropriate data bit and using the data direction bit as the programmed data value. After a reset or power-on, these bits will be set to a binary one, enabling the I/O as an input with weak pull-up. 4-11 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 20h: Port Bypass Control 0 (PBC0) Register Name: Address: Reset Value: Description PBC0 20h 00XX_XX1Xb Port Bypass Control 0 7 Port Bypass Control Enable 6 Signal Detected Interrupt Enable 5 4 3 2 1 Force Bypass 0 Signal Detected Bit(s) 7 Bit Label PBCEN Access R/W Description Port Bypass Control Enable When this bit is set, P3.1 and P3.0 are automatically configured to provide a Force Bypass output pin and a Signal Detected input pin. Any other configuration which may have previously been enabled through other control registers will be overridden. When this bit is reset, the remaining bits in this register have no effect on the operation of P3.1 and P3.0. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input will be enabled to generate an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin will assert and a binary value equal to the address of this register will appear in the BCIS register. When this bit is reset, transitions on the signal detected input will not generate an interrupt condition. 1 FB R/W Force Bypass This bit controls the P3.1 I/O pin which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in bypass mode. This register bit is automatically cleared when the synchronized and filtered P3.0 input is low which results in a maximum latency of 400 nanoseconds from detection of the loss of a high speed signal to the deassertion of the P3.1 output. NOTE: Since all I/O pins on the device power-on as inputs with weak internal pull-ups, it is possible to define the default state of the force bypass function through the use of an external pull-down resistor. The default state of the I/O can be determined by reading this register since the read value of the register bits are always available through an input synchronizer and filter. Once the default state is determined, a write to the FB bit of this register with the default values as well as setting the PBCEN bit ensures that the port bypass control functions have been enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains high. 0 SD R/W Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P3.0 I/O pin which has been connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, a high speed signal has been detected by the signal detect unit. If this bit is reset, a high speed signal has not been detected by the signal detect unit. 4-12 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 21h: Port Bypass Control 1 (PBC1) Register Name: Address: Reset Value: Description PBC1 21h 00XX_XX1Xb Port Bypass Control 1 7 Port Bypass Control Enable 6 Signal Detected Interrupt Enable 5 4 3 2 1 Force Bypass 0 Signal Detected Bit(s) 7 Bit Label PBCEN Access R/W Description Port Bypass Control Enable When this bit is set, P3.3 and P3.2 are automatically configured to provide a Force Bypass output pin and a Signal Detected input pin. Configurations for these I/O pins which may have previously been enabled through other control registers will be overridden except for the bypass select function (bits 6 and 5 of the appropriate Bit Control Registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P3.3 and P3.2. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input will be enabled to generate an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin will assert and a binary value equal to the address of this register will appear in the BCIS register. When this bit is reset, transitions on the signal detected input will not generate an interrupt condition. 1 FB R/W Force Bypass This bit controls the P3.3 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in bypass mode. This register bit is automatically cleared when the synchronized and filtered P3.2 input is low which results in a maximum latency of 400 nanosceonds from detection of the loss of a high speed signal to the de-assertion of the P3.1 output. NOTE: Since all I/O pins on the device power-on as inputs with weak internal pull-ups, it is possible to define the default state of the force bypass function through the use of an external pull-down resistor. The default state of the I/O can be determined by reading this register since the read value of the register bits are always available through an input synchronizer and filter. Once the default state is determined, a write to the FB bit of this register with the default values as well as setting the PBCEN bit ensures that the port bypass control functions have been enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains high. 0 SD R/W Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P3.2 I/O pin which has been connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, a high speed signal has been detected by the signal detect unit. If this bit is reset, a high speed signal has not been detected by the signal detect unit. 4-13 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 22h: Port Bypass Control 2 (PBC2) Register Name: Address: Reset Value: Description PBC2 22h 00XX_XX1Xb Port Bypass Control 2 7 Port Bypass Control Enable 6 Signal Detected Interrupt Enable 5 4 3 2 1 Force Bypass 0 Signal Detected Bit(s) 7 Bit Label PBCEN Access R/W Description Port Bypass Control Enable When this bit is set, P3.5 and P3.4 are automatically configured to provide a Force Bypass output pin and a Signal Detected input pin. Configurations for these I/O pins which may have previously been enabled through other control registers will be overridden except for the bypass select function (bits 6 and 5 of the appropriate Bit Control Registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P3.5 and P3.4. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input will be enabled to generate an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin will assert and a binary value equal to the address of this register will appear in the BCIS register. When this bit is reset, transitions on the signal detected input will not generate an interrupt condition. 1 FB R/W Force Bypass This bit controls the P3.5 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in bypass mode. This register bit is automatically cleared when the synchronized and filtered P3.4 input is low which results in a maximum latency of 400 nanosceonds from detection of the loss of a high speed signal to the de-assertion of the P3.1 output. NOTE: Since all I/O pins on the device power-on as inputs with weak internal pull-ups, it is possible to define the default state of the force bypass function through the use of an external pull-down resistor. The default state of the I/O can be determined by reading this register since the read value of the register bits are always available through an input synchronizer and filter. Once the default state is determined, a write to the FB bit of this register with the default values as well as setting the PBCEN bit ensures that the port bypass control functions have been enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains high. 0 SD R/W Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P3.4 I/O pin which has been connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, a high speed signal has been detected by the signal detect unit. If this bit is reset, a high speed signal has not been detected by the signal detect unit. 4-14 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 23h: Port Bypass Control 3 (PBC3) Register Name: Address: Reset Value: Description PBC3 23h 00XX_XX1Xb Port Bypass Control 3 7 Port Bypass Control Enable 6 Signal Detected Interrupt Enable 5 4 3 2 1 Force Bypass 0 Signal Detected Bit(s) 7 Bit Label PBCEN Access R/W Description Port Bypass Control Enable When this bit is set, P3.7 and P3.6 are automatically configured to provide a Force Bypass output pin and a Signal Detected input pin. Configurations for these I/O pins which may have previously been enabled through other control registers will be overridden except for the bypass select function (bits 6 and 5 of the appropriate Bit Control Registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P3.7 and P3.6. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input will be enabled to generate an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin will assert and a binary value equal to the address of this register will appear in the BCIS register. When this bit is reset, transitions on the signal detected input will not generate an interrupt condition. 1 FB R/W Force Bypass This bit controls the P3.7 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in bypass mode. This register bit is automatically cleared when the synchronized and filtered P3.6 input is low which results in a maximum latency of 400 nanosceonds from detection of the loss of a high speed signal to the de-assertion of the P3.1 output. NOTE: Since all I/O pins on the device power-on as inputs with weak internal pull-ups, it is possible to define the default state of the force bypass function through the use of an external pull-down resistor. The default state of the I/O can be determined by reading this register since the read value of the register bits are always available through an input synchronizer and filter. Once the default state is determined, a write to the FB bit of this register with the default values as well as setting the PBCEN bit ensures that the port bypass control functions have been enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains high. 0 SD R/W Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P3.4 I/O pin which has been connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, a high speed signal has been detected by the signal detect unit. If this bit is reset, a high speed signal has not been detected by the signal detect unit. 4-15 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 24h: Port Bypass Control 4 (PBC4) Register Name: Address: Reset Value: Description PBC4 24h 00XX_XX1Xb Port Bypass Control 4 7 Port Bypass Control Enable 6 Signal Detected Interrupt Enable 5 4 3 2 1 Force Bypass 0 Signal Detected Bit(s) 7 Bit Label PBCEN Access R/W Description Port Bypass Control Enable When this bit is set, P4.1 and P4.0 are automatically configured to provide a Force Bypass output pin and a Signal Detected input pin. Configurations for these I/O pins which may have previously been enabled through other control registers will be overridden except for the bypass select function (bits 6 and 5 of the appropriate Bit Control Registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P4.1 and P4.0. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input will be enabled to generate an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin will assert and a binary value equal to the address of this register will appear in the BCIS register. When this bit is reset, transitions on the signal detected input will not generate an interrupt condition. 1 FB R/W Force Bypass This bit controls the P4.1 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in bypass mode. This register bit is automatically cleared when the synchronized and filtered P4.0 input is low which results in a maximum latency of 400 nanosceonds from detection of the loss of a high speed signal to the de-assertion of the P3.1 output. NOTE: Since all I/O pins on the device power-on as inputs with weak internal pull-ups, it is possible to define the default state of the force bypass function through the use of an external pull-down resistor. The default state of the I/O can be determined by reading this register since the read value of the register bits are always available through an input synchronizer and filter. Once the default state is determined, a write to the FB bit of this register with the default values as well as setting the PBCEN bit ensures that the port bypass control functions have been enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains high. 0 SD R/W Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P3.4 I/O pin which has been connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, a high speed signal has been detected by the signal detect unit. If this bit is reset, a high speed signal has not been detected by the signal detect unit. 4-16 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 25h: Port Bypass Control 5 (PBC5) Register Name: Address: Reset Value: Description PBC5 25h 00XX_XX1Xb Port Bypass Control 5 7 Port Bypass Control Enable 6 Signal Detected Interrupt Enable 5 4 3 2 1 Force Bypass 0 Signal Detected Bit(s) 7 Bit Label PBCEN Access R/W Description Port Bypass Control Enable When this bit is set, P4.3 and P4.2 are automatically configured to provide a Force Bypass output pin and a Signal Detected input pin. Configurations for these I/O pins which may have previously been enabled through other control registers will be overridden except for the bypass select function (bits 6 and 5 of the appropriate Bit Control Registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P4.3 and P4.2. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input will be enabled to generate an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin will assert and a binary value equal to the address of this register will appear in the BCIS register. When this bit is reset, transitions on the signal detected input will not generate an interrupt condition. 1 FB R/W Force Bypass This bit controls the P4.3 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in bypass mode. This register bit is automatically cleared when the synchronized and filtered P4.2 input is low which results in a maximum latency of 400 nanosceonds from detection of the loss of a high speed signal to the de-assertion of the P3.1 output. NOTE: Since all I/O pins on the device power-on as inputs with weak internal pull-ups, it is possible to define the default state of the force bypass function through the use of an external pull-down resistor. The default state of the I/O can be determined by reading this register since the read value of the register bits are always available through an input synchronizer and filter. Once the default state is determined, a write to the FB bit of this register with the default values as well as setting the PBCEN bit ensures that the port bypass control functions have been enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains high. 0 SD R/W Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P3.4 I/O pin which has been connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, a high speed signal has been detected by the signal detect unit. If this bit is reset, a high speed signal has not been detected by the signal detect unit. 4-17 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 26h: Port Bypass Control 6 (PBC6) Register Name: Address: Reset Value: Description PBC6 26h 00XX_XX1Xb Port Bypass Control 6 7 Port Bypass Control Enable 6 Signal Detected Interrupt Enable 5 4 3 2 1 Force Bypass 0 Signal Detected Bit(s) 7 Bit Label PBCEN Access R/W Description Port Bypass Control Enable When this bit is set, P4.5 and P4.4 are automatically configured to provide a Force Bypass output pin and a Signal Detected input pin. Configurations for these I/O pins which may have previously been enabled through other control registers will be overridden except for the bypass select function (bits 6 and 5 of the appropriate Bit Control Registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P4.5 and P4.4. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input will be enabled to generate an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin will assert and a binary value equal to the address of this register will appear in the BCIS register. When this bit is reset, transitions on the signal detected input will not generate an interrupt condition. 1 FB R/W Force Bypass This bit controls the P4.5 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in bypass mode. This register bit is automatically cleared when the synchronized and filtered P4.4 input is low which results in a maximum latency of 400 nanosceonds from detection of the loss of a high speed signal to the de-assertion of the P3.1 output. NOTE: Since all I/O pins on the device power-on as inputs with weak internal pull-ups, it is possible to define the default state of the force bypass function through the use of an external pull-down resistor. The default state of the I/O can be determined by reading this register since the read value of the register bits are always available through an input synchronizer and filter. Once the default state is determined, a write to the FB bit of this register with the default values as well as setting the PBCEN bit ensures that the port bypass control functions have been enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains high. 0 SD R/W Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P3.4 I/O pin which has been connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, a high speed signal has been detected by the signal detect unit. If this bit is reset, a high speed signal has not been detected by the signal detect unit. 4-18 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 27h: Port Bypass Control 7 (PBC7) Register Name: Address: Reset Value: Description PBC7 27h 00XX_XX1Xb Port Bypass Control 7 7 Port Bypass Control Enable 6 Signal Detected Interrupt Enable 5 4 3 2 1 Force Bypass 0 Signal Detected Bit(s) 7 Bit Label PBCEN Access R/W Description Port Bypass Control Enable When this bit is set, P4.7 and P4.6 are automatically configured to provide a Force Bypass output pin and a Signal Detected input pin. Configurations for these I/O pins which may have previously been enabled through other control registers will be overridden except for the bypass select function (bits 6 and 5 of the appropriate Bit Control Registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P4.7 and P4.6. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input will be enabled to generate an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin will assert and a binary value equal to the address of this register will appear in the BCIS register. When this bit is reset, transitions on the signal detected input will not generate an interrupt condition. 1 FB R/W Force Bypass This bit controls the P4.7 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in bypass mode. This register bit is automatically cleared when the synchronized and filtered P4.6 input is low which results in a maximum latency of 400 nanosceonds from detection of the loss of a high speed signal to the de-assertion of the P3.1 output. NOTE: Since all I/O pins on the device power-on as inputs with weak internal pull-ups, it is possible to define the default state of the force bypass function through the use of an external pull-down resistor. The default state of the I/O can be determined by reading this register since the read value of the register bits are always available through an input synchronizer and filter. Once the default state is determined, a write to the FB bit of this register with the default values as well as setting the PBCEN bit ensures that the port bypass control functions have been enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains high. 0 SD R/W Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P3.4 I/O pin which has been connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, a high speed signal has been detected by the signal detect unit. If this bit is reset, a high speed signal has not been detected by the signal detect unit. 4-19 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 30h: Fan Speed Control 0 Register (FSC0) Register Name: Address: Reset Value: Description FSC0 30h 00XX_XX00b Fan Speed Control 0. This register affects pin P2.4. 7 Fan Speed Control Enable 6 Fan Speed Interrupt Enable 5 4 3 2 1 Fan Divisor 1 0 Fan Divisor 0 Bit(s) 7 Bit Label FSCEN Access R/W Description Fan Speed Control Enable When this bit is set, P2.4 is automatically configured to provide a fan speed monitoring input. Configurations for this I/O pin which may have previously been enabled through other control registers will be overridden except for the bypass select function (bits 6 and 5 of the appropriate Bit Control Registers). If the appropriate bypass bits have been set, the odd numbered fan speed input pins (P2.1, P2.3, P2.5, or P2.7) will be configured as outputs. When this bit is reset, the remaining bits in this register have no effect on the operation of P2.4. When enabled as a fan speed monitoring input, pulses from the fan tachometer output gate an internal 20KHz clock into an eight-bit counter. A divisor value stored in bits one and zero of this register allow the user to select one of four nominal RPM values based on fan tachometer outputs which pulse twice per revolution. The FSCC0 register provides the user with an accurate binary fan speed count value which can be used to determine the current RPM value of the fan. Incoming pulses are filtered and conditioned to accommodate the slow rise and fall times typical of fan tachometer outputs. The maximum input signal is limited to a range of VSS to VDD. If this input is supplied from a fan tachometer output which exceeds this range, external components will be required to limit the signal to an acceptable range. 6 FSIEN R/W Fan Speed Interrupt Enable When this bit is set, the P2.4 input will be enabled to generate an interrupt if the eight bit counter value is greater than or equal to the count overflow value loaded into the FSCO0 register. If the condition occurs, the INT# pin will assert and a binary value equal to the address of this register will appear in the BCIS register. When this bit is reset, the fan speed monitoring logic will not generate an interrupt condition. 1:0 FD1-0 R/W Fan Divisor These two bits determine the divisor value used to determine the correct range of RPM values supplied to the eight-bit fan speed counter. Table 4-3 describes the available divisor values. The decimal count value can be calculated using the following equation: Decimal-Count-Value = (1,200,000)/(RPM X Divisor) Any nominal RPM value can be used in the above equation along with the appropriate divisor as long as the maximum non-failure count value does not exceed the limits of an eight-bit counter. Typical applications may consider 60% to 70% of normal RPM a fan failure which would result in a decimal count value of 250(FAh) and 214(D6h) respectively at the above stated RPM values. 4-20 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet Table 4-3: Fan Divisor FD1 0 0 1 1 FD0 0 1 0 1 Divisor 1 2 4 8 Nominal RPM 8000 4000 2000 1000 Decimal Count Value 150(96h) 150(96h) 150(96h) 150(96h) 4-21 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 31h: Fan Speed Count Overflow 0 (FSCO0, R/W) Register Name: Address: Reset Value: Description FSCO0 31h 0000_0000b Fan Speed Count Overflow 0. This register affects pin P2.4 7 6 5 4 3 2 1 0 Fan Speed Count Overflow Bit(s) 7 Bit Label FSCO7-0 Access R/W Description Fan Speed Count Overflow These eight bits are compared to the eight-bit fan speed counter. If the counter exceeds this value, an interrupt will be generated. This register should be loaded prior to setting the Fan Speed Control Enable (FSCEN) bit in the FSC0 register to avoid generating unintentional interrupts. The overflow count value can be determined using the following equation where FF% is equal to the percentage of nominal RPM which constitutes a fan failure: Decimal-Overflow-Count-Value = (1,200,000)/(RPM X Divisor X FF%) Based on the above equation, a divisor of 8 and a detected fan failure at 70% of nominal RPM, the fan speed monitoring logic is capable of supporting a low end nominal RPM of 850. High end RPM values are basically unlimited but counter resolution will be diminished above 8000 RPM. 4-22 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 32h: Fan Speed Current Count 0 (FSCC0) Register Name: Address: Reset Value: Description FSCC0 32h 0000_0000b Fan Speed Current Count 0. This register affects pin P P2.4. 7 6 5 4 3 2 1 0 Fan Speed Current Count Bit(s) 7 Bit Label FSCO7-0 Access R Description These eight bits, when enabled by setting the FSCEN bit in the FSC0 register provide the user with an accurate binary fan speed count value which can be used to determine the current RPM value of the fan. A minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. The following equation can be used to determine the current RPM value of the fan: RPM = (1,200,000)/(Decimal-Count-Value X Divisor) When the result of a read of this register is 00h, an accurate fan speed count value has not been generated indicating that the fan has not completed a minimum of one revolution. When the result of a read of this register is FFh, the fan is rotating very slowly or there are no tachometer pulses present. When operating in a polled mode with the FSIEN bit reset in the FSC0 register, this register will automatically update with an accurate fan speed count once per revolution of the fan. When operating in an interrupt mode with the FSIEN bit set in the FSC0 register, this register will automatically update with an accurate fan speed count once per revolution of the fan until an interrupt is generated. Once the interrupt is generated, the value will remain stable until the interrupt is cleared. When the interrupt is cleared, this register will also be cleared indicating that a valid RPM value is in the process of being generated. 4-23 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 34h: Fan Speed Control 1 (FSC1) Register Name: Address: Reset Value: Description FSC1 34h 00XX_XX00b Fan Speed Control 1. This register affects pin P2.5 7 Fan Speed Control Enable 6 Fan Speed Interrupt Enable 5 4 3 2 1 Fan Divisor 1 0 Fan Divisor 0 Bit(s) 7 Bit Label FSCEN Access R/W Description Fan Speed Control Enable When this bit is set, P2.5 is automatically configured to provide a fan speed monitoring input. Configurations for this I/O pin which may have previously been enabled through other control registers will be overridden except for the bypass select function (bits 6 and 5 of the appropriate Bit Control Registers). If the appropriate bypass bits have been set, the odd numbered fan speed input pins (P1.1, P1.3, P1.5, P1.7, P2.1, P2.3, P2.5 or P2.7) will be configured as outputs. When this bit is reset, the remaining bits in this register have no effect on the operation of P2.5. When enabled as a fan speed monitoring input, pulses from the fan tachometer output gate an internal 20KHz clock into an eight-bit counter. A divisor value stored in bits one and zero of this register allow the user to select one of four nominal RPM values based on fan tachometer outputs which pulse twice per revolution. The FSCC1 register provides the user with an accurate binary fan speed count value which can be used to determine the current RPM value of the fan. Incoming pulses are filtered and conditioned to accommodate the slow rise and fall times typical of fan tachometer outputs. The maximum input signal is limited to a range of VSS to VDD. If this input is supplied from a fan tachometer output which exceeds this range, external components will be required to limit the signal to an acceptable range. 6 FSIEN R/W Fan Speed Interrupt Enable When this bit is set, the P2.5 input will be enabled to generate an interrupt if the eight bit counter value is greater than or equal to the count overflow value loaded into the FSCO1 register. If the condition occurs, the INT# pin will assert and a binary value equal to the address of this register will appear in the BCIS register. When this bit is reset, the fan speed monitoring logic will not generate an interrupt condition. 1:0 FD1-0 R/W Fan Divisor These two bits determine the divisor value used to determine the correct range of RPM values supplied to the eight-bit fan speed counter. Table 4-4 describes the available divisor values: The decimal count value can be calculated using the following equation: Decimal-Count-Value = (1,200,000)/(RPM X Divisor) Any nominal RPM value can be used in the above equation along with the appropriate divisor as long as the maximum non-failure count value does not exceed the limits of an eight-bit counter. Typical applications may consider 60% to 70% of normal RPM a fan failure which would result in a decimal count value of 250 (FAh) and 214 (D6h) respectively at the above stated RPM values. 4-24 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet Table 4-4: Fan Divisor FD1 0 0 1 1 FD0 0 1 0 1 Divisor 1 2 4 8 Nominal RPM 8000 4000 2000 1000 Decimal Count Value 150(96h) 150(96h) 150(96h) 150(96h) 4-25 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 35h: Fan Speed Count Overflow 1 (FSCO1) Register Name: Address: Reset Value: Description FSCO1 35h 0000_0000b Fan Speed Count Overflow 1. This register affects pin P2.5 7 6 5 4 3 2 1 0 Fan Speed Count Overflow Bit(s) 7 Bit Label FSCO7-0 Access R/W Description Fan Speed Count Overflow These eight bits are compared to the eight-bit fan speed counter. If the counter exceeds this value, an interrupt will be generated. This register should be loaded prior to setting the Fan Speed Control Enable (FSCEN) bit in the FSC1 register to avoid generating unintentional interrupts. The overflow count value can be determined using the following equation where FF% is equal to the percentage of nominal RPM which constitutes a fan failure: Decimal-Overflow-Count-Value = (1,200,000)/(RPM X Divisor X FF%) Based on the above equation, a divisor of 8 and a detected fan failure at 70% of nominal RPM, the fan speed monitoring logic is capable of supporting a low end nominal RPM of 850. High end RPM values are basically unlimited but counter resolution will be diminished above 8000 RPM. 4-26 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 36h: Fan Speed Current Count 1 (FSCC1) Register Name: Address: Reset Value: Description FSCC1 36h 0000_0000b Fan Speed Current Count 1. This register affects pin P2.5. 7 6 5 4 3 2 1 0 Fan Speed Current Count Bit(s) 7 Bit Label FSCO7-0 Access R Description These eight bits, when enabled by setting the FSCEN bit in the FSC1 register provide the user with an accurate binary fan speed count value which can be used to determine the current RPM value of the fan. A minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. The following equation can be used to determine the current RPM value of the fan: RPM = (1,200,000)/(Decimal-Count-Value X Divisor) When the result of a read of this register is 00h, an accurate fan speed count value has not been generated indicating that the fan has not completed a minimum of one revolution. When the result of a read of this register is FFh, the fan is rotating very slowly or there are no tachometer pulses present. When operating in a polled mode with the FSIEN bit reset in the FSC1 register, this register will automatically update with an accurate fan speed count once per revolution of the fan. When operating in an interrupt mode with the FSIEN bit set in the FSC1 register, this register will automatically update with an accurate fan speed count once per revolution of the fan until an interrupt is generated. Once the interrupt is generated, the value will remain stable until the interrupt is cleared. When the interrupt is cleared, this register will also be cleared indicating that a valid RPM value is in the process of being generated. 4-27 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 38h: Fan Speed Control 2 (FSC2) Register Name: Address: Reset Value: Description FSC2 38h 00XX_XX00b Fan Speed Control 2. This register affects pin P2.6 7 Fan Speed Control Enable 6 Fan Speed Interrupt Enable 5 4 3 2 1 Fan Divisor 1 0 Fan Divisor 0 Bit(s) 7 Bit Label FSCEN Access R/W Description Fan Speed Control Enable When this bit is set, P2.6 is automatically configured to provide a fan speed monitoring input. Configurations for this I/O pin which may have previously been enabled through other control registers will be overridden except for the bypass select function (bits 6 and 5 of the appropriate Bit Control Registers). If the appropriate bypass bits have been set, the odd numbered fan speed input pins (P1.1, P1.3, P1.5, P1.7, P2.1, P2.3, P2.5 or P2.7) will be configured as outputs. When this bit is reset, the remaining bits in this register have no effect on the operation of P2.6. When enabled as a fan speed monitoring input, pulses from the fan tachometer output gate an internal 20KHz clock into an eight-bit counter. A divisor value stored in bits one and zero of this register allow the user to select one of four nominal RPM values based on fan tachometer outputs which pulse twice per revolution. The FSCC2 register provides the user with an accurate binary fan speed count value which can be used to determine the current RPM value of the fan. Incoming pulses are filtered and conditioned to accommodate the slow rise and fall times typical of fan tachometer outputs. The maximum input signal is limited to a range of VSS to VDD. If this input is supplied from a fan tachometer output which exceeds this range, external components will be required to limit the signal to an acceptable range. 6 FSIEN R/W Fan Speed Interrupt Enable When this bit is set, the P2.6 input will be enabled to generate an interrupt if the eight bit counter value is greater than or equal to the count overflow value loaded into the FSCO0 register. If the condition occurs, the INT# pin will assert and a binary value equal to the address of this register will appear in the BCIS register. When this bit is reset, the fan speed monitoring logic will not generate an interrupt condition. 1:0 FD1-0 R/W Fan Divisor These two bits determine the divisor value used to determine the correct range of RPM values supplied to the eight-bit fan speed counter. Table 4-5 describes the available divisor values: The decimal count value can be calculated using the following equation: Decimal-Count-Value = (1,200,000)/(RPM X Divisor) Any nominal RPM value can be used in the above equation along with the appropriate divisor as long as the maximum non-failure count value does not exceed the limits of an eight-bit counter. Typical applications may consider 60% to 70% of normal RPM a fan failure which would result in a decimal count value of 250 (FAh) and 214 (D6h) respectively at the above stated RPM values. 4-28 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet Table 4-5: Fan Divisor FD1 0 0 1 1 FD0 0 1 0 1 Divisor 1 2 4 8 Nominal RPM 8000 4000 2000 1000 Decimal Count Value 150(96h) 150(96h) 150(96h) 150(96h) 4-29 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 39h: Fan Speed Count Overflow 2 (FSCO2) Register Name: Address: Reset Value: Description FSCO2 39h 0000_0000b Fan Speed Count Overflow 2. This register affects pin P2.6. 7 6 5 4 3 2 1 0 Fan Speed Count Overflow Bit(s) 7 Bit Label FSCO7-0 Access R/W Description Fan Speed Count Overflow These eight bits are compared to the eight-bit fan speed counter. If the counter exceeds this value, an interrupt will be generated. This register should be loaded prior to setting the Fan Speed Control Enable (FSCEN) bit in the FSC2 register to avoid generating unintentional interrupts. The overflow count value can be determined using the following equation where FF% is equal to the percentage of nominal RPM which constitutes a fan failure: Decimal-Overflow-Count-Value = (1,200,000)/(RPM X Divisor X FF%) Based on the above equation, a divisor of 8 and a detected fan failure at 70% of nominal RPM, the fan speed monitoring logic is capable of supporting a low end nominal RPM of 850. High end RPM values are basically unlimited but counter resolution will be diminished above 8000 RPM. 4-30 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 3Ah: Fan Speed Current Count 2 (FSCC2) Register Name: Address: Reset Value: Description FSCC2 3Ah 0000_0000b Fan Speed Current Count 2. This register affects pin P2.6. 7 6 5 4 3 2 1 0 Fan Speed Current Count Bit(s) 7 Bit Label FSCO7-0 Access R/W Description These eight bits, when enabled by setting the FSCEN bit in the FSC2 register provide the user with an accurate binary fan speed count value which can be used to determine the current RPM value of the fan. A minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. The following equation can be used to determine the current RPM value of the fan: RPM = (1,200,000)/(Decimal-Count-Value X Divisor) When the result of a read of this register is 00h, an accurate fan speed count value has not been generated indicating that the fan has not completed a minimum of one revolution. When the result of a read of this register is FFh, the fan is rotating very slowly or there are no tachometer pulses present. When operating in a polled mode with the FSIEN bit reset in the FSC2 register, this register will automatically update with an accurate fan speed count once per revolution of the fan. When operating in an interrupt mode with the FSIEN bit set in the FSC2 register, this register will automatically update with an accurate fan speed count once per revolution of the fan until an interrupt is generated. Once the interrupt is generated, the value will remain stable until the interrupt is cleared. When the interrupt is cleared, this register will also be cleared indicating that a valid RPM value is in the process of being generated. 4-31 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 3Ch: Fan Speed Control 3 (FSC3) Register Name: Address: Reset Value: Description FSC3 3Ch 00XX_XX00b Fan Speed Control 3. This register affects pin P2.7. 7 Fan Speed Control Enable 6 Fan Speed Interrupt Enable 5 4 3 2 1 Fan Divisor 1 0 Fan Divisor 0 Bit(s) 7 Bit Label FSCEN Access R/W Description Fan Speed Control Enable When this bit is set, P2.7 is automatically configured to provide a fan speed monitoring input. Configurations for this I/O pin which may have previously been enabled through other control registers will be overridden except for the bypass select function (bits 6 and 5 of the appropriate Bit Control Registers). If the appropriate bypass bits have been set, the odd numbered fan speed input pins (P1.1, P1.3, P1.5, P1.7, P2.1, P2.3, P2.5 or P2.7) will be configured as outputs. When this bit is reset, the remaining bits in this register have no effect on the operation of P2.7. When enabled as a fan speed monitoring input, pulses from the fan tachometer output gate an internal 20KHz clock into an eight-bit counter. A divisor value stored in bits one and zero of this register allow the user to select one of four nominal RPM values based on fan tachometer outputs which pulse twice per revolution. The FSCC3 register provides the user with an accurate binary fan speed count value which can be used to determine the current RPM value of the fan. Incoming pulses are filtered and conditioned to accommodate the slow rise and fall times typical of fan tachometer outputs. The maximum input signal is limited to a range of VSS to VDD. If this input is supplied from a fan tachometer output which exceeds this range, external components will be required to limit the signal to an acceptable range. 6 FSIEN R/W Fan Speed Interrupt Enable When this bit is set, the P2.7 input will be enabled to generate an interrupt if the eight bit counter value is greater than or equal to the count overflow value loaded into the FSCO0 register. If the condition occurs, the INT# pin will assert and a binary value equal to the address of this register will appear in the BCIS register. When this bit is reset, the fan speed monitoring logic will not generate an interrupt condition. 1:0 FD1-0 R/W Fan Divisor These two bits determine the divisor value used to determine the correct range of RPM values supplied to the eight-bit fan speed counter. Table 4-6 describes the available divisor values: The decimal count value can be calculated using the following equation: Decimal-Count-Value = (1,200,000)/(RPM X Divisor) Any nominal RPM value can be used in the above equation along with the appropriate divisor as long as the maximum non-failure count value does not exceed the limits of an eight-bit counter. Typical applications may consider 60% to 70% of normal RPM a fan failure which would result in a decimal count value of 250 (FAh) and 214 (D6h) respectively at the above stated RPM values. 4-32 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet Table 4-6: Fan Divisor FD1 0 0 1 1 FD0 0 1 0 1 Divisor 1 2 4 8 Nominal RPM 8000 4000 2000 1000 Decimal Count Value 150(96h) 150(96h) 150(96h) 150(96h) 4-33 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 3Dh: Fan Speed Count Overflow 3 (FSCO3) Register Name: Address: Reset Value: Description FSCO3 3Dh 0000_0000b Fan Speed Count Overflow 3. This register affects pin P2.7. 7 6 5 4 3 2 1 0 Fan Speed Count Overflow Bit(s) 7 Bit Label FSCO7-0 Access R/W Description Fan Speed Count Overflow These eight bits are compared to the eight-bit fan speed counter. If the counter exceeds this value, an interrupt will be generated. This register should be loaded prior to setting the Fan Speed Control Enable (FSCEN) bit in the FSC1 register to avoid generating unintentional interrupts. The overflow count value can be determined using the following equation where FF% is equal to the percentage of nominal RPM which constitutes a fan failure: Decimal-Overflow-Count-Value = (1,200,000)/(RPM X Divisor X FF%) Based on the above equation, a divisor of 8 and a detected fan failure at 70% of nominal RPM, the fan speed monitoring logic is capable of supporting a low end nominal RPM of 850. High end RPM values are basically unlimited but counter resolution will be diminished above 8000 RPM. 4-34 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 3Eh: Fan Speed Current Count 3 (FSCC3) Register Name: Address: Reset Value: Description FSCC3 3Eh 0000_0000b Fan Speed Current Count 3. This register affects pin P2.7. 7 6 5 4 3 2 1 0 Fan Speed Current Count Bit(s) 7 Bit Label FSCO7-0 Access R/W Description These eight bits, when enabled by setting the FSCEN bit in the FSC3 register provide the user with an accurate binary fan speed count value which can be used to determine the current RPM value of the fan. A minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. The following equation can be used to determine the current RPM value of the fan: RPM = (1,200,000)/(Decimal-Count-Value X Divisor) When the result of a read of this register is 00h, an accurate fan speed count value has not been generated indicating that the fan has not completed a minimum of one revolution. When the result of a read of this register is FFh, the fan is rotating very slowly or there are no tachometer pulses present. When operating in a polled mode with the FSIEN bit reset in the FSC3 register, this register will automatically update with an accurate fan speed count once per revolution of the fan. When operating in an interrupt mode with the FSIEN bit set in the FSC3 register, this register will automatically update with an accurate fan speed count once per revolution of the fan until an interrupt is generated. Once the interrupt is generated, the value will remain stable until the interrupt is cleared. When the interrupt is cleared, this register will also be cleared indicating that a valid RPM value is in the process of being generated. 4-35 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 80h-87h: Bit Control Port 0 Registers (BCP00-BCP07) Register Name: Address: Reset Value: Description BCP00-BCP07 80h - 87h 0000_001Xb Bit Control Port 0 Registers These eight registers provide individual bit control for the Port 0 I/O pins. All register bits are identical from a control and status perspective with the only difference being the individual I/O pin controlled. The Data Direction (bit 1) and General Purpose Data (bit 0) bits are effectively the same bits found in the DDP0 and GPD0 registers, with parallel read and write paths. 7 6 5 4 3 Function Select 2 1 Data Direction 0 General Purpose Data Bit(s) 4:2 Bit Label FS2-0 Access R/W Description Function Select These three bits, along with the DD and GPD bits, determine the function of each I/ O pin. When configured as an output, these bits determine the rate at which the high current drive I/O will toggle, providing a simple mechanism for flashing LED's. The five bits allow the user to select one of seven flash rates as well as drive the LED both on and off. It is assumed that the LED is connected to VDD through an external current limiting resistor. Table 4-7 describes the possible combinations which can be used to drive an LED. When configured as an input, these bits determine the type of I/O pin edge transition which will generate an interrupt condition. Transition detectors within the device will filter the changes observed at the I/O pin and determine if a valid transition has occurred. If a valid transition occurs, the INT# pin will assert and a binary value equal to the address of this register will appear in the BCIS register. Table 4-8 describes the available input edge combinations. NOTE: When configuring an I/O pin from an output to an input with interrupt enabled, it is suggested that the data direction change and interrupt enabling be accomplished with separate register write operations. This guarantees that any I/O transition which occurs as a result of the data direction change which may rely on the weak internal pull-up will not generate an unexpected interrupt. 1 DD R/W Data Direction This bit determines the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. Additionally, an open-drain or open-source function can be developed by resetting or setting the appropriate data bit and using the data direction bit as the programmed data value. After a reset or power-on, this bit will be set to a binary one, enabling the I/O pin as an input with weak pull-up. 0 GPD R/W General Purpose Data When the I/O pin has been enabled as an output, writing this bit determines the data value which will be present on the corresponding I/O pin. If the I/O pin has been enabled as an input, reading this register bit will represent the current voltage applied to the pin. At no time will this bit directly represent the value latched into the data register. If the pin is enabled as an input and there is no signal applied, a weak internal pull-up resistor will hold the pin at a binary one. After a reset or power-on, this register bit will be set to a binary one, but the value returned from a register read will be the level applied to the pin since by default each pin is an input. 4-36 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet Table 4-7: LED Combinations FS2 0 0 0 0 0 0 1 1 1 1 FS1 0 0 0 0 1 1 0 0 1 1 FS0 0 0 0 1 0 1 0 1 0 1 DD 0 0 1 0 0 0 0 0 0 0 GPD 0 1 X X X X X X X X I/O State output low output high pulled-up input output toggling output toggling output toggling output toggling output toggling output toggling output toggling LED State LED turned on LED turned off LED turned off - default state LED flashing at 0.25Hz LED flashing at 0.33Hz LED flashing at 0.50Hz LED flashing at 1.00Hz LED flashing at 2.00Hz LED flashing at 3.08Hz LED flashing at 4.00Hz NOTE: The I/O is driven in an open drain mode when configured as a toggling output. Table 4-8: Input Edge Combinations FS2 0 X X X 1 FS1 0 0 1 1 0 FS0 0 1 0 1 0 DD 1 1 1 1 1 GPD X X X X X Interrupt Condition No interrupt generated - default state Interrupt generated on a rising edge Interrupt generated on a falling edge Interrupt generated on either edge No interrupt generated 4-37 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 90h-97h: Bit Control Port 1 Registers (BCP10-BCP17) Register Name: Address: Reset Value: Description BCP10-BCP17 90h-97h 0000_001Xb Bit Control Port 1 Registers These eight registers provide individual bit control for the Port 0 I/O pins. All register bits are identical from a control and status perspective with the only difference being the individual I/O pin controlled and the presence of the bypass function. The Data Direction (bit 1) and General Purpose Data (bit 0) bits are effectively the same bits found in the DDP0 and GPD0 registers, with parallel read and write paths. These eight registers function the same as the eight Bit Control Port 0 Registers, described above, except that they relate to the Port 1 I/O pins. 7 6 5 4 3 Function Select 2 1 Data Direction 0 General Purpose Data Bit(s) 4:2 Bit Label FS2-0 Access R/W Description Function Select These three bits, along with the DD and GPD bits, determine the function of each I/ O pin. When configured as an output, these bits determine the rate at which the high current drive I/O will toggle, providing a simple mechanism for flashing LED's. The five bits allow the user to select one of seven flash rates as well as drive the LED both on and off. It is assumed that the LED is connected to VDD through an external current limiting resistor. Table 4-7 describes the possible combinations which can be used to drive an LED. When configured as an input, these bits determine the type of I/O pin edge transition which will generate an interrupt condition. Transition detectors within the device will filter the changes observed at the I/O pin and determine if a valid transition has occurred. If a valid transition occurs, the INT# pin will assert and a binary value equal to the address of this register will appear in the BCIS register. Table 4-8 describes the available input edge combinations. NOTE: When configuring an I/O pin from an output to an input with interrupt enabled, it is suggested that the data direction change and interrupt enabling be accomplished with separate register write operations. This guarantees that any I/O transition which occurs as a result of the data direction change which may rely on the weak internal pull-up will not generate an unexpected interrupt. 1 DD R/W Data Direction This bit determines the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. Additionally, an open-drain or open-source function can be developed by resetting or setting the appropriate data bit and using the data direction bit as the programmed data value. After a reset or power-on, this bit will be set to a binary one, enabling the I/O pin as an input with weak pull-up. 4-38 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet Bit(s) 0 Bit Label GPD Access R/W Description General Purpose Data When the I/O pin has been enabled as an output, writing this bit determines the data value which will be present on the corresponding I/O pin. If the I/O pin has been enabled as an input, reading this register bit will represent the current voltage applied to the pin. At no time will this bit directly represent the value latched into the data register. If the pin is enabled as an input and there is no signal applied, a weak internal pull-up resistor will hold the pin at a binary one. After a reset or power-on, this register bit will be set to a binary one, but the value returned from a register read will be the level applied to the pin since by default each pin is an input. 4-39 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet 98h-9Bh: Pulse Width Modulation Control Registers (PWMC0-PWMC3) Register Name: Address: Reset Value: Description PWMC0-PWMC3 98h-9Bh X000_0000b Pulse Width Modulation Control These four registers provide a pulse width modulated output which can optionally be made available on the P2.0 through P2.3 I/O pins. Configurations for these I/O pins which may have previously been enabled through other control registers will be overridden if either or both of the PWBF bits are set. The PWBF bits have higher priority control over the P2.0 through P2.3 I/O pins than any other mode of operation. The pulse width modulated outputs are based on a 32 step counter and provide values from a 3.125% to a 100% duty cycle in 3.125% increments. 7 6 5 4 3 2 Pulse Width Percentage 1 0 Pulse Width Base Frequency Bit(s) 6:5 Bit Label PWBF1-0 Access R/W Description Pulse Width Base Frequency These two bits determine the base operating frequency of the pulse width modulated output. These frequencies are based on the input clock rate of 10.0MHz. Three additional base frequency ranges are available and are selected through bits 5 and 4 of the Backplane Controller Option Register located at address FDh. The following table describes the default base frequencies: PWBF1 0 PWBF0 0 Pulse Width Base Frequency normal operation - control is provided through GPD1/DDP1 or BCP1 26KHz base frequency 52KHz base frequency 104KHz base frequency 0 1 1 1 0 1 4:0 PWP4-0 R/W Pulse Width Percentage These five bits determine the percentage of high time that the output pulse will contain. There are 32 steps that can be adjusted in 3.125% increments. Table 4-9 describes the available percentages: Table 4-9: Pulse Width Percentages PWP4 0 0 0 PWP3 0 0 0 PWP2 0 0 0 PWP1 0 0 1 PWP0 0 1 0 Pulse Width Percentage 3.125% on/high time 6.25% on/high time 9.375% on/high time 4-40 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet Table 4-9: Pulse Width Percentages PWP4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PWP3 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PWP2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PWP1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PWP0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Pulse Width Percentage 12.5% on/high time 15.625% on/high time 18.75% on/high time 21.875% on/high time 25.0% on/high time 28.125% on/high time 31.25% on/high time 34.375% on/high time 37.5% on/high time 40.625% on/high time 43.75% on/high time 46.875% on/high time 50.0% on/high time 53.125% on/high time 56.25% on/high time 59.375% on/high time 62.5% on/high time 65.625% on/high time 68.75% on/high time 71.875% on/high time 75.0% on/high time 78.125% on/high time 81.25% on/high time 84.375% on/high time 87.5% on/high time 90.625% on/high time 93.75% on/high time 96.875% on/high time 100% on/high time 4-41 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet A0h-A7h: Bit Control Port 2 Registers (BCP20-BCP27) Register Name: Address: Reset Value: Description BCP20-BCP27 A0h-A7h 0000_001Xb Bit Control Port 2 Registers These eight registers provide individual bit control for the Port 0 I/O pins. All register bits are identical from a control and status perspective with the only difference being the individual I/O pin controlled and the presence of the bypass function. The Data Direction (bit 1) and General Purpose Data (bit 0) bits are effectively the same bits found in the DDP0 and GPD0 registers, with parallel read and write paths. These eight registers function the same as the eight Bit Control Port 0 Registers, described above, except that they relate to the Port 2 I/O pins. 7 6 5 4 3 Function Select 2 1 Data Direction 0 General Purpose Data Bit(s) 4:2 Bit Label FS2-0 Access R/W Description Function Select These three bits, along with the DD and GPD bits, determine the function of each I/ O pin. When configured as an output, these bits determine the rate at which the high current drive I/O will toggle, providing a simple mechanism for flashing LED's. The five bits allow the user to select one of seven flash rates as well as drive the LED both on and off. It is assumed that the LED is connected to VDD through an external current limiting resistor. Table 4-7 describes the possible combinations which can be used to drive an LED. When configured as an input, these bits determine the type of I/O pin edge transition which will generate an interrupt condition. Transition detectors within the device will filter the changes observed at the I/O pin and determine if a valid transition has occurred. If a valid transition occurs, the INT# pin will assert and a binary value equal to the address of this register will appear in the BCIS register. Table 4-8 describes the available input edge combinations. NOTE: When configuring an I/O pin from an output to an input with interrupt enabled, it is suggested that the data direction change and interrupt enabling be accomplished with separate register write operations. This guarantees that any I/O transition which occurs as a result of the data direction change which may rely on the weak internal pull-up will not generate an unexpected interrupt. 1 DD R/W Data Direction This bit determines the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. Additionally, an open-drain or open-source function can be developed by resetting or setting the appropriate data bit and using the data direction bit as the programmed data value. After a reset or power-on, this bit will be set to a binary one, enabling the I/O pin as an input with weak pull-up. 4-42 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet Bit(s) 0 Bit Label GPD Access R/W Description General Purpose Data When the I/O pin has been enabled as an output, writing this bit determines the data value which will be present on the corresponding I/O pin. If the I/O pin has been enabled as an input, reading this register bit will represent the current voltage applied to the pin. At no time will this bit directly represent the value latched into the data register. If the pin is enabled as an input and there is no signal applied, a weak internal pull-up resistor will hold the pin at a binary one. After a reset or power-on, this register bit will be set to a binary one, but the value returned from a register read will be the level applied to the pin since by default each pin is an input. 4-43 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet B0h-B7h: Bit Control Port 3 Registers (BCP30-BCP37) Register Name: Address: Reset Value: Description BCP30-BCP37 B0h-B7h 0000_001Xb Bit Control Port 3 Registers These eight registers provide individual bit control for the Port 0 I/O pins. All register bits are identical from a control and status perspective with the only difference being the individual I/O pin controlled and the presence of the bypass function. The Data Direction (bit 1) and General Purpose Data (bit 0) bits are effectively the same bits found in the DDP0 and GPD0 registers, with parallel read and write paths. These eight registers function the same as the eight Bit Control Port 0 Registers, described above, except that they relate to the Port 3 I/O pins. In addition, the control of the individual I/O pins assigned to these registers can be overridden by the PBC0, PBC1, PBC2 and PBC3 registers when port bypass control is required. 7 6 5 4 3 Function Select 2 1 Data Direction 0 General Purpose Data Bit(s) 4:2 Bit Label FS2-0 Access R/W Description Function Select These three bits, along with the DD and GPD bits, determine the function of each I/ O pin. When configured as an output, these bits determine the rate at which the high current drive I/O will toggle, providing a simple mechanism for flashing LED's. The five bits allow the user to select one of seven flash rates as well as drive the LED both on and off. It is assumed that the LED is connected to VDD through an external current limiting resistor. Table 4-7 describes the possible combinations which can be used to drive an LED. When configured as an input, these bits determine the type of I/O pin edge transition which will generate an interrupt condition. Transition detectors within the device will filter the changes observed at the I/O pin and determine if a valid transition has occurred. If a valid transition occurs, the INT# pin will assert and a binary value equal to the address of this register will appear in the BCIS register. Table 4-8 describes the available input edge combinations. NOTE: When configuring an I/O pin from an output to an input with interrupt enabled, it is suggested that the data direction change and interrupt enabling be accomplished with separate register write operations. This guarantees that any I/O transition which occurs as a result of the data direction change which may rely on the weak internal pull-up will not generate an unexpected interrupt. 1 DD R/W Data Direction This bit determines the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. Additionally, an open-drain or open-source function can be developed by resetting or setting the appropriate data bit and using the data direction bit as the programmed data value. After a reset or power-on, this bit will be set to a binary one, enabling the I/O pin as an input with weak pull-up. 4-44 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet Bit(s) 0 Bit Label GPD Access R/W Description General Purpose Data When the I/O pin has been enabled as an output, writing this bit determines the data value which will be present on the corresponding I/O pin. If the I/O pin has been enabled as an input, reading this register bit will represent the current voltage applied to the pin. At no time will this bit directly represent the value latched into the data register. If the pin is enabled as an input and there is no signal applied, a weak internal pull-up resistor will hold the pin at a binary one. After a reset or power-on, this register bit will be set to a binary one, but the value returned from a register read will be the level applied to the pin since by default each pin is an input. 4-45 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet C0h-C7h: Bit Control Port 4 Registers (BCP40-BCP47) Register Name: Address: Reset Value: Description BCP40-BCP47 C0h-C7h 0000_001Xb Bit Control Port 11 Registers These eight registers provide individual bit control for the Port 0 I/O pins. All register bits are identical from a control and status perspective with the only difference being the individual I/O pin controlled and the presence of the bypass function. The Data Direction (bit 1) and General Purpose Data (bit 0) bits are effectively the same bits found in the DDP0 and GPD0 registers, with parallel read and write paths. These eight registers function the same as the eight Bit Control Port 0 Registers, described above, except that they relate to the Port 4 I/O pins. In addition, the control of the individual I/O pins assigned to these registers can be overridden by the PBC4, PBC5, PBC6 and PBC7 registers when port bypass control is required. 7 6 5 4 3 Function Select 2 1 Data Direction 0 General Purpose Data Bit(s) 4:2 Bit Label FS2-0 Access R/W Description Function Select These three bits, along with the DD and GPD bits, determine the function of each I/ O pin. When configured as an output, these bits determine the rate at which the high current drive I/O will toggle, providing a simple mechanism for flashing LED's. The five bits allow the user to select one of seven flash rates as well as drive the LED both on and off. It is assumed that the LED is connected to VDD through an external current limiting resistor. Table 4-7 describes the possible combinations which can be used to drive an LED. When configured as an input, these bits determine the type of I/O pin edge transition which will generate an interrupt condition. Transition detectors within the device will filter the changes observed at the I/O pin and determine if a valid transition has occurred. If a valid transition occurs, the INT# pin will assert and a binary value equal to the address of this register will appear in the BCIS register. Table 4-8 describes the available input edge combinations. NOTE: When configuring an I/O pin from an output to an input with interrupt enabled, it is suggested that the data direction change and interrupt enabling be accomplished with separate register write operations. This guarantees that any I/O transition which occurs as a result of the data direction change which may rely on the weak internal pull-up will not generate an unexpected interrupt. 1 DD R/W Data Direction This bit determines the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. Additionally, an open-drain or open-source function can be developed by resetting or setting the appropriate data bit and using the data direction bit as the programmed data value. After a reset or power-on, this bit will be set to a binary one, enabling the I/O pin as an input with weak pull-up. 4-46 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet Bit(s) 0 Bit Label GPD Access R/W Description General Purpose Data When the I/O pin has been enabled as an output, writing this bit determines the data value which will be present on the corresponding I/O pin. If the I/O pin has been enabled as an input, reading this register bit will represent the current voltage applied to the pin. At no time will this bit directly represent the value latched into the data register. If the pin is enabled as an input and there is no signal applied, a weak internal pull-up resistor will hold the pin at a binary one. After a reset or power-on, this register bit will be set to a binary one, but the value returned from a register read will be the level applied to the pin since by default each pin is an input. 4-47 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet F8h: Backplane Controller Interrupt Status (BCIS) Register Name: Address: Reset Value: Description BCIS F8h 0000_0000b Backplane Controller Interrupt Status Register 7 6 5 4 Interrupt Active 3 2 1 0 Bit(s) 7:0 Bit Label IA7-0 Access R Description Interrupt Active These eight bits determine the currently active interrupt source which has been enabled through the Port Bypass Control registers, the Fan Speed Control registers or the Bit Control registers. The address of the Port Bypass Control registers, the address of the Bit Control registers or the address of the Fan Speed Control registers will be generated as an indicator of the currently active interrupt source. If multiple interrupt sources are active, the value generated will be prioritized from the lowest binary value to the highest binary value. To clear the current interrupt and deassert the INT# pin, a value of FFh must be written to this register. If a higher binary value/lower priority interrupt source is still active, the new value will be generated and the INT# pin will re-assert. 4-48 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet FCh: Backplane Controller Test (BCT) Register Name: Address: Reset Value: Description BCT FCh 0XXX_X000b Backplane Controller Interrupt Status Register 7 Soft Reset 6 5 4 3 2 Fan Speed Bypass 1 Flash Rate Bypass 0 Serial Interface Filter Bypass Bit(s) 7 Bit Label SRST Access R/W Description Soft Reset Setting this bit resets the device at the end of the current serial transfer. All I/O's, control registers, clock dividers and the slave state machine are reset by this bit. This bit is self resetting and writes of a zero to this bit will have no effect on the current state of the device. 2 FSB R/W Fan Speed Bypass Setting this bit causes the main clock divider for the fan speed monitors to be bypassed. Bypassing the main clock divider causes the fan speed counters to operate 500 times faster than normal. When reset or after power-on, the normal clock divider will be activated. This bit should not be set during normal operation. 1 FRB R/W Flash Rate Bypass Setting this bit causes the main clock divider for the flash rate generators to be bypassed. Bypassing the main clock divider causes the expected flash rates to be 125,000 times faster than normal. When reset or after power-on, the normal clock divider will be activated. This bit should not be set during normal operation. 0 SIFB R/W Serial Interface Filter Bypass Setting this bit causes the digital filters on the SCL and SDA pins to be bypassed. Bypassing the filters allows the serial transfer speed to be increased for test purposes. When reset or after power-on, normal filtering will be activated. This bit should not be set during normal operation. 4-49 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet FDh: Backplane Controller Option (BCO) Register Name: Address: Reset Value: Description BCO FDh X000_XXXXb Backplane Controller Interrupt Status Register 7 6 Tach Filter Extend 5 4 3 2 1 0 Pulse Width Modulation Divider Select Bit(s) 6 Bit Label TFE Access R/W Description Tach Filter Extend Setting this bit causes the input filters on P1.0 through P2.7 to be extended from a two stage voting circuit to a five stage voting circuit. Additional noise immunity of approximately 300 nanoseconds will be achieved. This bit enables the filter extension logic on all tach inputs and is independent of the tach control logic. The extended filters on P1.0 through P2.7 can be used in other applications with noisy signaling that require an enhanced input filter. After a reset or power-on, this register bit will be cleared to a zero, enabling normal input filter operation. 5:4 PDS1-0 R/W Pulse Width Modulation Divider Select These two bits determine the divider that is used for the pulse width modulation circuits. The base frequency range of all pulse width modulation circuits are controlled by these bits. Each pulse width modulation circuit can be programmed to select one of the three available frequencies within the range. After a reset or power-on, these register bits will be cleared to a zero. The following table describes the available frequency ranges: Table 4-10: Pulse Width Modulation Frequencies PDS1 0 0 1 1 PDS0 0 1 0 1 Pulse Width Modulation Frequency Range 26KHz, 52KHz or 104KHz (divide by 3) 5.2KHz, 10.4KHz or 20.8KHz (divide by 15) 1.04KHz, 2.08KHz or 4.16KHz (divide by 75) 208Hz, 416Hz, 833Hz (divide by 375) 4-50 Revision 4.0 November 10, 2004 Control Registers Control Register Definition SSC050-01 Data Sheet FFh: Backplane Controller Version (VER) Register Name: Address: Reset Value: Description VER FFh 0001_0001b Backplane Controller Version Register 7 6 5 4 Version 3 2 1 0 Bit(s) 7:0 Bit Label VER7-0 Access R/W Description Version These bits define the current version of the Backplane Controller. If revisions are required, these bits will change to reflect the latest version of the device. In general, changes to bits 3 through 0 will reflect a minor revision and changes to bits 7 through 4 will reflect a major revision or different device type. Firmware should check this register to determine the current capabilities of the device. NOTE: The SSC050-01 and SSC050 currently utilize the same binary value in the Version Register. However, the device type can be determined by performing the following register write and read before configuring the device for normal operation. Write a 15h to the Pulse Width Modulation Control Register at location 98h. Read this register and check the result, if the register reads back 15h, the device is a SSC050-01, if the register reads back 00h, the device is a SSC050. 4-51 Revision 4.0 November 10, 2004 Electrical Characteristics Maximum Ratings SSC050-01 Data Sheet Chapter 5 Electrical Characteristics MAXIMUM RATINGS Table 5-1: Absolute Maximum Ratings Parameter DC Supply Voltage LVTTL Input Voltage 5 Volt Compatible Input Voltage DC Input Current Storage Temperature Range Latchup Current Symbol Vdd Vin Vin Iin Tstg Ilp Limits -0.3 to +3.9 -1.0 to VDD+0.3 -1.0 to +6.5 ±10 -40 to +125 ±150 Unit V V V uA °C mA DC CHARACTERISTICS Table 5-2: Operating Conditions Parameter Supply Voltage Supply Current Operating Ambient Temperature Range Symbol Vdd Idd TA -40 Min 3.00 Max 3.60 50 +85 Unit V mA °C 5-1 Revision 4.0 November 10, 2004 Electrical Characteristics DC Characteristics SSC050-01 Data Sheet Table 5-3: General Purpose I/O Ports, P4, P3, P2, P1, P0 Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Schmitt Threshold - Positive Schmitt Threshold - Negative Schmitt Hysteresis Input Current with Pull-up Three State Output Leakage (Device Test Mode) Symbol Voh Vol Vih Vil Vt+ VtVh Iin Ioz Vin=Vss 0.8 0.4 -25 -10 -125 +10 Condition Ioh=12mA Iol=12mA Min 2.4 Vss 2.0 Vss-0.5 Max Vdd 0.4 5.5 0.8 2.0 Unit V V V V V V V uA uA Table 5-4: Two-wire Serial Interface, SDA Parameter Output Low Voltage Input High Voltage Input Low Voltage Schmitt Threshold - Positive Schmitt Threshold - Negative Schmitt Hysteresis Input Current Three State Output Leakage Symbol Vol Vih Vil Vt+ VtVh Iin Ioz Vin=Vdd/Vss 0.8 0.4 -10 -10 +10 +10 Condition Iol=4mA Min Vss 2.0 Vss-0.5 Max 0.4 5.5 0.8 2.0 Unit V V V V V V uA uA 5-2 Revision 4.0 November 10, 2004 Electrical Characteristics DC Characteristics SSC050-01 Data Sheet Table 5-5: Two-wire Serial Interface, SCL Parameter Input High Voltage Input Low Voltage Schmitt Threshold - Positive Schmitt Threshold - Negative Schmitt Hysteresis Input Current Symbol Vih Vil Vt+ VtVh Iin Vin=Vdd/Vss 0.8 0.4 -10 +10 Condition Min 2.0 Vss-0.5 Max 5.5 0.8 2.0 Unit V V V V V uA Table 5-6: Address Inputs, A2, A1, A0, ASEL Parameter Input High Voltage Input Low Voltage Schmitt Threshold - Positive Schmitt Threshold - Negative Schmitt Hysteresis Input Current Symbol Vih Vil Vt+ VtVh Iin Vin=Vdd/Vss 0.8 0.4 -10 +10 Condition Min 2.0 Vss-0.5 Max 5.5 0.8 2.0 Unit V V V V V uA Table 5-7: Interrupt Output, INT# Parameter Output Low Voltage Symbol Vol Condition Iol=4mA Min Vss Max 0.4 Unit V Table 5-8: Test Inputs: TEST0, TEST1, TEST2 Parameter Input High Voltage Input Low Voltage Schmitt Threshold - Positive Schmitt Threshold - Negative Schmitt Hysteresis Input Current Symbol Vih Vil Vt+ VtVh Iin Vin=Vdd/Vss 0.8 0.4 -10 +10 Condition Min 2.0 Vss-0.5 Max 5.5 0.8 2.0 Unit V V V V V uA 5-3 Revision 4.0 November 10, 2004 Electrical Characteristics DC Characteristics SSC050-01 Data Sheet Table 5-9: Oscillator/Clock Input, OSCI Parameter Input High Voltage Input Low Voltage Switching Threshold Input Current Symbol Vih Vil Vt Iin Vin=Vdd/Vss -10 Condition Min Vdd/2 Vss-0.5 Max Vdd+0.3 Vdd/2 Vdd/2 +10 Unit V V V uA Table 5-10: Oscillator Output, OSCO Parameter Output High Voltage Output Low Voltage Symbol Voh Vol Condition Ioh=4mA Iol=4mA Min Vdd-0.3 Vss Max Vdd Vss+0.3 Unit V V 5-4 Revision 4.0 November 10, 2004 Electrical Characteristics AC Characteristics SSC050-01 Data Sheet AC CHARACTERISTICS External Clock Timing Table 5-11: Low Frequency Operation Parameter Nominal Frequency Frequency Range Clock Cycle Time Clock Low Time Clock High Time Clock Slew Rate Symbol F F t1 t2 t3 t4 Condition Min 9.5 8.0 80 32 32 1 Max 10.5 12.5 125 75 75 Unit MHz MHz ns ns ns V/ns CLOCK CYCLE TIMING t1 CLOCK t2 t3 t4 Figure 5-1. Clock Cycle Timing 5-5 Revision 4.0 November 10, 2004 Electrical Characteristics AC Characteristics SSC050-01 Data Sheet Table 5-12: Two-Wire Serial Interface Timing Parameter Symbol Standard Mode Min SCL Clock Frequency Bus Free Time Hold Time - Start Condition SCL Low Time SCL High Time Setup Time - Start Condition Hold Time - Data Setup Time - Data Setup Time - Stop Condition fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tsu:sto 0 4.7 4.0 4.7 4.0 4.7 0 250 4.0 Max 100 Fast Mode Min 0 1.3 0.6 1.3 0.6 0.6 0 100 0.6 0.9 Max 400 KHz us us us us us us ns us Unit TWO WIRE SERIAL INTERFACE TIMING SCL tlow thd:sta SDA tsu:sta S T A R T tsu:dat tbuf S T O P thigh thd:dat tsu:sto Figure 5-2. 5-6 Revision 4.0 November 10, 2004 Electrical Characteristics AC Characteristics SSC050-01 Data Sheet Two-wire Serial Interface Operation The following diagrams illustrate the two-wire serial interface read and write capabilities of the SSC050-01. All operations can be performed in any order. S T A R T MULTI-BYTE WRITE S SLAVE ADDRESS WORD ADDRESS (n) DATA n DATA n+1 DATA n+x S T O P P A S E L A C K A C K A C K A C K A C K S T A R T BYTE WRITE S SLAVE ADDRESS WORD ADDRESS DATA S T O P P A S E L A C K A C K A C K S T A R T MULTI-BYTE READ S SLAVE ADDRESS WORD ADDRESS (n) S T A R T S A C K SLAVE ADDRESS DATA n DATA n+1 DATA n+x S T O P P A S E L A C K A S E L A C K A C K A C K S T A R T BYTE READ S SLAVE ADDRESS WORD ADDRESS (n) S T A R T S A C K SLAVE ADDRESS DATA n S T O P P A S E L A C K A S E L A C K Figure 5-3. Two-Wire Serial Interface Operation Oscillator Requirements The SSC050-01 can use an external 3.3 volt 8.0MHz to 12.5MHz clock source connected to the OSCI pin with CKSEL2 tied to VSS. An external 3.3 volt 32.0MHz to 50.0MHz clock source can be connected to the OSCI pin with CKSEL2 tied to VDD and CKSEL1 tied to VSS. An external 3.3 volt 48.0MHz to 75.0MHz clock source can be connected to the OSCI pin with CKSEL2 tied to VDD and CKSEL1 tied to VDD. Alternatively, an 8.0MHz to 12.5MHz crystal and several passive components 5-7 Revision 4.0 November 10, 2004 Electrical Characteristics AC Characteristics SSC050-01 Data Sheet may be used. The following diagrams illustrate the two options available when using a crystal. The passive components shown will function properly for all crystal frequencies. Option 1 requires fewer external components due to the high input capacitance of the OSCI pin and results in a stable configuration. Option 2 represents a classic approach with a higher level of stability. OPTION 1 SSC050-01 OSCI 10MHz 390 ohm 30 pF Vss OSCO OPTION 2 SSC050-01 OSCI 30 pF 10MHz Vss 10M ohm 390 ohm 30 pF Vss Figure 5-4. Oscillator Options OSCO 5-8 Revision 4.0 November 10, 2004 Electrical Characteristics AC Characteristics SSC050-01 Data Sheet External Reset Circuit The SSC050-01 supports an internal Power-On Reset circuit that eliminates the need for an external reset source. However, the device does support a mechanism that allows the use of an external reset for those applications where a system reset is available and required. The following diagrams show the external connections required. The external reset source must be active high and does not need to be synchronous to the clock source of the SSC050-01. TEST0 and TEST2 must remain at a low level during the reset sequence. The minimum external reset pulse width is 50 nanoseconds. Two-wire serial transactions to the SSC050-01 must not commence until a minimum of 500 nanoseconds after the deassertion of the external reset pulse. Option 1 should be used when ASEL is normally held low (the device type identifier value is 1000b). Option 2 should be used when ASEL is normally held high (the device type identifier value is 1100b). OPTION 1 SSC050-01 ASEL Active High System Reset TEST1 OPTION 2 SSC050-01 Vdd Active High System Reset ASEL TEST1 Figure 5-5. External Reset Circuit Options 5-9 Revision 4.0 November 10, 2004 Electrical Characteristics AC Characteristics SSC050-01 Data Sheet Optional External Tach Filter The fan tach inputs of the SSC050-01 utilize schmitt trigger input buffers and are also internally digitally filtered. However, excessive external noise on a tach input can result in inaccurate fan speed current count values. The use of an external low pass filter along with the use of the extended tach filter mode (Tach Filter Extend, bit 6 of register FDh) of the SSC050-01 will eliminate inaccurate current count values. The following circuit provides excellent noise rejection at all possible RPM ranges supported by the SSC050-01. Vdd SSC050-01 3.3K ohm 330 ohm 0.1 uF Vss Figure 5-6. Optional External Tach Filter Fan Tach Output P2.4-P2.7 5-10 Revision 4.0 November 10, 2004 Mechanical Drawing SSC050-01 Data Sheet Chapter 6 MECHANICAL DRAWING 20.00 18.00 17.90 12.00 14.00 64 12345 23.90 3.40 MAX 2.80 0.18 0.20 0.40 1.95 1.00 0.80 NOTE: ALL DIMENSIONS ARE NOMINAL UNLESS OTHERWISE SPECIFIED Figure 6-1. Mechanical Drawing 6-1 Revision 4.0 November 10, 2004 Ordering Information SSC050-01 Data Sheet Chapter 7 ORDERING INFORMATION The SSC050-01 device is available in two package types. L2A050-01 is a 64-pin plastic quad flat pack (PQFP). The device is also available in a lead(Pb)-free package, VSC050XKM-01. Lead(Pb)-free products from Maxim comply with the temperatures and profiles defined in the joint IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard. SSC050-01 Two-Wire Serial Backplane Controller Part Number L2A050-01 VSC050XKM-01 Description 64-pin PQFP Lead(Pb)-free 64-pin PQFP 7-1 Revision 4.0 November 10, 2004