VSC056XKM

Revision 4.1 January 2008 VSC056 Data Sheet Enhanced Two-Wire Serial Backplane Controller FEATURES • • • • • • Up to 64 bits of user-definable, bidirectional general-purpose inputs and outputs Integrated port bypass, clock recovery and signal detect support for up to 16 drives Eight programmable fan speed monitoring inputs Eight programmable pulse-width modulated fan control outputs Up to 32 programmable input-to-output bypass pairs Two clock input ranges: 8.0 MHz to 12.5 MHz (external crystal or external clock source) and 32.0 MHz to 75.0 MHz (external clock source) Selectable direct LED drive flashing capability Pin-programmable addressing for up to 16 devices on a single serial bus 5-V tolerant high current I/O, Slave mode two-wire serial interface and interrupt output Ten programmable LED pulse train circuits One 24-bit general-purpose timer (supports a timeout greater than four seconds with a 12.5 MHz core clock) • • • • Up to 16 subaddressed Master mode two-wire serial interface ports External reset of the slave two-wire serial core Enhanced fan speed monitor input filters 20% of package pins are power and ground for excellent noise immunity and long-term reliability APPLICATIONS • • • • • • • • • Enterprise storage environments Storage Area Network (SAN) appliances Network Attached Storage (NAS) systems Fabric Attached Storage (FAS) systems Rack-mounted servers with RAID JBOD arrays Disk-based backup storage Near-line storage replacement systems Fixed-content storage systems • • • • • To order the VSC056 device, see “Ordering Information,” page 134. GENERAL DESCRIPTION The VSC056 device is an I/O-intensive peripheral device that is intended to be part of a cost-effective Fibre Channel Arbitrated Loop (FC-AL), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), or Serial ATA (SATA) enclosure management solution. The device contains an address-programmable two-wire serial interface, a block of control and status registers, I/O port control logic, specialized port bypass control logic, and a clockgeneration block. Along with an external crystal, the device can be configured to support up to 64 bits of general-purpose I/O; or 16 bits of general-purpose I/O, 32 bits of port bypass control (16 pairs supporting 16 drives), eight fan speed monitoring inputs, and eight pulse-width modulated general-purpose control outputs. The VSC056 supports various combinations of individual port bypass circuit (PBC), clock recovery unit (CRU), and signal detect unit (SDU) functions, as well as integrated solutions. The control register portion of the device allows the user to individually program each I/O pin as an input, an output, or an open-drain or open-source output. Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 of 134 VSC056 Data Sheet Additional control features include: selectable flash rates for direct LED drive, input edge detection for interrupt generation, input to output bypass capability, fan speed monitoring control, and pulse-width modulated output control. Support for sub-addressing additional two-wire serial slave devices using a set of seven control registers is included. This capability allows up to 16 independent Master mode two-wire serial slave ports to be created using 32 of the I/O pins. The addressing capability of the VSC056 includes three pins, which are used for device addressing, as well as one pin that can be used to select two device type identifiers. Sixteen VSC056 devices can be used in a single two-wire serial interface system. Block Diagram I/OPorts P0.0 − P0.7 P1.0 − P1.7 P2.0 − P2.7 P3.0 − P3.7 P4.0 − P4.7 P5.0 − P5.7 P6.0 − P6.7 P7.0 − P7.7 OSCI OSCO CKSEL0 CKSEL1 CKSEL2 SYNCEN SY NC# Clock Generator andDiv iders Pulse-Width Modulation Control Fan Speed Sensors I/OControl andLED Flashing Port By pass Control SDA SCL A2 − A0 ASEL INT# RESET Two-Wire Slav e Interf ace Interrupt Priority and Control Power-On Reset 2 of 134 Revision 4.1 January 2008 VSC056 Data Sheet TYPICAL APPLICATIONS FC-AL Drive Enclosure Configuration ● ● Basic port bypass configuration Support for up to 128 drives: Backplane Controller supports up to two sets of CRU/SDU functions and drives, and 16 Backplane Controllers can be attached simultaneously to the serial bus Four-drive implementation is shown below; four-channel PBC with two CRU/SDU functions and generalpurpose I/O lines for drive control and status, and other enclosure control functions. ● Figure 1. Single Loop, Single Controller with Four Drives Copper or Optics Local I/O (x8) PBC_EN VSC7142 VSC120 X24C16 EEPROM Embedded Controller Flash Memory Driv e Bay 1 PBC_EN1 PBC_EN2 PBC_EN3 PBC_EN4 Two-Wire Serial Interf ace Driv e Bay 2 VSC7147 Driv e Bay 3 Driv e Bay 4 Temperature Sensor (LM75) VSC056 Enhanced Backplane Controller LEDs (x8) Power Supplies Fans (x4) 3 of 134 Revision 4.1 January 2008 VSC056 Data Sheet General-Purpose I/O Configuration ● ● Controlled by general-purpose microcontroller with two-wire serial interface Support for up to 1024 I/O lines: Backplane controller supports up to 64 I/O lines and 16 backplane controllers can be simultaneously attached to the serial bus Four-backplane controller implementation is shown here with shared open-drain interrupt ● Figure 2. Four Backplane Controllers, 256 Bidirectional I/O Lines Microcontroller with Two-Wire Serial Interf ace Two-Wire Serial Interf ace Interrupt (optional) I/O I/O I/O I/O I/O I/O I/O I/O (x8) (x8) (x8) (x8) (x8) (x8) (x8) (x8) I/O I/O I/O I/O I/O I/O I/O I/O (x8) (x8) (x8) (x8) (x8) (x8) (x8) (x8) VSC056 Enhanced Backplane Controller VSC056 Enhanced Backplane Controller VSC056 Enhanced Backplane Controller I/O I/O I/O I/O I/O I/O I/O I/O (x8) (x8) (x8) (x8) (x8) (x8) (x8) (x8) VSC056 Enhanced Backplane Controller I/O I/O I/O I/O I/O I/O I/O I/O (x8) (x8) (x8) (x8) (x8) (x8) (x8) (x8) 4 of 134 Revision 4.1 January 2008 VSC056 Data Sheet Contents General Description..................................................................................................... Features ........................................................................................................................ Applications ................................................................................................................. Typical Applications .................................................................................................... Revision History........................................................................................................... 1 2 1 1 1 3 9 Introduction ....................................................................................................... 10 Functional Descriptions ................................................................................... 11 2.1 2.2 2.3 2.4 2.5 Two-Wire Serial Interface ............................................................................................................11 Control Registers .........................................................................................................................11 I/O Logic ......................................................................................................................................13 Clock Generator ..........................................................................................................................13 Power-on Reset ...........................................................................................................................14 3 Registers ............................................................................................................ 15 3.1 3.2 Control Registers .........................................................................................................................15 Control Register Definitions .........................................................................................................21 3.2.1 00h: General-Purpose I/O Port 0 Data (GPD0) .............................................................21 3.2.2 01h: General-Purpose I/O Port 1 Data (GPD1) .............................................................22 3.2.3 02h: General-Purpose I/O Port 2 Data (GPD2) .............................................................22 3.2.4 03h: General-Purpose I/O Port 3 Data (GPD3) .............................................................23 3.2.5 04h: General-Purpose I/O Port 4 Data (GPD4) .............................................................23 3.2.6 05h: General-Purpose I/O Port 5 Data (GPD5) .............................................................24 3.2.7 06h: General-Purpose I/O Port 6 Data (GPD6) .............................................................24 3.2.8 07h: General-Purpose I/O Port 7 Data (GPD7) .............................................................25 3.2.9 10h: I/O Port 0 Data Direction (DDP0) ...........................................................................25 3.2.10 11h: I/O Port 1 Data Direction (DDP1) ...........................................................................26 3.2.11 12h: I/O Port 2 Data Direction (DDP2) ...........................................................................26 3.2.12 13h: I/O Port 3 Data Direction (DDP3) ...........................................................................27 3.2.13 14h: I/O Port 4 Data Direction (DDP4) ...........................................................................27 3.2.14 15h: I/O Port 5 Data Direction (DDP5) ...........................................................................28 3.2.15 16h: I/O Port 6 Data Direction (DDP6) ...........................................................................28 3.2.16 17h: I/O Port 7 Data Direction (DDP7) ...........................................................................29 3.2.17 20h: Port Bypass Control 0 (PBC0) ...............................................................................30 3.2.18 21h: Port Bypass Control 1 (PBC1) ...............................................................................31 3.2.19 22h: Port Bypass Control 2 (PBC2) ...............................................................................32 3.2.20 23h: Port Bypass Control 3 (PBC3) ...............................................................................33 3.2.21 24h: Port Bypass Control 4 (PBC4) ...............................................................................34 3.2.22 25h: Port Bypass Control 5 (PBC5) ...............................................................................35 3.2.23 26h: Port Bypass Control 6 (PBC6) ...............................................................................36 5 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.24 3.2.25 3.2.26 3.2.27 3.2.28 3.2.29 3.2.30 3.2.31 3.2.32 3.2.33 3.2.34 3.2.35 3.2.36 3.2.37 3.2.38 3.2.39 3.2.40 3.2.41 3.2.42 3.2.43 3.2.44 3.2.45 3.2.46 3.2.47 3.2.48 3.2.49 3.2.50 3.2.51 3.2.52 3.2.53 3.2.54 3.2.55 3.2.56 3.2.57 3.2.58 3.2.59 3.2.60 3.2.61 3.2.62 3.2.63 3.2.64 3.2.65 3.2.66 3.2.67 27h: Port Bypass Control 7 (PBC7) ...............................................................................37 28h: Port Bypass Control 8 (PBC8) ...............................................................................38 29h: Port Bypass Control 9 (PBC9) ...............................................................................39 2Ah: Port Bypass Control 10 (PBC10) ...........................................................................40 2Bh: Port Bypass Control 11 (PBC11) ...........................................................................41 2Ch: Port Bypass Control 12 (PBC12) ..........................................................................42 2Dh: Port Bypass Control 13 (PBC13) ..........................................................................43 2Eh: Port Bypass Control 14 (PBC14) ...........................................................................44 2Fh: Port Bypass Control 15 (PBC15) ...........................................................................45 30h: Fan Speed Control 0 (FSC0) .................................................................................46 31h: Fan Speed Count Overflow 0 (FSCO0) .................................................................47 32h: Fan Speed Current Count 0 (FSCC0) ...................................................................47 34h: Fan Speed Control 1 (FSC1) .................................................................................48 35h: Fan Speed Count Overflow 1 (FSCO1) .................................................................49 36h: Fan Speed Current Count 1 (FSCC1) ...................................................................49 38h: Fan Speed Control 2 (FSC2) .................................................................................50 39h: Fan Speed Count Overflow 2 (FSCO2) .................................................................51 3Ah: Fan Speed Current Count 2 (FSCC2) ...................................................................51 3Ch: Fan Speed Control 3 (FSC3) ................................................................................52 3Dh: Fan Speed Count Overflow 3 (FSCO3) ................................................................53 3Eh: Fan Speed Current Count 3 (FSCC3) ...................................................................53 40h: Fan Speed Control 4 (FSC4) .................................................................................54 41h: Fan Speed Count Overflow 4 (FSCO4) .................................................................55 42h: Fan Speed Current Count 4 (FSCC4) ...................................................................55 44h: Fan Speed Control 5 (FSC5) .................................................................................56 45h: Fan Speed Count Overflow 5 (FSCO5) .................................................................57 46h: Fan Speed Current Count 5 (FSCC5) ...................................................................57 48h: Fan Speed Control 6 (FSC6) .................................................................................58 49h: Fan Speed Count Overflow 6 (FSCO6) .................................................................59 4Ah: Fan Speed Current Count 6 (FSCC6) ...................................................................59 4Ch: Fan Speed Control 7 (FSC7) ................................................................................60 4Dh: Fan Speed Count Overflow 7 (FSCO7) ................................................................61 4Eh: Fan Speed Current Count 7 (FSCC7) ...................................................................61 70h: Pulse Train Control 00 (PTC00) ............................................................................62 71h: Pulse Train Control 01 (PTC01) ............................................................................63 72h: Pulse Train Control 10 (PTC10) ............................................................................64 73h: Pulse Train Control 11 (PTC11) ............................................................................65 74h: Pulse Train Control 20 (PTC20) ............................................................................66 75h: Pulse Train Control 21 (PTC21) ............................................................................67 76h: Pulse Train Control 30 (PTC30) ............................................................................68 77h: Pulse Train Control 31 (PTC31) ............................................................................69 78h: Pulse Train Control 40 (PTC40) ............................................................................70 79h: Pulse Train Control 41 (PTC41) ............................................................................71 7Ah: Pulse Train Control 50 (PTC50) ............................................................................72 6 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.68 3.2.69 3.2.70 3.2.71 3.2.72 3.2.73 3.2.74 3.2.75 3.2.76 3.2.77 3.2.78 3.2.79 3.2.80 3.2.81 3.2.82 3.2.83 3.2.84 3.2.85 3.2.86 3.2.87 3.2.88 3.2.89 3.2.90 3.2.91 3.2.92 3.2.93 3.2.94 3.2.95 3.2.96 3.2.97 3.2.98 3.2.99 3.2.100 3.2.101 7Bh: Pulse Train Control 51 (PTC51) ............................................................................73 7Ch: Pulse Train Control 60 (PTC60) ............................................................................74 7Dh: Pulse Train Control 61 (PTC61) ............................................................................75 7Eh: Pulse Train Control 70 (PTC70) ............................................................................76 7Fh: Pulse Train Control 71 (PTC71) ............................................................................77 80h-87h: Bit Control Port 0 (BCP00-BCP07) .................................................................78 88h: Pulse Train Control 80 (PTC80) ............................................................................81 89h: Pulse Train Control 81 (PTC81) ............................................................................82 8Ch: Pulse Train Control 90 (PTC90) ............................................................................83 8Dh: Pulse Train Control 91 (PTC91) ............................................................................84 90h-97h: Bit Control Port 1 (BCP10-BCP17) .................................................................85 98h-9Fh: Pulse-Width Modulation Control (PWMC0-PWMC7) .....................................87 A0h-A7h: Bit Control Port 2 (BCP20-BCP27) ................................................................89 B0h-B7h: Bit Control Port 3 (BCP30-BCP37) ................................................................91 C0h-C7h: Bit Control Port 4 (BCP40-BCP47) ................................................................93 CCh: General-Purpose Timer Count 0 (GPTC0) ...........................................................95 CDh: General-Purpose Timer Count 1 (GPTC1) ...........................................................95 CEh: General-Purpose Timer Count 2 (GPTC2) ...........................................................96 CFh: General-Purpose Timer Enable (GPTE) ...............................................................96 D0h-D7h: Bit Control Port 5 (BCP50-BCP57) ................................................................97 E0h-E7h: Bit Control Port 6 (BCP60-BCP67) ................................................................99 E8h: Master Interface Clock Divider (MICD) ................................................................101 E9h: Master Interface Port Select (MIPS) ....................................................................102 EAh: Master Interface Data (MID) ...............................................................................102 EBh: Master Interface Command (MIC) ......................................................................103 ECh: Master Interface Low-Level Control (MILC) ........................................................107 EDh: Master Interface Status (MIS) .............................................................................107 EEh: Master Interface Read Data (MIRD) ...................................................................108 F0h-F7h: Bit Control Port 7 (BCP70-BCP77) ..............................................................108 F8h: Backplane Controller Interrupt Status (BCIS) ......................................................110 FCh: Backplane Controller Test (BCT) ........................................................................111 FDh: Clock Select Control (CSC) ................................................................................111 FEh: Clock Divider Control (CDC) ...............................................................................113 FFh: Backplane Controller Version (VER) ...................................................................114 4 Electrical Specifications ................................................................................. 115 4.1 DC Characteristics ....................................................................................................................115 4.1.1 General-Purpose I/O Ports ..........................................................................................115 4.1.2 Two-Wire Serial Interface ............................................................................................116 4.1.3 Address Inputs .............................................................................................................116 4.1.4 Interrupt Output ............................................................................................................117 4.1.5 Reset, Test, and Synchronization Clock Control Inputs ..............................................117 4.1.6 Device Synchronization ...............................................................................................117 4.1.7 Oscillator and Clock Input ............................................................................................118 7 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.1.8 Oscillator Output ..........................................................................................................118 AC Characteristics .....................................................................................................................119 4.2.1 External Clock Timing ..................................................................................................119 4.2.2 Two-Wire Serial Interface Timing ................................................................................120 Operating Conditions .................................................................................................................121 Maximum Ratings ......................................................................................................................121 Two-Wire Serial Interface Operation ..........................................................................................122 Oscillator Requirements ............................................................................................................123 External Reset Circuit ................................................................................................................123 Optional External Tach Filter ....................................................................................................124 5 Pin Descriptions .............................................................................................. 125 5.1 5.2 Pin Diagram ...............................................................................................................................125 Pin Identifications ......................................................................................................................127 6 Package Information ....................................................................................... 132 6.1 6.2 6.3 Thermal Specifications ..............................................................................................................132 Moisture Sensitivity ...................................................................................................................132 Package Drawing .......................................................................................................................132 7 Ordering Information ...................................................................................... 134 8 of 134 Revision 4.1 January 2008 VSC056 Data Sheet REVISION HISTORY This section describes changes that have been implemented in this document. The changes are listed by revision, starting with the most recent publication. Revision 4.1 Revision 4.1 of this data sheet was published in January 2008. The following is a summary of the changes implemented in the data sheet. ● The power supply voltage for the recommended operating conditions were corrected. The minimum power supply voltage is 3.0 V and maximum is 3.6 V. For more information, see Table 22, page 121. Revision 4.0 Revision 4.0 of this data sheet was published in April 2007. The following is a summary of the changes implemented in the data sheet: ● The electrostatic discharge voltage was added. For charged device model, it is ±1500 V. For human body model, it is a Class 2 rating. The moisture sensitivity is now specified as level 3. ● Revision 2.0 Revision 2.0 of this data sheet was published in October 2006. This is the first publication of this document. 9 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 1 Introduction This data sheet provides reference information for the Maxim Enhanced Two-Wire Serial Backplane Controller, VSC056. It is intended for system designers and software and firmware developers who are using this device to support enclosure management functions or other related remote I/O expansion tasks. TheVSC056 is package and power supply compatible with the VSC055. The VSC056 is similar to the VSC055 in feature and function, except for differences in the reset and clock out functions. This document assumes that the user is familiar with the two-wire serial interfaces, the programmable I/O control, and the operation of FC-AL control functions, such as a PBC (port bypass controller), a CRU (clock recovery unit), and an SDU (signal detect unit). The user may also need to be familiar with Fibre Channel Arbitrated Loop (FC-AL) operation and SCSI Enclosure Services (SES). 10 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 2 Functional Descriptions The VSC056 device is composed of five major functional blocks: ● ● ● ● ● a Slave mode two-wire serial interface a block of control registers general-purpose I/O and specialized port bypass control logic a clock generator power-on reset control logic The VSC056 fully supports a generic two-wire serial interface and is compatible with other industrystandard devices that support this interface at both 100 kHz and 400 kHz. 2.1 Two-Wire Serial Interface The VSC056 device supports a single Slave mode two-wire serial interface. All interchip communication to a microcontroller takes place over this bus. The interface supports a 3-bit address bus that allows the user to select one of eight possible addresses. The address bus is compared to bits 3:1 of the slave address byte. The slave address byte is the first byte transmitted to the device after a START condition. The VSC056 supports two pin-selectable, 4-bit device type identifier values, 1000b and 1100b. The address bits and the device identifier allow the use of up to 16 devices on a single two-wire serial interface. The serial interface control logic includes: ● ● ● ● ● a slave state machine address comparison logic serial-to-parallel and parallel-to-serial conversion register read/write control filtering for the clock and data line A read or write transaction is determined by the least significant bit (R/W) of the first byte transferred. Write accesses require a 3-byte transfer. The first byte is the slave address with the R/W bit LOW, the second byte contains the register address, and the third byte is the write data. Read access requires a 4-byte transfer since data transfer direction can not change after receipt of the slave address byte. The first byte is the slave address with the R/W bit LOW, the second byte contains the register address, the third byte is a repeated slave address with the R/W bit HIGH, and the fourth byte is the read data. If the transaction is a write, the data will be latched into the appropriate register during the acknowledge of the third byte. All transactions to or from the device complete during the acknowledge of the third byte allowing the user to immediately initiate another transfer to the device. Sequential read or write transactions are allowed and are extensions of the above protocol with additional data bytes added to the end of the transaction. All sequential transactions cause the internal address to increment by one, regardless of the register address. 2.2 Control Registers The VSC056 device contains six groups of control registers. Each group supports a specific function within the device as follows: ● ● ● the first group is the port data registers the second group is the data direction registers the third group contains special bit control features 11 of 134 Revision 4.1 January 2008 VSC056 Data Sheet ● ● ● the fourth group supports the port bypass control function the fifth group supports fan speed monitoring the sixth group supports pulse-width modulated fan speed control The VSC056 device contains 164 registers to support all required functions. In normal I/O operation, each 8-bit group of I/O pins are controlled by a pair of registers, Port Data and Data Direction. The use of these pairs of registers allows each I/O line to be individually configured as an input with internal pull-up, output or open-drain output with internal pull-up. The bit control features are enabled through a separate register for each I/O pin. The Bit Control registers allow the user to independently configure each I/O pin to enable one of the special control features, as well as to control Port Data and Data Direction (which are shadowed copies of the standard control bits found in the Port Data and Data Direction registers). Each I/O pin that has been configured as an input can also be configured to assert the open-drain interrupt pin when a rising edge, a falling edge, or either edge is detected on the I/O pin. An Interrupt Status register provides the user with a binary indication of which I/O pin is the source of the current interrupt. Each I/O pin that is configured as an output can automatically generate one of seven selectable flashing rates, which can be driven in an open source or open drain mode. Additionally, two of the standard flash rates can be modified as well as eight dedicated programmable circuits to generate user defined pulse trains for unique flashing sequences. By providing all I/O control capability in a single register, the user can control the operation of the I/O on a pin-by-pin basis. Two additional bits in the odd-numbered bit control registers of each port can configure the pin as an output, which follows the corresponding even-numbered input of each port. As an example, P0.0 becomes the input source of P0.1, which would be programmed as an output operating in one of the three available modes. The outputs can be configured as totem pole, open-drain or open-source drive, allowing a closer approximation of the input driver. The Port Bypass registers control the operation of a selected group of I/O lines, which can be dedicated to support various combinations of individual PBC/CRU/SDU functions and integrated solutions. Enabling port bypass control causes the normal or bit control register settings to be overridden. Any further changes to the affected registers have no effect. Each Port Bypass Control register automatically configures the I/O lines to support a Force Bypass output and a Signal Detected input. The Fan Speed registers control the operation of eight programmable inputs that can be used to monitor signals from fans equipped with tachometer outputs. Enabling fan speed control causes the normal or bit control register settings to be overridden. Any further changes to the affected registers have no effect. Each group of three registers provides the capability to enable the function, to establish a user-defined RPM overflow value that indicates a failure, and to determine the current RPM value of the fan. The digital filters on the fan speed inputs can be enabled to increase the normal 100 ns to 200 ns filter to 400 ns to 500 ns. The Pulse-Width Modulation Control registers enable internal logic to provide duty cycles of 0% to 100% in 3% increments at default frequencies of 26 kHz, 52 kHz, and 104 kHz. Optionally, the PWM outputs can be programmed for three additional frequency ranges of 5.2 kHz, 10.4 kHz, and 20.8 kHz or 1.04 kHz 2.08 kHz, and 4.16 kHz or 208 Hz, 416 Hz and 833 Hz. These outputs can vary the speed of up to eight fans through the use of external drivers and power MOSFETs or pulse-width to voltage converters. They can also be used to support other pulse-width modulated requirements within the system. 12 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 2.3 I/O Logic Each general-purpose 5-V tolerant I/O pin is controlled by a set of registers in the Control register block. The I/O supports a high current drive output buffer that can be configured as a totem pole or open-drain driver. The input section of the I/O supports TTL signaling and includes an internal weak pull-up device. This allows unused I/O pins to be left unconnected without high-current drain issues. The port bypass control I/O pins, which are shared with Port 3, Port 4, Port 5, and Port 6, are generated using the same buffer logic as the other ports. When enabled in Port Bypass Control mode, internal logic overrides the existing configuration, with each I/O pin dedicated to the specific port bypass function. All I/O lines default as inputs with the weak internal pull-up enabled. 2.4 Clock Generator Clock generation for the device is composed of an internal oscillator, divider circuits, and a distribution network. It supports nominal clock frequencies of: ● ● ● ● ● ● ● ● 8.0 MHz 8.33 MHz 8.854 MHz 10.0 MHz 33.33 MHz 40.0 MHz 50.0 MHz 53.125 MHz The three CKSEL inputs select one of the eight available fixed clock frequencies. The internal lowfrequency clock (8.0 MHz to 12.5 MHz) is used for filtering incoming serial interface signals and interrupt sources, as well as for clocking the slave state machine. Divided clocks provide the source for LED flash rate generators. The oscillator provides a stable clock source for the device and requires the use of an offchip crystal with a frequency of 8.0 MHz, 8.33 MHz, 8.854 MHz, or 10.0 MHz and related passive components or external clock source. The available fixed clock rates have been selected to allow the use of other system clocks which may be available as well as low-cost crystals. The following table describes the CKSEL settings for the available fixed input clocks and the associated divider value. Table 1. CKSEL Settings CKSEL2 VSS VSS VSS VSS VDD VDD VDD VDD CKSEL1 VSS VSS VDD VDD VSS VSS VDD VDD CKSEL0 VSS VDD VSS VDD VSS VDD VSS VDD Input Clock 10.0 MHz 8.33 MHz 8.854 MHz 8.0 MHz 40.0 MHz 33.33 MHz 53.125 MHz 50.0 MHz Divider N/A N/A N/A N/A ÷4 ÷4 ÷6 ÷6 Internal Clock 10.0 MHz 8.33 MHz 8.854 MHz 8.0 MHz 10.0 MHz 8.33 MHz 8.854 MHz 8.33 MHz 13 of 134 Revision 4.1 January 2008 VSC056 Data Sheet The VSC056 device can operate at frequencies other than those listed in the above table and maintain accurate fan speed and LED control frequencies, as well as continue to meet both the Standard mode (100 kHz) and Fast mode (400 kHz) serial interface timings. Frequencies from 8.0 MHz to 12.5 MHz and 32.0 MHz to 75.0 MHz are allowable as long as they meet the AC timing requirements. For information on AC timing requirements, see “AC Characteristics,” page 119. The Clock Divider Control Register (CDC), located at FEh, can be programmed to override the divider value selected by the CKSEL input pins and adjust the divided clock source used for the fan speed and LED control logic. The pulse-width modulated outputs are not controlled by this logic and can vary based on the input frequency. For examples of various frequency settings, based on both the CKSEL inputs and the appropriate CDC register value, see“FEh: Clock Divider Control (CDC),” page 113. Logic within the VSC056 synchronizes the divided clocks between devices attached to the same two-wire serial bus with no more than 200 ns of skew when the fixed divider frequencies are used. Multiple devices can then be used to drive different LEDs at the same frequency, providing a synchronized visible indication. Devices attached to different two-wire serial busses can be synchronized by enabling the SYNC# pin. This pin, which is connected to the SYNC# pin of all VSC056 devices in the system, provides a sync pulse based on a programmable delay that is greater than the slowest selected LED flash rate. For more information about the programmable capabilities of this feature, see “FDh: Clock Select Control (CSC),” page 111. 2.5 Power-on Reset Power-on reset (POR) is accomplished by the use of an internal POR cell. The external RESET# pin provides the ability to reset the two-wire serial interface core, allowing for easy recovery of the two-wire serial bus after a warm restart or at any time deemed appropriate within the system. If the external RESET# pin is used, it can be driven by a power supply supervisor circuit, a reset pulse sourced from another device, or a simple circuit composed of a resistor, a capacitor, and a diode. The external reset source does not have to be synchronous to the VSC056 clock input. If the external resistor-capacitor-diode circuit is used, the components selected must be able to provide a valid LOW to HIGH transition after VDD is stable. If the RESET# pin is not used, it must be connected to VDD. After power on, the serial interface state machine always returns an idle state while waiting for a START condition to appear on the SCL and SDA pins. A proper power-on reset sequence clears the serial interface state machine, the clock generators, the control registers, the I/O control logic, and the port bypass control logic. The divided clocks used for LED flash rate generation are also in a known state. Regardless of the effectiveness of the power-on reset mechanism, it is strongly recommended that the control registers and the I/O control logic be cleared through the Soft Reset register bit. This can be accomplished by writing a 80h to the BCT Register (FCh), followed immediately by a two-wire STOP condition. This bit is self-resetting and does not require further attention. 14 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3 Registers This section contains descriptions for the device-specific control registers. All register locations are fixed within the device and are mapped for easy access, as well as for future enhancements. 3.1 Control Registers The control register section is separated into three sub-sections: a register map, an address map, and bit level descriptions of all registers. The register map lists all registers by operating address. The address map shows the relative layout of all control registers. Although all registers can be accessed at any time and no register function interferes with the operation of the serial interface, changing register bits does have an immediate effect on the respective I/O lines. The following table provides the mapping of the registers. Table 2. Register Map Data Memory Address 00h 01h 02h 03h 04h 05h 06h 07h 10h 11h 12h 13h 14h 15h 16h 17h 20h 21h 22h 23h 24h 25h 26h 27h 28h Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Label GPD0 GPD1 GPD2 GPD3 GPD4 GPD5 GPD6 GPD7 DDP0 DDP1 DDP2 DDP3 DDP4 DDP5 DDP6 DDP7 PBC0 PBC1 PBC2 PBC3 PBC4 PBC5 PBC6 PBC7 PBC8 Description General-Purpose I/O Port 0 Data Register General-Purpose I/O Port 1 Data Register General-Purpose I/O Port 2 Data Register General-Purpose I/O Port 3 Data Register General-Purpose I/O Port 4 Data Register General-Purpose I/O Port 5 Data Register General-Purpose I/O Port 6 Data Register General-Purpose I/O Port 7 Data Register I/O Port 0 Data Direction Register I/O Port 1 Data Direction Register I/O Port 2 Data Direction Register I/O Port 3 Data Direction Register I/O Port 4 Data Direction Register I/O Port 5 Data Direction Register I/O Port 6 Data Direction Register I/O Port 7 Data Direction Register Port Bypass Control 0 Register Port Bypass Control 1 Register Port Bypass Control 2 Register Port Bypass Control 3 Register Port Bypass Control 4 Register Port Bypass Control 5 Register Port Bypass Control 6 Register Port Bypass Control 7 Register Port Bypass Control 8 Register 15 of 134 Revision 4.1 January 2008 VSC056 Data Sheet Table 2. Register Map (continued) Data Memory Address 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 34h 35h 36h 38h 39h 3Ah 3Ch 3Dh 3Eh 40h 41h 42h 44h 45h 46h 48h 49h 4Ah 4Ch 4Dh 4Eh 70h 71h 72h 73h 74h 75h 76h 77h 78h Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R R/W R/W R R/W R/W R R/W R/W R R/W R/W R R/W R/W R R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W Label PBC9 PBC10 PBC11 PBC12 PBC13 PBC14 PBC15 FSC0 FSCO0 FSCC0 FSC1 FSCO1 FSCC1 FSC2 FSCO2 FSCC2 FSC3 FSCO3 FSCC3 FSC4 FSCO4 FSCC4 FSC5 FSCO5 FSCC5 FSC6 FSCO6 FSCC6 FSC7 FSCO7 FSCC7 PTC00 PTC01 PTC10 PTC11 PTC20 PTC21 PTC30 PTC31 PTC40 Description Port Bypass Control 9 Register Port Bypass Control 10 Register Port Bypass Control 11 Register Port Bypass Control 12 Register Port Bypass Control 13 Register Port Bypass Control 14 Register Port Bypass Control 15 Register Fan Speed Control 0 Register Fan Speed Count Overflow 0 Register Fan Speed Current Count 0 Register Fan Speed Control 1 Register Fan Speed Count Overflow 1 Register Fan Speed Current Count 1 Register Fan Speed Control 2 Register Fan Speed Count Overflow 2 Register Fan Speed Current Count 2 Register Fan Speed Control 3 Register Fan Speed Count Overflow 3 Register Fan Speed Current Count 3 Register Fan Speed Control 4 Register Fan Speed Count Overflow 4 Register Fan Speed Current Count 4 Register Fan Speed Control 5 Register Fan Speed Count Overflow 5 Register Fan Speed Current Count 5 Register Fan Speed Control 6 Register Fan Speed Count Overflow 6 Register Fan Speed Current Count 6 Register Fan Speed Control 7 Register Fan Speed Count Overflow 7 Register Fan Speed Current Count 7 Register Pulse Train 0 Control 0 Register Pulse Train 0 Control 1 Register Pulse Train 1 Control 0 Register Pulse Train 1 Control 1 Register Pulse Train 2 Control 0 Register Pulse Train 2 Control 1 Register Pulse Train 3 Control 0 Register Pulse Train 3 Control 1 Register Pulse Train 4 Control 0 Register 16 of 134 Revision 4.1 January 2008 VSC056 Data Sheet Table 2. Register Map (continued) Data Memory Address 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ch 8Dh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Label PTC41 PTC50 PTC51 PTC60 PTC61 PTC70 PTC71 BCP00 BCP01 BCP02 BCP03 BCP04 BCP05 BCP06 BCP07 PTC80 PTC81 PTC90 PTC91 BCP10 BCP11 BCP12 BCP13 BCP14 BCP15 BCP16 BCP17 PWMC0 PWMC1 PWMC2 PWMC3 PWMC4 PWMC5 PWMC6 PWMC7 BCP20 BCP21 BCP22 BCP23 BCP24 Description Pulse Train 4 Control 1 Register Pulse Train 5 Control 0 Register Pulse Train 5 Control 1 Register Pulse Train 6 Control 0 Register Pulse Train 6 Control 1 Register Pulse Train 7 Control 0 Register Pulse Train 7 Control 1 Register Bit Control Port 0 - Bit 0 Register Bit Control Port 0 - Bit 1 Register Bit Control Port 0 - Bit 2 Register Bit Control Port 0 - Bit 3 Register Bit Control Port 0 - Bit 4 Register Bit Control Port 0 - Bit 5 Register Bit Control Port 0 - Bit 6 Register Bit Control Port 0 - Bit 7 Register Pulse Train 8 Control 0 Register Pulse Train 8 Control 1 Register Pulse Train 9 Control 0 Register Pulse Train 9 Control 1 Register Bit Control Port 1 - Bit 0 Register Bit Control Port 1 - Bit 1 Register Bit Control Port 1 - Bit 2 Register Bit Control Port 1 - Bit 3 Register Bit Control Port 1 - Bit 4 Register Bit Control Port 1 - Bit 5 Register Bit Control Port 1 - Bit 6 Register Bit Control Port 1 - Bit 7 Register Pulse-Width Modulation Control 0 Register Pulse-Width Modulation Control 1 Register Pulse-Width Modulation Control 2 Register Pulse-Width Modulation Control 3 Register Pulse-Width Modulation Control 4 Register Pulse-Width Modulation Control 5 Register Pulse-Width Modulation Control 6 Register Pulse-Width Modulation Control 7 Register Bit Control Port 2 - Bit 0 Register Bit Control Port 2 - Bit 1 Register Bit Control Port 2 - Bit 2 Register Bit Control Port 2 - Bit 3 Register Bit Control Port 2 - Bit 4 Register 17 of 134 Revision 4.1 January 2008 VSC056 Data Sheet Table 2. Register Map (continued) Data Memory Address A5h A6h A7h B0h B1h B2h B3h B4h B5h B6h B7h C0h C1h C2h C3h C4h C5h C6h C7h CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h E0h E1h E2h E3h E4h E5h E6h E7h E8h Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Label BCP25 BCP26 BCP27 BCP30 BCP31 BCP32 BCP33 BCP34 BCP35 BCP36 BCP37 BCP40 BCP41 BCP42 BCP43 BCP44 BCP45 BCP46 BCP47 GPTC0 GPTC1 GPTC2 GPTE BCP50 BCP51 BCP52 BCP53 BCP54 BCP55 BCP56 BCP57 BCP60 BCP61 BCP62 BCP63 BCP64 BCP65 BCP66 BCP67 MICD Description Bit Control Port 2 - Bit 5 Register Bit Control Port 2 - Bit 6 Register Bit Control Port 2 - Bit 7 Register Bit Control Port 3 - Bit 0 Register Bit Control Port 3 - Bit 1 Register Bit Control Port 3 - Bit 2 Register Bit Control Port 3 - Bit 3 Register Bit Control Port 3 - Bit 4 Register Bit Control Port 3 - Bit 5 Register Bit Control Port 3 - Bit 6 Register Bit Control Port 3 - Bit 7 Register Bit Control Port 4 - Bit 0 Register Bit Control Port 4 - Bit 1 Register Bit Control Port 4 - Bit 2 Register Bit Control Port 4 - Bit 3 Register Bit Control Port 4 - Bit 4 Register Bit Control Port 4 - Bit 5 Register Bit Control Port 4 - Bit 6 Register Bit Control Port 4 - Bit 7 Register General-Purpose Timer Count 0 Register General-Purpose Timer Count 1 Register General-Purpose Timer Count 2 Register General-Purpose Timer Enable Register Bit Control Port 5 - Bit 0 Register Bit Control Port 5 - Bit 1 Register Bit Control Port 5 - Bit 2 Register Bit Control Port 5 - Bit 3 Register Bit Control Port 5 - Bit 4 Register Bit Control Port 5 - Bit 5 Register Bit Control Port 5 - Bit 6 Register Bit Control Port 5 - Bit 7 Register Bit Control Port 6 - Bit 0 Register Bit Control Port 6 - Bit 1 Register Bit Control Port 6 - Bit 2 Register Bit Control Port 6 - Bit 3 Register Bit Control Port 6 - Bit 4 Register Bit Control Port 6 - Bit 5 Register Bit Control Port 6 - Bit 6 Register Bit Control Port 6 - Bit 7 Register Master Interface Clock Divider Register 18 of 134 Revision 4.1 January 2008 VSC056 Data Sheet Table 2. Register Map (continued) Data Memory Address E9h EAh EBh ECh EDh EEh F0h F1h F2h F3h F4h F5h F6h F7h F8h FCh FDh FEh FFh Access R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Label MIPS MID MIC MILC MIS MIRD BCP70 BCP71 BCP72 BCP73 BCP74 BCP75 BCP76 BCP77 BCIS BCT CSC CDC VER Description Master Interface Port Select Register Master Interface Data Register Master Interface Command Register Master Interface Low-Level Control Register Master Interface Status Register Master Interface Read Data Register Bit Control Port 7 - Bit 0 Register Bit Control Port 7 - Bit 1 Register Bit Control Port 7 - Bit 2 Register Bit Control Port 7 - Bit 3 Register Bit Control Port 7 - Bit 4 Register Bit Control Port 7 - Bit 5 Register Bit Control Port 7 - Bit 6 Register Bit Control Port 7 - Bit 7 Register Backplane Controller Interrupt Status Register Backplane Controller Test Register Clock Select Control Register Clock Divider Control Register Backplane Controller Version Register The following table provides the mapping of the register sets by address. Table 3. Address Map 11b GPD3 GPD7 reserved DDP3 DDP7 reserved PBC3 PBC7 PBC11 PBC15 reserved reserved reserved reserved reserved reserved reserved 10b GPD2 GPD6 reserved DDP2 DDP6 reserved PBC2 PBC6 PBC10 PBC14 FSCC0 FSCC1 FSCC2 FSCC3 FSCC4 FSCC5 FSCC6 01b GPD1 GPD5 reserved DDP1 DDP5 reserved PBC1 PBC5 PBC9 PBC13 FSCO0 FSCO1 FSCO2 FSCO3 FSCO4 FSCO5 FSCO6 00b GPD0 GPD4 reserved DDP0 DDP4 reserved PBC0 PBC4 PBC8 PBC12 FSC0 FSC1 FSC2 FSC3 FSC4 FSC5 FSC6 Address 00h 04h 08h-0Ch 10h 14h 18h-1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h 19 of 134 Revision 4.1 January 2008 VSC056 Data Sheet Table 3. Address Map (continued) 11b reserved reserved PTC11 PTC31 PTC51 PTC71 BCP03 BCP07 reserved reserved BCP13 BCP17 PWMC3 PWMC7 BCP23 BCP27 reserved BCP33 BCP37 reserved BCP43 BCP47 reserved GPTE BCP53 BCP57 reserved BCP63 BCP67 MIC reserved BCP73 BCP77 reserved VER 10b FSCC7 reserved PTC10 PTC30 PTC50 PTC70 BCP02 BCP06 reserved reserved BCP12 BCP16 PWMC2 PWMC6 BCP22 BCP26 reserved BCP32 BCP36 reserved BCP42 BCP46 reserved GPTC2 BCP52 BCP56 reserved BCP62 BCP66 MID MIRD BCP72 BCP76 reserved CDC 01b FSCO7 reserved PTC01 PTC21 PTC41 PTC51 BCP01 BCP05 PTC41 PTC51 BCP11 BCP15 PWMC1 PWMC5 BCP21 BCP25 reserved BCP31 BCP35 reserved BCP41 BCP45 reserved GPTC1 BCP51 BCP55 reserved BCP61 BCP65 MIPS MIS BCP71 BCP75 reserved CSC 00b FSC7 reserved PTC00 PTC20 PTC40 PTC50 BCP00 BCP04 PTC40 PTC50 BCP10 BCP14 PWMC0 PWMC4 BCP20 BCP24 reserved BCP30 BCP34 reserved BCP40 BCP44 reserved GPTC0 BCP50 BCP54 reserved BCP60 BCP64 MICD MILC BCP70 BCP74 BCIS BCT Address 4Ch 50h-6Ch 70h 74h 78h 7Ch 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h-ACh B0h B4h B8h-BCh C0h C4h C8h CCh D0h D4h D8h-DCh E0h E4h E8h ECh F0h F4h F8h FCh 20 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2 Control Register Definitions The control register definitions provides a bit-level description of all register bits, including power on and default values. The terms set and assert refer to bits that are programmed to a binary 1. The terms reset, deassert, and clear refer to bits that are programmed to a binary 0. Reserved bits are represented by RES and always return an unknown value. These bits should be masked. Bits that are reserved should never be set to a binary 1, because these bits may be defined in future versions of the device. 3.2.1 00h: General-Purpose I/O Port 0 Data (GPD0) The following table shows the bit assignments for the General-Purpose I/O Port 0 Data register. Register Name: Address: Reset Value: Bit 7:0 Bit Label GPD0.7–0 GPD0 00h XXXX_XXXXb Access R/W Description General-Purpose Data When the I/O pin is enabled as an output, writing these bits determines the data value that will be present on the corresponding I/O pin. If the I/O pin is enabled as an input, reading these register bits represent the current voltage applied to the pin. At no time do the bits directly represent the value latched into the data register. If a pin is enabled as an input and there is no signal applied, weak internal pull-up resistors hold the pin at a binary 1. After a reset or power on, the register bits are set to a binary 1, however, the value returned from a register read is the level applied to the pin since each pin is an input by default. GPD Read Data Filter GPD Write Data D CK Q I/O Port DD Write Data D CK Q DD Read Data Figure 3. I/O Port Block Diagram 21 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.2 01h: General-Purpose I/O Port 1 Data (GPD1) The following table shows the bit assignments for the General-Purpose I/O Port 1 Data register. Register Name: Address: Reset Value: Bit 7:0 Bit Label GPD1.7-0 GPD1 01h XXXX_XXXXb Access Description R/W General-Purpose Data When the I/O pin is enabled as an output, writing these bits determines the data value that will be present on the corresponding I/O pin. If the I/O pin is enabled as an input, reading these register bits represents the current voltage applied to the pin. At no time do the bits directly represent the value latched into the data register If a pin is enabled as an input and there is no signal applied, weak internal pull-up resistors hold the pin at a binary 1. After a reset or power on, the register bits are set to a binary 1, however, the value returned from a register read is the level applied to the pin since each pin is an input by default. 3.2.3 02h: General-Purpose I/O Port 2 Data (GPD2) The following table shows the bit assignments for the General-Purpose I/O Port 2 Data register. Register Name: Address: Reset Value: Bit 7:0 Bit Label GPD2.7-0 GPD2 02h XXXX_XXXXb Access Description R/W General-Purpose Data When the I/O pin is enabled as an output, writing these bits determines the data value that will be present on the corresponding I/O pin. If the I/O pin is enabled as an input, reading these register bits represents the current voltage applied to the pin. At no time do the bits directly represent the value latched into the data register. If a pin is enabled as an input and there is no signal applied, weak internal pull-up resistors hold the pin at a binary 1. After a reset or power on, the register bits are set to a binary 1, however, the value returned from a register read is the level applied to the pin since each pin is an input by default. 22 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.4 03h: General-Purpose I/O Port 3 Data (GPD3) The following table shows the bit assignments for the General-Purpose I/O Port 3 Data register. Control of the individual I/O pins in this register can be overridden by the PBC0, PBC1, PBC2, and PBC3 registers when port bypass control is required. Register Name: Address: Reset Value: Bit 7:0 Bit Label GPD3.7-0 GPD3 03h XXXX_XXXXb Access Description R/W General-Purpose Data When the I/O pin is enabled as an output, writing these bits determines the data value that will be present on the corresponding I/O pin. If the I/O pin is enabled as an input, reading these register bits represents the current voltage applied to the pin. At no time do the bits directly represent the value latched into the data register. If a pin is enabled as an input and there is no signal applied, weak internal pullup resistors hold the pin at a binary 1. After a reset or power on, the register bits are set to a binary 1, but the value returned from a register read is the level applied to the pin since each pin is an input by default. 3.2.5 04h: General-Purpose I/O Port 4 Data (GPD4) The following table shows the bit assignments for the General-Purpose I/O Port 4 Data register. Control of the individual I/O pins in this register can be overridden by the PBC4, PBC5, PBC6, and PBC7 registers when port bypass control is required. Register Name: Address: Reset Value: Bit 7:0 Bit Label GPD4.7-0 GPD4 04h XXXX_XXXXb Access R/W Description General-Purpose Data When the I/O pin is enabled as an output, writing these bits determines the data value that will be present on the corresponding I/O pin. If the I/O pin is enabled as an input, reading these register bits represents the current voltage applied to the pin. At no time do the bits directly represent the value latched into the data register. If a pin is enabled as an input and there is no signal applied, weak internal pullup resistors hold the pin at a binary 1. After a reset or power on, the register bits are set to a binary 1, but the value returned from a register read is the level applied to the pin since each pin is an input by default. 23 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.6 05h: General-Purpose I/O Port 5 Data (GPD5) The following table shows the bit assignments for the General-Purpose I/O Port 5 Data register. Control of the individual I/O pins in this register can be overridden by the PBC8, PBC9, PBC10, and PBC11 registers when port bypass control is required. Register Name: Address: Reset Value: Bit 7:0 Bit Label GPD5.7-0 GPD5 05h XXXX_XXXXb Access R/W Description General-Purpose Data When the I/O pin is enabled as an output, writing these bits determines the data value that will be present on the corresponding I/O pin. If the I/O pin is enabled as an input, reading these register bits represents the current voltage applied to the pin. At no time do the bits directly represent the value latched into the data register. If a pin is enabled as an input and there is no signal applied, weak internal pullup resistors hold the pin at a binary 1. After a reset or power on, the register bits are set to a binary 1, but the value returned from a register read is the level applied to the pin since each pin is an input by default. 3.2.7 06h: General-Purpose I/O Port 6 Data (GPD6) The following table shows the bit assignments for the General-Purpose I/O Port 6 Data register. Control of the individual I/O pins in this register can be overridden by the PBC12, PBC13, PBC14, and PBC15 registers when port bypass control is required. Register Name: Address: Reset Value: Bit 7:0 Bit Label GPD6.7-0 GPD6 06h XXXX_XXXXb Access R/W Description General-Purpose Data When the I/O pin has been enabled as an output, writing these bits determines the data value that will be present on the corresponding I/O pin. If the I/O pin has been enabled as an input, reading these register bits represents the current voltage applied to the pin. At no time do the bits directly represent the value latched into the data register. If a pin is enabled as an input and there is no signal applied, weak internal pull-up resistors hold the pin at a binary 1. After a reset or power on, the register bits are set to a binary 1, however, the value returned from a register read is the level applied to the pin since each pin is an input by default. 24 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.8 07h: General-Purpose I/O Port 7 Data (GPD7) The following table shows the bit assignments for the General-Purpose I/O Port 7 Data register. Register Name: Address: Reset Value: Bit 7:0 Bit Label GPD7.7-0 GPD7 07h XXXX_XXXXb Access Description R/W General-Purpose Data When the I/O pin is enabled as an output, writing these bits determines the data value that will be present on the corresponding I/O pin. If the I/O pin is enabled as an input, reading these register bits represents the current voltage applied to the pin. At no time do the bits directly represent the value latched into the data register. If a pin is enabled as an input and there is no signal applied, weak internal pullup resistors hold the pin at a binary 1. After a reset or power on, the register bits are set to a binary 1, however, the value returned from a register read is the level applied to the pin since each pin is an input by default. 3.2.9 10h: I/O Port 0 Data Direction (DDP0) The following table shows the bit assignments for the I/O Port 0 Data Direction register. Register Name: Address: Reset Value: Bit 7:0 Bit Label DDP0.7-0 DDP0 10h 1111_1111b Access R/W Description Data Direction These bits determine the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. To implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. After a reset or power on, these bits are set to a binary 1, enabling the I/O as an input with weak pull-up. 25 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.10 11h: I/O Port 1 Data Direction (DDP1) The following table shows the bit assignments for the I/O Port 1 Data Direction register. Register Name: Address: Reset Value: Bit 7:0 Bit Label DDP1.7-0 DDP1 11h 1111_1111b Access Description R/W Data Direction These bits determine the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. To implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. After a reset or power on, these bits are set to a binary 1, enabling the I/O as an input with weak pull-up. 3.2.11 12h: I/O Port 2 Data Direction (DDP2) The following table shows the bit assignments for the I/O Port 2 Data Direction register. Register Name: Address: Reset Value: Bit 7:0 Bit Label DDP2.7-0 DDP2 12h 1111_1111b Access Description R/W Data Direction These bits determine the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. To implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. After a reset or power on, these bits are set to a binary 1, enabling the I/O as an input with weak pull-up. 26 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.12 13h: I/O Port 3 Data Direction (DDP3) The following table shows the bit assignments for the I/O Port 3 Data Direction register. Control of the individual I/O pins in this register can be overridden by the PBC0, PBC1, PBC2, and PBC3 registers when port bypass control is required. Register Name: Address: Reset Value: Bit 7:0 Bit Label DDP3.7-0 DDP3 13h 1111_1111b Access Description R/W Data Direction These bits determine the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. To implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. After a reset or power on, these bits are set to a binary 1, enabling the I/O as an input with weak pull-up. 3.2.13 14h: I/O Port 4 Data Direction (DDP4) The following table shows the bit assignments for the I/O Port 4 Data Direction register. Control of the individual I/O pins in this register can be overridden by the PBC4, PBC5, PBC6, and PBC7 registers when port bypass control is required. Register Name: Address: Reset Value: Bit 7:0 Bit Label DDP4.7-0 DDP4 14h 1111_1111b Access R/W Description Data Direction These bits determine the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. To implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. After a reset or power on, these bits are set to a binary 1, enabling the I/O as an input with weak pull-up. 27 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.14 15h: I/O Port 5 Data Direction (DDP5) The following table shows the bit assignments for the I/O Port 5 Data Direction register. Control of the individual I/O pins in this register can be overridden by the PBC8, PBC9, PBC10, and PBC11 registers when port bypass control is required. Register Name: Address: Reset Value: Bit 7:0 Bit Label DDP5.7-0 DDP5 15h 1111_1111b Access R/W Description Data Direction These bits determine the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. To implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. After a reset or power on, these bits are set to a binary 1, enabling the I/O as an input with weak pull-up. 3.2.15 16h: I/O Port 6 Data Direction (DDP6) The following table shows the bit assignments for the I/O Port 6 Data Direction register. Control of the individual I/O pins in this register can be overridden by the PBC12, PBC13, PBC14, and PBC15 registers when port bypass control is required. Register Name: Address: Reset Value: Bit 7:0 Bit Label DDP6.7-0 DDP6 16h 1111_1111b Access R/W Description Data Direction These bits determine the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. To implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. After a reset or power on, these bits are set to a binary 1, enabling the I/O as an input with weak pull-up. 28 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.16 17h: I/O Port 7 Data Direction (DDP7) The following table shows the bit assignments for the I/O Port 7 Data Direction register. Register Name: Address: Reset Value: Bit 7:0 Bit Label DDP7.7-0 DDP7 17h 1111_1111b Access R/W Description Data Direction These bits determine the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. To implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. After a reset or power on, these bits are set to a binary 1, enabling the I/O as an input with weak pull-up. 29 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.17 20h: Port Bypass Control 0 (PBC0) The following table shows the bit assignments for the Port Bypass Control 0 register. This register affects the P3.1 and P3.0 pins. Register Name: Address: Reset Value: Bit 7 Bit Label PBCEN PBC0 20h 00XX_XX1Xb Access R/W Description Port Bypass Control Enable When this bit is set, P3.1 and P3.0 are automatically configured as a Force Bypass (FB) output pin and a Signal Detected (SD) input pin. Configurations for these I/O pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P3.1 and P3.0. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input generates an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 1 RES FB R R/W Reserved. Force Bypass This bit controls the P3.1 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in Normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in Bypass mode. This register bit is automatically cleared when the synchronized and filtered P3.0 input is LOW, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the P3.1 output. Note: Because all I/O pins on the device power up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. The default state of the I/O can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. After the default state is determined, write the default value to the FB bit of this register and set the PBCEN bit to ensure that the port bypass control functions are enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains HIGH. Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P3.0 I/O pin, which has been connected to the signal detected output of a PBC/ CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal. 0 SD R/W 30 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.18 21h: Port Bypass Control 1 (PBC1) The following table shows the bit assignments for the Port Bypass Control 1 register. This register functions the same as the Port Bypass Control 0 register except it affects the P3.3 and P3.2 pins. Register Name: Address: Reset Value: Bit 7 Bit Label PBCEN PBC1 21h 00XX_XX1Xb Access R/W Description Port Bypass Control Enable When this bit is set, P3.3 and P3.2 are automatically configured as an FB output pin and an SD input pin. Configurations for these I/O pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P3.3 and P3.2. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input generates an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 1 RES FB R R/W Reserved. Force Bypass This bit controls the P3.2 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in Normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in Bypass mode. This register bit is automatically cleared when the synchronized and filtered P3.2 input is LOW, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the P3.3 output. Note: Because all I/O pins on the device power up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. The default state of the I/O can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. After the default state is determined, to ensure that the port bypass control functions are enabled correctly, write the default value to the FB bit of this register and set the PBCEN bit. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains HIGH. Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P3.2 I/O pin, which is connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal. 0 SD R/W 31 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.19 22h: Port Bypass Control 2 (PBC2) The following table shows the bit assignments for the Port Bypass Control 2 register. This register functions the same as the Port Bypass Control 0 register except it affects the P3.5 and P3.4 pins. Register Name: Address: Reset Value: Bit 7 Bit Label PBCEN PBC2 22h 00XX_XX1Xb Access R/W Description Port Bypass Control Enable When this bit is set, P3.5 and P3.4 are automatically configured as an FB output pin and an SD input pin. Configurations for these I/O pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P3.5 and P3.4. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input generates an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 1 RES FB R R/W Reserved. Force Bypass This bit controls the P3.5 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in Normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in Bypass mode. This register bit is automatically cleared when the synchronized and filtered P3.4 input is LOW, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the P3.5 output. Note: Because all I/O pins on the device power up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. The default state of the I/O can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. After the default state is determined, write the default value to the FB bit of this register and set the PBCEN bit to ensure that the port bypass control functions are enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains HIGH. Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P3.4 I/O pin, which is connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal. 0 SD R/W 32 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.20 23h: Port Bypass Control 3 (PBC3) The following table shows the bit assignments for the Port Bypass Control 3 register. This register functions the same as the Port Bypass Control 0 register except it affects the P3.7 and P3.6 pins. Register Name: Address: Reset Value: Bit 7 Bit Label PBCEN PBC3 23h 00XX_XX1Xb Access R/W Description Port Bypass Control Enable When this bit is set, P3.7 and P3.6 are automatically configured as an FB output pin and an SD input pin. Configurations for these I/O pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P3.7 and P3.6. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input generates an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 1 RES FB R R/W Reserved. Force Bypass This bit controls the P3.7 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in Normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in Bypass mode. This register bit is automatically cleared when the synchronized and filtered P3.6 input is LOW, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the P3.7 output. Note: Because all I/O pins on the device power up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. The default state of the I/O can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. After the default state is determined, write the default value to the FB bit of this register and set the PBCEN bit to ensure that the port bypass control functions are enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains HIGH. Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P3.6 I/O pin, which is connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal. 0 SD R/W 33 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.21 24h: Port Bypass Control 4 (PBC4) The following table shows the bit assignments for the Port Bypass Control 4 register. This register functions the same as the Port Bypass Control 0 register except it affects the P4.1 and P4.0 pins. Register Name: Address: Reset Value: Bit 7 Bit Label PBCEN PBC4 24h 00XX_XX1Xb Access R/W Description Port Bypass Control Enable When this bit is set, P4.1 and P4.0 are automatically configured as an FB output pin and an SD input pin. Configurations for these I/O pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P4.1 and P4.0. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input generates an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 1 RES FB R R/W Reserved. Force Bypass This bit controls the P4.1 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in Normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in Bypass mode. This register bit is automatically cleared when the synchronized and filtered P4.0 input is LOW, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the P4.1 output. Note: Because all I/O pins on the device power up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. The default state of the I/O can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. After the default state is determined, write the default value to the FB bit of this register and set the PBCEN bit to ensure that the port bypass control functions are enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains HIGH. Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P4.0 I/O pin, which is connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal. 0 SD R/W 34 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.22 25h: Port Bypass Control 5 (PBC5) The following table shows the bit assignments for the Port Bypass Control 5 register. This register functions the same as the Port Bypass Control 0 register except it affects the P4.3 and P4.2 pins. Register Name: Address: Reset Value: Bit 7 Bit Label PBCEN PBC5 25h 00XX_XX1Xb Access R/W Description Port Bypass Control Enable When this bit is set, P4.3 and P4.2 are automatically configured as an FB output pin and an SD input pin. Configurations for these I/O pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P4.3 and P4.2. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input generates an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 1 RES FB R R/W Reserved. Force Bypass This bit controls the P4.3 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in Normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in Bypass mode. This register bit is automatically cleared when the synchronized and filtered P4.2 input is LOW, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the P4.3 output. Note: Because all I/O pins on the device power up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. The default state of the I/O can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. After the default state is determined, write the default value to the FB bit of this register and set the PBCEN bit to ensure that the port bypass control functions are enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains HIGH. Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P4.2 I/O pin, which is connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal. 0 SD R/W 35 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.23 26h: Port Bypass Control 6 (PBC6) The following table shows the bit assignments for the Port Bypass Control 6 register. This register functions the same as the Port Bypass Control 0 register except it affects the P4.5 and P4.4 pins. Register Name: Address: Reset Value: Bit 7 Bit Label PBCEN PBC6 26h 00XX_XX1Xb Access R/W Description Port Bypass Control Enable When this bit is set, P4.5 and P4.4 are automatically configured as an FB output pin and an SD input pin. Configurations for these I/O pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P4.5 and P4.4. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input generates an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 1 RES FB R R/W Reserved. Force Bypass This bit controls the P4.5 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in Normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in Bypass mode. This register bit is automatically cleared when the synchronized and filtered P4.4 input is LOW, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the P4.5 output. Note: Because all I/O pins on the device power up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. The default state of the I/O can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. After the default state is determined, write the default value to the FB bit of this register and set the PBCEN bit to ensure that the port bypass control functions are enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains HIGH. Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P4.4 I/O pin, which has been connected to the signal detected output of a PBC/ CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal. 0 SD R/W 36 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.24 27h: Port Bypass Control 7 (PBC7) The following table shows the bit assignments for the Port Bypass Control 7 register. This register functions the same as the Port Bypass Control 0 register except it affects the P4.7 and P4.6 pins. Register Name: Address: Reset Value: Bit 7 Bit Label PBCEN PBC7 27h 00XX_XX1Xb Access R/W Description Port Bypass Control Enable When this bit is set, P4.7 and P4.6 are automatically configured as an FB output pin and an SD input pin. Configurations for these I/O pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P4.7 and P4.6. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input generates an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 1 RES FB R R/W Reserved. Force Bypass This bit controls the P4.7 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in Normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in Bypass mode. This register bit is automatically cleared when the synchronized and filtered P4.6 input is LOW, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the P4.7 output. Note: Because all I/O pins on the device power up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. The default state of the I/O can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. After the default state is determined, write the default value to the FB bit of this register and set the PBCEN bit to ensure that the port bypass control functions are enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains HIGH. Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P4.6 I/O pin, which has been connected to the signal detected output of a PBC/ CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal. 0 SD R/W 37 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.25 28h: Port Bypass Control 8 (PBC8) The following table shows the bit assignments for the Port Bypass Control 8 register. This register functions the same as the Port Bypass Control 0 register except it affects the P5.1 and P5.0 pins. Register Name: Address: Reset Value: Bit 7 Bit Label PBCEN PBC8 28h 00XX_XX1Xb Access R/W Description Port Bypass Control Enable When this bit is set, P5.1 and P5.0 are automatically configured as an FB output pin and an SD input pin. Configurations for these I/O pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P5.1 and P5.0. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input generates an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 1 RES FB R R/W Reserved. Force Bypass This bit controls the P5.1 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in Normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in Bypass mode. This register bit is automatically cleared when the synchronized and filtered P5.0 input is LOW, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the P5.1 output. Note: Because all I/O pins on the device power up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. The default state of the I/O can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. After the default state is determined, write the default value to the FB bit of this register and set the PBCEN bit to ensure that the port bypass control functions are enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains HIGH. Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P5.0 I/O pin, which is connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal. 0 SD R/W 38 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.26 29h: Port Bypass Control 9 (PBC9) The following table shows the bit assignments for the Port Bypass Control 9 register. This register functions the same as the Port Bypass Control 0 register except it affects the P5.3 and P5.2 pins. Register Name: Address: Reset Value: Bit 7 Bit Label PBCEN PBC9 29h 00XX_XX1Xb Access R/W Description Port Bypass Control Enable When this bit is set, P5.3 and P5.2 are automatically configured as an FB output pin and an SD input pin. Configurations for these I/O pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P5.3 and P5.2. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input generates an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 1 RES FB R R/W Reserved. Force Bypass This bit controls the P5.3 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in Normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in Bypass mode. This register bit is automatically cleared when the synchronized and filtered P5.2 input is LOW, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the P5.3 output. Note: Because all I/O pins on the device power up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. The default state of the I/O can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. After the default state is determined, write the default value to the FB bit of this register and set the PBCEN bit to ensure that the port bypass control functions are enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains HIGH. Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P5.2 I/O pin, which is connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal. 0 SD R/W 39 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.27 2Ah: Port Bypass Control 10 (PBC10) The following table shows the bit assignments for the Port Bypass Control 10 register. This register functions the same as the Port Bypass Control 0 register except it affects the P5.5 and P5.4 pins. Register Name: Address: Reset Value: Bit 7 Bit Label PBCEN PBC10 2Ah 00XX_XX1Xb Access R/W Description Port Bypass Control Enable When this bit is set, P5.5 and P5.4 are automatically configured as an FB output pin and an SD input pin. Configurations for these I/O pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P5.5 and P5.4. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input generates an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 1 RES FB R R/W Reserved. Force Bypass This bit controls the P5.5 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in Normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in Bypass mode. This register bit is automatically cleared when the synchronized and filtered P5.4 input is LOW, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the P5.5 output. Note: Because all I/O pins on the device power up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. The default state of the I/O can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. After the default state is determined, write the default value to the FB bit of this register and set the PBCEN bit to ensure that the port bypass control functions are enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains HIGH. Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P5.4 I/O pin, which is connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal. 0 SD R/W 40 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.28 2Bh: Port Bypass Control 11 (PBC11) The following table shows the bit assignments for the Port Bypass Control 11 register. This register functions the same as the Port Bypass Control 0 register except it affects the P5.7 and P5.6 pins. Register Name: Address: Reset Value: Bit 7 Bit Label PBCEN PBC11 2Bh 00XX_XX1Xb Access R/W Description Port Bypass Control Enable When this bit is set, P5.7 and P5.6 are automatically configured as an FB output pin and an SD input pin. Configurations for these I/O pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P5.7 and P5.6. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input generates an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 1 RES FB R R/W Reserved. Force Bypass This bit controls the P5.7 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in Normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in Bypass mode. This register bit is automatically cleared when the synchronized and filtered P5.6 input is LOW, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the P5.7 output. Note: Because all I/O pins on the device power up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. The default state of the I/O can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. After the default state is determined, write the default value to the FB bit of this register and set the PBCEN bit to ensure that the port bypass control functions are enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains HIGH. Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P5.6 I/O pin, which has been connected to the signal detected output of a PBC/ CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal. 0 SD R/W 41 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.29 2Ch: Port Bypass Control 12 (PBC12) The following table shows the bit assignments for the Port Bypass Control 12 register. This register functions the same as the Port Bypass Control 0 register except it affects the P6.1 and P6.0 pins. Register Name: Address: Reset Value: Bit 7 Bit Label PBCEN PBC12 2Ch 00XX_XX1Xb Access R/W Description Port Bypass Control Enable When this bit is set, P6.1 and P6.0 are automatically configured as an FB output pin and an SD input pin. Configurations for these I/O pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P6.1 and P6.0. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input generates an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 1 RES FB R R/W Reserved. Force Bypass This bit controls the P6.1 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in Normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in Bypass mode. This register bit is automatically cleared when the synchronized and filtered P6.0 input is LOW, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the P6.1 output. Note: Because all I/O pins on the device power up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. The default state of the I/O can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. After the default state is determined, write the default value to the FB bit of this register and set the PBCEN bit to ensure that the port bypass control functions are enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains HIGH. Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P6.0 I/O pin, which has been connected to the signal detected output of a PBC/ CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal. 0 SD R/W 42 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.30 2Dh: Port Bypass Control 13 (PBC13) The following table shows the bit assignments for the Port Bypass Control 13 register. This register functions the same as the Port Bypass Control 0 register except it affects the P6.3 and P6.2 pins. Register Name: Address: Reset Value: Bit 7 Bit Label PBCEN PBC13 2Dh 00XX_XX1Xb Access R/W Description Port Bypass Control Enable When this bit is set, P6.3 and P6.2 are automatically configured as an FB output pin and an SD input pin. Configurations for these I/O pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P6.3 and P6.2. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input generates an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 1 RES FB R R/W Reserved. Force Bypass This bit controls the P6.3 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in Normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in Bypass mode. This register bit is automatically cleared when the synchronized and filtered P6.2 input is LOW, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the P6.3 output. Note: Because all I/O pins on the device power up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. The default state of the I/O can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. After the default state is determined, write the default value to the FB bit of this register and set the PBCEN bit to ensure that the port bypass control functions are enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains HIGH. Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P6.2 I/O pin, which has been connected to the signal detected output of a PBC/ CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal. 0 SD R/W 43 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.31 2Eh: Port Bypass Control 14 (PBC14) The following table shows the bit assignments for the Port Bypass Control 14 register. This register functions the same as the Port Bypass Control 0 register except it affects the P6.5 and P6.4 pins. Register Name: Address: Reset Value: Bit 7 Bit Label PBCEN PBC14 2Eh 00XX_XX1Xb Access R/W Description Port Bypass Control Enable When this bit is set, P6.5 and P6.4 are automatically configured as an FB output pin and an SD input pin. Configurations for these I/O pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P6.5 and P6.4. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input generates an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 1 RES FB R R/W Reserved. Force Bypass This bit controls the P6.5 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in Normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in Bypass mode. This register bit is automatically cleared when the synchronized and filtered P6.4 input is LOW, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the P6.5 output. Note: Because all I/O pins on the device power up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. The default state of the I/O can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. After the default state is determined, write the default value to the FB bit of this register and set the PBCEN bit to ensure that the port bypass control functions are enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains HIGH. Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P6.4 I/O pin, which has been connected to the signal detected output of a PBC/CRU/ SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal. 0 SD R/W 44 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.32 2Fh: Port Bypass Control 15 (PBC15) The following table shows the bit assignments for the Port Bypass Control 15 register. This register functions the same as the Port Bypass Control 0 register except it affects the P6.7 and P6.6 pins. Register Name: Address: Reset Value: Bit 7 Bit Label PBCEN PBC15 2Fh 00XX_XX1Xb Access R/W Description Port Bypass Control Enable When this bit is set, P6.7 and P6.6 are automatically configured as an FB output pin and an SD input pin. Configurations for these I/O pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). When this bit is reset, the remaining bits in this register have no effect on the operation of P6.7 and P6.6. 6 SDIEN R/W Signal Detected Interrupt Enable When this bit is set, the SD input generates an interrupt if a transition occurs on the pin. If a transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 1 RES FB R R/W Reserved. Force Bypass This bit controls the P6.7 I/O pin, which is configured as a totem pole output by setting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU function is not enabled and the port bypass circuit is in Normal mode. When this bit is reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port bypass circuit is in Bypass mode. This register bit is automatically cleared when the synchronized and filtered P6.6 input is LOW, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the P6.7 output. Note: Because all I/O pins on the device power up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. The default state of the I/O can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. After the default state is determined, write the default value to the FB bit of this register and set the PBCEN bit to ensure that the port bypass control functions are enabled correctly. Additional writes to this register can enable or disable the force bypass functions at any time as long as the SD input remains HIGH. Signal Detected When the PBCEN bit is set, this bit becomes a read-only indication of the P6.6 I/O pin, which has been connected to the signal detected output of a PBC/CRU/ SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal. 0 SD R/W 45 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.33 30h: Fan Speed Control 0 (FSC0) The following table shows the bit assignments for the Fan Speed Control 0 register. This register affects the P2.0 pin. Register Name: Address: Reset Value: Bit 7 Bit Label FSCEN FSC0 30h 00XX_XX00b Access R/W Description Fan Speed Control Enable When this bit is set, P2.0 is automatically configured to provide a fan speed monitoring input. Configurations for this I/O pin that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). If the appropriate bypass bits are set, the odd-numbered fan speed input pins (P2.1, P2.3, P2.5, or P2.7) are configured as outputs. When this bit is reset, the remaining bits in this register have no effect on the operation of P2.0. When enabled as a fan speed monitoring input, pulses from the fan tachometer output gate an internal 20 kHz clock into an 8-bit counter. A divisor value stored in bits 1 and 0 of this register allow the user to select one of four nominal RPM values based on fan tachometer outputs, which pulse twice per revolution. The FSCC0 register provides the user with an accurate binary fan speed count value that can be used to determine the current RPM value of the fan. Incoming pulses are filtered and conditioned to accommodate the slow rise and fall times typical of fan tachometer outputs. The maximum input signal is limited to a range of VSS to VDD. If this input is supplied from a fan tachometer output that exceeds this range, external components are required to limit the signal to an acceptable range. 6 FSIEN R/W Fan Speed Interrupt Enable When this bit is set, the P2.0 input generates an interrupt if the 8-bit counter value is greater than or equal to the count overflow value loaded into the FSCO0 register. If this condition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, the fan speed monitoring logic does not generate an interrupt condition. 5:2 1:0 RES FD1-0 R R/W Reserved. Fan Divisor These two bits determine the divisor value used to determine the correct range of RPM values supplied to the 8-bit fan speed counter. The available fan divisor values are as follows: FD1 0 0 1 1 FD0 0 1 0 1 Divisor 1 2 4 8 Nominal RPM Decimal Count Value 8000 4000 2000 1000 150 (96h) 150 (96h) 150 (96h) 150 (96h) The decimal count value can be calculated using the following equation: Decimal count value = (1,200,000) / (RPM × divisor) Any nominal RPM value can be used in the above equation with the appropriate divisor as long as the maximum non-failure count value does not exceed the limits of an 8-bit counter. Typical applications can consider 60% to 70% of nominal RPM a fan failure, which would result in a decimal count value of 250 (FAh) and 214 (D6h), respectively, at the above stated RPM values. 46 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.34 31h: Fan Speed Count Overflow 0 (FSCO0) The following table shows the bit assignments for the Fan Speed Count Overflow 0 register. This register affects the P2.0 pin. Register Name: Address: Reset Value: Bit 7:0 Bit Label FSCO7-0 FSCO0 31h 0000_0000b Access R/W Description Fan Speed Count Overflow These eight bits are compared to the 8-bit fan speed counter. If the counter exceeds this value, an interrupt is generated. This register should be loaded prior to setting the FSCEN bit in the FSC0 register to avoid generating unintentional interrupts. The overflow count value can be determined using the following equation, where FF% is equal to the percentage of nominal RPM that constitutes a fan failure: Decimal overflow count value = (1,200,000) / (RPM × divisor × FF%) Based on the above equation, a divisor of 8, and a detected fan failure at 70% of nominal RPM, the fan speed monitoring logic can support a low-end nominal RPM of 850. High-end RPM values are basically unlimited; however, counter resolution is diminished above 8000 RPM. 3.2.35 32h: Fan Speed Current Count 0 (FSCC0) The following table shows the bit assignments for the Fan Speed Current Count 0 register. This register affects the P2.0 pin. Register Name: Address: Reset Value: Bit 7:0 Bit Label FSCC7-0 FSCC0 32h 0000_0000b Access R Description These eight bits, when enabled by setting the FSCEN bit in the FSC0 register, provide the user with an accurate binary fan speed count value that can be used to determine the current RPM value of the fan. A minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. The following equation can be used to determine the current RPM value of the fan: RPM = (1,200,000) / (Decimal count value × divisor) When the result of a read of this register is 00h, an accurate fan speed count value is not generated, indicating that the fan has not completed a minimum of one revolution. When the result of a read of this register is FFh, the fan is rotating very slowly or there are no tachometer pulses present. When operating in a polled mode, with the FSIEN bit reset in the FSC0 register, this register is automatically updated with an accurate fan speed count once per revolution of the fan. When operating in an Interrupt mode with the FSIEN bit set in the FSC0 register, this register is automatically updated with an accurate fan speed count, once per revolution of the fan, until an interrupt is generated. After the interrupt is generated, the value remains stable until the interrupt is cleared. When the interrupt is cleared, this register is also cleared, indicating that a valid RPM value is in the process of being generated. 47 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.36 34h: Fan Speed Control 1 (FSC1) The following table shows the bit assignments for the Fan Speed Control 1 register. This register functions same the Fan Speed Control 0 register except it affects the P2.1 pin. Register Name: Address: Reset Value: Bit 7 Bit Label FSCEN FSC1 34h 00XX_XX00b Access R/W Description Fan Speed Control Enable When this bit is set, P2.1 is automatically configured to provide a fan speed monitoring input. Configurations for this I/O pin that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). If the appropriate bypass bits are set, the odd-numbered fan speed input pins (P2.1, P2.3, P2.5, or P2.7) are configured as outputs. When this bit is reset, the remaining bits in this register have no effect on the operation of P2.1. When enabled as a fan speed monitoring input, pulses from the fan tachometer output gate an internal 20 kHz clock into an 8-bit counter. A divisor value stored in bits 1 and 0 of this register allow the user to select one of four nominal RPM values based on fan tachometer outputs, which pulse twice per revolution. The FSCC1 register provides the user with an accurate binary fan speed count value that can be used to determine the current RPM value of the fan. Incoming pulses are filtered and conditioned to accommodate the slow rise and fall times typical of fan tachometer outputs. The maximum input signal is limited to a range of VSS to VDD. If this input is supplied from a fan tachometer output that exceeds this range, external components are required to limit the signal to an acceptable range. 6 FSIEN R/W Fan Speed Interrupt Enable When this bit is set, the P2.1 input generates an interrupt if the 8-bit counter value is greater than or equal to the count overflow value loaded into the FSCO1 register. If this condition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, the fan speed monitoring logic does not generate an interrupt condition. 5:2 1:0 RES FD1-0 R R/W Reserved. Fan Divisor These two bits determine the divisor value used to determine the correct range of RPM values supplied to the 8-bit fan speed counter. The available fan divisor values are as follows: FD1 0 0 1 1 FD0 0 1 0 1 Divisor 1 2 4 8 Nominal RPM Decimal Count Value 8000 4000 2000 1000 150 (96h) 150 (96h) 150 (96h) 150 (96h) The decimal count value can be calculated using the following equation: Decimal count value = (1,200,000) / (RPM × divisor) Any nominal RPM value can be used in the above equation with the appropriate divisor as long as the maximum non-failure count value does not exceed the limits of an 8-bit counter. Typical applications may consider 60% to 70% of nominal RPM a fan failure, which would result in a decimal count value of 250 (FAh) and 214 (D6h), respectively, at the above stated RPM values. 48 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.37 35h: Fan Speed Count Overflow 1 (FSCO1) The following table shows the bit assignments for the Fan Speed Count Overflow 1 register. This register functions same the Fan Speed Count Overflow 0 register except it affects the P2.1 pin. Register Name: Address: Reset Value: Bit 7:0 Bit Label FSCO7-0 FSCO1 35h 0000_0000b Access R/W Description Fan Speed Count Overflow These eight bits are compared to the 8-bit fan speed counter. If the counter exceeds this value, an interrupt is generated. This register should be loaded prior to setting the FSCEN bit in the FSC1 register to avoid generating unintentional interrupts. The overflow count value can be determined using the following equation, where FF% is equal to the percentage of nominal RPM that constitutes a fan failure: Decimal overflow count value = (1,200,000) / (RPM × divisor × FF%) Based on the above equation, a divisor of 8, and a detected fan failure at 70% of nominal RPM, the fan speed monitoring logic can support a low-end nominal RPM of 850. High-end RPM values are basically unlimited; however, counter resolution is diminished above 8000 RPM. 3.2.38 36h: Fan Speed Current Count 1 (FSCC1) The following table shows the bit assignments for the Fan Speed Current Count 1 register. This register functions same the Fan Speed Current Count 0 register except it affects the P2.1 pin. Register Name: Address: Reset Value: Bit 7:0 Bit Label FSCC7-0 FSCC1 36h 0000_0000b Access R Description These eight bits, when enabled by setting the FSCEN bit in the FSC1 register, provide the user with an accurate binary fan speed count value that can be used to determine the current RPM value of the fan. A minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. The following equation can be used to determine the current RPM value of the fan: RPM = (1,200,000) / (Decimal count value × divisor) When the result of a read of this register is 00h, an accurate fan speed count value is not generated, indicating that the fan has not completed a minimum of one revolution. When the result of a read of this register is FFh, the fan is rotating very slowly or there are no tachometer pulses present. When operating in a polled mode, with the FSIEN bit reset in the FSC1 register, this register is automatically updated with an accurate fan speed count once per revolution of the fan. When operating in an Interrupt mode with the FSIEN bit set in the FSC1 register, this register is automatically updated with an accurate fan speed count, once per revolution of the fan, until an interrupt is generated. After the interrupt is generated, the value remains stable until the interrupt is cleared. When the interrupt is cleared, this register is also cleared, indicating that a valid RPM value is in the process of being generated. 49 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.39 38h: Fan Speed Control 2 (FSC2) The following table shows the bit assignments for the Fan Speed Control 2 register. This register functions same the Fan Speed Control 0 register except it affects the P2.2 pin. Register Name: Address: Reset Value: Bit 7 Bit Label FSCEN FSC2 38h 00XX_XX00b Access R/W Description Fan Speed Control Enable When this bit is set, P2.2 is automatically configured to provide a fan speed monitoring input. Configurations for this I/O pin that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). If the appropriate bypass bits are set, the odd-numbered fan speed input pins (P2.1, P2.3, P2.5, or P2.7) are configured as outputs. When this bit is reset, the remaining bits in this register have no effect on the operation of P2.2. When enabled as a fan speed monitoring input, pulses from the fan tachometer output gate an internal 20 kHz clock into an 8-bit counter. A divisor value stored in bits 1 and 0 of this register allow the user to select one of four nominal RPM values based on fan tachometer outputs, which pulse twice per revolution. The FSCC2 register provides the user with an accurate binary fan speed count value that can be used to determine the current RPM value of the fan. Incoming pulses are filtered and conditioned to accommodate the slow rise and fall times typical of fan tachometer outputs. The maximum input signal is limited to a range of VSS to VDD. If this input is supplied from a fan tachometer output that exceeds this range, external components are required to limit the signal to an acceptable range. 6 FSIEN R/W Fan Speed Interrupt Enable When this bit is set, the P2.2 input generates an interrupt if the 8-bit counter value is greater than or equal to the count overflow value loaded into the FSCO2 register. If this condition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, the fan speed monitoring logic does not generate an interrupt condition. 5:2 1:0 RES FD1-0 R R/W Reserved. Fan Divisor These two bits determine the divisor value used to determine the correct range of RPM values supplied to the 8-bit fan speed counter. The available fan divisor values are as follows: FD1 0 0 1 1 FD0 0 1 0 1 Divisor 1 2 4 8 Nominal RPM Decimal Count Value 8000 4000 2000 1000 150 (96h) 150 (96h) 150 (96h) 150 (96h) The decimal count value can be calculated using the following equation: Decimal count value = (1,200,000) / (RPM × divisor) Any nominal RPM value can be used in the above equation with the appropriate divisor as long as the maximum non-failure count value does not exceed the limits of an 8-bit counter. Typical applications may consider 60% to 70% of nominal RPM a fan failure, which would result in a decimal count value of 250 (FAh) and 214 (D6h), respectively, at the above stated RPM values. 50 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.40 39h: Fan Speed Count Overflow 2 (FSCO2) The following table shows the bit assignments for the Fan Speed Count Overflow 2 register. This register functions same the Fan Speed Count Overflow 0 register except it affects the P2.2 pin. Register Name: Address: Reset Value: Bit 7:0 Bit Label FSCO7-0 FSCO2 39h 0000_0000b Access R/W Description Fan Speed Count Overflow These eight bits are compared to the 8-bit fan speed counter. If the counter exceeds this value, an interrupt is generated. This register should be loaded prior to setting the FSCEN bit in the FSC2 register to avoid generating unintentional interrupts. The overflow count value can be determined using the following equation, where FF% is equal to the percentage of nominal RPM that constitutes a fan failure: Decimal overflow count value = (1,200,000) / (RPM × divisor × FF%) Based on the above equation, a divisor of 8, and a detected fan failure at 70% of nominal RPM, the fan speed monitoring logic can support a low-end nominal RPM of 850. High-end RPM values are basically unlimited; however, counter resolution is diminished above 8000 RPM. 3.2.41 3Ah: Fan Speed Current Count 2 (FSCC2) The following table shows the bit assignments for the Fan Speed Current Count 2 register. This register functions same the Fan Speed Current Count 0 register except it affects the P2.2 pin. Register Name: Address: Reset Value: Bit 7:0 Bit Label FSCC7-0 FSCC2 3Ah 0000_0000b Access R Description These eight bits, when enabled by setting the FSCEN bit in the FSC2 register, provide the user with an accurate binary fan speed count value that can be used to determine the current RPM value of the fan. A minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. The following equation can be used to determine the current RPM value of the fan: RPM = (1,200,000) / (Decimal count value × divisor) When the result of a read of this register is 00h, an accurate fan speed count value is not generated, indicating that the fan has not completed a minimum of one revolution. When the result of a read of this register is FFh, the fan is rotating very slowly or there are no tachometer pulses present. When operating in a polled mode, with the FSIEN bit reset in the FSC2 register, this register is automatically updated with an accurate fan speed count once per revolution of the fan. When operating in an Interrupt mode with the FSIEN bit set in the FSC2 register, this register is automatically updated with an accurate fan speed count, once per revolution of the fan, until an interrupt is generated. Once the interrupt is generated, the value remains stable until the interrupt is cleared. When the interrupt is cleared, this register is also cleared, indicating that a valid RPM value is in the process of being generated. 51 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.42 3Ch: Fan Speed Control 3 (FSC3) The following table shows the bit assignments for the Fan Speed Control 3 register. This register functions same the Fan Speed Control 0 register except it affects the P2.3 pin. Register Name: Address: Reset Value: Bit 7 Bit Label FSCEN FSC3 3Ch 00XX_XX00b Access R/W Description Fan Speed Control Enable When this bit is set, P2.3 is automatically configured to provide a fan speed monitoring input. Configurations for this I/O pin that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). If the appropriate bypass bits are set, the odd-numbered fan speed input pins (P2.1, P2.3, P2.5, or P2.7) are configured as outputs. When this bit is reset, the remaining bits in this register have no effect on the operation of P2.3. When enabled as a fan speed monitoring input, pulses from the fan tachometer output gate an internal 20 kHz clock into an 8-bit counter. A divisor value stored in bits 1 and 0 of this register allow the user to select one of four nominal RPM values based on fan tachometer outputs, which pulse twice per revolution. The FSCC3 register provides the user with an accurate binary fan speed count value that can be used to determine the current RPM value of the fan. Incoming pulses are filtered and conditioned to accommodate the slow rise and fall times that are typical of fan tachometer outputs. The maximum input signal is limited to a range of VSS to VDD. If this input is supplied from a fan tachometer output that exceeds this range, external components are required to limit the signal to an acceptable range. 6 FSIEN R/W Fan Speed Interrupt Enable When this bit is set, the P2.3 input generates an interrupt if the 8-bit counter value is greater than or equal to the count overflow value loaded into the FSCO3 register. If this condition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, the fan speed monitoring logic does not generate an interrupt condition. 5:2 1:0 RES FD1-0 R R/W Reserved. Fan Divisor These two bits determine the divisor value used to determine the correct range of RPM values supplied to the 8-bit fan speed counter. The available fan divisor values are as follows: FD1 0 0 1 1 FD0 0 1 0 1 Divisor 1 2 4 8 Nominal RPM Decimal Count Value 8000 4000 2000 1000 150 (96h) 150 (96h) 150 (96h) 150 (96h) The decimal count value can be calculated using the following equation: Decimal count value = (1,200,000) / (RPM × divisor) Any nominal RPM value can be used in the above equation with the appropriate divisor as long as the maximum non-failure count value does not exceed the limits of an 8-bit counter. Typical applications may consider 60% to 70% of nominal RPM a fan failure, which would result in a decimal count value of 250 (FAh) and 214 (D6h), respectively, at the above stated RPM values. 52 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.43 3Dh: Fan Speed Count Overflow 3 (FSCO3) The following table shows the bit assignments for the Fan Speed Count Overflow 3 register. This register functions same the Fan Speed Count Overflow 0 register except it affects the P2.3 pin. Register Name: Address: Reset Value: Bit 7:0 Bit Label FSCO7-0 FSCO3 3Dh 0000_0000b Access R/W Description Fan Speed Count Overflow These eight bits are compared to the 8-bit fan speed counter. If the counter exceeds this value, an interrupt is generated. This register should be loaded prior to setting the FSCEN bit in the FSC3 register to avoid generating unintentional interrupts. The overflow count value can be determined using the following equation, where FF% is equal to the percentage of nominal RPM that constitutes a fan failure: Decimal overflow count value = (1,200,000) / (RPM × divisor × FF%) Based on the above equation, a divisor of 8, and a detected fan failure at 70% of nominal RPM, the fan speed monitoring logic can support a low-end nominal RPM of 850. High-end RPM values are basically unlimited; however, counter resolution is diminished above 8000 RPM. 3.2.44 3Eh: Fan Speed Current Count 3 (FSCC3) The following table shows the bit assignments for the Fan Speed Current Count 3 register. This register functions same the Fan Speed Current Count 0 register except it affects the P2.3 pin. Register Name: Address: Reset Value: Bit 7:0 Bit Label FSCC7-0 FSCC3 3Eh 0000_0000b Access R Description These eight bits, when enabled by setting the FSCEN bit in the FSC3 register provide the user with an accurate binary fan speed count value that can be used to determine the current RPM value of the fan. A minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. The following equation can be used to determine the current RPM value of the fan: RPM = (1,200,000) / (Decimal count value × divisor) When the result of a read of this register is 00h, an accurate fan speed count value has not been generated indicating that the fan has not completed a minimum of one revolution. When the result of a read of this register is FFh, the fan is rotating very slowly or there are no tachometer pulses present. When operating in a polled mode, with the FSIEN bit reset in the FSC3 register, this register is automatically updated with an accurate fan speed count once per revolution of the fan. When operating in an Interrupt mode with the FSIEN bit set in the FSC3 register, this register is automatically updated with an accurate fan speed count, once per revolution of the fan, until an interrupt is generated. After the interrupt is generated, the value remains stable until the interrupt is cleared. When the interrupt is cleared, this register is also cleared, indicating that a valid RPM value is in the process of being generated. 53 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.45 40h: Fan Speed Control 4 (FSC4) The following table shows the bit assignments for the Fan Speed Control 4 register. This register functions same the Fan Speed Control 0 register except it affects the P2.4 pin. Register Name: Address: Reset Value: Bit 7 Bit Label FSCEN FSC4 40h 00XX_XX00b Access R/W Description Fan Speed Control Enable When this bit is set, P2.4 is automatically configured to provide a fan speed monitoring input. Configurations for this I/O pin that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). If the appropriate bypass bits are set, the odd-numbered fan speed input pins (P2.1, P2.3, P2.5, or P2.7) are configured as outputs. When this bit is reset, the remaining bits in this register have no effect on the operation of P2.4. When enabled as a fan speed monitoring input, pulses from the fan tachometer output gate an internal 20 kHz clock into an 8-bit counter. A divisor value stored in bits 1 and 0 of this register allow the user to select one of four nominal RPM values based on fan tachometer outputs, which pulse twice per revolution. The FSCC4 register provides the user with an accurate binary fan speed count value that can be used to determine the current RPM value of the fan. Incoming pulses are filtered and conditioned to accommodate the slow rise and fall times typical of fan tachometer outputs. The maximum input signal is limited to a range of VSS to VDD. If this input is supplied from a fan tachometer output that exceeds this range, external components are required to limit the signal to an acceptable range. 6 FSIEN R/W Fan Speed Interrupt Enable When this bit is set, the P2.4 input generates an interrupt if the 8-bit counter value is greater than or equal to the count overflow value loaded into the FSCO4 register. If this condition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, the fan speed monitoring logic does not generate an interrupt condition. 5:2 1:0 RES FD1-0 R R/W Reserved. Fan Divisor These two bits determine the divisor value used to determine the correct range of RPM values supplied to the 8-bit fan speed counter. The available fan divisor values are as follows: FD1 0 0 1 1 FD0 0 1 0 1 Divisor 1 2 4 8 Nominal RPM Decimal Count Value 8000 4000 2000 1000 150 (96h) 150 (96h) 150 (96h) 150 (96h) The decimal count value can be calculated using the following equation: Decimal count value = (1,200,000) / (RPM × divisor) Any nominal RPM value can be used in the above equation with the appropriate divisor as long as the maximum non-failure count value does not exceed the limits of an 8-bit counter. Typical applications may consider 60% to 70% of nominal RPM a fan failure, which would result in a decimal count value of 250 (FAh) and 214 (D6h), respectively, at the above stated RPM values. 54 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.46 41h: Fan Speed Count Overflow 4 (FSCO4) The following table shows the bit assignments for the Fan Speed Count Overflow 4 register. This register functions same the Fan Speed Count Overflow 0 register except it affects the P2.4 pin. Register Name: Address: Reset Value: Bit 7:0 Bit Label FSCO7-0 FSCO4 41h 0000_0000b Access R/W Description Fan Speed Count Overflow These eight bits are compared to the 8-bit fan speed counter. If the counter exceeds this value, an interrupt is generated. This register should be loaded prior to setting the FSCEN bit in the FSC4 register to avoid generating unintentional interrupts. The overflow count value can be determined using the following equation, where FF% is equal to the percentage of nominal RPM, which constitutes a fan failure: Decimal overflow count value = (1,200,000) / (RPM × divisor × FF%) Based on the above equation, a divisor of 8, and a detected fan failure at 70% of nominal RPM, the fan speed monitoring logic can support a low-end nominal RPM of 850. High-end RPM values are basically unlimited; however, counter resolution is diminished above 8000 RPM. 3.2.47 42h: Fan Speed Current Count 4 (FSCC4) The following table shows the bit assignments for the Fan Speed Current Count 4 register. This register functions the same as Fan Speed Current Count 0 register except it affects the P2.4 pin. Register Name: Address: Reset Value: Bit 7:0 Bit Label FSCC7-0 FSCC4 42h 0000_0000b Access R Description These eight bits, when enabled by setting the FSCEN bit in the FSC4 register, provide the user with an accurate binary fan speed count value that can be used to determine the current RPM value of the fan. A minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. The following equation can be used to determine the current RPM value of the fan: RPM = (1,200,000) / (Decimal count value × divisor) When the result of a read of this register is 00h, an accurate fan speed count value is not generated, indicating that the fan has not completed a minimum of one revolution. When the result of a read of this register is FFh, the fan is rotating very slowly or there are no tachometer pulses present. When operating in a polled mode, with the FSIEN bit reset in the FSC4 register, this register is automatically updated with an accurate fan speed count once per revolution of the fan. When operating in an Interrupt mode with the FSIEN bit set in the FSC4 register, this register is automatically updated with an accurate fan speed count, once per revolution of the fan, until an interrupt is generated. After the interrupt is generated, the value remains stable until the interrupt is cleared. When the interrupt is cleared, this register is also cleared, indicating that a valid RPM value is in the process of being generated. 55 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.48 44h: Fan Speed Control 5 (FSC5) The following table shows the bit assignments for the Fan Speed Control 5 register. This register functions same the Fan Speed Control 0 register, except it affects the P2.5 pin. Register Name: Address: Reset Value: Bit 7 Bit Label FSCEN FSC5 44h 00XX_XX00b Access R/W Description Fan Speed Control Enable When this bit is set, P2.5 is automatically configured to provide a fan speed monitoring input. Configurations for this I/O pin that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). If the appropriate bypass bits are set, the odd-numbered fan speed input pins (P2.1, P2.3, P2.5, or P2.7) are configured as outputs. When this bit is reset, the remaining bits in this register have no effect on the operation of P2.5. When enabled as a fan speed monitoring input, pulses from the fan tachometer output gate an internal 20 kHz clock into an 8-bit counter. A divisor value stored in bits 1 and 0 of this register allow the user to select one of four nominal RPM values based on fan tachometer outputs, which pulse twice per revolution. The FSCC5 register provides the user with an accurate binary fan speed count value that can be used to determine the current RPM value of the fan. Incoming pulses are filtered and conditioned to accommodate the slow rise and fall times typical of fan tachometer outputs. The maximum input signal is limited to a range of VSS to VDD. If this input is supplied from a fan tachometer output that exceeds this range, external components are required to limit the signal to an acceptable range. 6 FSIEN R/W Fan Speed Interrupt Enable When this bit is set, the P2.5 input generates an interrupt if the 8-bit counter value is greater than or equal to the count overflow value loaded into the FSCO5 register. If this condition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, the fan speed monitoring logic does not generate an interrupt condition. 5:2 1:0 RES FD1-0 R R/W Reserved. Fan Divisor These two bits determine the divisor value used to determine the correct range of RPM values supplied to the 8-bit fan speed counter. The available fan divisor values are as follows: FD1 0 0 1 1 FD0 0 1 0 1 Divisor 1 2 4 8 Nominal RPM Decimal Count Value 8000 4000 2000 1000 150 (96h) 150 (96h) 150 (96h) 150 (96h) The decimal count value can be calculated using the following equation: Decimal count value = (1,200,000) / (RPM × divisor) Any nominal RPM value can be used in the above equation with the appropriate divisor as long as the maximum non-failure count value does not exceed the limits of an 8-bit counter. Typical applications may consider 60% to 70% of nominal RPM a fan failure, which would result in a decimal count value of 250 (FAh) and 214 (D6h), respectively, at the above stated RPM values. 56 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.49 45h: Fan Speed Count Overflow 5 (FSCO5) The following table shows the bit assignments for the Fan Speed Count Overflow 5 register. This register functions same the Fan Speed Count Overflow 0 register except it affects the P2.5 pin. Register Name: Address: Reset Value: Bit 7:0 Bit Label FSCO7-0 FSCO5 45h 0000_0000b Access R/W Description Fan Speed Count Overflow These eight bits are compared to the 8-bit fan speed counter. If the counter exceeds this value, an interrupt is generated. This register should be loaded prior to setting the FSCEN bit in the FSC5 register to avoid generating unintentional interrupts. The overflow count value can be determined using the following equation, where FF% is equal to the percentage of nominal RPM, which constitutes a fan failure: Decimal overflow count value = (1,200,000) / (RPM × divisor × FF%) Based on the above equation, a divisor of 8, and a detected fan failure at 70% of nominal RPM, the fan speed monitoring logic can support a low-end nominal RPM of 850. High-end RPM values are basically unlimited; however, counter resolution is diminished above 8000 RPM. 3.2.50 46h: Fan Speed Current Count 5 (FSCC5) The following table shows the bit assignments for the Fan Speed Current Count 5 register. This register functions the same as Fan Speed Current Count 0 register except it affects the P2.5 pin. Register Name: Address: Reset Value: Bit 7:0 Bit Label FSCC7-0 FSCC5 46h 0000_0000b Access R Description These eight bits, when enabled by setting the FSCEN bit in the FSC5 register, provide the user with an accurate binary fan speed count value that can be used to determine the current RPM value of the fan. A minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. The following equation can be used to determine the current RPM value of the fan: RPM = (1,200,000)/(Decimal count value × divisor) When the result of a read of this register is 00h, an accurate fan speed count value is not generated, indicating that the fan has not completed a minimum of one revolution. When the result of a read of this register is FFh, the fan is rotating very slowly or there are no tachometer pulses present. When operating in a polled mode, with the FSIEN bit reset in the FSC5 register, this register is automatically updated with an accurate fan speed count once per revolution of the fan. When operating in an Interrupt mode with the FSIEN bit set in the FSC5 register, this register is automatically updated with an accurate fan speed count, once per revolution of the fan until an interrupt is generated. After the interrupt is generated, the value remains stable until the interrupt is cleared. When the interrupt is cleared, this register is also be cleared, indicating that a valid RPM value is in the process of being generated. 57 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.51 48h: Fan Speed Control 6 (FSC6) The following table shows the bit assignments for the Fan Speed Control 6 register. This register functions same the Fan Speed Control 0 register except it affects the P2.6 pin. Register Name: Address: Reset Value: Bit 7 Bit Label FSCEN FSC6 48h 00XX_XX00b Access R/W Description Fan Speed Control Enable When this bit is set, P2.6 is automatically configured to provide a fan speed monitoring input. Configurations for this I/O pin that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). If the appropriate bypass bits are set, the odd-numbered fan speed input pins (P2.1, P2.3, P2.5, or P2.7) are configured as outputs. When this bit is reset, the remaining bits in this register have no effect on the operation of P2.6. When enabled as a fan speed monitoring input, pulses from the fan tachometer output gate an internal 20 kHz clock into an 8-bit counter. A divisor value stored in bits 1 and 0 of this register allow the user to select one of four nominal RPM values based on fan tachometer outputs, which pulse twice per revolution. The FSCC6 register provides the user with an accurate binary fan speed count value that can be used to determine the current RPM value of the fan. Incoming pulses are filtered and conditioned to accommodate the slow rise and fall times typical of fan tachometer outputs. The maximum input signal is limited to a range of VSS to VDD. If this input is supplied from a fan tachometer output that exceeds this range, external components are required to limit the signal to an acceptable range. 6 FSIEN R/W Fan Speed Interrupt Enable When this bit is set, the P2.6 input generates an interrupt if the 8-bit counter value is greater than or equal to the count overflow value loaded into the FSCO6 register. If this condition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, the fan speed monitoring logic will not generate an interrupt condition. 5:2 1:0 RES FD1-0 R R/W Reserved. Fan Divisor These two bits determine the divisor value used to determine the correct range of RPM values supplied to the 8-bit fan speed counter. The available fan divisor values are as follows: FD1 0 0 1 1 FD0 0 1 0 1 Divisor 1 2 4 8 Nominal RPM Decimal Count Value 8000 4000 2000 1000 150 (96h) 150 (96h) 150 (96h) 150 (96h) The decimal count value can be calculated using the following equation: Decimal count value = (1,200,000) / (RPM × divisor) Any nominal RPM value can be used in the above equation with the appropriate divisor as long as the maximum non-failure count value does not exceed the limits of an 8-bit counter. Typical applications may consider 60% to 70% of nominal RPM a fan failure, which would result in a decimal count value of 250 (FAh) and 214 (D6h), respectively, at the above stated RPM values. 58 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.52 49h: Fan Speed Count Overflow 6 (FSCO6) The following table shows the bit assignments for the Fan Speed Count Overflow 6 register. This register functions same the Fan Speed Count Overflow 0 register except it affects the P2.6 pin. Register Name: Address: Reset Value: Bit 7:0 Bit Label FSCO7-0 FSCO6 49h 0000_0000b Access R/W Description Fan Speed Count Overflow These eight bits are compared to the 8-bit fan speed counter. If the counter exceeds this value, an interrupt is generated. This register should be loaded prior to setting the FSCEN bit in the FSC6 register to avoid generating unintentional interrupts. The overflow count value can be determined using the following equation, where FF% is equal to the percentage of nominal RPM that constitutes a fan failure: Decimal overflow count value = (1,200,000) / (RPM × divisor × FF%) Based on the above equation, a divisor of 8, and a detected fan failure at 70% of nominal RPM, the fan speed monitoring logic can support a low-end nominal RPM of 850. High-end RPM values are basically unlimited; however, counter resolution is diminished above 8000 RPM. 3.2.53 4Ah: Fan Speed Current Count 6 (FSCC6) The following table shows the bit assignments for the Fan Speed Current Count 6 register. This register functions the same as Fan Speed Current Count 0 register except it affects the P2.6 pin. Register Name: Address: Reset Value: Bit 7:0 Bit Label FSCC7-0 FSCC6 4Ah 0000_0000b Access R Description These eight bits, when enabled by setting the FSCEN bit in the FSC6 register, provide the user with an accurate binary fan speed count value that can be used to determine the current RPM value of the fan. A minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. The following equation can be used to determine the current RPM value of the fan: RPM = (1,200,000) /( Decimal count value × divisor) When the result of a read of this register is 00h, an accurate fan speed count value is not generated, indicating that the fan has not completed a minimum of one revolution. When the result of a read of this register is FFh, the fan is rotating very slowly or no tachometer pulses are present. When operating in a polled mode, with the FSIEN bit reset in the FSC6 register, this register is automatically updated with an accurate fan speed count once per revolution of the fan. When operating in an Interrupt mode with the FSIEN bit set in the FSC6 register, this register is automatically updated with an accurate fan speed count, once per revolution of the fan, until an interrupt is generated. After the interrupt is generated, the value remains stable until the interrupt is cleared. When the interrupt is cleared, this register is also cleared, indicating that a valid RPM value is in the process of being generated. 59 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.54 4Ch: Fan Speed Control 7 (FSC7) The following table shows the bit assignments for the Fan Speed Control 7 register. This register functions same the Fan Speed Control 0 register except it affects the P2.7 pin. Register Name: Address: Reset Value: Bit 7 Bit Label FSCEN FSC7 4Ch 00XX_XX00b Access R/W Description Fan Speed Control Enable When this bit is set, P2.7 is automatically configured to provide a fan speed monitoring input. Configurations for this I/O pin that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). If the appropriate bypass bits are set, the odd-numbered fan speed input pins (P2.1, P2.3, P2.5, or P2.7) are configured as outputs. When this bit is reset, the remaining bits in this register have no effect on the operation of P2.7. When enabled as a fan speed monitoring input, pulses from the fan tachometer output gate an internal 20 kHz clock into an 8-bit counter. A divisor value stored in bits 1 and 0 of this register allow the user to select one of four nominal RPM values based on fan tachometer outputs, which pulse twice per revolution. The FSCC7 register provides the user with an accurate binary fan speed count value that can be used to determine the current RPM value of the fan. Incoming pulses are filtered and conditioned to accommodate the slow rise and fall times typical of fan tachometer outputs. The maximum input signal is limited to a range of VSS to VDD. If this input is supplied from a fan tachometer output that exceeds this range, external components are required to limit the signal to an acceptable range. 6 FSIEN R/W Fan Speed Interrupt Enable When this bit is set, the P2.7 input generates an interrupt if the 8-bit counter value is greater than or equal to the count overflow value loaded into the FSCO7 register. If this condition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. When this bit is reset, the fan speed monitoring logic does not generate an interrupt condition. 5:2 1:0 RES FD1-0 R R/W Reserved. Fan Divisor These two bits determine the divisor value used to determine the correct range of RPM values supplied to the 8-bit fan speed counter. The available fan divisor values are as follows: FD1 0 0 1 1 FD0 0 1 0 1 Divisor 1 2 4 8 Nominal RPM Decimal Count Value 8000 4000 2000 1000 150 (96h) 150 (96h) 150 (96h) 150 (96h) The decimal count value can be calculated using the following equation: Decimal count value = (1,200,000) / (RPM × divisor) Any nominal RPM value can be used in the above equation with the appropriate divisor as long as the maximum non-failure count value does not exceed the limits of an 8-bit counter. Typical applications may consider 60% to 70% of nominal RPM a fan failure, which would result in a decimal count value of 250 (FAh) and 214 (D6h), respectively, at the above stated RPM values. 60 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.55 4Dh: Fan Speed Count Overflow 7 (FSCO7) The following table shows the bit assignments for the Fan Speed Count Overflow 7 register. This register functions same the Fan Speed Count Overflow 0 register except it affects the P2.7 pin. Register Name: Address: Reset Value: Bit 7:0 Bit Label FSCO7-0 FSCO7 4Dh 0000_0000b Access R/W Description Fan Speed Count Overflow These eight bits are compared to the 8-bit fan speed counter. If the counter exceeds this value, an interrupt is generated. This register should be loaded prior to setting the FSCEN bit in the FSC7 register to avoid generating unintentional interrupts. The overflow count value can be determined using the following equation, where FF% is equal to the percentage of nominal RPM that constitutes a fan failure: Decimal overflow count value = (1,200,000) / (RPM × divisor × FF%) Based on the above equation, a divisor of 8, and a detected fan failure at 70% of nominal RPM, the fan speed monitoring logic can support a low-end nominal RPM of 850. High-end RPM values are basically unlimited; however, counter resolution is diminished above 8000 RPM. 3.2.56 4Eh: Fan Speed Current Count 7 (FSCC7) The following table shows the bit assignments for the Fan Speed Current Count 7 register. This register functions the same as Fan Speed Current Count 0 except it affects the P2.7 pin. Register Name: Address: Reset Value: Bit 7:0 Bit Label FSCC7-0 FSCC7 4Eh 0000_0000b Access R Description These eight bits, when enabled by setting the FSCEN bit in the FSC7 register, provide the user with an accurate binary fan speed count value that can be used to determine the current RPM value of the fan. A minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. The following equation can be used to determine the current RPM value of the fan: RPM = (1,200,000) / (Decimal count value × divisor) When the result of a read of this register is 00h, an accurate fan speed count value is not generated, indicating that the fan has not completed a minimum of one revolution. When the result of a read of this register is FFh, the fan is rotating very slowly or no tachometer pulses are present. When operating in a polled mode, with the FSIEN bit reset in the FSC7 register, this register is automatically updated with an accurate fan speed count once per revolution of the fan. When operating in an Interrupt mode with the FSIEN bit set in the FSC7 register, this register is automatically updated with an accurate fan speed count, once per revolution of the fan, until an interrupt is generated. After the interrupt is generated, the value remains stable until the interrupt is cleared. When the interrupt is cleared, this register is also cleared, indicating that a valid RPM value is in the process of being generated. 61 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.57 70h: Pulse Train Control 00 (PTC00) This register, along with the PTC01 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC00 register provides eight of the twelve bits available in the programmable pulse train. The PTC01 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC00 register with a 45h and the PTC01 register with a C1h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 125 ms. If the default values of this register or the PTC01 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111. The following table shows the bit assignments for the Pulse Train Control 00 register. Register Name: Address: Reset Value: Bit 7:0 Bit Label PT7-0 PTC00 70h 0000_0000b Access R/W Description Pulse Train These eight bits are the first bits shifted out from 0 to 7 and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time. 62 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.58 71h: Pulse Train Control 01 (PTC01) This register, along with the PTC00 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC00 register provides eight of the twelve bits available in the programmable pulse train. The PTC01 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC00 register with a 45h and the PTC01 register with a C1h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 125 ms. If the default values of this register or the PTC00 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111. The following table shows the bit assignments for the Pulse Train Control 01 register. Register Name: Address: Reset Value: Bit 7:6 Bit Label TPW1-0 PTC01 71h 0000_0000b Access R/W Description Train Pulse Width These two bits define the pulse width of each of the pulse train bits. The available pulse widths are as follows: TPW1 0 0 1 1 5:4 PTL1-0 R/W TPW0 0 1 0 1 Train Pulse Width 41.67 ms 55.55 ms 83.33 ms 125 ms Pulse Train Length These two bits define the pulse-train length, which is the number of pulse train bits that is shifted out before returning to bit 0. The available pulse train lengths are as follows: PTL1 0 0 1 1 PTL0 0 1 0 1 Pulse-Train Length 12 pulse train bits from 0 to 11 10 pulse train bits from 0 to 9 9 pulse train bits from 0 to 8 8 pulse train bits from 0 to 7 3:0 PT11-8 R/W Pulse Train These four bits are the last bits shifted out from 0 to 3 and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time. 63 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.59 72h: Pulse Train Control 10 (PTC10) This register, along with the PTC11 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC10 register provides eight of the twelve bits available in the programmable pulse train. The PTC11 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC10 register with a 45h and the PTC11 register with a C1h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 125 ms. If the default values of this register or the PTC11 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111. The following table shows the bit assignments for the Pulse Train Control 10 register. Register Name: Address: Reset Value: Bit 7:0 Bit Label PT7-0 PTC10 72h 0000_0000b Access R/W Description Pulse Train These eight bits are the first bits shifted out from 0 to 7 and define the on/off time for the flash rate. 1: defines LED on time 0: defines LED off time. 64 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.60 73h: Pulse Train Control 11 (PTC11) This register, along with the PTC10 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC10 register provides eight of the twelve bits available in the programmable pulse train. The PTC11 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC10 register with a 45h and the PTC11 register with a C1h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 125 ms. If the default values of this register or the PTC10 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111.The following table shows the bit assignments for the Pulse Train Control 11 register. Register Name: Address: Reset Value: Bit 7:6 Bit Label TPW1-0 PTC11 73h 0000_0000b Access R/W Description Train Pulse Width These two bits define the pulse width of each of the pulse train bits. The available pulse widths are as follows: TPW1 0 0 1 1 5:4 PTL1-0 R/W TPW0 0 1 0 1 Train Pulse Width 41.67 ms 55.55 ms 83.33 ms 125 ms Pulse Train Length These two bits define the pulse train length, which is the number of pulse train bits that is shifted out before returning to bit 0. The available pulse train lengths are as follows: PTL1 0 0 1 1 PTL0 0 1 0 1 Pulse Train Length 12 pulse train bits from 0 to 11 10 pulse train bits from 0 to 9 9 pulse train bits from 0 to 8 8 pulse train bits from 0 to 7 3:0 PT11-8 R/W Pulse Train These four bits are the last bits shifted out from 0 to 3 and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time. 65 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.61 74h: Pulse Train Control 20 (PTC20) This register, along with the PTC21 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC20 register provides eight of the twelve bits available in the programmable pulse train. The PTC21 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC20 register with a 45h and the PTC21 register with a C1h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 125 ms. If the default values of this register or the PTC21 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111. The following table shows the bit assignments for the Pulse Train Control 20 register. Register Name: Address: Reset Value: Bit 7:0 Bit Label PT7-0 PTC20 74h 0000_0000b Access R/W Description Pulse Train These eight bits are the first bits shifted out from 0 to 7 and define the on/off time for the flash rate. 1: defines LED on time 0: defines LED off time. 66 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.62 75h: Pulse Train Control 21 (PTC21) This register, along with the PTC20 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC20 register provides eight of the twelve bits available in the programmable pulse train. The PTC21 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC20 register with a 45h and the PTC21 register with a C1h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 125 ms. If the default values of this register or the PTC20 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111. The following table shows the bit assignments for the Pulse Train Control 21 register. Register Name: Address: Reset Value: Bit 7:6 Bit Label TPW1-0 PTC21 75h 0000_0000b Access R/W Description Train Pulse Width These two bits define the pulse width of each of the pulse train bits. The available pulse widths are as follows: TPW1 0 0 1 1 5:4 PTL1-0 R/W TPW0 0 1 0 1 Train Pulse Width 41.67 ms 55.55 ms 83.33 ms 125 ms Pulse Train Length These two bits define the pulse train length, which is the number of pulse train bits that is shifted out before returning to bit 0. The available pulse train lengths are as follows: PTL1 0 0 1 1 PTL0 0 1 0 1 Pulse Train Length 12 pulse train bits from 0 to 11 10 pulse train bits from 0 to 9 9 pulse train bits from 0 to 8 8 pulse train bits from 0 to 7 3:0 PT11-8 R/W Pulse Train These four bits are the last bits shifted out from 0 to 3 and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time. 67 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.63 76h: Pulse Train Control 30 (PTC30) This register, along with the PTC31 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC30 register provides eight of the twelve bits available in the programmable pulse train. The PTC31 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC30 register with a 45h and the PTC31 register with a C1h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 125 ms. If the default values of this register or the PTC31 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111. The following table shows the bit assignments for the Pulse Train Control 30 register. Register Name: Address: Reset Value: Bit 7:0 Bit Label PT7-0 PTC30 76h 0000_0000b Access R/W Description Pulse Train These eight bits are the first bits shifted out from 0 to 7 and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time. 68 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.64 77h: Pulse Train Control 31 (PTC31) This register, along with the PTC30 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC30 register provides eight of the twelve bits available in the programmable pulse train. The PTC31 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC30 register with a 45h and the PTC31 register with a C1h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 125 ms. If the default values of this register or the PTC30 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111. The following table shows the bit assignments for the Pulse Train Control 31 register. Register Name: Address: Reset Value: Bit 7:6 Bit Label TPW1-0 PTC31 77h 0000_0000b Access R/W Description Train Pulse Width These two bits define the pulse width of each of the pulse train bits.The available pulse widths are as follows: TPW1 0 0 1 1 5:4 PTL1-0 R/W TPW0 0 1 0 1 Train Pulse Width 41.67 ms 55.55 ms 83.33 ms 125 ms Pulse Train Length These two bits define the pulse train length, which is the number of pulse train bits that is shifted out before returning to bit 0. The available pulse train lengths are as follows: PTL1 0 0 1 1 PTL0 0 1 0 1 Pulse Train Length 12 pulse train bits from 0 to 11 10 pulse train bits from 0 to 9 9 pulse train bits from 0 to 8 8 pulse train bits from 0 to 7 3:0 PT11-8 R/W Pulse Train These four bits are the last bits shifted out from 0 to 3 and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time. 69 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.65 78h: Pulse Train Control 40 (PTC40) This register, along with the PTC41 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length and the on/off time to derive a specific visual indication. The PTC40 register provides eight of the twelve bits available in the programmable pulse train. The PTC41 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC40 register with a 45h and the PTC41 register with a 01h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 166.67 ms. If the default values of this register or the PTC41 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111. The following table shows the bit assignments for the Pulse Train Control 40 register. Register Name: Address: Reset Value: Bit 7:0 Bit Label PT7-0 PTC40 78h 0000_0000b Access R/W Description Pulse Train These eight bits are the first bits shifted out from 0 to 7 and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time. 70 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.66 79h: Pulse Train Control 41 (PTC41) This register, along with the PTC40 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC40 register provides eight of the twelve bits available in the programmable pulse train. The PTC41 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC40 register with a 45h and the PTC41 register with a 01h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 166.67 ms. If the default values of this register or the PTC40 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111. The following table shows the bit assignments for the Pulse Train Control 41 register. Register Name: Address: Reset Value: Bit 7:6 Bit Label TPW1-0 PTC41 79h 0000_0000b Access R/W Description Train Pulse Width These two bits define the pulse width of each of the pulse train bits. The available pulse widths are as follows: TPW1 0 0 1 1 5:4 PTL1-0 R/W TPW0 0 1 0 1 Train Pulse Width 41.67 ms 55.55 ms 83.33 ms 125 ms Pulse Train Length These two bits define the pulse train length, which is the number of pulse train bits that is shifted out before returning to bit 0. The available pulse train lengths are as follows: PTL1 0 0 1 1 PTL0 0 1 0 1 Pulse Train Length 12 pulse train bits from 0 to 11 10 pulse train bits from 0 to 9 9 pulse train bits from 0 to 8 8 pulse train bits from 0 to 7 3:0 PT11-8 R/W Pulse Train These four bits are the last bits shifted out from 0 to 3 and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time. 71 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.67 7Ah: Pulse Train Control 50 (PTC50) This register, along with the PTC51 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC50 register provides eight of the twelve bits available in the programmable pulse train. The PTC51 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC50 register with a 45h and the PTC51 register with a 01h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 166.67 ms. If the default values of this register or the PTC51 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111. The following table shows the bit assignments for the Pulse Train Control 50 register. Register Name: Address: Reset Value: Bit 7:0 Bit Label PT7-0 PTC50 7Ah 0000_0000b Access R/W Description Pulse Train These eight bits are the first bits shifted out from 0 to 7 and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time. 72 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.68 7Bh: Pulse Train Control 51 (PTC51) This register, along with the PTC50 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC50 register provides eight of the twelve bits available in the programmable pulse train. The PTC51 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC50 register with a 45h and the PTC51 register with a 01h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 166.67 ms. If the default values of this register or the PTC50 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111. The following table shows the bit assignments for the Pulse Train Control 51 register.) Register Name: Address: Reset Value: Bit 7:6 Bit Label TPW1-0 PTC51 7Bh 0000_0000b Access R/W Description Train Pulse Width These two bits define the pulse width of each of the pulse train bits. The available pulse widths are as follows: TPW1 0 0 1 1 5:4 PTL1-0 R/W TPW0 0 1 0 1 Train Pulse Width 41.67 ms 55.55 ms 83.33 ms 125 ms Pulse Train Length These two bits define the pulse train length, which is the number of pulse train bits that is shifted out before returning to bit 0. The available pulse train lengths are as follows: PTL1 0 0 1 1 PTL0 0 1 0 1 Pulse Train Length 12 pulse train bits from 0 to 11 10 pulse train bits from 0 to 9 9 pulse train bits from 0 to 8 8 pulse train bits from 0 to 7 3:0 PT11-8 R/W Pulse Train These four bits are the last bits shifted out from 0 to 3 and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time. 73 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.69 7Ch: Pulse Train Control 60 (PTC60) This register, along with the PTC61 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length and the on/off time to derive a specific visual indication. The PTC60 register provides eight of the twelve bits available in the programmable pulse train. The PTC61 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC60 register with a 45h and the PTC61 register with a 01h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 166.67 ms. If the default values of this register or the PTC61 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111. The following table shows the bit assignments for the Pulse Train Control 60 register. Register Name: Address: Reset Value: Bit 7:0 Bit Label PT7-0 PTC60 7Ch 0000_0000b Access R/W Description Pulse Train These eight bits are the first bits shifted out from 0 to 7 and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time. 74 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.70 7Dh: Pulse Train Control 61 (PTC61) This register, along with the PTC60 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length and the on/off time to derive a specific visual indication. The PTC60 register provides eight of the twelve bits available in the programmable pulse train. The PTC61 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC60 register with a 45h and the PTC61 register with a 01h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 166.67 ms. If the default values of this register or the PTC60 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111. The following table shows the bit assignments for the Pulse Train Control 61 register. Register Name: Address: Reset Value: Bit 7:6 Bit Label TPW1-0 PTC61 7Dh 0000_0000b Access R/W Description Train Pulse Width These two bits define the pulse width of each of the pulse train bits. The available pulse widths are as follows: TPW1 0 0 1 1 5:4 PTL1-0 R/W TPW0 0 1 0 1 Train Pulse Width 41.67 ms 55.55 ms 83.33 ms 125 ms Pulse Train Length These two bits define the pulse train length, which is the number of pulse train bits that is shifted out before returning to bit 0. The available pulse train lengths are as follows: PTL1 0 0 1 1 PTL0 0 1 0 1 Pulse Train Length 12 pulse train bits from 0 to 11 10 pulse train bits from 0 to 9 9 pulse train bits from 0 to 8 8 pulse train bits from 0 to 7 3:0 PT11-8 R/W Pulse Train These four bits are the last bits shifted out from 0 to 3 and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time. 75 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.71 7Eh: Pulse Train Control 70 (PTC70) This register, along with the PTC71 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC70 register provides eight of the twelve bits available in the programmable pulse train. The PTC71 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC70 register with a 45h and the PTC71 register with a 01h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 166.67 ms. If the default values of this register or the PTC71 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111. The following table shows the bit assignments for the Pulse Train Control 71 register. Register Name: Address: Reset Value: Bit 7:0 Bit Label PT7-0 PTC70 7Eh 0000_0000b Access R/W Description Pulse Train These eight bits are the first bits shifted out from 0 to 7 and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time. 76 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.72 7Fh: Pulse Train Control 71 (PTC71) This register, along with the PTC70 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC70 register provides eight of the twelve bits available in the programmable pulse train. The PTC71 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC70 register with a 45h and the PTC71 register with a 01h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 166.67 ms. If the default values of this register or the PTC70 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111. The following table shows the bit assignments for the Pulse Train Control 71 register. Register Name: Address: Reset Value: Bit 7:6 Bit Label TPW1-0 PTC71 7Fh 0000_0000b Access R/W Description Train Pulse Width These two bits define the pulse width of each of the pulse train bits. The available pulse widths are as follows: TPW1 0 0 1 1 5:4 PTL1-0 R/W TPW0 0 1 0 1 Train Pulse Width 41.67 ms 55.55 ms 83.33 ms 125 ms Pulse Train Length These two bits define the pulse train length, which is the number of pulse train bits that is shifted out before returning to bit 0. The available pulse train lengths are as follows: PTL1 0 0 1 1 PTL0 0 1 0 1 Pulse Train Length 12 pulse train bits from 0 to 11 10 pulse train bits from 0 to 9 9 pulse train bits from 0 to 8 8 pulse train bits from 0 to 7 3:0 PT11-8 R/W Pulse Train These four bits are the last bits shifted out from 0 to 3 and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time. 77 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.73 80h-87h: Bit Control Port 0 (BCP00-BCP07) These eight registers provide individual bit control for the Port 0 I/O pins. All register bits are identical from a control and status perspective, with the only difference being the individual I/O pin controlled and the presence of the bypass function. The Data Direction (bit 1) and General-Purpose Data (bit 0) bits are effectively the same bits found in the DDP0 and GPD0 registers, with parallel read and write paths. The following table shows the bit assignments for the Bit Control Port 0 registers. Register Name: Address: Reset Value: Bit 7 Bit Label PTE BCP00-BCP07 80h - 87h 0000_001Xb Access R/W Description Pulse Train Enable This bit, along with the FS (Function Select) bits, enables one of eight pulse train circuits controlled by the pulse train registers PTC00 through PTC71 (70h through 7Fh) as the output drive function for this I/O pin. When this bit is set, the FS bits select one of eight pulse train circuits instead of the normal fixed-rate LED flashing circuits or the normal output drive mode. For the various LED drive control modes, see Table 5, page 80. After a reset or power on, this bit is cleared. 6:5 BYP1-0 R/W Bypass Select These two bits determine the bypass function of the odd-numbered I/O pins P0.7, P0.5, P0.3, and P0.1. Setting either or both of these bits causes the I/O pin to be configured as an output that reflects the input state of the corresponding even-numbered I/O pins P0.6, P0.4, P0.2, and P0.0. As an example, P0.1 can be configured as an output that follows the signal applied to the P0.0 input. These two register bits only appear in the odd-numbered bit control registers BCP07, BCP05, BCP03, and BCP01. For the available output drive combinations, see Table 4, page 80. Note: These bits are only used when the bypass function is desired. They should not be set when normal GPIO operation, PBC operation, or fan speed monitoring are selected through the appropriate registers or through the use of the FS, DD, and GPD bits. The PWM function (Port 0 only) and bypass function are the highest priority controls for the appropriate I/O pin. The next highest priorities are the PBC function (Port 3 through Port 6) and fan speed monitoring (Port 1 and Port 2). The lowest priorities are the bit control features found in the GPD, DD, and BCP registers. Only one mode of operation should be enabled for each I/O pin at any time. If a mode change is desired, first disable the existing mode, then enable the new mode. 78 of 134 Revision 4.1 January 2008 VSC056 Data Sheet Bit 4:2 Bit Label FS2-0 Access R/W Description Function Select These three bits, along with the PTE, DD, and GPD bits, determine the function of each I/O pin. When configured as an output, the FS2-0 bits determine the rate at which the high current drive I/O toggles, providing a simple mechanism for flashing LEDs. The DD and GPD bits can be used to drive each I/O individually and to take the place of the byte wide controls found in the DD and GPD registers. Note that the DD bit is always de-asserted to configure the I/O as an output. Asserting the DD bit tri-states the I/O and effectively configures the I/O as an input. The six bits allow the user to select one of seven flash rates or eight user-programmable pulse trains, as well as to drive the LED both on and off. The output can be enabled to drive in an open-source (output drives to VDD with an external pulldown resistor) or open-drain (output drives to VSS with an external pull-up) configuration when using the flashing mechanism. For available combinations to drive an LED, see Table 5, page 80. When configured as an input, the DD bit is asserted. These bits determine the type of I/O pin edge transition that generates an interrupt condition. Transition detectors within the device filter the changes observed at the I/O pin and determine if a valid transition has occurred. If a valid transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. For available input edge combinations, see Table 6, page 81. Note: When configuring an I/O pin from an output to an input with interrupt enabled, it is recommended that the data direction change and interrupt enabling be accomplished with separate register write operations. This guarantees that any I/O transition that occurs as a result of the data direction change, which may rely on the weak internal pull-up resistor, does not generate an unexpected interrupt. 1 DD R/W Data Direction This bit determines the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. To implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. After a reset or power on, these bits are set to a binary 1, enabling the I/O as an input with weak pull-up. 0 GPD R/W General-Purpose Data When the I/O pin has been enabled as an output, writing this bit determines the data value that is present on the corresponding I/O pin. If the I/O pin is enabled as an input, reading this register bit represents the current voltage applied to the pin. At no time does this bit directly represent the value latched into the data register. If the pin is enabled as an input and there is no signal applied, a weak internal pull-up resistor holds the pin at a binary 1. After a reset or power on, this register bit is set to a binary 1, however, the value returned from a register read is the level applied to the pin since each pin is an input by default. 79 of 134 Revision 4.1 January 2008 VSC056 Data Sheet Table 4 shows the available output drive combinations. Table 4. Bypass Driving Modes BYP0 0 0 1 1 BYP1 0 1 0 1 Bypass Driving Mode Normal GPIO operation, control is defined by the FS2-0, DD, and GPD bits Open-drain drive, active driver to VSS only Open-drain source, active driver to VDD only Totem pole drive, active driver to VSS and VDD Table 5 shows the available combinations that can be used to drive an LED. Table 5. LED Options PTE 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 FS2 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 FS1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 FS0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DD 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPD X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I/O State Input with weak internal pull-up resistor, default state Output driven LOW to VSS Output toggling at 0.25 Hz, drive to VSS only Output toggling at 0.33 Hz, drive to VSS only Output toggling at 0.50 Hz, drive to VSS only Output toggling at 1.00 Hz, drive to VSS only Output toggling at 2.00 Hz, drive to VSS only Output toggling at 3.08 Hz, drive to VSS only Output toggling at 4.00 Hz, drive to VSS only Pulse Train 0 selected, drive to VSS only Pulse Train 1 selected, drive to VSS only Pulse Train 2 selected, drive to VSS only Pulse Train 3 selected, drive to VSS only Pulse Train 4 selected, drive to VSS only Pulse Train 5 selected, drive to VSS only Pulse Train 6 selected, drive to VSS only Pulse Train 7 selected, drive to VSS only Output driven HIGH to VDD Output toggling at 0.25 Hz, drive to VDD only Output toggling at 0.33 Hz, drive to VDD only Output toggling at 0.50 Hz, drive to VDD only Output toggling at 1.00 H, drive to VDD only Output toggling at 2.00 Hz, drive to VDD only Output toggling at 3.08 Hz, drive to VDD only Output toggling at 4.00 Hz, drive to VDD only Pulse Train 0 selected, drive to VDD only Pulse Train 1 selected, drive to VDD only Pulse Train 2 selected, drive to VDD only Pulse Train 3 selected, drive to VDD only Pulse Train 4 selected, drive to VDD only Pulse Train 5 selected, drive to VDD only 80 of 134 Revision 4.1 January 2008 VSC056 Data Sheet Table 5. LED Options (continued) PTE 1 1 FS2 1 1 FS1 1 1 FS0 0 1 DD 0 0 GPD 1 1 I/O State Pulse Train 6 selected, drive to VDD only Pulse Train 7 selected, drive to VDD only Table 6 shows the available input edge combinations. Table 6. Input Edge Combinations FS2 0 X X X 1 FS1 0 0 1 1 0 FS0 0 1 0 1 0 DD 1 1 1 1 1 GPD X X X X X Interrupt Condition No interrupt generated, default Interrupt generated on a rising edge Interrupt generated on a falling edge Interrupt generated on either edge No interrupt generated 3.2.74 88h: Pulse Train Control 80 (PTC80) This register, along with the PTC81 register, provides a user-programmable LED flashing pulse train that defines the 0.33 Hz flash rate (selectable in the bit control registers) at power on. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC80 register provides eight of the twelve bits available in the programmable pulse train. The PTC81 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC80 register with a 45h and the PTC81 register with a 01h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 166.67 ms. If the default values of this register or the PTC51 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111. The following table shows the bit assignments for the Pulse Train Control 80 register. Register Name: Address: Reset Value: Bit 7:0 Bit Label PT7-0 PTC80 88h 0011_1111b Access R/W Description Pulse Train These eight bits are the first bits shifted out from 0 to 7 and define the on/off time for the 0.33 Hz (FS2-FS0 = 010b in the selected Bit Control register) flash rate. 1: defines LED on time. 0: defines LED off time. 81 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.75 89h: Pulse Train Control 81 (PTC81) This register, along with the PTC80 register, provides a user-programmable LED flashing pulse train that defines the 0.33 Hz flash rate (selectable in the bit control registers) at power on. The user can adjust the pulse duration, pulse train length, and the on/off time to derive a specific visual indication. The PTC80 register provides eight of the twelve bits available in the programmable pulse train. The PTC81 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC80 register with a 45h and the PTC81 register with a 01h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 166.67 ms. If the default values of this register or the PTC80 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111. The following table shows the bit assignments for the Pulse Train Control 81 register. Register Name: Address: Reset Value: Bit 7:6 Bit Label TPW1-0 PTC81 89h 0100_0000b Access R/W Description Train Pulse Width These two bits define the pulse width of each of the pulse train bits. The available pulse widths are as follows: TPW1 0 0 1 1 5:4 PTL1-0 R/W Pulse Train Length These two bits define the pulse train length, which is the number of pulse train bits that is shifted out before returning to bit 0. The available pulse train lengths are as follows: PTL1 0 0 1 1 3:0 PT11-8 R/W Pulse Train These four bits are the last bits shifted out from 0 to 3 and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time. PTL0 0 1 0 1 Pulse Train Length 12 pulse train bits from 0 to 11 10 pulse train bits from 0 to 9 9 pulse train bits from 0 to 8 8 pulse train bits from 0 to 7 TPW0 0 1 0 1 Train Pulse Width 166.67 ms 250.0 ms 333.3 ms 500.0 ms 82 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.76 8Ch: Pulse Train Control 90 (PTC90) This register, along with the PTC91 register, provides a user-programmable LED flashing pulse train that defines the 0.25 Hz flash rate (selectable in the bit control registers) at power on. The user can adjust the pulse duration, pulse train length, and the on/off time to derive a specific visual indication. The PTC90 register provides eight of the twelve bits available in the programmable pulse train. The PTC91 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC90 register with a 45h and the PTC91 register with a 01h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 166.67 ms. If the default values of this register or the PTC91 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111. The following table shows the bit assignments for the Pulse Train Control 90 registers. Register Name: Address: Reset Value: Description Bit 7:0 Bit Label PT7-0 PTC90 8Ch 0011_1111b Pulse Train Control 90 Access R/W Description Pulse Train These eight bits are the first bits shifted out from 0 to 7 and define the on/off time for the 0.25 Hz (FS2-FS0 = 001b in the selected bit control register) flash rate. 1: defines LED on time. 0: defines LED off time. 83 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.77 8Dh: Pulse Train Control 91 (PTC91) This register, along with the PTC90 register, provides a user-programmable LED flashing pulse train that defines the 0.25 Hz flash rate (selectable in the bit control registers) at power on. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC90 register provides eight of the twelve bits available in the programmable pulse train. The PTC91 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. As an example, the pulse train can be used to develop a visual heartbeat indication by programming the PTC90 register with a 45h and the PTC91 register with a 01h. This combination develops a pulse train with two blinks followed by a gap with the on times of the LED equal to 166.67 ms. If the default values of this register or the PTC90 register are modified, and synchronization to other LED flash rates is desired, the SYNC# pin must be enabled. To enable the SYNC# pin, tie the SYNCEN pin to VDD, connect an external 10 kΩ pull-up resistor to the SYNC# pin, and place the proper synchronization value in bits 3:0 of the Clock Select Control register. For information on the Clock Select Control register, see “FDh: Clock Select Control (CSC),” page 111. The following table shows the bit assignments for the Pulse Train Control 91 registers. Register Name: Address: Reset Value: Bit 7:6 Bit Label TPW1-0 PTC91 8Bh 1000_0000b Access R/W Description Train Pulse Width These two bits define the pulse width of each of the pulse train bits. The available pulse widths are as follows: TPW1 0 0 1 1 5:4 PTL1-0 R/W TPW0 0 1 0 1 Train Pulse Width 166.67 ms 250.0 ms 333.3 ms 500.0 ms Pulse Train Length These two bits define the pulse train length, which is the number of pulse train bits that is shifted out before returning to bit 0. The available pulse train lengths are given below. PTL1 0 0 1 1 PTL0 0 1 0 1 Pulse Train Length 12 pulse train bits from 0 to 11 10 pulse train bits from 0 to 9 9 pulse train bits from 0 to 8 8 pulse train bits from 0 to 7 3:0 PT11-8 R/W Pulse Train These four bits are the last bits shifted out from 0 to 3 and define the on/off time for the flash rate. 1: defines an LED on time. 0: defines an LED off time. 84 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.78 90h-97h: Bit Control Port 1 (BCP10-BCP17) These eight registers function the same as the Bit Control Port 0 register except they provide individual bit control for the Port 1 I/O pins. All register bits are identical from a control and status perspective, with the only difference being the individual I/O pin controlled and the presence of the bypass function. The Data Direction (bit 1) and General-Purpose Data (bit 0) bits are effectively the same bits found in the DDP0 and GPD0 registers, with parallel read and write paths. For information about the functionality of the Bit Control Port 0 registers, see “80h-87h: Bit Control Port 0 (BCP00-BCP07),” page 78. The following table shows the bit assignments for the Bit Control Port 1 registers. Register Name: Address: Reset Value: Bit 7 Bit Label PTE BCP10-BCP17 90h-97h 0000_001Xb Access R/W Description Pulse Train Enable This bit, along with the FS bits, enables one of eight pulse train circuits controlled by the pulse train registers, PTC00 through PTC71 (70h through 7Fh), as the output drive function for this I/O pin. When this bit is set, the FS bits select one of eight pulse train circuits instead of the normal fixed-rate LED flashing circuits or the normal output drive mode. For the various LED drive control modes, see Table 5, page 80. After a reset or power on, this bit is cleared. 6:5 BYP1-0 R/W Bypass Select These two bits determine the bypass function of the odd-numbered I/O pins P0.7, P0.5, P0.3, and P0.1. Setting either or both of these bits causes the I/O pin to be configured as an output that reflects the input state of the corresponding even-numbered I/O pins P0.6, P0.4, P0.2, and P0.0. As an example, P0.1 can be configured as an output that follows the signal applied to the P0.0 input. These two register bits only appear in the odd-numbered bit control registers BCP07, BCP05, BCP03, and BCP01. For available output drive combinations, see Table 4, page 80. Note: These bits are only used when the bypass function is desired. They should not be set when normal GPIO operation, PBC operation, or fan speed monitoring are selected through the appropriate registers or through the use of the FS, DD, and GPD bits. The PWM function (Port 0 only) and bypass function are the highest priority controls for the appropriate I/O pin. The next highest priorities are the PBC function (Port 3 through Port 6) and fan speed monitoring (Port 1 and Port 2). The lowest priorities are the bit control features found in the GPD, DD, and BCP registers. Only one mode of operation should be enabled for each I/O pin at any time. If a mode change is desired, first disable the existing mode and then enable the new mode. 85 of 134 Revision 4.1 January 2008 VSC056 Data Sheet Bit 4:2 Bit Label FS2-0 Access R/W Description Function Select These three bits, along with the PTE, DD, and GPD bits, determine the function of each I/O pin. When configured as an output, the FS2-0 bits determine the rate at which the high current drive I/O toggles, providing a simple mechanism for flashing LEDs. The DD and GPD bits can be used to drive each I/O individually and to take the place of the byte wide controls found in the DD and GPD registers. Note that the DD bit is always de-asserted to configure the I/O as an output. Asserting the DD bit tri-states the I/O and effectively configures the I/O as an input. The six bits allow the user to select one of seven flash rates or eight user-programmable pulse trains, as well as to drive the LED both on and off. The output can be enabled to drive in an open-source (output drives to VDD with an external pull-down resistor) or open-drain (output drives to VSS with an external pull-up) configuration when using the flashing mechanism. For available combinations to drive an LED, see Table 5, page 80. When configured as an input, the DD bit is asserted. These bits determine the type of I/O pin edge transition that generates an interrupt condition. Transition detectors within the device filter the changes observed at the I/O pin and determine if a valid transition has occurred. If a valid transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. For available input edge combinations, see Table 6, page 81. Note: When configuring an I/O pin from an output to an input with interrupt enabled, it is recommended that the data direction change and interrupt enabling be accomplished with separate register write operations. This guarantees that any I/O transition that occurs as a result of the data direction change, which may rely on the weak internal pull-up resistor, does not generate an unexpected interrupt. 1 DD R/W Data Direction This bit determines the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. To implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. After a reset or power on, these bits are set to a binary 1, enabling the I/O as an input with weak pull-up. 0 GPD R/W General-Purpose Data When the I/O pin has been enabled as an output, writing this bit determines the data value that is present on the corresponding I/O pin. If the I/O pin has been enabled as an input, reading this register bit represents the current voltage applied to the pin. At no time does this bit directly represent the value latched into the data register. If the pin is enabled as an input and there is no signal applied, a weak internal pull-up resistor holds the pin at a binary 1. After a reset or power on, this register bit is set to a binary 1; however, the value returned from a register read is the level applied to the pin since each pin is an input by default. 86 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.79 98h-9Fh: Pulse-Width Modulation Control (PWMC0-PWMC7) These eight registers provide a pulse-width modulated output that can optionally be made available on each of the Port 1 I/O pins. Configurations for these I/O pins that may have been previously enabled through other control registers are overridden if either one or both of the PWBF bits are set. The PWBF bits have higher priority control over the Port 1 I/O pins than any other mode of operation. The pulse-width modulated outputs are based on a 32-step counter and provide values from a 3.125% to a 100% duty cycle in 3.125% increments. The following table shows the bit assignments for the Pulse-Width Modulation Control registers. Register Name: Address: Reset Value: Bit 6:5 Bit Label PWBF1-0 PWMC0-PWMC7 98h-9Fh X000_0000b Access R/W Description Pulse-Width Base Frequency These two bits determine the base operating frequency of the pulse-width modulated output. These frequencies vary with the input clock rate and are nominally based on a 10.0 MHz clock source. The available base frequencies are as follows. PWBF1 0 0 1 1 4:0 PWP4-0 R/W PWBF0 0 1 0 1 Pulse-Width Base Frequency Normal operation—control is provided through GPD1/DDP1 or BCP1 26 kHz base frequency 52 kHz base frequency 104 kHz base frequency Pulse-Width Percentage These five bits determine the percentage of high time that the output pulse contains. There are 32 steps that can be adjusted in 3.125% increments. For the available percentages of high time, see Table 7, page 87. The following table shows the available percentages of high time for the pulse width for the PWP4-0 bits. Table 7. Pulse-Width Percentages PWP4 0 0 0 0 0 0 0 0 0 0 0 0 0 PWP3 0 0 0 0 0 0 0 0 1 1 1 1 1 PWP2 0 0 0 0 1 1 1 1 0 0 0 0 1 PWP1 0 0 1 1 0 0 1 1 0 0 1 1 0 PWP0 0 1 0 1 0 1 0 1 0 1 0 1 0 Pulse-Width Percentage 3.125% on/high time 6.25% on/high time 9.375% on/high time 12.5% on/high time 15.625% on/high time 18.75% on/high time 21.875% on/high time 25.0% on/high time 28.125% on/high time 31.25% on/high time 34.375% on/high time 37.5% on/high time 40.625% on/high time 87 of 134 Revision 4.1 January 2008 VSC056 Data Sheet Table 7. Pulse-Width Percentages (continued) PWP4 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PWP3 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PWP2 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PWP1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PWP0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Pulse-Width Percentage 43.75% on/high time 46.875% on/high time 50.0% on/high time 53.125% on/high time 56.25% on/high time 59.375% on/high time 62.5% on/high time 65.625% on/high time 68.75% on/high time 71.875% on/high time 75.0% on/high time 78.125% on/high time 81.25% on/high time 84.375% on/high time 87.5% on/high time 90.625% on/high time 93.75% on/high time 96.875% on/high time 100% on/high time 88 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.80 A0h-A7h: Bit Control Port 2 (BCP20-BCP27) These eight registers function the same as the Bit Control Port 0 registers except they provide individual bit control for the Port 2 I/O pins. All register bits are identical from a control and status perspective, with the only difference being the individual I/O pin controlled and the presence of the bypass function. The Data Direction (bit 1) and General-Purpose Data (bit 0) bits are effectively the same bits found in the DDP0 and GPD0 registers, with parallel read and write paths. For information about the functionality of the Bit Control Port 0 registers, see “80h-87h: Bit Control Port 0 (BCP00-BCP07),” page 78. The following table shows the bit assignments for the Bit Control Port 2 registers. Register Name: Address: Reset Value: Bit 7 Bit Label PTE BCP20-BCP27 A0h-A7h 0000_001Xb Access R/W Description Pulse Train Enable This bit, along with the FS bits, enables one of eight pulse train circuits controlled by the pulse train registers, PTC00 through PTC71 (70h through 7Fh), as the output drive function for this I/O pin. When the PTE bit set, the FS bits select one of eight pulse train circuits instead of the normal fixed-rate LED flashing circuits or the normal output drive mode. For the various LED drive control modes, see Table 5, page 80. After a reset or power on, this bit is cleared. 6:5 BYP1-0 R/W Bypass Select These two bits determine the bypass function of the odd-numbered I/O pins P0.7, P0.5, P0.3, and P0.1. Setting either one or both of these bits causes the I/O pin to be configured as an output that reflects the input state of the corresponding even-numbered I/O pins P0.6, P0.4, P0.2, and P0.0. As an example, P0.1 can be configured as an output that follows the signal applied to the P0.0 input. These two register bits only appear in the odd-numbered bit control registers BCP07, BCP05, BCP03, and BCP01. For the available output drive combinations, see Table 4, page 80. Note: These bits are only used when the bypass function is desired. They should not be set when normal GPIO operation, PBC operation, or fan speed monitoring are selected through the appropriate registers or through the use of the FS, DD, and GPD bits. The PWM function (Port 0 only) and bypass function are the highest priority controls for the appropriate I/O pin. The next highest priorities are the PBC function (Port 3 through Port 6) and fan speed monitoring (Port 1 and Port 2). The lowest priorities are the bit control features found in the GPD, DD, and BCP registers. Only one mode of operation should be enabled for each I/O pin at any time. If a mode change is desired, first disable the existing mode, then enable the new mode. 89 of 134 Revision 4.1 January 2008 VSC056 Data Sheet Bit 4:2 Bit Label FS2-0 Access R/W Description Function Select These three bits, along with the PTE, DD, and GPD bits, determine the function of each I/O pin. When configured as an output, the FS2-0 bits determine the rate at which the high current drive I/O toggles, providing a simple mechanism for flashing LEDs. The DD and GPD bits can be used to drive each I/O individually and to take the place of the byte wide controls found in the DD and GPD registers. Note that the DD bit is always de-asserted to configure the I/O as an output. Asserting the DD bit tri-states the I/O and effectively configures the I/O as an input. The six bits allow the user to select one of seven flash rates or eight userprogrammable pulse trains, as well as to drive the LED both on and off. The output can be enabled to drive in an open-source (output drives to VDD with an external pull-down resistor) or open-drain (output drives to VSS with an external pull-up) configuration when using the flashing mechanism. For available combinations to drive an LED, see Table 5, page 80. When configured as an input, the DD bit is asserted. These bits determine the type of I/O pin edge transition that generates an interrupt condition. Transition detectors within the device filter the changes observed at the I/O pin and determine if a valid transition has occurred. If a valid transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. For available input edge combinations, see Table 6, page 81. Note: When configuring an I/O pin from an output to an input with interrupt enabled, it is recommended that the data direction change and interrupt enabling be accomplished with separate register write operations. This guarantees that any I/O transition that occurs as a result of the data direction change, which may rely on the weak internal pull-up resistor, does not generate an unexpected interrupt. 1 DD R/W Data Direction This bit determines the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. To implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. After a reset or power on, these bits are set to a binary 1, enabling the I/O as an input with weak pull-up. 0 GPD R/W General-Purpose Data When the I/O pin is enabled as an output, writing this bit determines the data value, which is present on the corresponding I/O pin. If the I/O pin has been enabled as an input, reading this register bit represents the current voltage applied to the pin. At no time does this bit directly represent the value latched into the data register. If the pin is enabled as an input and there is no signal applied, a weak internal pull-up resistor holds the pin at a binary 1. After a reset or power on, this register bit is set to a binary 1; however, the value returned from a register read is the level applied to the pin since each pin is an input by default. 90 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.81 B0h-B7h: Bit Control Port 3 (BCP30-BCP37) These eight registers function the same as the Bit Control Port 0 registers except they provide individual bit control for the Port 3 I/O pins. All register bits are identical from a control and status perspective, with the only difference being the individual I/O pin controlled and the presence of the bypass function. The Data Direction (bit 1) and General-Purpose Data (bit 0) bits are effectively the same bits found in the DDP0 and GPD0 registers, with parallel read and write paths. Additionally, the control of the individual I/O pins assigned to these registers can be overridden by the PBC0, PBC1, PBC2, and PBC3 registers when port bypass control is required. For information about the functionality of the Bit Control Port 0 registers, see “80h-87h: Bit Control Port 0 (BCP00-BCP07),” page 78. The following table shows the bit assignments for the Bit Control Port 3 registers. Register Name: Address: Reset Value: Bit 7 Bit Label PTE BCP30-BCP37 B0h-B7h 0000_001Xb Access R/W Description Pulse Train Enable This bit, along with the FS bits, enables one of eight pulse train circuits controlled by the pulse train registers, PTC00 through PTC71 (70h through 7Fh), as the output drive function for this I/O pin. When this bit is set, the FS bits select one of eight pulse train circuits instead of the normal fixed-rate LED flashing circuits or the normal output drive mode. For the various LED drive control modes, see Table 5, page 80. After a reset or power on, this bit is cleared. 6:5 BYP1-0 R/W Bypass Select These two bits determine the bypass function of the odd-numbered I/O pins P0.7, P0.5, P0.3, and P0.1. Setting either or both of these bits causes the I/O pin to be configured as an output that reflects the input state of the corresponding even-numbered I/O pins P0.6, P0.4, P0.2, and P0.0. As an example, P0.1 can be configured as an output that follows the signal applied to the P0.0 input. These two register bits only appear in the odd-numbered bit control registers BCP07, BCP05, BCP03, and BCP01. For the available output drive combinations, see Table 4, page 80. Note: These bits are only used when the bypass function is desired. They should not be set when normal GPIO operation, PBC operation, or fan speed monitoring are selected through the appropriate registers or through the use of the FS, DD, and GPD bits. The PWM function (Port 0 only) and bypass function are the highest priority controls for the appropriate I/O pin. The next highest priorities are the PBC function (Port 3 through Port 6) and fan speed monitoring (Port 1 and Port 2). The lowest priorities are the bit control features found in the GPD, DD, and BCP registers. Only one mode of operation should be enabled for each I/O pin at any time. If a mode change is desired, first disable the existing mode, then enable the new mode. 91 of 134 Revision 4.1 January 2008 VSC056 Data Sheet Bit 4:2 Bit Label FS2-0 Access R/W Description Function Select These three bits, along with the PTE, DD, and GPD bits, determine the function of each I/O pin. When configured as an output, the FS2-0 bits determine the rate at which the high current drive I/O toggles, providing a simple mechanism for flashing LEDs. The DD and GPD bits can be used to drive each I/O individually and to take the place of the byte wide controls found in the DD and GPD registers. Note that the DD bit is always de-asserted to configure the I/O as an output. Asserting the DD bit tri-states the I/O and effectively configures the I/O as an input. The six bits allow the user to select one of seven flash rates or eight userprogrammable pulse trains, as well as to drive the LED both on and off. The output can be enabled to drive in an open-source (output drives to VDD with an external pull-down resistor) or open-drain (output drives to VSS with an external pull-up) configuration when using the flashing mechanism. For available combinations to drive an LED, see Table 5, page 80. When configured as an input, the DD bit is asserted. These bits determine the type of I/O pin edge transition that generates an interrupt condition. Transition detectors within the device filter the changes observed at the I/O pin and determine if a valid transition has occurred. If a valid transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. For available input edge combinations, see Table 6, page 81. Note: When configuring an I/O pin from an output to an input with interrupt enabled, it is recommended that the data direction change and interrupt enabling be accomplished with separate register write operations. This guarantees that any I/O transition that occurs as a result of the data direction change, which may rely on the weak internal pull-up resistor, does not generate an unexpected interrupt. 1 DD R/W Data Direction This bit determines the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. To implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. After a reset or power on, these bits are set to a binary 1, enabling the I/O as an input with weak pull-up. 0 GPD R/W General-Purpose Data When the I/O pin is enabled as an output, writing this bit determines the data value that is present on the corresponding I/O pin. If the I/O pin is enabled as an input, reading this register bit represents the current voltage applied to the pin. At no time does this bit directly represent the value latched into the data register. If the pin is enabled as an input and there is no signal applied, a weak internal pull-up resistor holds the pin at a binary 1. After a reset or power on, this register bit is set to a binary 1; however, the value returned from a register read is the level applied to the pin since each pin is an input by default. 92 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.82 C0h-C7h: Bit Control Port 4 (BCP40-BCP47) These eight registers function the same as the Bit Control Port 0 registers except they provide individual bit control for the Port 4 I/O pins. All register bits are identical from a control and status perspective, with the only difference being the individual I/O pin controlled and the presence of the bypass function. The Data Direction (bit 1) and General-Purpose Data (bit 0) bits are effectively the same bits found in the DDP0 and GPD0 registers, with parallel read and write paths. Additionally, the control of the individual I/O pins assigned to these registers can be overridden by the PBC4, PBC5, PBC6, and PBC7 registers when port bypass control is required. For information about the functionality of the Bit Control Port 0 registers, see “80h-87h: Bit Control Port 0 (BCP00-BCP07),” page 78. The following table shows the bit assignments for the Bit Control Port 4 registers. Register Name: Address: Reset Value: Bit 7 Bit Label PTE BCP40-BCP47 C0h-C7h 0000_001Xb Access R/W Description Pulse Train Enable This bit, along with the FS bits, enables one of eight pulse train circuits controlled by the pulse train registers, PTC00 through PTC71 (70h through 7Fh), as the output drive function for this I/O pin. When this bit is set, the FS bits select one of eight pulse train circuits instead of the normal fixed-rate LED flashing circuits or the normal output drive mode. For the various LED drive control modes, see Table 5, page 80. After a reset or power on, this bit is cleared. 6:5 BYP1-0 R/W Bypass Select These two bits determine the bypass function of the odd-numbered I/O pins P0.7, P0.5, P0.3, and P0.1. Setting either or both of these bits causes the I/O pin to be configured as an output that reflects the input state of the corresponding even-numbered I/O pins P0.6, P0.4, P0.2, and P0.0. As an example, P0.1 can be configured as an output that follows the signal applied to the P0.0 input. These two register bits only appear in the odd-numbered bit control registers BCP07, BCP05, BCP03, and BCP01. For the available output drive combinations, see Table 4, page 80. Note: These bits are only used when the bypass function is desired. They should not be set when normal GPIO operation, PBC operation, or fan speed monitoring are selected through the appropriate registers or through the use of the FS, DD, and GPD bits. The PWM function (Port 0 only) and bypass function are the highest priority controls for the appropriate I/O pin. The next highest priorities are the PBC function (Port 3 through Port 6) and fan speed monitoring (Port 1 and Port 2). The lowest priorities are the bit control features found in the GPD, DD, and BCP registers. Only one mode of operation should be enabled for each I/O pin at any time. If a mode change is desired, first disable the existing mode, then enable the new mode. 93 of 134 Revision 4.1 January 2008 VSC056 Data Sheet Bit 4:2 Bit Label FS2-0 Access R/W Description Function Select These three bits, along with the PTE, DD, and GPD bits, determine the function of each I/O pin. When configured as an output, the FS2-0 bits determine the rate at which the high current drive I/O toggles, providing a simple mechanism for flashing LEDs. The DD and GPD bits can be used to drive each I/O individually and to take the place of the byte wide controls found in the DD and GPD registers. Note that the DD bit is always de-asserted to configure the I/O as an output. Asserting the DD bit tri-states the I/O and effectively configures the I/O as an input. The six bits allow the user to select one of seven flash rates or eight user-programmable pulse trains, as well as to drive the LED both on and off. The output can be enabled to drive in an open-source (output drives to VDD with an external pull-down resistor) or open-drain (output drives to VSS with an external pull-up) configuration when using the flashing mechanism. For available combinations to drive an LED, see Table 5, page 80. When configured as an input, the DD bit is asserted. These bits determine the type of I/O pin edge transition that generates an interrupt condition. Transition detectors within the device filter the changes observed at the I/O pin and determine if a valid transition has occurred. If a valid transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. For available input edge combinations, see Table 6, page 81. Note: When configuring an I/O pin from an output to an input with interrupt enabled, it is recommended that the data direction change and interrupt enabling be accomplished with separate register write operations. This guarantees that any I/O transition that occurs as a result of the data direction change, which may rely on the weak internal pull-up resistor, does not generate an unexpected interrupt. 1 DD R/W Data Direction This bit determines the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. To implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. After a reset or power on, these bits are set to a binary 1, enabling the I/O as an input with weak pull-up. 0 GPD R/W General-Purpose Data When the I/O pin is enabled as an output, writing this bit determines the data value that is present on the corresponding I/O pin. If the I/O pin is enabled as an input, reading this register bit represents the current voltage applied to the pin. At no time does this bit directly represent the value latched into the data register. If the pin is enabled as an input and there is no signal applied, a weak internal pull-up resistor holds the pin at a binary 1. After a reset or power on, this register bit is set to a binary 1; however, the value returned from a register read is the level applied to the pin since each pin is an input by default. 94 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.83 CCh: General-Purpose Timer Count 0 (GPTC0) The following table shows the bit assignments for the General-Purpose Timer Count 0 register. Register Name: Address: Reset Value: Bit 7:0 Bit Label TC7-0 GPTC0 CCh 0000_0000b Access R/W Description Timer Count These eight bits are part of the 24-bit general-purpose timer down counter initial count value. Writing to this register causes the timer to update and to initiate a countdown from the new value if the timer has been enabled in the GPTE register. Clearing this register, along with the GPTC1 and GPTC2 registers, stops the down counter and disables the interrupt generation logic. After a reset or power on, these bits are cleared. 3.2.84 CDh: General-Purpose Timer Count 1 (GPTC1) The following table shows the bit assignments for the General-Purpose Timer Count 1 register. Register Name: Address: Reset Value: Bit 7:0 Bit Label TC15-8 GPTC1 CDh 0000_0000b Access R/W Description Timer Count These eight bits are part of the 24-bit general-purpose timer down counter initial count value. Writing to this register causes the timer to update and to initiate a countdown from the new value if the timer has been enabled in the GPTE register. Clearing this register, along with the GPTC0 and GPTC2 registers, stops the down counter and disables the interrupt generation logic. After a reset or power on, these bits are cleared. 95 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.85 CEh: General-Purpose Timer Count 2 (GPTC2) The following table shows the bit assignments for the General-Purpose Timer Count 2 register. Register Name: Address: Reset Value: Bit 7:0 Bit Label TC23-16 GPTC2 CEh 0000_0000b Access R/W Description Timer Count These eight bits are part of the 24-bit general-purpose timer down counter initial count value. Writing to this register causes the timer to update and initiate a countdown from the new value if the timer has been enabled in the GPTE register. Clearing this register, along with the GPTC0 and GPTC1 registers, stops the down counter and disables the interrupt generation logic. After a reset or power on, these bits are cleared. 3.2.86 CFh: General-Purpose Timer Enable (GPTE) The following table shows the bit assignments for the General-Purpose Timer Enable register. Register Name: Address: Reset Value: Bit 7:1 0 Bit Label RES GPTE GPTE CFh 0000_0000b Access R R/W Description Reserved. General-Purpose Timer Enable This bit enables the general-purpose timer to down count and generate an interrupt when the timer reaches zero. The general-purpose timer down counts using a clock source that is a divide-by-three of the core clock (8.0 MHz to 12.5 MHz), resulting in a timer count resolution of 375 ns to 240 ns. When the timer initial count is set to all 1s, the maximum timeout is greater than four seconds when using a 12.5 MHz core clock. When the 24-bit timer reaches a value of zero, the interrupt output of the VSC056 is asserted. The timer then re-loads with the initial count value found in the GPTC0, GPTC1, and GPTC2 registers and begins counting down again. Writing a value of FFh to the BCIS register clears this interrupt. After a reset or power on, this bit is cleared, disabling the timer and timer interrupt. 96 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.87 D0h-D7h: Bit Control Port 5 (BCP50-BCP57) These eight registers function the same as the eight Bit Control Port 0 registers except that they relate to the Port 5 I/O pins. In addition, the control of the individual I/O pins assigned to these registers can be overridden by the PBC8, PBC9, PBC10, and PBC11 registers when port bypass control is required. For information about the functionality of the Bit Control Port 0 registers, see “80h-87h: Bit Control Port 0 (BCP00-BCP07),” page 78. The following table shows the bit assignments for the Bit Control Port 5 registers. Register Name: Address: Reset Value: Bit 7 Bit Label PTE BCP50-BCP57 D0h-D7h 0000_001Xb Access R/W Description Pulse Train Enable This bit, along with the FS bits, enables one of eight pulse train circuits controlled by the pulse train registers, PTC00 through PTC71 (70h through 7Fh), as the output drive function for this I/O pin. When the PTE bit set, the FS bits select one of eight pulse train circuits instead of the normal fixed-rate LED flashing circuits or the normal output drive mode. For the various LED drive control modes, see Table 5, page 80. After a reset or power on, this bit is cleared. 6:5 BYP1-0 R/W Bypass Select These two bits determine the bypass function of the odd-numbered I/O pins P0.7, P0.5, P0.3, and P0.1. Setting either or both of these bits causes the I/O pin to be configured as an output that reflects the input state of the corresponding even-numbered I/O pins P0.6, P0.4, P0.2, and P0.0. As an example, P0.1 can be configured as an output that follows the signal applied to the P0.0 input. These two register bits only appear in the odd-numbered bit control registers BCP07, BCP05, BCP03, and BCP01. For the available output drive combinations, see Table 4, page 80. Note: These bits are only used when the bypass function is desired. They should not be set when normal GPIO operation, PBC operation, or fan speed monitoring are selected through the appropriate registers or through the use of the FS, DD, and GPD bits. The PWM function (Port 0 only) and bypass function are the highest priority controls for the appropriate I/O pin. The next highest priorities are the PBC function (Port 3 through Port 6) and fan speed monitoring (Port 1 and Port 2). The lowest priorities are the bit control features found in the GPD, DD, and BCP registers. Only one mode of operation should be enabled for each I/O pin at any time. If a mode change is desired, first disable the existing mode, then enable the new mode. 97 of 134 Revision 4.1 January 2008 VSC056 Data Sheet Bit 4:2 Bit Label FS2-0 Access R/W Description Function Select These three bits, along with the PTE, DD, and GPD bits, determine the function of each I/O pin. When configured as an output, the FS2-0 bits determine the rate at which the high current drive I/O toggles, providing a simple mechanism for flashing LEDs. The DD and GPD bits can be used to drive each I/O individually and to take the place of the byte wide controls found in the DD and GPD registers. Note that the DD bit is always de-asserted to configure the I/O as an output. Asserting the DD bit tri-states the I/O and effectively configures the I/O as an input. The six bits allow the user to select one of seven flash rates or eight userprogrammable pulse trains, as well as to drive the LED both on and off. The output can be enabled to drive in an open-source (output drives to VDD with an external pull-down resistor) or open-drain (output drives to VSS with an external pull-up) configuration when using the flashing mechanism. For available combinations to drive an LED, see Table 5, page 80. When configured as an input, the DD bit is asserted. These bits determine the type of I/O pin edge transition that generates an interrupt condition. Transition detectors within the device filter the changes observed at the I/O pin and determine if a valid transition has occurred. If a valid transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. For available input edge combinations, see Table 6, page 81. Note: When configuring an I/O pin from an output to an input with interrupt enabled, it is recommended that the data direction change and interrupt enabling be accomplished with separate register write operations. This guarantees that any I/O transition that occurs as a result of the data direction change, which may rely on the weak internal pull-up resistor, does not generate an unexpected interrupt. 1 DD R/W Data Direction This bit determines the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. To implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. After a reset or power on, these bits are set to a binary 1, enabling the I/O as an input with weak pull-up. 0 GPD R/W General-Purpose Data When the I/O pin is enabled as an output, writing this bit determines the data value that is present on the corresponding I/O pin. If the I/O pin has been enabled as an input, reading this register bit represents the current voltage applied to the pin. At no time does this bit directly represent the value latched into the data register. If the pin is enabled as an input and there is no signal applied, a weak internal pull-up resistor holds the pin at a binary 1. After a reset or power on, this register bit is set to a binary 1; however, the value returned from a register read is the level applied to the pin since each pin is an input by default. 98 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.88 E0h-E7h: Bit Control Port 6 (BCP60-BCP67) These eight registers function the same as the eight Bit Control Port 0 registers except that they relate to the Port 6 I/O pins. In addition, the control of the individual I/O pins assigned to these registers can be overridden by the PBC12, PBC13, PBC14, and PBC15 registers when port bypass control is required. For information about the functionality of the Bit Control Port 0 registers, see “80h-87h: Bit Control Port 0 (BCP00-BCP07),” page 78. The following table shows the bit assignments for the Bit Control Port 6 registers. Register Name: Address: Reset Value: Bit 7 Bit Label PTE BCP60-BCP67 E0h-E7h 0000_001Xb Access R/W Description Pulse Train Enable This bit, along with the FS bits, enables one of eight pulse train circuits controlled by the pulse train registers, PTC00 through PTC71 (70h through 7Fh), as the output drive function for this I/O pin. When the PTE bit is set, the FS bits select one of eight pulse train circuits instead of the normal fixed-rate LED flashing circuits or the normal output drive mode. For the various LED drive control modes, see Table 5, page 80. After a reset or power on, this bit is cleared. 6:5 BYP1-0 R/W Bypass Select These two bits determine the bypass function of the odd-numbered I/O pins P0.7, P0.5, P0.3, and P0.1. Setting either or both of these bits causes the I/O pin to be configured as an output that reflects the input state of the corresponding even-numbered I/O pins P0.6, P0.4, P0.2, and P0.0. As an example, P0.1 can be configured as an output that follows the signal applied to the P0.0 input. These two register bits only appear in the odd-numbered bit control registers BCP07, BCP05, BCP03, and BCP01. For the available output drive combinations, see Table 4, page 80. Note: These bits are only used when the bypass function is desired. They should not be set when normal GPIO operation, PBC operation, or fan speed monitoring are selected through the appropriate registers or through the use of the FS, DD, and GPD bits. The PWM function (Port 0 only) and bypass function are the highest priority controls for the appropriate I/O pin. The next highest priorities are the PBC function (Port 3 through Port 6) and fan speed monitoring (Port 1 and Port 2). The lowest priorities are the bit control features found in the GPD, DD, and BCP registers. Only one mode of operation should be enabled for each I/O pin at any time. If a mode change is desired, first disable the existing mode, then enable the new mode. 99 of 134 Revision 4.1 January 2008 VSC056 Data Sheet Bit 4:2 Bit Label FS2-0 Access R/W Description Function Select These three bits, along with the PTE, DD, and GPD bits, determine the function of each I/O pin. When configured as an output, the FS2-0 bits determine the rate at which the high current drive I/O toggles, providing a simple mechanism for flashing LEDs. The DD and GPD bits can be used to drive each I/O individually and to take the place of the byte wide controls found in the DD and GPD registers. Note that the DD bit is always de-asserted to configure the I/O as an output. Asserting the DD bit tri-states the I/O and effectively configures the I/O as an input. The six bits allow the user to select one of seven flash rates or eight userprogrammable pulse trains, as well as to drive the LED both on and off. The output can be enabled to drive in an open-source (output drives to VDD with an external pull-down resistor) or open-drain (output drives to VSS with an external pull-up) configuration when using the flashing mechanism. For available combinations to drive an LED, see Table 5, page 80. When configured as an input, the DD bit is asserted. These bits determine the type of I/O pin edge transition that generates an interrupt condition. Transition detectors within the device filter the changes observed at the I/O pin and determine if a valid transition has occurred. If a valid transition occurs, the INT# pin asserts and a binary value equal to the address of this register appears in the BCIS register. For available input edge combinations, see Table 6, page 81. Note: When configuring an I/O pin from an output to an input with interrupt enabled, it is recommended that the data direction change and interrupt enabling be accomplished with separate register write operations. This guarantees that any I/O transition that occurs as a result of the data direction change, which may rely on the weak internal pull-up resistor, does not generate an unexpected interrupt. 1 DD R/W Data Direction This bit determines the direction of the data flow through the I/O pin. To enable the respective I/O pin as an input, set the appropriate bit. To enable the respective I/O pin as an output, reset the appropriate bit. Each I/O pin can be individually configured as a true bidirectional function. To implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. After a reset or power on, these bits are set to a binary 1, enabling the I/O as an input with weak pull-up. 0 GPD R/W General-Purpose Data When the I/O pin has been enabled as an output, writing this bit determines the data value that is present on the corresponding I/O pin. If the I/O pin is enabled as an input, reading this register bit represents the current voltage applied to the pin. At no time does this bit directly represent the value latched into the data register. If the pin is enabled as an input and there is no signal applied, a weak internal pull-up resistor holds the pin at a binary 1. After a reset or power on, this register bit is set to a binary 1, but the value returned from a register read is the level applied to the pin since, by default, each pin is an input. 100 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.89 E8h: Master Interface Clock Divider (MICD) The following seven registers comprise the Master Interface function. This function provides the ability to re-configure 32 of the I/O pins on a pair-by-pair basis as a Master mode two-wire serial interface. Ports 4, 5, 6, and 7 can be re-configured with four interface pairs per port. Each even-numbered port pin can be configured as an SDA function, with the corresponding odd-numbered port pins configured as an SCL function. The following table shows the bit assignments for the Master Interface Clock Divider register. Register Name: Address: Reset Value: Bit 7 Bit Label MSCE MICD E8h 0X00_0000b Access R/W Description Master Interface SCL Clock Low Extend Setting this bit changes the duty cycle of the Master Interface SCL clock output from a 50% low-50% high duty cycle to a 75% low-25% high duty cycle. This allows for better matching of fast mode (400 kHz) interface timings. After a reset or power on, this bit is cleared, enabling the default duty cycle. 6 5:0 RES DIV5-0 R R/W Reserved. Master Interface Clock Divider These six bits determine the SCL clock frequency of the Master Interface. The Master Interface uses a four-cycle state machine to drive the SCL output. All timings for the Master Interface are based on this four-cycle state machine. The frequency of operation desired is based on the divider value along with the core clock frequency of the VSC056. For the various divider values that result in common frequencies of operation, see Table 8, page 101. The following table lists the various divider values that result in common frequencies of operation. Table 8. Master Interface Clock Divider Core Clock 8.0 MHz 10.0 MHz 12.5 MHz 8.0 MHz 10.0 MHz 12.5 MHz 8.0 MHz 10.0 MHz 12.5 MHz DIV5-0 27h 31h 3Eh 13h 18h 1Fh 04h 06h 07h Divider 40 50 63 20 25 32 4 7 8 SM 4 4 4 4 4 4 4 4 4 Master Interface SCL Clock Frequency 50.0 kHz 50.0 kHz 49.6 kHz 100.0 kHz 100.0 kHz 97.6 kHz 400.0 kHz 357.1 kHz 390.6 kHz 101 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.90 E9h: Master Interface Port Select (MIPS) The following table shows the bit assignments for the Master Interface Port Select register. Register Name: Address: Reset Value: Bit 7 Bit Label MIPE MIPS E9h 0X00_0000b Access R/W Description Master Interface Port Enable This bit enables the Master Interface on to the selected set of GPIO pins based on the port select and bit select bits. Setting this bit enables the interface allowing the Master Interface to transfer data over the selected GPIO pins based on register control. Clearing this bit disables the interface and returns control of the GPIO pins to other functions within this device. After a reset or power on, this bit is cleared. 6:5 4:2 RES PS2-0 R R/W Reserved. These three bits determine the port selected for Master mode two-wire serial transfers. Valid ports for the VSC056 include Port 4 (4h), Port 5 (5h), Port 6 (6h), and Port 7 (7h). Values other than those specified do not enable the interface. After a reset or power on, these bits are cleared. 1:0 BS1-0 R/W Master Interface Bit Select These two bits determine the bits within a port selected for master mode twowire serial transfers. 00b: enables the SDA function on bit 0 and the SCL function on bit 1 of the port. 01b: enables the SDA function on bit 2 and the SCL function on bit 3 of the port. 10b: enables the SDA function on bit 4 and the SCL function on bit 5 of the port. 11b: enables the SDA function on bit 6 and the SCL function on bit 7 of the port. After a reset or power on, these bits are cleared. 3.2.91 EAh: Master Interface Data (MID) The following table shows the bit assignments for the Master Interface Data register. Register Name: Address: Reset Value: Bit 7:0 Bit Label MD7-0 MID EAh 0000_0000b Access R/W Description Master Interface Data These eight bits store data to be used for serial write operations or received from serial read operations. After a reset or power on, these bits are cleared. 102 of 134 Revision 4.1 January 2008 VSC056 Data Sheet 3.2.92 EBh: Master Interface Command (MIC) The following table shows the bit assignments for the Master Interface Command register. Register Name: Address: Reset Value: Bit 7 Bit Label SDAI MIC EBh 1100_0000b Access R Description Serial Data Input This read-only bit indicates the current state of the master serial interface SDA input. 1: SDA signal is tri-stated and is being pulled HIGH by an external pull-up resistor. 0: device (including the VSC056) is actively driving a low value onto the SDA wire. After a reset or power on, this bit is unknown. 6 SDAO R/W Serial Data Output This bit provides low-level drive control of the master serial interface SDA signal. Setting this bit allows the automatic functions of this master serial interface to control the SDA output value. Clearing this bit forces a zero value onto the serial bus, regardless of the state of the automatic controls. Under normal circumstances, this bit should always be written to a 1. The read value for this bit returns the programmed wired-AND output value being driven, not the live value on the serial bus. After a reset or power on, this bit is set. 5 SRST R/W Soft Reset Setting this bit performs a soft reset operation. The soft reset operation clears all state machines and returns the master serial interface to an idle (nondriving) state with regard to SCL and SDA. The soft reset is one clock in duration. This bit is self-clearing. After a reset or power on, this bit is cleared. 4 GO R/W GO Setting this bit initiates a byte transfer on the serial bus. This bit automatically clears itself when the transfer is complete. After a reset or power on, this bit is cleared. 3 RW R/W Read/Write This bit determines whether the immediate byte to be transferred is a read or a write transaction. If this bit is set, the transfer is a read. If this bit is cleared, the transfer is a write. After a reset or power on, this bit is cleared. 2 ACK R/W Serial Bus Acknowledge This bit provides control for the acknowledge bit of a serial byte transfer. Setting this bit for a read transaction causes the serial interface to drive the ACK bit at the end of the transaction’s bit sequence. This must be used for all but the last byte of sequential read operations. Reading this bit after a write transaction has completed indicates whether or not the targeted slave device acknowledged the byte transfer. After a reset or power on, this bit is cleared. 103 of 134 Revision 4.1 January 2008 VSC056 Data Sheet Bit 1 Bit Label STO Access R/W Description Stop Condition This bit controls the STOP condition of a serial transfer. Setting this bit directs the master serial interface to generate a stop bit sequence (rising edge on SDA while SCL is HIGH) after transferring the immediate byte. This should only be done to end a telegram. After a reset or power on, this bit is cleared. 0 STA R/W Start Condition This bit provides control for the start condition of a serial transfer. Setting this bit directs the master serial interface to generate a start bit sequence (falling edge on SDA while SCL is HIGH) prior to transferring the immediate byte. This operation should be initiated at the beginning of a telegram and as required for restarts during read transactions. After a reset or power on, this bit is cleared. Operating Notes for the Master Serial Interface Encoded Two-Wire Serial Commands 52h - Read byte with stop, no acknowledge (used at the end of read telegrams) 54h - Read byte with acknowledge (used for middle bytes during sequential reads) 58h - Write byte (used for end of address writes or middle bytes of sequential writes) 59h - Write byte with start (used for the beginning of all telegrams and restarts) 5Ah - Write byte with stop (used for end of write telegrams) 60h - Soft reset The sequence for normal two-wire serial protocol compliant write operations is: 1. Issue start bit, send the slave device address and write bit (0) in the LSB. 2. Send the slave device's register address, this can zero bytes or in some slave devices this may be multiple bytes. 3. Send the byte to be written to the slave device, followed by a stop bit. Pseudo-code to perform two-wire serial protocol compliant writes using this core: Send slave device address: 1) --> MID register (data) 6) Write 58h to MIC register (command) 7) Poll the MIS register (status) until bit 0 = 1 8) Test bit 1, if set continue, if clear then the slave device did not acknowledge 104 of 134 Revision 4.1 January 2008 VSC056 Data Sheet (repeat steps 5-8 if there are multiple register address bytes or data bytes) Send data written to slave device register with a stop: 9) --> MID register (data) 10) Write 5Ah to the MIC register (command) 11) Poll the MIS register until bit 0 = 1 12) Test bit 1, if set continue, if clear then the slave device did not acknowledge The sequence for normal two-wire serial protocol compliant read operations is: 1) Issue start bit, send the slave device address and write bit (0) in LSB 2) Send the slave device's register address, this can zero bytes or in some slave devices this may be multiple bytes. 3) Issue another start bit (re-start condition), send the slave device address and read bit (1) in the LSB. 4) Read a byte from the slave device, or multiple bytes if the slave device supports sequential reads. 4a) For sequential reads, issue the Read Byte with ACK command (54h) for all but the last byte. 4b) Issue the Read Byte with stop, no ACK command (52h) for the last byte. Pseudo-code to perform two-wire serial protocol compliant reads using this core: Send slave device address: 1) --> MID register (data) 6) Write 58h to MIC register (command) 7) Poll the MIS register (status) until bit 0 = 1 8) Test bit 1, if set continue, if clear then the slave device did not acknowledge (repeat steps 5-8 if there are multiple register address bytes) Issue re-start with slave device address and read bit: 9)