5102ALP-RP-F-H

5102ALP 16-Bit, 20 KHz A/D Converter +VDIG DGND -VDIG -VDIG RT S CLKIN XOUT STBY DGND +VDIG TR K1 TR K2 CR /FIN S SS H/SDL HOLD CH1/2 S CLK +LPTBIT NC -VDIG DGND +VDIG 22 23 1 44 +VANLOG AGND -VANLOG SP LEE SCKMOD LPTS TATUS +VANLOG AIN2 -VANLOG AGND R FBUF E VR F E AIN1 OUTMOD BP/UP CODE S DATA +LPTV -LPTV -VANLOG AGND +VAN VA+ VADGND VDVD+ AGND AIN1 AIN2 CH1/2 + + VREF + TEST SCKMOD + Comparator OUTMOD CLKIN XOUT REFBUF HOLD SLEEP RST STBY CODE BP/UP CRS/FIN TRK1 TRK2 SSH/SDL SDATA Clock Generator Control Calibration SRAM SCLK Microcontroller 16-Bit charge Redistribution DAC Memory FEATURES: • Monolithic CMOS A/D converters - Inherent sampling architecture - 2-channel input multiplexer - Flexible serial output port • Conversion time - 5102A: 40 µ s • Linearity error: ±0.001% FS - Guaranteed no missing codes • Self-calibration maintains accuracy - Over time and temperature • Fully latchup protected DESCRIPTION: Maxwell Technologies’ 5102ALPRP is a 16-bit monolithic CMOS analog-to-digital converter capable of 20 kHz throughput. On-chip self-calibration achieves nonlinearity of ±0.001% of FS and guarantees 16-bit no missing codes over the entire specified temperature range. Offset and full-scale errors are minimized during the calibration cycle, eliminating the need for external trimming. The 5102ALP each consist of a 2-channel input multiplexer, DAC, conversion and calibration microcontroller, clock generator, comparator, and serial communications port. The inherent sampling architecture of the device eliminates the need for an external track and hold amplifier. Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while improving the TID performance in most space environments. This product is available with screening up to Maxwell Technologies self-defined Class K. 01.17.05 REV 3 All data sheets are subject to change without notice 1 (858) 503-3300 Fax: (858) 503-3301 - www.maxwell.com ©2005 Maxwell Technologies Inc. All rights reserved. 16-Bit, 20 KHz A/D Converter TABLE 1. 5102ALP ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, ALL VOLTAGES WITH RESPECT TO GROUND) PARAMETER DC Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog 1 5102ALP SYMBOL VD+ VDVA+ VAIIN VINA VIND TA TSTG MIN -0.3 0.3 -0.3 0.3 -(VA-) -0.3 -0.3 -15 -65 MAX 6.0 -6.0 6.0 -6.0 ±10 (VA+) 0.3 (VA+) 0.3 55 150 UNIT V Input Current, Any Pin Except Supplies 2 Analog Input Voltage (AIN and VREF pins) Digital Input Voltage Ambient Operating Temperature Storage Temperature 1. In addition, VD+ must not be greater than (VA+) 0.3V. 2. Transient currents of up to 100 mA will not cause SCR latchup. mA V V oC oC Memory TABLE 2. 5102ALP RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, ALL VOLTAGES WITH RESPECT TO GROUND) PARAMETER DC Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog Analog Reference Voltage Analog Input Voltage 1 Unipolar Bipolar SYMBOL VD+ VDVA+ VAVREF VAIN AGND -VREF --VREF VREF MIN 4.5 -4.5 4.5 -4.5 2.5 TYP 5.0 -5.0 5.0 -5.0 4.5 MAX VA+ -5.5 5.5 -5.5 (VA+) -0.5 V V UNIT V 1. The 5102ALPRP can accept input voltage up to the analog supplies (VA+ and VA-). They will produce an output of all 1s for inputs above VREF and all 0s for inputs below AGND in unipolar mode and -VREF in bipolar mode, with binary coding (CODE = low). 01.17.05 REV 3 All data sheets are subject to change without notice 2 ©2005 Maxwell Technologies Inc. All rights reserved. 16-Bit, 20 KHz A/D Converter 5102ALP TABLE 3. ANALOG CHARACTERISTICS (TA = TMIN TO TMAX; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 4.5V; FULL-SCALE INPUT SINEWAVE, 200 HZ; CLKIN = 1.6 MHZ; fS = 20 KHZ; BIPOLAR MODE; FRN MODE; AIN1 AND AIN2 TIED TOGETHER, EACH CHANNEL TESTED SEPARATELY; ANALOG SOURCE IMPEDANCE = 50 W WITH 1000 PF TO AGND UNLESS OTHERWISE SPECIFIED) PARAMETER Accuracy Resolution 1 Full Scale Error 2 Drift 3 Unipolar Offset 2 Drift 3 Bipolar Offset 2 Drift 3 Bipolar Negative Full Scale Error 2 Drift 2 Integral Nonlinearity Differential Nonlinearity Dynamic Performance (Bipolar Mode) Peak Harmonic or Spurious Noise 2, 4 Total Harmonic Distortion 4 Signal-to-Noise Ratio 2, 4 0 dB Input -60 dB Input Noise 5 Unipolar Mode Bipolar Mode Analog Input Aperture Time Aperture Jitter Input Capacitance 6, 4 Unipolar Mode Bipolar Mode Conversion and Throughput Conversion Time 7 Acquisition Time 8 Throughput 9, 10 Power Supplies tc ta ftp ---40.625 9.375 20 ---µs µs kHz ----30 100 335 215 ----ns ps pF 94 -87 ---100 0.002 90 30 35 70 ----µ Vrms --dB % dB RES FSE VOFF BOFF BNFSE INL DNL 16 -----------±1 ±2 ±1 ±2 ±2 ±2 ±2 ±2 -±1 -±5 -±5 -±5 -±5 -±3 -Bits LSB DLSB LSB DLSB LSB DLSB LSB DLSB SYMBOL MIN TYP MAX UNIT Memory LSB LSB 01.17.05 REV 3 All data sheets are subject to change without notice 3 ©2005 Maxwell Technologies Inc. All rights reserved. 16-Bit, 20 KHz A/D Converter 5102ALP TABLE 3. ANALOG CHARACTERISTICS (TA = TMIN TO TMAX; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 4.5V; FULL-SCALE INPUT SINEWAVE, 200 HZ; CLKIN = 1.6 MHZ; fS = 20 KHZ; BIPOLAR MODE; FRN MODE; AIN1 AND AIN2 TIED TOGETHER, EACH CHANNEL TESTED SEPARATELY; ANALOG SOURCE IMPEDANCE = 50 W WITH 1000 PF TO AGND UNLESS OTHERWISE SPECIFIED) PARAMETER Power Supply Current 11 Positive Analog Negative Analog (SLEEP High) Positive Digital Negative Digital Power Consumption 11, 12 (SLEEP High) (SLEEP Low) Power Supply Rejection 13 Positive Supplies Negative Supplies SYMBOL IA+ IAID+ IDPdo Pds PSR PSR MIN --------TYP 8.5 -7.7 0.5 -0.5 85 45 84 84 MAX 12 -11 1.5 -1.5 mW 130 -dB --UNIT mA 1. Minimum resolution for which no missing codes are guaranteed over the specified temperature range. 2. Applies after calibration at any temperature within the specified temperature range. 3. Total drift over specified temperature range after calibration at power-up at 25°C. 4. Guaranteed by characterization (5102A die). 5. Wideband noise aliased into the baseband. Referred to the input. 6. Applied only in the track mode. When converting or calibrating, input capacitance will not exceed 30 pF. 7. Conversion time scales directly to the master clock speed. The times shown are for synchronous, internal loopback (FRN mode). In PDT, RBT, and SSC modes, asynchronrous delay between the falling edge of HOLD and the start of conversion may add to the apparent conversion time. This delay will not exceed 1 master clock cycle + 140 ns. 8. The 5102ALPRP requires 6 clock cycles of coarse charge, followed by a minimum of 5.625 µ s of fine charge. FRN mode allows 9 clock cycles for fine charge which provides for the minimum 5.625 µ s with a 1.6 MHz clock; however, in PDT, RBT, or SSC modes, at clock frequencies less than 1.6 MHz, fine charge may be less than 9 clock cycles. 9. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions affecting acquisition and conversion times described above. 10.Typical value (measured). 11. All outputs unloaded. All inputs at VD+ or DGND. 12.Power consumption in the sleep mode applies with no master clock applied (CLKIN held high or low). 13.With 300 mV p-p, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection improves by 6 dB in the unipolar mode to 90 dB. Memory TABLE 4. 5102ALP SWITCHING CHARACTERISTICS (TA = TMIN TO TMAX; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; INPUTS: LOGIC 0 = 0V, LOGIC 1 = VD+; CL = 50 PF) PARAMETER CLKIN Period 1, 2 CLKIN Low Time CLKIN High Time SYMBOL tclk tclkl tclkh MIN 0.5 200 200 01.17.05 REV 3 TYP ---- MAX 10 --- UNIT µs ns ns All data sheets are subject to change without notice 4 ©2005 Maxwell Technologies Inc. All rights reserved. 16-Bit, 20 KHz A/D Converter 5102ALP SYMBOL fxtal trst tdrrs tcal tdrsh1 tdfsh4 tdfsh2 tdfsh1 tdrsh thold tdhlri thcf tsclk tsckll tsclkh tdss tdhs tdts tslkl tslkh tss tsh trsclk trsdl thfs tchfs MIN --150 -----66tclk -1tclk + 20 300 275 1000 500 500 -----2tclk - 100 2tclk - 100 --6tclk -TYP 1.6 20 -100 2,882,040 80 -60 -120 ------100 140 65 2tclk 2tclk --2tclk 2tclk -7tclk MAX ------68tclk + 260 -68tclk + 260 -63tclk 64tclk 1tclk + 10 ---150 230 125 -----2tclk + 200 8tclk + 200 -UNIT MHz ms ns ns tclk ns ns ns ns ns ns ns TABLE 4. 5102ALP SWITCHING CHARACTERISTICS (TA = TMIN TO TMAX; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; INPUTS: LOGIC 0 = 0V, LOGIC 1 = VD+; CL = 50 PF) PARAMETER Crystal Frequency 1, 2 SLEEP Rising to Oscillator Stable 3 RST Pulse Width 4 RST to STBY Falling RST Rising to STBY Rising CH1/2 Edge to TRK1, TRK2 Rising 5 CH1/2 Edge to TRK1, TRK2 Falling 5 HOLD to SSH Falling 6 HOLD to TRK1, TRK2, Falling 6 HOLD to TRK1, TRK2, SSH Rising 6 HOLD Pulse Width 7 HOLD to CH1/2 Edge 6 HOLD Falling to CLKIN Falling 7 PDT and RBT Modes SCLK Input Pulse Period SCLK Input Pulse Width Low SCLK Input Pulse Width High SCLK Input Falling to SDATA Valid HOLD Falling to SDATA Valid - PDT Mode TRK1, TRK2 Falling to SDATA Valid 8 FRN and SSC Modes SCLK Output Pulse Width Low SCLK Output Pulse Width High SDATA Valid Before Rising SCLK SDATA Valid After Rising SCLK SDL Falling to 1st Rising SCLK Last Rising SCLK to SDL Rising HOLD Falling to 1st Falling SCLK CH1/2 Edge to 1st Falling SCLK tclk tclk ns ns ns ns ns tclk ns ns ns ns ns ns Memory ns 1. Minimum CLKIN period is 0.625 µ s is FRN mode (20 kHz sample rate). 2. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency is 1.6 MHz in FRN mode (20 kHz sample rate). 3. With a 2.0 MHz crystal, two 33 pF loading capacitors and a 10 MW parallel resistor. 4. Guaranteed by initial characterization (5102A die). 5. These times are for FRN mode. 6. These times are for PDT and RBT modes. 01.17.05 REV 3 All data sheets are subject to change without notice 5 ©2005 Maxwell Technologies Inc. All rights reserved. 16-Bit, 20 KHz A/D Converter 5102ALP 7. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must be latched by a falling edge of CLKIN. Conversion will begin on the next rising edge of CLKIN after HOLD is latched. 8. Only valid for TRK1, TRK2 falling when SCLK is low. If SCLK is high when TRK1, TRK2 falls, then SDATA is valid tdss time after the next falling SCLK. TABLE 5. 5102ALP DIGITAL CHARACTERISTICS (TA = TMIN TO TMAX; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%) PARAMETER Calibration Memory Retention Power Supply Voltage VA+ & VD+ 1 High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage 2 Low-Level Output Voltage - IOUT = 1.6 mA Input Leakage Current Digital Output Pin Capacitance SYMBOL VMR VIH VIL VOH VOL IIN COUT MIN 2.0 2.0 -(VD+) -1.0 ---TYP ------9 MAX --0.8 -0.4 10 -UNIT V V V V V µA pF Memory 1. VA- and VD- can be any value from zero to -5V for memory retention. Neither VA- or VD- should be allowed to go positive. AIN1, AIN2 or VREF must not be greater than VA+ or VD+. This parameter is guaranteed by characterization. 2. IOUT = -100 µ A. This specification guarantees TTL compatibility (VOH = 2.4V @ IOUT = -40 µ A. LPT™ OPERATION Latchup Protection Technology (LPT™) automatically detects an increase in the supply current of the 5102ALP converter due to a single event effect and internally cycle the power to the converter off, then on, which restores the steady state operation of the device. If data outputs are connected to a bus with other bus driver circuits, all external data bus drivers must be tri-stated and individual pull up resistors to the supply voltage (if used on the data bus) must no be less than 10 K ohm typical to assure proper single event effect recovery. STATUS can also be used to generate an input to the system data processor indicating that an LPT™ cycle has occurred, and the protected device output accuracy may not be met until after the respective recovery time to the event. The STATUS signal is generated from an advanced CMOS logic gate output. This output may not exhibit a monotonic fall time and may even oscillate briefly while power is being restored to the protected device and the decoupling capacitance is charged. Loading on the STATUS output should be minimized because this signal is used internally by the 5102ALP. It is recommended that load current not exceed 2 mA and load capacitance be kept will below 1000 pF. 01.17.05 REV 3 All data sheets are subject to change without notice 6 ©2005 Maxwell Technologies Inc. All rights reserved. 16-Bit, 20 KHz A/D Converter 5102ALP LPTTM BLOCK DIAGRAM +VDIG +VANA Current Sense 5102ALP Switch +LPTV Timer AIN 1 AIN 2 VREF Crowbar LPTBIT 5102A Control Logic LPTSTATUS Memory -LPTV Switch -VDIG -VANA Current Sense LATCH-UP PROTECTION CIRCUIT (LPT) PIN DESCRIPTION PIN 18 PIN NAME FUNCTION LPTBIT The LPT circuit will crowbar the power supplies to the SEI5102ALPRP for as long as a logical high is applied. Used to verify operation of the LPT. Normally a logical low or ground is applied to this input. -LPTV Negative power supply. VA- and VD- are connected and can be measured on this pin. Normally -5V. +LPTV Positive power supply. VA+ and VD+ are connected and can be measured on this pin. Normally +5V. 26 27 01.17.05 REV 3 All data sheets are subject to change without notice 7 ©2005 Maxwell Technologies Inc. All rights reserved. 16-Bit, 20 KHz A/D Converter LATCH-UP PROTECTION CIRCUIT (LPT) PIN DESCRIPTION PIN 39 PIN NAME LPTSTATUS FUNCTION A 0 to 5V square-wave will output during a latch condition. Normally low. 5102ALP . FIGURE 1. RESET AND CALIBRATION TIMING Memory FIGURE 2. CONTROL OUTPUT TIMING FIGURE 3. CHANNEL SELECTION TIMING 01.17.05 REV 3 All data sheets are subject to change without notice 8 ©2005 Maxwell Technologies Inc. All rights reserved. 16-Bit, 20 KHz A/D Converter FIGURE 4. START CONVERSION TIMING 5102ALP FIGURE 5. SERIAL DATA TIMING Memory FIGURE 6. DATA TRANSMISSION TIMING 01.17.05 REV 3 All data sheets are subject to change without notice 9 ©2005 Maxwell Technologies Inc. All rights reserved. 16-Bit, 20 KHz A/D Converter FIGURE 7. BYPASS CIRCUIT +VDIG DGND -VDIG -VDIG R ST CLKIN XOUT STBY DGND +VDIG TR K1 TR K2 CR S/FIN S SH/S DL HOLD CH1/2 S CLK +LPTBIT NC -VDIG DGND +VDIG 22 23 1 44 5102ALP +VANLOG AGND -VANLOG SP LEE S CKMOD LPTSTATUS +VANLOG AIN2 -VANLOG AGND R EFBUF VR EF AIN1 OUTMOD BP/UP CODE SDATA +LPTV -LPTV -VANLOG AGND +VANLOG Memory 1 µF + + 1 µF 4.7 µF + 4.7 µF + Note: 1. Cap must be connected to the device for proper operation. 4.7 µ F analog side. 1 µ F digital side. 2. Unused logic inputs should be tied to +VD or DGND. FIGURE 8. POWER-UP RESET CIRCUIT +5V 1N4148 R +VD RST C 01.17.05 REV 3 All data sheets are subject to change without notice 10 ©2005 Maxwell Technologies Inc. All rights reserved. 16-Bit, 20 KHz A/D Converter 5102ALP Memory 44 PIN FRP SYMBOL MIN A b c D E E1 E2 E3 e L Q S1 N 0.455 0.022 0.005 0.256 0.014 0.009 1.089 0.564 -0.410 0.044 DIMENSION NOM 0.282 0.017 0.010 1.100 0.570 -0.430 0.070 0.050 BSC 0.465 0.027 -44 0.475 0.032 -MAX 0.308 0.020 0.012 1.111 0.576 0.600 0.450 -- F44 Note: All dimensions in inches 01.17.05 REV 3 All data sheets are subject to change without notice 11 ©2005 Maxwell Technologies Inc. All rights reserved. 16-Bit, 20 KHz A/D Converter Important Notice: 5102ALP These data sheets are created using the chip manufacturers published specifications. MAxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against MAxwell TechnologiesInc. must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts. Memory 01.17.05 REV 3 All data sheets are subject to change without notice 12 ©2005 Maxwell Technologies Inc. All rights reserved. 16-Bit, 20 KHz A/D Converter Product Ordering Options 5102ALP Memory 01.17.05 REV 3 All data sheets are subject to change without notice 13 ©2005 Maxwell Technologies Inc. All rights reserved. 16-Bit, 20 KHz A/D Converter 5102ALP Model Number 5102ALP - RP - F - X Screening Flow Multi Chip Module (MCM)1 K = Maxwell Self-Defined Class K H = Maxwell Self-Defined Class H I = Industrial (testing @ -40°C, +25°C, +110°C) E = Engineering (testing @ +25°C) Package F = Flat Pack Memory Radiation Feature RP = RAD-PAK® package Base Product Nomenclature 16-Bit 20KHz A/D Converter 1) Products are manufactured and screened to Maxwell Technologies self-defined Class H and Class K flows. 01.17.05 REV 3 All data sheets are subject to change without notice 14 ©2005 Maxwell Technologies Inc. All rights reserved.