54LVTH162373RPFE

PRELIMINARY 3.3V 16-Bit Transparent D-Type Latches 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE 24 25 1 48 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 54LVTH162373 Logic Diagram (PositiveLogic) 1/24 1OE/2OE 1LE/2LE 48/25 C1 1D1/2D1 47/36 1D 2/13 1Q1/2Q1 54LVTH162373 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2LE To Seven Other Channels Logic Diagram Memory FEATURES: • 3.3V low voltage advanced BiCMOS technology (LVT) 16bit transparent D-type latches with 3-state outputs • Total dose hardness: - > 100 krad (Si), depending upon space mission • Excellent Single Event Effect: - SELTH: No LU > 119 MeV/mg/cm2 • Package: 48 pin RAD-PAK® flat package • Operating temperature range: - 55 to 125°C • Distributed VCC and GND pin configuration minimizes highspeed switching noise • Supports mixed-mode signal operation - 5V input and output voltages with 3.3V VCC • Supports unregulated battery operation down to 2.7V • Supports live insertion • Bus-hold data inputs eliminate the need for external pullup resistors DESCRIPTION: Maxwell Technologies’ 54LVTH162373 16-bit transparent Dtype latches with 3-state output features a greater than 100 krad (Si) total dose tolerance, depending upon space mission. The 54LVTH162373 is designed for low voltage (3.3V) VCC operation, but with the capability to provide a TTL interface to a 5V system environment. It is suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The 54LVTH162373 can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is low, the Q output are latched at the levels set up at the data (D) inputs. When LE is high, the Q outputs follow the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state or a high impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly. The high impedance state and the increased drive provide the capability to drive bus lines without the need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high impedance state. Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK provides greater than 100 krad (Si) radiation dose tolerance. This product is available with screening up to Class S. 1000596 12.19.01 Rev 1 All data sheets are subject to change without notice 1 (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com ©2001 Maxwell Technologies All rights reserved. PRELIMINARY 3.3V 16-Bit Transparent D-Type TABLE 1. PINOUT DESCRIPTION PIN 1, 24 2, 3, 5, 6, 8, 9, 11, 12 4, 10, 15, 21, 28, 34, 39, 45 7, 31, 42 13, 14, 16, 17, 19, 20, 22, 23 25, 48 26, 27, 29, 30, 32, 31, 32, 33, 35, 36 37, 38, 40, 41, 43, 44, 46, 47 SYMBOL 1OE-2OE 1Q1-1Q8 GND VCC 2Q1-2Q8 2LE-1LE 2D8-2D1 1D8-1D1 Outputs Ground Power Supply Outputs Latch Enable Inputs Inputs 54LVTH162373 DESCRIPTION Output Enable TABLE 2. 54LVTH162373 ABSOLUTE MAXIMUM RATINGS PARAMETER Supply voltage range Input voltage range 1 Memory SYMBOL VCC VI VO IO 2 MIN -0.5 -0.5 -0.5 ------65 MAX 4.6 7 7 30 30 -50 -50 0.85 150 UNIT V V V mA mA mA mA mW °C Voltage range applied to any output in the high state or power-off state 1 Current into any output in the low state Current into any output in the high state Input clamp current (VI < 0) Output clamp current (VO < O) Maximum power dissipation at TA = Storage temperature range 55°C 3 IO IIK IOK PD TS 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The maximum package power dissipation is calculated using a junction temperature of 150 °C and a board trace length of 750 mils. TABLE 3. DELTA LIMITS PARAMETER ICC(OL) ICC(OH) ICC(OD) VARIATION ±10% of specified value in Table 5 ±10% of specified value in Table 5 ±10% of specified value in Table 5 1000596 12.19.01 Rev 1 All data sheets are subject to change without notice 2 ©2001 Maxwell Technologies All rights reserved. PRELIMINARY 3.3V 16-Bit Transparent D-Type 54LVTH162373 SYMBOL VCC VIH VIL VI IOH IOL TA MIN 2.7 2 ------55 MAX 3.6 -0.8 5.5 -12 12 10 125 UNIT V V V V mA mA ns/V °C TABLE 4. 54LVTH162373 RECOMMENDED OPERATING CONDITIONS 1 PARAMETER Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate (outputs enabled) Operating temperature ∆t/∆v 1. Unused control inputs must be held high or low to prevent them from floating. TABLE 5. 54LVTH162373 DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ±10%, TA = -55 to 125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER Input Clamp Voltage High-Level Output Voltage Low-Level Output Voltage Input Current SYMBOL VIK VOH VOL II VCC = 2.7 VCC = 3V VCC = 3V VCC = 0 or 3.6V VCC = 3.6V VCC = 3.6V Hold Current Output Disabled Leakage Current - High Output Disabled Leakage Current - Low Power Up Current Power Down Current II(HOLD) VCC = 3V IOZH IOZL IOZPU2 IOZPD2 VCC = 3.6V, VO = 3V VCC = 3.6V, VO = 0.5V VCC = 0 to 1.5V, VO = 0.5V to 3V, OE = don’t care VCC = 1.5V to 0, VO = 0.5V to 3V, OE = don’t care TEST CONDITIONS II = -18mA IOH = -12 mA IOL = 12 mA VI = 5.5V VI = VCC or GND VI = VCC VI = 0 VI = 0.8V VI = 2V Control inputs Data Inputs Data Inputs MIN -2 -----75 -75 ----MAX -1.2 -0.8 10 ±1 1 -5 --5 -5 ±100 ±100 µA µA µA µA µA UNIT V V V µA Memory 1000596 12.19.01 Rev 1 All data sheets are subject to change without notice 3 ©2001 Maxwell Technologies All rights reserved. PRELIMINARY 3.3V 16-Bit Transparent D-Type 54LVTH162373 MIN Outputs high Outputs low Outputs disabled ------MAX 0.19 5 0.19 0.2 8 15 mA pF pF UNIT mA TABLE 5. 54LVTH162373 DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ±10%, TA = -55 to 125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER Supply Current SYMBOL ICC VCC = 3.6V IO = 0 VI = VCC or GND TEST CONDITIONS Delta Supply Current Input Capacitance Input Output Capacitance ∆ICC 1 VCC = 3V to 3.6V, One input at VCC -0.6V, Other inputs at VCC or GND C I2 CO2 VI = 3V or 0 VO = 3V or 0 1. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 2. Guaranteed by design. Memory TABLE 6. 54LVTH162373 AC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ±10%, TA = -55 to 125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER Pulse duration, LE high Setup time, data before LEØ Hold time, data after LEØ Propagation Delay Time D to Q Propagation Delay Time LE to Q Output Enable Time OE to Q Output Disable Time OE to Q SYMBOL tW tSU tH tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ VCC = 3.3V ± 0.3V MIN 3.3 1.5 1.8 1.3 1.4 2.1 2.1 1.3 1.3 2.0 1.0 MAX ---5.2 4.9 6.0 5.2 8.0 5.5 6.8 7.6 MIN 3.0 0.6 2 --------VCC = 2.7V MAX ---6.0 5.0 6.5 4.9 7.4 6.2 6.9 6.7 ns ns ns ns ns ns ns UNIT 1000596 12.19.01 Rev 1 All data sheets are subject to change without notice 4 ©2001 Maxwell Technologies All rights reserved. PRELIMINARY 3.3V 16-Bit Transparent D-Type fp 54LVTH162373 TABLE 7. FUNCTION TABLE (EACH 8-BIT SECTION) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z FIGURE 1. LOAD CIRCUIT Memory Figure Note: 1. CL includes probe and jig capacitance. PARAMETER MEASUREMENT INFORMATION TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 OPEN 6V GND FIGURE 2. PULSE DURATION 1000596 12.19.01 Rev 1 All data sheets are subject to change without notice 5 ©2001 Maxwell Technologies All rights reserved. PRELIMINARY 3.3V 16-Bit Transparent D-Type FIGURE 3. SETUP AND HOLD TIMES 54LVTH162373 FIGURE 4. PROPAGATION DELAY TIMES INVERTING AND NON-INVERTING OUTPUTS Memory FIGURE 5. ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING 1000596 12.19.01 Rev 1 All data sheets are subject to change without notice 6 ©2001 Maxwell Technologies All rights reserved. PRELIMINARY 3.3V 16-Bit Transparent D-Type Figure Notes: 54LVTH162373 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, ZO = 5Ω, tr < 2.5 ns, tf < 2.5 ns. 4. The outputs are measured one at a time with one transition per measurement. Memory 1000596 12.19.01 Rev 1 All data sheets are subject to change without notice 7 ©2001 Maxwell Technologies All rights reserved. PRELIMINARY 3.3V 16-Bit Transparent D-Type 54LVTH162373 Memory 48 PIN RAD-PAK® FLAT PACKAGE SYMBOL MIN A b c D E E1 E2 E3 e L Q S1 N 0.275 0.013 0.005 0.144 0.008 0.004 -0.370 -0.200 0.075 DIMENSION NOM 0.160 0.010 0.006 0.620 0.380 -0.210 0.085 0.025 BSC 0.285 0.019 0.018 48 0.295 0.045 -MAX 0.176 0.014 0.007 0.640 0.390 0.410 0.220 -- F48-01 Note: All dimensions in inches 1000596 12.19.01 Rev 1 All data sheets are subject to change without notice 8 ©2001 Maxwell Technologies All rights reserved. PRELIMINARY 3.3V 16-Bit Transparent D-Type Important Notice: 54LVTH162373 These data sheets are created using the chip manufacturer’s published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts. Memory 1000596 12.19.01 Rev 1 All data sheets are subject to change without notice 9 ©2001 Maxwell Technologies All rights reserved. PRELIMINARY 3.3V 16-Bit Transparent D-Type Product Ordering Options Model Number 54LVTH162373 RP F X Feature 54LVTH162373 Option Details Screening Flow Monolithic S = Maxwell Class S B = Maxwell Class B E = Engineering (testing @ +25°C) I = Industrial (testing @ -55°C, +25°C, +125°C) Memory Package F = Flat Pack Radiation Feature RP = RAD-PAK® package Base Product Nomenclature 3.3V 16-Bit Transparent D-Type Latches 1000596 12.19.01 Rev 1 All data sheets are subject to change without notice 10 ©2001 Maxwell Technologies All rights reserved.