72SD3232RPFI

72SD3232 1 Gbit SDRAM 32-Meg X 32-Bit X 4-Banks Logic Diagram (One Amplifier) Memory FEATURES: • 1 Gigabit ( 32-Meg X 32-Bit X 4-Banks) • RAD-PAK® radiation-hardened against natural space radiation • Total Dose Hardness: >100 krad (Si), depending upon space mission • Excellent Single Event Effects: SELTH > 85 MeV/mg/cm2 @ 25° C DESCRIPTION: Maxwell Technologies’ Synchronous Dynamic Random Access Memory (SDRAM) is ideally suited for space applications requiring high performance computing and high density memory storage. As microprocessors increase in speed and demand for higher density memory escalates, SDRAM has proven to be the ultimate solution by providing bit-counts up to 1 Gigabits and speeds up to 100 Megahertz. SDRAMs represent a significant advantage in memory technology over traditional SRAMs including the ability to burst data synchronously at high rates with automatic column-address generation, the ability to interleave between banks masking precharge time, and the ability to randomly change column address during each clock cycle. Maxwell Technologies’ patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding for a lifetime in orbit or space mission. In a typical GEO orbit, RAD-PAK® provides greater than 100 krads(Si) radiation dose tolerance. This product is available with screening up to Maxwell Technologies self-defined Class K. 02.04.05 Rev 3 • • • • • • • • • • JEDEC Standard 3.3V Power Supply Clock Frequency: 100 MHz Operation Operating tremperature: -55 to +125° C Auto Refresh Single pulsed RAS 2 Burst Sequence variations Sequential (BL =1/2/4/8) Interleave (BL = 1/2/4/8) Programmable CAS latency: 2/3 Power Down and Clock Suspend Modes LVTTL Compatible Inputs and Outputs Package: 72-Pin RAD-Stack Package All data sheets are subject to change without notice 1 (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com ©2005 Maxwell Technologies All rights reserved. 1 Gbit(32-Meg X 32-Bit X 4-Banks) SDRAM 72SD3232 Pinout Description Pin Descriptions Pin Name A0 to A12 BA0, BA1 Address Input Row Address A0 to A12 Column Address A0 to A9 Bank Select Address BA0/BA1 (BS) DQ0 to DQ7 DQ8 to DQ15 DQ16 to DQ23 DQ24 to DQ32 CS\ RAS\ CAS\ WE\ DQM 1 DQM 2 DQM 3 DQM 4 CLK1 CLK2 CKE Vcc Vss VccQ VssQ NC Data-Input/Output - Layer 1 Data-Input/Output - Layer 2 Function Memory Data-Input/Output - Layer 3 Data-Input/Output - Layer 4 Chip Select Row Address Strobe Column Address Strobe Write Enable Input/Output Mask - Layer 1 Input/Output Mask - Layer 2 Input/Output Mask - Layer 3 Input/Output Mask - Layer 4 Clock Input - Layer 1 & 3 Clock Input - Layer 2 & 4 Clock Enable Power for internal circuits Ground for internal circuits Power for DQ circuits Ground for DQ circuits No Connection 72SD3232 02.04.05 Rev 3 All data sheets are subject to change without notice 2 ©2005 Maxwell Technologies All rights reserved. 1 Gbit(32-Meg X 32-Bit X 4-Banks) SDRAM ‘ 72SD3232 TABLE 1. ABSOLUTE MAXIMUM RATINGS PARAMETER Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power Dissipation Operating Temperature Storage Temperature SYMBOL VIN VOUT VCC IOUT PD TOPR TSTG MAX -0.5 to VCC + 0.5 (< 4.6(max)) -0.5 to +4.6 50 1.0 -55 to +125 -65 to +150 UNIT V V mA W °C °C TABLE 2. RECOMMENDED OPERATING CONDITIONS (VCC = 3.3V + 0.3V, VCCQ = 3.3V + 0.3V, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED) CC Memory PARAMETER Supply Voltage SYMBOL M IN M AX VCC, V CCQ1,2 3.0 3.6 VSS, V SSQ3 0 0 Input High Voltage VIH1,4 2.0 VCC + 0.3 Input Low Voltage VIL1,5 -0.3 .8 1. All voltage referred to VSS 2. The supply voltage with all VCC and VCCQ pins must be on the same level 3. The supply voltage with all V SS a nd V SSQ pins must be on the same level 4. 5. VIH ( max) = VCC+2.0V for pulse width