7805ALPRPFH

7805ALP 16-Bit Latchup Protected ADC Logic Diagram Memory FEATURES: • 16-bit organization • Latchup Protection Technology™ • RAD-PAK® radiation-hardened against natural space radiation • Total dose hardness: - > 50 krads(Si), depending upon space mission • Latchup converted to reset. - Rate based on cross section and mission. • Package: - 28 pin RAD-PAK® flat pack - 28 pin RAD-PAK® DIP • 100 kHz min sampling rate • Standard ± 10V input range • Advance CMOS technology - 86 dB min SINAD with 20 kHz input - Single 5V supply operation - Utilizes internal or external reference - Full parallel data output - Power dissipation: 132 mW max DESCRIPTION: Maxwell Technologies’ 7805ALP high-speed analog-to-digital converter features a greater than 50 krad (Si) total dose tolerance, depending upon space mission. Using Mawell’s radiation-hardened RAD-PAK® packaging technology, the 7805ALP incorporates the commercial ADS7805 from Burr Brown. This device is latchup protected by Maxwell Technologies’ LPT™ technology. The 7805ALP, 16-bit sampling CMOS A/D . The device contains a complete 16-bit capacitor-based SAR A/D with S/H, reference, clock, interface for microprocessor use, and three-state output drivers. The 7805ALP is specified at a 100 kHz sampling rate, and guaranteed over the full temperature range. Laser-trimmed scaling resistors provide an industry-standard ± 10V input range, while the innovative design allows operation from a single 5V supply, with power dissipation of under 132 mW. Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK® provides greater than 50 krad (Si) radiation dose tolerance. This product is available with screening up to Maxwell Technologies self-defiened Class K. 01.10.05 Rev 9 All data sheets are subject to change without notice 1 (858) 503-3300 Fax: (858) 503-3301- www.maxwell.com ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC TABLE 1. 7805ALP PINOUT DESCRIPTION PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME VIN AGND1 REF CAP AGND2 D15 (MSB) D14 D13 D12 D11 D10 D9 D8 DGND D7 D6 D5 D4 D3 D2 D1 D0 (LSB) STATUS* R/C CS BUSY DECPLNG VS 0 0 0 0 0 0 0 0 0 I I 0 0 0 0 0 0 0 0 0 DIGITAL I/O DESCRIPTION Analog input. Analog ground. Used internally as ground reference point. Reference input/output. 2.2 µ F tantalum capacitor to ground 7805ALP Reference buffer capacitor. 2.2 µ F tantalum capacitor to ground. Analog ground. Data bit 15. Most Significant Bit (MSB) of conversion results. When STATUS is HIGH*, D15 must not be driven high. Data bit 14. When STATUS is HIGH*, D14 must not be driven high. Data bit 13. When STATUS is HIGH*, D13 must not be driven high. Data bit 12. When STATUS is HIGH*, D12 must not be driven high. Data bit 11. When STATUS is HIGH*, D11 must not be driven high. Data bit 10. When STATUS is HIGH*, D10 must not be driven high. Data bit 9. When STATUS is HIGH*, D9 must not be driven high. Data bit 8. When STATUS is HIGH*, D8 must not be driven high. Digital Ground Data bit 7. When STATUS is HIGH*, D7 must not be driven high. Data bit 6. When STATUS is HIGH*, D6 must not be driven high. Data bit 5. When STATUS is HIGH*, D5 must not be driven high. Data bit 4. When STATUS is HIGH*, D4 must not be driven high. Data bit 3. When STATUS is HIGH*, D3 must not be driven high. Data bit 2. When STATUS is HIGH*, D2 must not be driven high. Data bit 1. When STATUS is HIGH*, D1 must not be driven high. Data bit 0. Least Significant Bit (LSB) of conversion results. When STATUS is HIGH*, D0 must not be driven high. STATUS when HIGH indicates latchup protection is active and output data is invalid. Capacitive loading should not exceed 1000 pF. With CS LOW and BUSY HIGH, a falling edge of R/C initiates a new conversion. When STATUS is HIGH*, CS and R/C must not be driven high. Internally OR’d with R/C. If R/C LOW, a falling edge on CS initiates a new conversion. When STATUS is HIGH*, CS and R/C must not be driven high. At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs have been updated. Supply voltage high speed decoupling pin. Decouple to ground with 1.0 µ F ceramic capacitor. Supply input. Nominally 5V. Decouple to ground with 10 µ F tantalum capacitor. Memory 01.10.05 Rev 9 All data sheets are subject to change without notice 2 ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC TABLE 2. 7805ALP ABSOLUTE MAXIMUM RATINGS PARAMETER Analog Inputs SYMBOL VIN CAP REF DGND AGND1 AGND2 VS ΘJC -TJ ---MIN -25 VS 9 -0.3 -0.3 -0.3 --0.3 TYP ------7 -- 7805ALP MAX 25 AGND2 - 0.3 -0.3 0.3 0.3 VS + 0.3 11 825 165 UNIT V Ground Voltage Difference V Supply Input Digital Inputs Thermal Impedance Internal Power Dissipation Maximum Junction Temperature V V ° C/W mW °C TABLE 3. 7805ALP DC ACCURACY SPECIFICATIONS (VS = 5V, TA = -40 TO +85° C UNLESS OTHERWISE SPECIFIED) PARAMETER Integral Linearity Error Differential Linearity Error No Missing Codes Transition Noise Full Scale Error 2 3,4 1 Memory CONDITIONS SUBGROUPS MIN --15 ------ TYP ---1.3 -±7 -±2 -- MAX ±3 4, -1 --±0.5 -±10 -±8 UNIT LSB LSB Bits LSB % ppm/° C mV ppm/° C LSB Full Scale Error Drift Bipolar Zero Error 3 Bipolar Zero Error Drift Power Supply Sensitivity 1. Guaranteed by design 2. Typical rms noise at worst case transitions and temperatures. 3. Measured with various fixed resistors. 4.8V < VS < 5.25V -- 4. Full scale error is worst case - Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and included the effect of offset error. TABLE 4. 7805ALP DIGITAL INPUTS (VS = 5V, TA = -40 TO +85° C UNLESS OTHERWISE SPECIFIED) PARAMETER VIL VIH 01.10.05 Rev 9 SUBGROUPS 1, 2, 3 MIN -0.3 2.0 TYP --- MAX 0.8 VS +0.3 UNIT V V All data sheets are subject to change without notice 3 ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC TABLE 4. 7805ALP DIGITAL INPUTS (VS = 5V, TA = -40 TO +85° C UNLESS OTHERWISE SPECIFIED) PARAMETER IIL, IIH SUBGROUPS 1, 2, 3 MIN -TYP -- 7805ALP MAX ±10 UNIT µA TABLE 5. 7805ALP ANALOG INPUTS (VS = 5V, TA = -40 TO +85° C UNLESS OTHERWISE SPECIFIED) PARAMETER Voltage Ranges 1 Impedance Capacitance2 1. Tested by application of signal. 2. Guarenteed by design SUBGROUPS 1, 2, 3 1, 2, 3 -MIN -10 --TYP ±10 23 35 MAX 10 --UNIT V kΩ pF Memory TABLE 6. 7805ALP THROUGHPUT SPEED (VS = 5V, TA = -40 TO +85° C UNLESS OTHERWISE SPECIFIED) PARAMETER Conversion Time Complete Cycle (Acquire and Convert) Throughput Rate 1 SUBGROUPS 9, 10, 11 9, 10, 11 MIN --100 TYP 7.6 --- MAX 8 10 -- UNIT µs µs kHz 1. Guaranteed by design TABLE 7. 7805ALP AC ACCURACY SPECIFICATIONS (VS = 5V, TA = -40 TO +85° C UNLESS OTHERWISE SPECIFIED) PARAMETER Spurious-Free Dynamic Range Total Harmonic Distortion 1,2 Signal-to-(Noise + Distortion) 1,2 Signal-to-Noise 1,2 Full-Power Bandwidth 3 1. All specifications in dB are referred to a full-scale 10V input. 2. Guaranteed by design. 3. Full-power bandwidth defined as full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB or 10 bits of accuracy. 01.10.05 Rev 9 1,2 TEST CONDITIONS fIN = 45 kHz fIN = 45 kHz fIN = 45 kHz -60dB Input fIN = 45 kHz SUBGROUPS 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 MIN 90 -83 -83 -- TYP ---30 -250 MAX --90 ----- UNIT dB dB dB dB kHz All data sheets are subject to change without notice 4 ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC TABLE 8. 7805ALP SAMPLING DYNAMICS (VS = 5V, TA = -40 TO +85° C UNLESS OTHERWISE SPECIFIED) PARAMETER Aperture Delay Transient Response Overvoltage Recovery 1 7805ALP TEST CONDITIONS FS Step SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 MIN ---- TYP 40 2 150 MAX ---- UNIT nS µS nS 1. Recovers to specified performance after 2 x fS input overvoltage. TABLE 9. 7805ALP REFERENCE TABLE 10. (VS = 5V, TA = -40 TO +85° C UNLESS OTHERWISE SPECIFIED) PARAMETER Internal Reference Voltage Internal Reference Source Current (Must use external buffer) Internal Reference Drift External Reference Voltage Range for Specified Linearity 1 External Reference Current Drain 1. Tested by application of signal. 2. Guaranteed by design 2 SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 -- MIN 2.48 ----- TYP 2.5 1 8 2.5 -- MAX 2.52 ---100 UNIT V Memory µA ppm/° C V µA TABLE 11. 7805ALP DIGITAL OUTPUTS (VS = 5V, TA = -40 TO +85° C UNLESS OTHERWISE SPECIFIED) PARAMETER Data Formatting Data Coding VOL VOH Leakage Current Output Capacitance1 1. Guarenteed by design (ISINK = 1.6mA) 4.0 (ISOURCE = -400 µ A) High-Z State, VOUT = 0V to VS High-Z State 1, 2, 3 1, 2, 3 1, 2, 3 --4.0 --TEST CONDITIONS SUBGROUPS MIN TYP MAX UNIT (Parallel 16-bits Binary Two’s Complement) Binary Two’s Complement ---10 0.4 -±5 -V V µA pF 01.10.05 Rev 9 All data sheets are subject to change without notice 5 ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC TABLE 12. 7805ALP POWER SUPPLIES (VS = 5V, TA = -40 TO +85° C UNLESS OTHERWISE SPECIFIED) PARAMETER VS IS Power Dissipation fS = 100 kHz TEST CONDITIONS SUBGROUPS -1, 2, 3 1, 2, 3 MIN 4.8 --TYP 5 20.3 102 7805ALP MAX 5.25 -132.0 UNIT V mA mW TABLE 13. 7805ALP DIGITAL TIMING (VS = 5V, TA = -40 TO +85° C UNLESS OTHERWISE SPECIFIED) PARAMETER Bus Access Time Bus Relinquish Time SUBGROUPS 9, 10, 11 9, 10, 11 MIN --TYP --MAX 83 83 UNIT nS nS Memory TABLE 14. 7805ALP TEMPERATURE PARAMETER Specified Performance Derated Performance 1 Storage 1. Tested by application of signal. MIN -40 -55 -65 TYP ---MAX 85 125 150 UNIT °C °C °C TABLE 15. 7805ALP CONVERSION TIMING1 (VS = 5V, TA = -40 TO +85° C UNLESS OTHERWISE SPECIFIED) DESCRIPTION Convert pulse width Data valid delay after R/C low BUSY delay from R/C low BUSY low BUSY delay after end-of-conversion Aperture time Conversion time Acquisition time Throughput time Bus relinquish time SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t7 + t 8 t9 SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 MIN 40 --------10 TYP ----220 40 7.6 -9 35 MAX 7000 8 85 8 --8 2 10 83 UNIT ns µs ns µs ns ns µs µs µs ns 01.10.05 Rev 9 All data sheets are subject to change without notice 6 ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC TABLE 15. 7805ALP CONVERSION TIMING1 (VS = 5V, TA = -40 TO +85° C UNLESS OTHERWISE SPECIFIED) DESCRIPTION BUSY delay after data valid Previous data valid delay after R/C low R/C to CS setup time Time between conversions Bus access time 1. Tested by application of signal. SYMBOL t10 t11 t12 t13 t14 SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 MIN 50 -10 10 10 TYP 200 7.4 ---- 7805ALP MAX ----83 UNIT ns µs ns µs ns TABLE 16. 7805ALP CONTROL LINE FUNCTION FOR READ AND CONVERT CS 1 R/C X 0 0 0 1 1 1 0 0 X 0 X 0 1 0 0 BUSY X 1 1 OPERATION None. Databus is in Hi-Z state. Memory Initiates conversion "n". Databus remains in Hi-Z state. Initiates conversion "n". Databus enters Hi-Z state. Conversion "n" completed. Valid data from conversion "n" on the databus. Enables databus with valid data from conversion "n". Enables databus with valid data from conversion "n-1". Conversion "n" in progress. Enables databus with valid data from conversion "n-1". Conversion "n" in progress." New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C must be HIGH when BUSY goes HIGH. New convert commands ignored. Conversion "n" in progress. 01.10.05 Rev 9 All data sheets are subject to change without notice 7 ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC 7805ALP FIGURE 1. CONVERSION TIMING WITH OUTPUTS ENABLED AFTER CONVERSION (CS TIED LOW) Memory FIGURE 2. USING CS TO CONTROL CONVERSION AND READ TIMING LPT™ Operation Latchup Protection Technology (LPT™) automatically detects an increase in the supply current of the 7805ALP converter due to a single event effect and internally cycles the power to the converter off, then on, which restores the 01.10.05 Rev 9 All data sheets are subject to change without notice 8 ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC 7805ALP VS steady state operation of the device. A simplified block diagram of the 7805ALP circuitry is shown in Figure 1. The circuitry consists of a protected device, the ADS7805 die, a current sensor, a power switch, and a status output driver. CURRENT SENSOR POWER SWITCH STATUS OUTPUT STATUS DRIVER VDIG VANA PROTECTED DEVICE DECPLNG I/Os ADS7805 BYTE AGND1 AGND2 DGND 7805ALPRP Memory FIGURE 3. LATCHUP PROTECTION DIAGRAM Differences Between the7805A and the ADS7805 Because the 7805A uses the ADS7805 die to perform the analog to digital conversion function its operation and performance is very similar to the ADS7805 packaged part from Burr-Brown. In general the operation and application will be the same for both parts. There are two primary differences: the operation of the supply pins and the operation of the BYTE and STATUS pins. The ADS7805 provides separate analog and digital supply pins. The 7805A provides a single supply input VS pin in place of the VDIG pin which powers both the analog and digital circuitry through the LPT™ current sensor and power switch. The VS power supply should be treated as an analog supply and isolated from noise on the system digital power supply. The low side of the power switch connects to the ADS7805 die power pads and to the package DECPLNG pin which replaces the VANA pin. The DECPLNG pin allows low ESR ceramic capacitors to directly decouple the ADS7805 die. CAUTION: The DECPLNG pin must not be connected to the power supply since this will defeat the LPT™ power switch and could result in latchup of the device during operation in a radiation environment. Electrolytic capacitors should not be connected to the DECPLNG pin because the large capacitance will increase the recovery time of the 7805A. The primary functional difference between the ADS7805 and the 7805A is that the BYTE signal of the ADS7805 is internally grounded and the pin function is replaced by the STATUS output. Grounding the BYTE signal permanently assigns the data output signal bits 15:0 as shown in the 7805A pinout diagram where bit15 is the MSB and bit 0 is the LSB. A high level STATUS signal indicates that a single event induced latchup current was detected by the LPT™ circuitry causing power to be removed from the protected device. CAUTION: During the time that power is removed from the protected device, it is critical that external circuitry driving the device I/O pins does not backdrive the device supply. Backdriving the supply could contribute to an extended or even a permanent latchup condition. 01.10.05 Rev 9 All data sheets are subject to change without notice 9 ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC 7805ALP In order to prevent backdriving the supply, the STATUS signal should be used in the system to tri-state or gate external I/O drive circuits to a low state. Similarly, if the data outputs are connected to a bus with other bus driver circuits, all external data bus drivers must be tri-stated and individual pull up resistors to the supply voltage (if used on the data bus) must not be less than 10 KΩ typical to assure proper single event effect recovery. Tri-stating of inputs should occur within 100 nsec after the rise of the status pin. The BYTE signal can be made available in place of the STATUS signal at customer request. STATUS can also be used to generate an input to the system data processor indicating that an LPT™ cycle has occurred, and the protected device output accuracy may not be met until after the respective recovery time to the event. The STATUS signal is generated from an advanced CMOS logic gate output. This output may not exhibit a monotonic falltime and may even oscillate briefly while power is being restored to the protected device and the decoupling capacitance is charged. Loading on the STATUS output should be minimized because this signal is used internally by the 7805A. It is recommended that load current not exceed 2 mA and load capacitance be kept well below 1000 pF. A summary of the pin differences between the ADS7805 and 7805A is provided below. TABLE 16. PIN DIFFERENCES PIN NUMBER 23 ADS7805 BYTE 7805A STATUS PIN DIFFERENCE DESCRIPTION A high level STATUS signal indicates that power is removed from the ADS7805 die. I/O pins must not be driven high while this signal is active. The BYTE signal of the ADS7805 die is internally grounded but can also be made available in place of the STATUS pin at customer request. The ADS7805 VANA and VDIG die pads are connected together and are available at the DECPLNG pin. This pin allows external ceramic capacitors to directly decouple the power inputs to the ADS7805 die-to-analog ground. Decoupling capacitance should not exceed 0.2 uF typical. This pin must not be connected to a power supply directly since this will defeat the latchup protection circuitry. Electrolytic filter capacitors should not be connected to this pin but should be connected between the VS pin and ground. This is the power supply input for the LPT circuitry and the protected ADS7805 die. This supply should be treated as an analog supply with filtering and/or isolation from the noisy system digital power supply. The LPT latchup current sense and power switch circuitry is located between this pin and the DECPLNG pin. Memory 27 VANA DECPLNG 28 VDIG VS Example Circuits for Using the 7805A Figure 2 shows a typical application circuit for using the 7805A as an input to a digital data processor. This circuit shows the use of the STATUS pin to tri-state the control inputs when the latchup protection circuit cycles the power to the protected ADS7805 die. Figure 3 shows a typical application circuit for connecting the 7805A to a 16-bit data bus with multiple drivers on the bus. Tri-state buffers are used to isolate the 7805A data outputs from the data bus. Figure 4 shows the typical application circuit for connecting the 7805A to an 8-bit data bus. 01.10.05 Rev 9 All data sheets are subject to change without notice 10 ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC FIGURE 4. TYPICAL 7805A APPLICATION CIRCUIT 7805ALP Memory FIGURE 5. TYPICAL 7805A CIRCUIT WITH 16-BIT BUS INTERFACE 01.10.05 Rev 9 All data sheets are subject to change without notice 11 ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC FIGURE 6. TYPICAL 7805A CIRCUIT WITH 8-BIT BUS INTERFACE 7805ALP Memory Testing the 7805A Latchup Protection Circuitry The DECPLNG pin provides direct access to the 7805ALP converter supply pins for attaching external decoupling capacitor(s) to ground. This pin can also be used to test the LPT™ operation by sinking a pulsed current load to ground as shown in the test circuit in Figure 5 and as described in the LPT Operating Characteristics Table (Table 17) and LPT Timing diagram (Figure 7). This test approximates the operation of the 7805A in response to a single event latchup and recovery. During the time that the power is cycled, output signals and data from the 7805A are invalid. The STATUS signal HIGH indicates that power is removed from the ADS7805 die. All input pins must be driven low or tri-stated. When this signal is low, power is applied to the ADS7805 die. The STATUS signal can be used to measure the supply recovery time. The status signal can exhibit multiple transitions when power is re-applied and the decoupling capacitors are charged. The duration and number of transitions is dependent on the amount of capacitance used. The supply recovery time interval starts when the supply current rises (causing STATUS to go high) and ends when the STATUS signal stabilizes low again. Within the functional recovery time interval (typically 25 µ sec after the LPT circuit reapplies power), the normal functional operation of the converter is restored with less than 5% full scale error. Additional settling time is then required to return to full accurate operation. Defined recovery time intervals indicate that time to recover first is within 8-bit accuracy, then within 12 bit accuracy, and finally full 16-bit accuracy. These recovery times are primarily due to the single event and power cycling effects on the reference circuits and the settling times of their respective filter capacitors. TABLE 17. LPT™ OPERATING CHARACTERISTICS PARAMETER Supply threshold current - ITHR Protection time (IS Peak = .2A) - TPT Input tri-state time - TIOFF 01.10.05 Rev 9 MIN 56 --- TYP 77 1 -- MAX 99 -100 UNITS mA µ sec nsec All data sheets are subject to change without notice 12 ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC TABLE 17. LPT™ OPERATING CHARACTERISTICS PARAMETER Status instability time - TINST Supply recovery time (IS Peak = .2A) - TSR Functional recovery time (IS Peak = .2A) - TFR 8-Bit accuracy recovery time (IS Peak = .2A) - T8R 12-Bit accuracy recovery time (IS Peak = .2A) - T12R Full accuracy recovery time (IS Peak - .2A) - TFAR MIN -25 ----TYP -50 TSR + 25 75 250 425 7805ALP MAX 10 100 ----UNITS µ sec µ sec µ sec msec msec msec FIGURE 7. LPT™ TEST CIRCUIT Memory 01.10.05 Rev 9 All data sheets are subject to change without notice 13 ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC FIGURE 8. 7805ALP Memory FIGURE 9. SEU AND SEL CROSS SECTION 01.10.05 Rev 9 All data sheets are subject to change without notice 14 ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC 7805ALP Memory 28 PIN RAD-PAK® FLAT PACKAGE SYMBOL MIN A b c D E E1 E2 E3 e L Q S1 N 0.390 0.028 0.000 0.177 0.015 0.004 -0.400 -0.295 0.000 DIMENSION NOM 0.192 0.017 0.005 0.800 0.410 -0.300 0.055 0.050 BSC 0.400 0.032 0.067 28 0.410 0.036 -MAX 0.207 0.022 0.009 0.808 0.420 0.440 --- Note: All dimensions in inches 01.10.05 Rev 9 All data sheets are subject to change without notice 15 ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC 7805ALP Memory 28-PIN RAD-PAK® DUAL IN LINE PACKAGE SYMBOL MIN A b b2 c D E eA eA/2 e L Q S1 S2 N 0.165 0.015 0.005 0.005 -0.014 0.045 0.008 -0.585 DIMENSION NOM 0.185 0.018 0.050 0.010 1.600 0.595 0.600 BSC 0.300 BSC 0.100 BSC 0.175 0.030 0.125 -28 0.185 0.075 --MAX 0.225 0.026 0.065 0.018 1.616 0.605 Note: All dimensions in inches 01.10.05 Rev 9 All data sheets are subject to change without notice 16 ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC Important Notice: 7805ALP These data sheets are created using the chip manufacturer’s published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts. Memory 01.10.05 Rev 9 All data sheets are subject to change without notice 17 ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC Product Ordering Options 7805ALP Model Number 7805ALP RP X X Feature Option Details Screening Flow MCM1 K = Maxwell Self-Defined Class K H = Maxwell Self-Defined Class H I = Industrial (testing @ -40°C, +25°C, +85°C) E = Engineering (testing @ +25°C) Memory Package D = Dual In-line Package (DIP) F = Flat Pack Radiation Feature RP = RAD-PAK® package Base Product Nomenclature 16-Bit Latchup Protected ADC 1) Products are manufactured and screened to Maxwell Technologies self-defined Class H and Class K flows. 01.10.05 Rev 9 All data sheets are subject to change without notice 18 ©2005 Maxwell Technologies All rights reserved.