89C1632RPQH-30

89C1632 16 Megabit (512K x 32-Bit) MCM SRAM 16 Megabit (512k x 32-bit) SRAM MCM CS 1-4 Address OE, WE Power 4Mb SRAM 4Mb SRAM 4Mb SRAM 4Mb SRAM Ground MCM Memory I/O 0-7 I/O 8-15 I/O 16-23 I/O 24-31 Logic Diagram FEATURES: • Four 512k x 8 SRAM architecture • RAD-PAK® technology hardens against natural space radiation technology • Total dose hardness: - > 100 krad (Si), depending upon space mission • Excellent Single Event Effects: - SEL > 101MeV-cm2/mg - SEU threshold = 3 MeV-cm2/mg - SEU saturated cross section: 6E-9 cm2/bit • Package: 68-pin quad flat package • Fast access time: 20, 25 and 30 ns • Completely static memory - no clock or timing strobe required • Internal bypass capacitor • High-speed silicon-gate CMOS technology • 5V or 3V ± 10% power supply • Equal address and chip enable access times • Three-state outputs • All inputs and outputs are TTL compatible DESCRIPTION: Maxwell Technologies’ 89C1632 high-performance 16 Megabit Multi-Chip Module (MCM) Static Random Access Memory features a greater than 100 krad (Si) total dose tolerance, depending upon space mission. The four 4-Megabit SRAM die and bypass capacitors are incorporated into a high-reliable hermetic quad flat-pack ceramic package. With high-performance silicon-gate CMOS technology, the 89C1632 reduces power consumption and eliminates the need for external clocks or timing strobes. It is equipped with output enable (OE) and four byte enable (CS1 - CS4) inputs to allow greater system flexibility. When OE input is high, the output is forced to high impedance. Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. In a GEO orbit, RAD-PAK provides true greater than 100 krad (Si) total radiation dose tolerance, dependent upon space mission. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or a space mission. This product is available with screening up to Maxwell Technologies self-defined Class K. 01.10.05 Rev 3 All data sheets are subject to change without notice 1 (619) 503-3300 - Fax: (619) 503-3301 - www.maxwell.com ©2005 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit) MCM SRAM TABLE 1. PINOUT DESCRIPTION PIN 34-28, 42-36, 62-64, 7, 8 65 66 3-6 43-46, 48-56, 58-61, 9-12, 14-17, 19-22, 24-27 2, 67, 68 1, 18, 35, 52 13, 23, 47, 57 SYMBOL A0-A18 WE OE CS1 - CS4 I/O0-I/O31 NC VCC VSS DESCRIPTION Address Enable WriteEnable Output Enable Chip Enable Data Input/Output No Connection +5V Power Supply Ground 89C1632 TABLE 2. 89C1632 ABSOLUTE MAXIMUM RATINGS (VOLTAGE REFERENCED TO VSS = 0V) PARAMETER Power Supply Voltage Relative to VSS Voltage Relative to VSS for Any Pin Except VCC Power Dissipation Operating Temperature Storage Temperature SYMBOL VCC VIN, VOUT PD TA TS MIN -0.5 -0.5 --55 -65 MAX +7.0 VCC+0.5 4.0 +125 +150 UNITS V V W °C °C Memory TABLE 3. 89C1632 RECOMMENDED OPERATING CONDITIONS (VCC = 5.0 + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED) PARAMETER Supply Voltage, (Operating Voltage Range) Input High Voltage Input Low Voltage 1. VIH (max) = VCC + 2V ac (pulse width < 10ns) for I < 80 mA. 2. VIL (min) = -2.0V ac; (pulse width < 20 ns) for I < 80 mA. SYMBOL VCC VIH VIL MIN 4.5 2.2 -0.5 (2) MAX 5.5 VCC + 0.5 0.8 (1) UNITS V V V TABLE 4. 89C1632 DELTA LIMITS PARAMETER ICC 01.10.05 Rev 3 VARIATIONL +10% of stated value in table 5 All data sheets are subject to change without notice 2 ©2005 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit) MCM SRAM TABLE 4. 89C1632 DELTA LIMITS PARAMETER ISB ISB1 ILI VARIATIONL +10% of stated value in table 5 +10% of stated value in table 5 +10% of stated value in table 5 89C1632 TABLE 5. 89C1632 DC ELECTRICAL CHARACTERISTICS (VCC = 5.0 + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED) PARAMETER Input Leakage Current Output Leakage Current Average Operating Current Cycle Time: 20 ns 25 ns 30 ns Standby Power Supply Current CMOS Standby Power Supply Current Output Low Voltage Output High Voltage Input CS1 - CS4, OE, WE I/O0-7, I/O8-15, I/O16-23, I/O24-31 Input / Output Capacitance1 1. Guaranteed by design. Capacitance1 SYMBOL TEST CONDITIONS ILI ILO ICC VIN = 0 to VCC CS = VIH, VOUT = VSS to VCC Min. Cycle, 100% Duty, CS = VIL, IOUT = 0 mA VIN = VIH or VIL SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 ---1, 2, 3 1, 2, 3 ----MIN -8.0 -8.0 TYP ---800 760 720 240 60 mA mA MAX +8.0 +8.0 UNITS uA uA mA Memory ISB ISB1 CS= VIH, cycle time > 25ns CS > VCC - 0.2V, f = 0 MHz, VIN > VCC - 0.2V or VIN < 0.2V IOL = + 8.0 mA IOH = -4.0 mA VIN = 0 V VOL VOH CIN 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 -2.4 --- 0.4 -7 28 7 8 V V pF COUT VI/O = 0 V 4, 5, 6 pF TABLE 6. 89C1632 AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED) PARAMETER Input Pulse Level Output Timing Measurement Reference Level Input Rise/Fall Time 01.10.05 Rev 3 MIN 0.0 --- TYP ---- MAX 3.0 1.5 3.0 UNITS V V ns All data sheets are subject to change without notice 3 ©2005 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit) MCM SRAM (VCC = 5.0 + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED) PARAMETER Input Timing Measurement Reference Level MIN -TYP -- 89C1632 MAX 1.5 UNITS V TABLE 6. 89C1632 AC OPERATING CONDITIONS AND CHARACTERISTICS TABLE 7. 89C1632 READ CYCLE (VCC = 5.0 + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED) PARAMETER Read Cycle Time -20 -25 -30 Address Access Time -20 -25 -30 Chip Select to Output -20 -25 -30 Output Enable to Output -20 -25 -30 Output Enable to Low-Z Output -20 -25 -30 Chip Enable to Low-Z Output -20 -25 -30 Output Disable to High-Z Output -20 -25 -30 Chip Disable to High-Z Output -20 -25 -30 Output Hold from Address Change -20 -25 -30 SYMBOL tRC SUBGROUPS 9, 10, 11 20 25 30 tAA 9, 10, 11 ---tCO 9, 10, 11 ---tOE 9, 10, 11 ---tOLZ 9, 10, 11 ---tLZ 9, 10, 11 ---tOHZ 9, 10, 11 ---tHZ 9, 10, 11 ---tOH 9, 10, 11 3 3 3 ------5 6 8 ---ns 5 6 8 ---ns 3 3 3 ---ns 0 0 0 ---ns ---10 12 14 ns ---20 25 30 ns ---20 25 30 ------ns MIN TYP MAX UNITS ns Memory ns 01.10.05 Rev 3 All data sheets are subject to change without notice 4 ©2005 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit) MCM SRAM TABLE 8. 89C1632 FUNCTIONAL DESCRIPTION CS H L L L 1. X = don’t care. WE X1 H H L OE X1 H L X1 MODE Not Select Output Disable Read Write I/O PIN High-Z High-Z DOUT DIN 89C1632 SUPPLY CURRENT ISB, ISB1 ICC ICC ICC TABLE 9. 89C1632 WRITE CYCLE (VCC = 5.0 + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED) PARAMETER Write Cycle Time -20 -25 -30 Chip Select to End of Write -20 -25 -30 Address Set-up Time -20 -25 -30 Address Valid to End of Write -20 -25 -30 Write Pulse Width (OE High) -20 -25 -30 Write Pulse Width (OE Low) -20 -25 -30 Write Recovery Time -20 -25 -30 SYMBOL tWC SUBGROUPS 9, 10, 11 20 25 30 tCW 9, 10, 11 14 17 20 tAS 9, 10, 11 0 0 0 tAW 9, 10, 11 14 17 20 tWP 9, 10, 11 14 17 20 tWP1 9, 10, 11 20 25 30 tWR 9, 10, 11 0 0 0 ------ns ---ns ---ns ---ns ---ns ---ns MIN TYP MAX UNITS Memory ns 01.10.05 Rev 3 All data sheets are subject to change without notice 5 ©2005 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit) MCM SRAM TABLE 9. 89C1632 WRITE CYCLE (VCC = 5.0 + 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED) PARAMETER Write to Output High-Z -20 -25 -30 Data to Write Time Overlap -25 -30 Data Hold from Write Time -20 -25 -30 End Write to Output Low-Z -20 -25 -30 SYMBOL tWHZ SUBGROUPS 9, 10, 11 ---tDW 9, 10, 11 10 12 14 tDH 9, 10, 11 0 0 0 tOW 9, 10, 11 ---3 3 3 5 7 9 MIN TYP 89C1632 MAX ---ns ---ns ---ns ---UNITS ns Memory 01.10.05 Rev 3 All data sheets are subject to change without notice 6 ©2005 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit) MCM SRAM FIGURE 1. AC TEST LOADS 89C1632 FIGURE 2. TIMING WAVEFORM OF READ CYCLE (1) (ADDRESS CONTROLLED) Memory FIGURE 3. TIMING WAVEFORM OF READ CYCLE (2) (WE = VIH) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 01.10.05 Rev 3 All data sheets are subject to change without notice 7 ©2005 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit) MCM SRAM 89C1632 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage conditions, tHZ (max) is less than tLZ (min) both for a given device and from device to device. 5. Transition is measured +200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS = VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. FIGURE 4. TIMING WAVEFORM OF WRITE CYCLE (1) (OE CLOCK) Memory FIGURE 5. TIMING WAVEFORM OF WRITE CYCLE (2) (OE LOW FIIXED) 01.10.05 Rev 3 All data sheets are subject to change without notice 8 ©2005 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit) MCM SRAM 89C1632 FIGURE 6. TIMING WAVEFORM OF WRITE CYCLE (3) (CS CONTROLLED) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low. A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization of elimination of bus contention conditions is necessary during read and write cycle. 8. If CS foes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. DOUT is the read data of the new address. 10.When CS is low, I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. Memory 01.10.05 Rev 3 All data sheets are subject to change without notice 9 ©2005 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit) MCM SRAM 89C1632 FIGURE 7. SRAM HEAVY ION CROSS SECTION Memory FIGURE 8. SRAM PROTON SEU CROSS SECTION STATIC 01.10.05 Rev 3 All data sheets are subject to change without notice 10 ©2005 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit) MCM SRAM 89C1632 Memory 68 PIN RAD-PAK® QUAD FLAT PACKAGE SYMBOL MIN A b c D D1 e S1 F1 F2 L L1 L2 A1 N -1.239 1.429 2.485 2.485 1.690 0.180 0.206 0.015 0.008 1.479 DIMENSION NOM 0.225 0.017 0.009 1.494 0.800 0.050 BSC 0.339 1.244 1.434 2.510 2.500 1.700 0.195 68 -1.249 1.439 2.545 2.505 1.710 0.210 MAX 0.244 0.018 0.12 1.509 Q68-04 Note: All dimensions in inches 01.10.05 Rev 3 All data sheets are subject to change without notice 11 ©2005 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit) MCM SRAM Important Notice: 89C1632 These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts. Memory 01.10.05 Rev 3 All data sheets are subject to change without notice 12 ©2005 Maxwell Technologies. All rights reserved. 16 Megabit (512K x 32-Bit) MCM SRAM Product Ordering Options Model Number 89C1632 RP Q X -XX Feature Access Time 89C1632 Option Details 20 = 20 ns 25 = 25 ns 30 = 30 ns Screening Flow Multi Chip Module (MCM)1 K = Maxwell Self-Defined Class K H = Maxwell Self-Defined Class H I = Industrial (testing @ -55°C, +25°C, +125°C) E = Engineering (testing @ +25°C) Memory Package Q = Quad Flat Pack Radiation Feature RP = RAD-PAK® package Base Product Nomenclature 16 Megabit (512K x 32-Bit) MCM SRAM 1) Products are manufactured and screened to Maxwell Technologies self-defined Class H and Class K. 01.10.05 Rev 3 All data sheets are subject to change without notice 13 ©2005 Maxwell Technologies. All rights reserved.